From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-1.0 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2E01CC10F0E for ; Mon, 15 Apr 2019 14:36:08 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id E53A22075B for ; Mon, 15 Apr 2019 14:36:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727594AbfDOOgG convert rfc822-to-8bit (ORCPT ); Mon, 15 Apr 2019 10:36:06 -0400 Received: from mail-ed1-f66.google.com ([209.85.208.66]:33098 "EHLO mail-ed1-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725789AbfDOOgF (ORCPT ); Mon, 15 Apr 2019 10:36:05 -0400 Received: by mail-ed1-f66.google.com with SMTP id d55so14117209ede.0; Mon, 15 Apr 2019 07:36:03 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:content-transfer-encoding; bh=Is/ROkUMxoj6uAm+SAA3PnrEYqYSelRvNitd1y8NtLw=; b=DCL1EeTmtDHuhdaHmjtJzPibj8Vc/yGorw8KVNLQGUxhHQOgRAViXyxnXROYTU1Do6 Jf0wnGc5Jbzt32tnHhlc6sxYz8JdXrnd3y4TdAwnAjaZACxscOvOqVA2zibPGEPyQqSd xuhGFvV2fQcCivQJEb94DnAlLJmKDo5jNSL7NL7VpHVjMXgx6gwzYqpKPgd8KHWCCLul VSksQpu+EklJjai+wd6dCGUZsnJFTYdWP4QV+6g0oNszDt5WrtN4E+euGlEmnbc0iKUk GJ5pXBZgqzmCcue5mshAeAep/Ou+eKjPBQstO4tjtKEakPsNvxj7WmLY2rTbxlL4/S+7 xBwg== X-Gm-Message-State: APjAAAWuevbB8C5zjQUF4EXnzjmeVnovJnXeKGByQyvqroD7ZACoOQrd wpecWdaXlaiCom7m8Xn9wlcnobPAIDs= X-Google-Smtp-Source: APXvYqwicB/YQ4Y9AH5YYhev8hhO401p7PvXoVT62cOIfREGwHFVIegZykyKNMW0uXFO1/NWY2m+mw== X-Received: by 2002:a50:9816:: with SMTP id g22mr13967162edb.236.1555338962344; Mon, 15 Apr 2019 07:36:02 -0700 (PDT) Received: from mail-wr1-f41.google.com (mail-wr1-f41.google.com. [209.85.221.41]) by smtp.gmail.com with ESMTPSA id y5sm8742824eds.7.2019.04.15.07.36.00 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 15 Apr 2019 07:36:01 -0700 (PDT) Received: by mail-wr1-f41.google.com with SMTP id p10so22300237wrq.1; Mon, 15 Apr 2019 07:36:00 -0700 (PDT) X-Received: by 2002:a5d:6889:: with SMTP id h9mr24067198wru.12.1555338960223; Mon, 15 Apr 2019 07:36:00 -0700 (PDT) MIME-Version: 1.0 References: <20190412120730.473-1-megous@megous.com> <20190415142222.cytlvz7z3mjf7slm@core.my.home> In-Reply-To: <20190415142222.cytlvz7z3mjf7slm@core.my.home> From: Chen-Yu Tsai Date: Mon, 15 Apr 2019 22:35:47 +0800 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [linux-sunxi] [PATCH 0/3] Add basic support for RTC on Allwinner H6 SoC To: =?UTF-8?Q?Ond=C5=99ej_Jirman?= , Chen-Yu Tsai , Alessandro Zummo , Alexandre Belloni , Rob Herring , Mark Rutland , Maxime Ripard , linux-rtc@vger.kernel.org, devicetree , linux-arm-kernel , linux-kernel , linux-sunxi Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8BIT Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, Apr 15, 2019 at 10:22 PM 'Ondřej Jirman' via linux-sunxi wrote: > > Hi ChenYu, > > On Mon, Apr 15, 2019 at 04:18:12PM +0800, Chen-Yu Tsai wrote: > > On Fri, Apr 12, 2019 at 8:07 PM megous via linux-sunxi > > wrote: > > > > > > From: Ondrej Jirman > > > > > > I went through the datasheets for H6 and H5, and compared the differences. > > > RTCs are largely similar, but not entirely compatible. Incompatibilities > > > are in details not yet implemented by the rtc driver though. > > > > > > I also corrected the clock tree in H6 DTSI. > > > > Please also add DCXO clock input/output and XO clock input to the bindings > > and DT, and also fix up the clock tree. You can skip them in the driver for > > now, but please add a TODO. As long as you don't change the clock-output-name > > of osc24M, everything should work as before. > > That's a bit confusing. There's no clock-output-name for osc24M, nor for input > clock used in the dt-bindings or the driver. Perhaps you meant osc32k? Maybe > I'm misunderstanding something? I meant the clock-output-names in the device node of the external 24M crystal. > If you look at the datasheet page 349, it looks like RTC provides "hosc" > clock (to plls and the system) either from XO or DCXO oscillators. > The default selection depends on the voltage level on external PAD. > > So based on what you wrote, I suggest these actual changes/names: > > 1) Add DT docs for HOSC clock provided at index 3: > > - 3: HOSC, 24MHz clock that clocks the PLLs and most of the SoC (H6 only) Correct. > 2) Add bindings description for "osc24M-dc", "osc24M-m" input clocks in > addition to existing support for "osc32k". Name "osc24M-m" is based on > X24MIN/MOUT pins and datasheet's "clk_24mxo" name. > > 3) The RTC driver would now just registers a fixed HOSC clock with a name > gathered from the clock-output-names index 3 (if enabled by the new > export_hosc flag - only enabled on H6). You don't need to do this part yet. Since the CCU drivers are hard-wired (suprise) to use the global clock name "osc24M" as hosc source. The DT references are only for show ATM, so it doesn't matter if you implement the clocks in the RTC driver. However we want the DT to be correct, so that when we do get around to doing it, we won't have to update the DT again. It's up to you though. If you want to implement basic support, that's fine by me. However you won't be able to test it without hacking the CCU driver. After describing this, it seems that when we get to doing the clk parent rework, we'll be in a bad situation if we don't get rtc changes in before the CCU changes. > The driver would ignore the "osc24M-dc", "osc24M-m" input clocks. Or perhaps > it could just support a case where only one of these are used and make it the > only parent of the HOSC clock? They should just be DCXO and XO, based on the diagram. The names are local to the RTC, so they don't need to be globally unique. Whatever matches the datasheet is best. > HOSC default source selection is done based on external PAD setup, and > there's no need for runtime access/selection of HOSC source at the moment. Is it even possible to change it? > 4) In the future the RTC driver would be extended to support more refined > setup/muxing/runtime selection of osc24M-dc/osc24M-m. PRCM driver would > provide the osc24M-m clock, to be able for kernel to know how to gate it. > > The board's DTSI would have to link either "osc24M-dc", "osc24M-m" to nodes > describing an external crystal (or to PRCM clock in the future). It's a boards > choice on what crystals are actually used. 3 configs are possible - with one or > two crystals, connected to either one of XIN/XOUT X24MIN/X24MOUT pins or both. AFAIK, osc24M-dc would link directly to the external crystal, while osc24M-m would link to the external crystal first, then PRCM if it gets implemented. > Would that work? > > DT would still probably need a re-work in the future, if the PRCM clock > modeling the gate would be needed. Yeah. We'll deal with that when we get to it. To summarize, the goal is to get the DT right the first time. Regards ChenYu > regards, > o. > > > We just want the DT to describe what is actually there. For the XO input, > > you could just directly reference the external crystal node. The gate for > > it is likely somewhere in the PRCM block, which we don't have docs for. > > > > > There's a small detail here, that's not described absolutely correctly in > > > DTSI, but the difference is not really that material. ext_osc32k is > > > originally modelled as a fixed clock that feeds into RTC module, but in > > > reality it's the RTC module that implements via its registers enabling and > > > disabling of this oscillator/clock. > > > > > > Though: > > > - there's no other possible user of ext_osc32k than RTC module > > > - there's no other possible external configuration for the crystal > > > circuit that would need to be handled in the dts per board > > > > > > So I guess, while the description is not perfect, this patch series still > > > improves the current situation. Or maybe I'm misunderstanding something, > > > and &ext_osc32k node just describes a fact that there's a crystal on > > > the board. Then, everything is perhaps fine. :) > > > > Correct. The external clock nodes are modeling the crystal, not the internal > > clock gate / distributor. > > > > Were the vendor to not include the crystal (for whatever reasons), the DT > > should be able to describe it via the absence of the clock input, and the > > driver should correctly use the internal (inaccurate) oscillator. I realize > > the clocks property is required, and the driver doesn't handle this case > > either, so we might have to fix that if it were to appear in the wild. > > > > > For now, the enable bit for this oscillator is toggled by the re-parenting > > > code automatically, as needed. > > > > That's fine. No need to increase the clock tree depth. > > > > ChenYu > > > > > This patchset is necessary for implementing the WiFi/Bluetooth support > > > on boards using H6 SoC. > > > > > > Please take a look. > > > > > > Thank you and regards, > > > Ondrej Jirman > > > > > > Ondrej Jirman (3): > > > dt-bindings: Add compatible for H6 RTC > > > rtc: sun6i: Add support for H6 RTC > > > arm64: dts: sun50i-h6: Add support for RTC and fix the clock tree > > > > > > .../devicetree/bindings/rtc/sun6i-rtc.txt | 1 + > > > arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 30 +++++++------- > > > drivers/rtc/rtc-sun6i.c | 40 ++++++++++++++++++- > > > 3 files changed, 55 insertions(+), 16 deletions(-) > > > > > > -- > > > 2.21.0 > > > > > > -- > > > You received this message because you are subscribed to the Google Groups "linux-sunxi" group. > > > To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscribe@googlegroups.com. > > > For more options, visit https://groups.google.com/d/optout. > > -- > You received this message because you are subscribed to the Google Groups "linux-sunxi" group. > To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscribe@googlegroups.com. > For more options, visit https://groups.google.com/d/optout. From mboxrd@z Thu Jan 1 00:00:00 1970 From: Chen-Yu Tsai Subject: Re: [PATCH 0/3] Add basic support for RTC on Allwinner H6 SoC Date: Mon, 15 Apr 2019 22:35:47 +0800 Message-ID: References: <20190412120730.473-1-megous@megous.com> <20190415142222.cytlvz7z3mjf7slm@core.my.home> Reply-To: wens-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org Mime-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Return-path: Sender: linux-sunxi-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org In-Reply-To: <20190415142222.cytlvz7z3mjf7slm-9v8tmBix7cb9zxVx7UNMDg@public.gmane.org> List-Post: , List-Help: , List-Archive: , List-Unsubscribe: , To: =?UTF-8?Q?Ond=C5=99ej_Jirman?= , Chen-Yu Tsai , Alessandro Zummo , Alexandre Belloni , Rob Herring , Mark Rutland , Maxime Ripard , linux-rtc-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, devicetree , linux-arm-kernel , linux-kernel , linux-sunxi List-Id: devicetree@vger.kernel.org On Mon, Apr 15, 2019 at 10:22 PM 'Ond=C5=99ej Jirman' via linux-sunxi wrote: > > Hi ChenYu, > > On Mon, Apr 15, 2019 at 04:18:12PM +0800, Chen-Yu Tsai wrote: > > On Fri, Apr 12, 2019 at 8:07 PM megous via linux-sunxi > > wrote: > > > > > > From: Ondrej Jirman > > > > > > I went through the datasheets for H6 and H5, and compared the differe= nces. > > > RTCs are largely similar, but not entirely compatible. Incompatibilit= ies > > > are in details not yet implemented by the rtc driver though. > > > > > > I also corrected the clock tree in H6 DTSI. > > > > Please also add DCXO clock input/output and XO clock input to the bindi= ngs > > and DT, and also fix up the clock tree. You can skip them in the driver= for > > now, but please add a TODO. As long as you don't change the clock-outpu= t-name > > of osc24M, everything should work as before. > > That's a bit confusing. There's no clock-output-name for osc24M, nor for = input > clock used in the dt-bindings or the driver. Perhaps you meant osc32k? Ma= ybe > I'm misunderstanding something? I meant the clock-output-names in the device node of the external 24M cryst= al. > If you look at the datasheet page 349, it looks like RTC provides "hosc" > clock (to plls and the system) either from XO or DCXO oscillators. > The default selection depends on the voltage level on external PAD. > > So based on what you wrote, I suggest these actual changes/names: > > 1) Add DT docs for HOSC clock provided at index 3: > > - 3: HOSC, 24MHz clock that clocks the PLLs and most of the SoC (H6 onl= y) Correct. > 2) Add bindings description for "osc24M-dc", "osc24M-m" input clocks in > addition to existing support for "osc32k". Name "osc24M-m" is based on > X24MIN/MOUT pins and datasheet's "clk_24mxo" name. > > 3) The RTC driver would now just registers a fixed HOSC clock with a name > gathered from the clock-output-names index 3 (if enabled by the new > export_hosc flag - only enabled on H6). You don't need to do this part yet. Since the CCU drivers are hard-wired (suprise) to use the global clock name "osc24M" as hosc source. The DT references are only for show ATM, so it doesn't matter if you implement the clocks in the RTC driver. However we want the DT to be correct, so that when we do get around to doing it, we won't have to update the DT again. It's up to you though. If you want to implement basic support, that's fine by me. However you won't be able to test it without hacking the CCU driver. After describing this, it seems that when we get to doing the clk parent rework, we'll be in a bad situation if we don't get rtc changes in before the CCU changes. > The driver would ignore the "osc24M-dc", "osc24M-m" input clocks. Or p= erhaps > it could just support a case where only one of these are used and make= it the > only parent of the HOSC clock? They should just be DCXO and XO, based on the diagram. The names are local to the RTC, so they don't need to be globally unique. Whatever matches the datasheet is best. > HOSC default source selection is done based on external PAD setup, and > there's no need for runtime access/selection of HOSC source at the mom= ent. Is it even possible to change it? > 4) In the future the RTC driver would be extended to support more refined > setup/muxing/runtime selection of osc24M-dc/osc24M-m. PRCM driver woul= d > provide the osc24M-m clock, to be able for kernel to know how to gate = it. > > The board's DTSI would have to link either "osc24M-dc", "osc24M-m" to nod= es > describing an external crystal (or to PRCM clock in the future). It's a b= oards > choice on what crystals are actually used. 3 configs are possible - with= one or > two crystals, connected to either one of XIN/XOUT X24MIN/X24MOUT pins or = both. AFAIK, osc24M-dc would link directly to the external crystal, while osc24M-= m would link to the external crystal first, then PRCM if it gets implemented. > Would that work? > > DT would still probably need a re-work in the future, if the PRCM clock > modeling the gate would be needed. Yeah. We'll deal with that when we get to it. To summarize, the goal is to get the DT right the first time. Regards ChenYu > regards, > o. > > > We just want the DT to describe what is actually there. For the XO inpu= t, > > you could just directly reference the external crystal node. The gate f= or > > it is likely somewhere in the PRCM block, which we don't have docs for. > > > > > There's a small detail here, that's not described absolutely correctl= y in > > > DTSI, but the difference is not really that material. ext_osc32k is > > > originally modelled as a fixed clock that feeds into RTC module, but = in > > > reality it's the RTC module that implements via its registers enablin= g and > > > disabling of this oscillator/clock. > > > > > > Though: > > > - there's no other possible user of ext_osc32k than RTC module > > > - there's no other possible external configuration for the crystal > > > circuit that would need to be handled in the dts per board > > > > > > So I guess, while the description is not perfect, this patch series s= till > > > improves the current situation. Or maybe I'm misunderstanding somethi= ng, > > > and &ext_osc32k node just describes a fact that there's a crystal on > > > the board. Then, everything is perhaps fine. :) > > > > Correct. The external clock nodes are modeling the crystal, not the int= ernal > > clock gate / distributor. > > > > Were the vendor to not include the crystal (for whatever reasons), the = DT > > should be able to describe it via the absence of the clock input, and t= he > > driver should correctly use the internal (inaccurate) oscillator. I rea= lize > > the clocks property is required, and the driver doesn't handle this cas= e > > either, so we might have to fix that if it were to appear in the wild. > > > > > For now, the enable bit for this oscillator is toggled by the re-pare= nting > > > code automatically, as needed. > > > > That's fine. No need to increase the clock tree depth. > > > > ChenYu > > > > > This patchset is necessary for implementing the WiFi/Bluetooth suppor= t > > > on boards using H6 SoC. > > > > > > Please take a look. > > > > > > Thank you and regards, > > > Ondrej Jirman > > > > > > Ondrej Jirman (3): > > > dt-bindings: Add compatible for H6 RTC > > > rtc: sun6i: Add support for H6 RTC > > > arm64: dts: sun50i-h6: Add support for RTC and fix the clock tree > > > > > > .../devicetree/bindings/rtc/sun6i-rtc.txt | 1 + > > > arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 30 +++++++------- > > > drivers/rtc/rtc-sun6i.c | 40 +++++++++++++++++= +- > > > 3 files changed, 55 insertions(+), 16 deletions(-) > > > > > > -- > > > 2.21.0 > > > > > > -- > > > You received this message because you are subscribed to the Google Gr= oups "linux-sunxi" group. > > > To unsubscribe from this group and stop receiving emails from it, sen= d an email to linux-sunxi+unsubscribe-/JYPxA39Uh5TLH3MbocFF+G/Ez6ZCGd0@public.gmane.org > > > For more options, visit https://groups.google.com/d/optout. > > -- > You received this message because you are subscribed to the Google Groups= "linux-sunxi" group. > To unsubscribe from this group and stop receiving emails from it, send an= email to linux-sunxi+unsubscribe-/JYPxA39Uh5TLH3MbocFF+G/Ez6ZCGd0@public.gmane.org > For more options, visit https://groups.google.com/d/optout. --=20 You received this message because you are subscribed to the Google Groups "= linux-sunxi" group. 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[209.85.221.45]) by smtp.gmail.com with ESMTPSA id s14sm4588015eda.26.2019.04.15.07.36.00 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 15 Apr 2019 07:36:00 -0700 (PDT) Received: by mail-wr1-f45.google.com with SMTP id q1so22323242wrp.0 for ; Mon, 15 Apr 2019 07:36:00 -0700 (PDT) X-Received: by 2002:a5d:6889:: with SMTP id h9mr24067198wru.12.1555338960223; Mon, 15 Apr 2019 07:36:00 -0700 (PDT) MIME-Version: 1.0 References: <20190412120730.473-1-megous@megous.com> <20190415142222.cytlvz7z3mjf7slm@core.my.home> In-Reply-To: <20190415142222.cytlvz7z3mjf7slm@core.my.home> From: Chen-Yu Tsai Date: Mon, 15 Apr 2019 22:35:47 +0800 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [linux-sunxi] [PATCH 0/3] Add basic support for RTC on Allwinner H6 SoC To: =?UTF-8?Q?Ond=C5=99ej_Jirman?= , Chen-Yu Tsai , Alessandro Zummo , Alexandre Belloni , Rob Herring , Mark Rutland , Maxime Ripard , linux-rtc@vger.kernel.org, devicetree , linux-arm-kernel , linux-kernel , linux-sunxi X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190415_073603_276035_0E8C1116 X-CRM114-Status: GOOD ( 49.37 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org T24gTW9uLCBBcHIgMTUsIDIwMTkgYXQgMTA6MjIgUE0gJ09uZMWZZWogSmlybWFuJyB2aWEgbGlu dXgtc3VueGkKPGxpbnV4LXN1bnhpQGdvb2dsZWdyb3Vwcy5jb20+IHdyb3RlOgo+Cj4gSGkgQ2hl bll1LAo+Cj4gT24gTW9uLCBBcHIgMTUsIDIwMTkgYXQgMDQ6MTg6MTJQTSArMDgwMCwgQ2hlbi1Z dSBUc2FpIHdyb3RlOgo+ID4gT24gRnJpLCBBcHIgMTIsIDIwMTkgYXQgODowNyBQTSBtZWdvdXMg dmlhIGxpbnV4LXN1bnhpCj4gPiA8bGludXgtc3VueGlAZ29vZ2xlZ3JvdXBzLmNvbT4gd3JvdGU6 Cj4gPiA+Cj4gPiA+IEZyb206IE9uZHJlaiBKaXJtYW4gPG1lZ291c0BtZWdvdXMuY29tPgo+ID4g Pgo+ID4gPiBJIHdlbnQgdGhyb3VnaCB0aGUgZGF0YXNoZWV0cyBmb3IgSDYgYW5kIEg1LCBhbmQg Y29tcGFyZWQgdGhlIGRpZmZlcmVuY2VzLgo+ID4gPiBSVENzIGFyZSBsYXJnZWx5IHNpbWlsYXIs IGJ1dCBub3QgZW50aXJlbHkgY29tcGF0aWJsZS4gSW5jb21wYXRpYmlsaXRpZXMKPiA+ID4gYXJl IGluIGRldGFpbHMgbm90IHlldCBpbXBsZW1lbnRlZCBieSB0aGUgcnRjIGRyaXZlciB0aG91Z2gu Cj4gPiA+Cj4gPiA+IEkgYWxzbyBjb3JyZWN0ZWQgdGhlIGNsb2NrIHRyZWUgaW4gSDYgRFRTSS4K PiA+Cj4gPiBQbGVhc2UgYWxzbyBhZGQgRENYTyBjbG9jayBpbnB1dC9vdXRwdXQgYW5kIFhPIGNs b2NrIGlucHV0IHRvIHRoZSBiaW5kaW5ncwo+ID4gYW5kIERULCBhbmQgYWxzbyBmaXggdXAgdGhl IGNsb2NrIHRyZWUuIFlvdSBjYW4gc2tpcCB0aGVtIGluIHRoZSBkcml2ZXIgZm9yCj4gPiBub3cs IGJ1dCBwbGVhc2UgYWRkIGEgVE9ETy4gQXMgbG9uZyBhcyB5b3UgZG9uJ3QgY2hhbmdlIHRoZSBj bG9jay1vdXRwdXQtbmFtZQo+ID4gb2Ygb3NjMjRNLCBldmVyeXRoaW5nIHNob3VsZCB3b3JrIGFz IGJlZm9yZS4KPgo+IFRoYXQncyBhIGJpdCBjb25mdXNpbmcuIFRoZXJlJ3Mgbm8gY2xvY2stb3V0 cHV0LW5hbWUgZm9yIG9zYzI0TSwgbm9yIGZvciBpbnB1dAo+IGNsb2NrIHVzZWQgaW4gdGhlIGR0 LWJpbmRpbmdzIG9yIHRoZSBkcml2ZXIuIFBlcmhhcHMgeW91IG1lYW50IG9zYzMyaz8gTWF5YmUK PiBJJ20gbWlzdW5kZXJzdGFuZGluZyBzb21ldGhpbmc/CgpJIG1lYW50IHRoZSBjbG9jay1vdXRw dXQtbmFtZXMgaW4gdGhlIGRldmljZSBub2RlIG9mIHRoZSBleHRlcm5hbCAyNE0gY3J5c3RhbC4K Cj4gSWYgeW91IGxvb2sgYXQgdGhlIGRhdGFzaGVldCBwYWdlIDM0OSwgaXQgbG9va3MgbGlrZSBS VEMgcHJvdmlkZXMgImhvc2MiCj4gY2xvY2sgKHRvIHBsbHMgYW5kIHRoZSBzeXN0ZW0pIGVpdGhl ciBmcm9tIFhPIG9yIERDWE8gb3NjaWxsYXRvcnMuCj4gVGhlIGRlZmF1bHQgc2VsZWN0aW9uIGRl cGVuZHMgb24gdGhlIHZvbHRhZ2UgbGV2ZWwgb24gZXh0ZXJuYWwgUEFELgo+Cj4gU28gYmFzZWQg b24gd2hhdCB5b3Ugd3JvdGUsIEkgc3VnZ2VzdCB0aGVzZSBhY3R1YWwgY2hhbmdlcy9uYW1lczoK Pgo+IDEpIEFkZCBEVCBkb2NzIGZvciBIT1NDIGNsb2NrIHByb3ZpZGVkIGF0IGluZGV4IDM6Cj4K PiAgIC0gMzogSE9TQywgMjRNSHogY2xvY2sgdGhhdCBjbG9ja3MgdGhlIFBMTHMgYW5kIG1vc3Qg b2YgdGhlIFNvQyAoSDYgb25seSkKCkNvcnJlY3QuCgo+IDIpIEFkZCBiaW5kaW5ncyBkZXNjcmlw dGlvbiBmb3IgIm9zYzI0TS1kYyIsICJvc2MyNE0tbSIgaW5wdXQgY2xvY2tzIGluCj4gICAgYWRk aXRpb24gdG8gZXhpc3Rpbmcgc3VwcG9ydCBmb3IgIm9zYzMyayIuIE5hbWUgIm9zYzI0TS1tIiBp cyBiYXNlZCBvbgo+ICAgIFgyNE1JTi9NT1VUIHBpbnMgYW5kIGRhdGFzaGVldCdzICJjbGtfMjRt eG8iIG5hbWUuCj4KPiAzKSBUaGUgUlRDIGRyaXZlciB3b3VsZCBub3cganVzdCByZWdpc3RlcnMg YSBmaXhlZCBIT1NDIGNsb2NrIHdpdGggYSBuYW1lCj4gICAgZ2F0aGVyZWQgZnJvbSB0aGUgY2xv Y2stb3V0cHV0LW5hbWVzIGluZGV4IDMgKGlmIGVuYWJsZWQgYnkgdGhlIG5ldwo+ICAgIGV4cG9y dF9ob3NjIGZsYWcgLSBvbmx5IGVuYWJsZWQgb24gSDYpLgoKWW91IGRvbid0IG5lZWQgdG8gZG8g dGhpcyBwYXJ0IHlldC4gU2luY2UgdGhlIENDVSBkcml2ZXJzIGFyZSBoYXJkLXdpcmVkCihzdXBy aXNlKSB0byB1c2UgdGhlIGdsb2JhbCBjbG9jayBuYW1lICJvc2MyNE0iIGFzIGhvc2Mgc291cmNl LiBUaGUgRFQKcmVmZXJlbmNlcyBhcmUgb25seSBmb3Igc2hvdyBBVE0sIHNvIGl0IGRvZXNuJ3Qg bWF0dGVyIGlmIHlvdSBpbXBsZW1lbnQKdGhlIGNsb2NrcyBpbiB0aGUgUlRDIGRyaXZlci4KCkhv d2V2ZXIgd2Ugd2FudCB0aGUgRFQgdG8gYmUgY29ycmVjdCwgc28gdGhhdCB3aGVuIHdlIGRvIGdl dCBhcm91bmQgdG8KZG9pbmcgaXQsIHdlIHdvbid0IGhhdmUgdG8gdXBkYXRlIHRoZSBEVCBhZ2Fp bi4KCkl0J3MgdXAgdG8geW91IHRob3VnaC4gSWYgeW91IHdhbnQgdG8gaW1wbGVtZW50IGJhc2lj IHN1cHBvcnQsIHRoYXQncwpmaW5lIGJ5IG1lLiBIb3dldmVyIHlvdSB3b24ndCBiZSBhYmxlIHRv IHRlc3QgaXQgd2l0aG91dCBoYWNraW5nIHRoZQpDQ1UgZHJpdmVyLgoKQWZ0ZXIgZGVzY3JpYmlu ZyB0aGlzLCBpdCBzZWVtcyB0aGF0IHdoZW4gd2UgZ2V0IHRvIGRvaW5nIHRoZSBjbGsgcGFyZW50 CnJld29yaywgd2UnbGwgYmUgaW4gYSBiYWQgc2l0dWF0aW9uIGlmIHdlIGRvbid0IGdldCBydGMg Y2hhbmdlcyBpbiBiZWZvcmUKdGhlIENDVSBjaGFuZ2VzLgoKPiAgICBUaGUgZHJpdmVyIHdvdWxk IGlnbm9yZSB0aGUgIm9zYzI0TS1kYyIsICJvc2MyNE0tbSIgaW5wdXQgY2xvY2tzLiBPciBwZXJo YXBzCj4gICAgaXQgY291bGQganVzdCBzdXBwb3J0IGEgY2FzZSB3aGVyZSBvbmx5IG9uZSBvZiB0 aGVzZSBhcmUgdXNlZCBhbmQgbWFrZSBpdCB0aGUKPiAgICBvbmx5IHBhcmVudCBvZiB0aGUgSE9T QyBjbG9jaz8KClRoZXkgc2hvdWxkIGp1c3QgYmUgRENYTyBhbmQgWE8sIGJhc2VkIG9uIHRoZSBk aWFncmFtLiBUaGUgbmFtZXMgYXJlIGxvY2FsCnRvIHRoZSBSVEMsIHNvIHRoZXkgZG9uJ3QgbmVl ZCB0byBiZSBnbG9iYWxseSB1bmlxdWUuIFdoYXRldmVyIG1hdGNoZXMgdGhlCmRhdGFzaGVldCBp cyBiZXN0LgoKPiAgICBIT1NDIGRlZmF1bHQgc291cmNlIHNlbGVjdGlvbiBpcyBkb25lIGJhc2Vk IG9uIGV4dGVybmFsIFBBRCBzZXR1cCwgYW5kCj4gICAgdGhlcmUncyBubyBuZWVkIGZvciBydW50 aW1lIGFjY2Vzcy9zZWxlY3Rpb24gb2YgSE9TQyBzb3VyY2UgYXQgdGhlIG1vbWVudC4KCklzIGl0 IGV2ZW4gcG9zc2libGUgdG8gY2hhbmdlIGl0PwoKPiA0KSBJbiB0aGUgZnV0dXJlIHRoZSBSVEMg ZHJpdmVyIHdvdWxkIGJlIGV4dGVuZGVkIHRvIHN1cHBvcnQgbW9yZSByZWZpbmVkCj4gICAgc2V0 dXAvbXV4aW5nL3J1bnRpbWUgc2VsZWN0aW9uIG9mIG9zYzI0TS1kYy9vc2MyNE0tbS4gUFJDTSBk cml2ZXIgd291bGQKPiAgICBwcm92aWRlIHRoZSBvc2MyNE0tbSBjbG9jaywgdG8gYmUgYWJsZSBm b3Iga2VybmVsIHRvIGtub3cgaG93IHRvIGdhdGUgaXQuCj4KPiBUaGUgYm9hcmQncyBEVFNJIHdv dWxkIGhhdmUgdG8gbGluayBlaXRoZXIgIm9zYzI0TS1kYyIsICJvc2MyNE0tbSIgdG8gbm9kZXMK PiBkZXNjcmliaW5nIGFuIGV4dGVybmFsIGNyeXN0YWwgKG9yIHRvIFBSQ00gY2xvY2sgaW4gdGhl IGZ1dHVyZSkuIEl0J3MgYSBib2FyZHMKPiBjaG9pY2UgIG9uIHdoYXQgY3J5c3RhbHMgYXJlIGFj dHVhbGx5IHVzZWQuIDMgY29uZmlncyBhcmUgcG9zc2libGUgLSB3aXRoIG9uZSBvcgo+IHR3byBj cnlzdGFscywgY29ubmVjdGVkIHRvIGVpdGhlciBvbmUgb2YgWElOL1hPVVQgWDI0TUlOL1gyNE1P VVQgcGlucyBvciBib3RoLgoKQUZBSUssIG9zYzI0TS1kYyB3b3VsZCBsaW5rIGRpcmVjdGx5IHRv IHRoZSBleHRlcm5hbCBjcnlzdGFsLCB3aGlsZSBvc2MyNE0tbQp3b3VsZCBsaW5rIHRvIHRoZSBl eHRlcm5hbCBjcnlzdGFsIGZpcnN0LCB0aGVuIFBSQ00gaWYgaXQgZ2V0cyBpbXBsZW1lbnRlZC4K Cj4gV291bGQgdGhhdCB3b3JrPwo+Cj4gRFQgd291bGQgc3RpbGwgcHJvYmFibHkgbmVlZCBhIHJl LXdvcmsgaW4gdGhlIGZ1dHVyZSwgaWYgdGhlIFBSQ00gY2xvY2sKPiBtb2RlbGluZyB0aGUgZ2F0 ZSB3b3VsZCBiZSBuZWVkZWQuCgpZZWFoLiBXZSdsbCBkZWFsIHdpdGggdGhhdCB3aGVuIHdlIGdl dCB0byBpdC4KCgpUbyBzdW1tYXJpemUsIHRoZSBnb2FsIGlzIHRvIGdldCB0aGUgRFQgcmlnaHQg dGhlIGZpcnN0IHRpbWUuCgpSZWdhcmRzCkNoZW5ZdQoKCj4gcmVnYXJkcywKPiAgIG8uCj4KPiA+ IFdlIGp1c3Qgd2FudCB0aGUgRFQgdG8gZGVzY3JpYmUgd2hhdCBpcyBhY3R1YWxseSB0aGVyZS4g Rm9yIHRoZSBYTyBpbnB1dCwKPiA+IHlvdSBjb3VsZCBqdXN0IGRpcmVjdGx5IHJlZmVyZW5jZSB0 aGUgZXh0ZXJuYWwgY3J5c3RhbCBub2RlLiBUaGUgZ2F0ZSBmb3IKPiA+IGl0IGlzIGxpa2VseSBz b21ld2hlcmUgaW4gdGhlIFBSQ00gYmxvY2ssIHdoaWNoIHdlIGRvbid0IGhhdmUgZG9jcyBmb3Iu Cj4gPgo+ID4gPiBUaGVyZSdzIGEgc21hbGwgZGV0YWlsIGhlcmUsIHRoYXQncyBub3QgZGVzY3Jp YmVkIGFic29sdXRlbHkgY29ycmVjdGx5IGluCj4gPiA+IERUU0ksIGJ1dCB0aGUgZGlmZmVyZW5j ZSBpcyBub3QgcmVhbGx5IHRoYXQgbWF0ZXJpYWwuIGV4dF9vc2MzMmsgaXMKPiA+ID4gb3JpZ2lu YWxseSBtb2RlbGxlZCBhcyBhIGZpeGVkIGNsb2NrIHRoYXQgZmVlZHMgaW50byBSVEMgbW9kdWxl LCBidXQgaW4KPiA+ID4gcmVhbGl0eSBpdCdzIHRoZSBSVEMgbW9kdWxlIHRoYXQgaW1wbGVtZW50 cyB2aWEgaXRzIHJlZ2lzdGVycyBlbmFibGluZyBhbmQKPiA+ID4gZGlzYWJsaW5nIG9mIHRoaXMg b3NjaWxsYXRvci9jbG9jay4KPiA+ID4KPiA+ID4gVGhvdWdoOgo+ID4gPiAtIHRoZXJlJ3Mgbm8g b3RoZXIgcG9zc2libGUgdXNlciBvZiBleHRfb3NjMzJrIHRoYW4gUlRDIG1vZHVsZQo+ID4gPiAt IHRoZXJlJ3Mgbm8gb3RoZXIgcG9zc2libGUgZXh0ZXJuYWwgY29uZmlndXJhdGlvbiBmb3IgdGhl IGNyeXN0YWwKPiA+ID4gICBjaXJjdWl0IHRoYXQgd291bGQgbmVlZCB0byBiZSBoYW5kbGVkIGlu IHRoZSBkdHMgcGVyIGJvYXJkCj4gPiA+Cj4gPiA+IFNvIEkgZ3Vlc3MsIHdoaWxlIHRoZSBkZXNj cmlwdGlvbiBpcyBub3QgcGVyZmVjdCwgdGhpcyBwYXRjaCBzZXJpZXMgc3RpbGwKPiA+ID4gaW1w cm92ZXMgdGhlIGN1cnJlbnQgc2l0dWF0aW9uLiBPciBtYXliZSBJJ20gbWlzdW5kZXJzdGFuZGlu ZyBzb21ldGhpbmcsCj4gPiA+IGFuZCAmZXh0X29zYzMyayBub2RlIGp1c3QgZGVzY3JpYmVzIGEg ZmFjdCB0aGF0IHRoZXJlJ3MgYSBjcnlzdGFsIG9uCj4gPiA+IHRoZSBib2FyZC4gVGhlbiwgZXZl cnl0aGluZyBpcyBwZXJoYXBzIGZpbmUuIDopCj4gPgo+ID4gQ29ycmVjdC4gVGhlIGV4dGVybmFs IGNsb2NrIG5vZGVzIGFyZSBtb2RlbGluZyB0aGUgY3J5c3RhbCwgbm90IHRoZSBpbnRlcm5hbAo+ ID4gY2xvY2sgZ2F0ZSAvIGRpc3RyaWJ1dG9yLgo+ID4KPiA+IFdlcmUgdGhlIHZlbmRvciB0byBu b3QgaW5jbHVkZSB0aGUgY3J5c3RhbCAoZm9yIHdoYXRldmVyIHJlYXNvbnMpLCB0aGUgRFQKPiA+ IHNob3VsZCBiZSBhYmxlIHRvIGRlc2NyaWJlIGl0IHZpYSB0aGUgYWJzZW5jZSBvZiB0aGUgY2xv Y2sgaW5wdXQsIGFuZCB0aGUKPiA+IGRyaXZlciBzaG91bGQgY29ycmVjdGx5IHVzZSB0aGUgaW50 ZXJuYWwgKGluYWNjdXJhdGUpIG9zY2lsbGF0b3IuIEkgcmVhbGl6ZQo+ID4gdGhlIGNsb2NrcyBw cm9wZXJ0eSBpcyByZXF1aXJlZCwgYW5kIHRoZSBkcml2ZXIgZG9lc24ndCBoYW5kbGUgdGhpcyBj YXNlCj4gPiBlaXRoZXIsIHNvIHdlIG1pZ2h0IGhhdmUgdG8gZml4IHRoYXQgaWYgaXQgd2VyZSB0 byBhcHBlYXIgaW4gdGhlIHdpbGQuCj4gPgo+ID4gPiBGb3Igbm93LCB0aGUgZW5hYmxlIGJpdCBm b3IgdGhpcyBvc2NpbGxhdG9yIGlzIHRvZ2dsZWQgYnkgdGhlIHJlLXBhcmVudGluZwo+ID4gPiBj b2RlIGF1dG9tYXRpY2FsbHksIGFzIG5lZWRlZC4KPiA+Cj4gPiBUaGF0J3MgZmluZS4gTm8gbmVl ZCB0byBpbmNyZWFzZSB0aGUgY2xvY2sgdHJlZSBkZXB0aC4KPiA+Cj4gPiBDaGVuWXUKPiA+Cj4g PiA+IFRoaXMgcGF0Y2hzZXQgaXMgbmVjZXNzYXJ5IGZvciBpbXBsZW1lbnRpbmcgdGhlIFdpRmkv Qmx1ZXRvb3RoIHN1cHBvcnQKPiA+ID4gb24gYm9hcmRzIHVzaW5nIEg2IFNvQy4KPiA+ID4KPiA+ ID4gUGxlYXNlIHRha2UgYSBsb29rLgo+ID4gPgo+ID4gPiBUaGFuayB5b3UgYW5kIHJlZ2FyZHMs Cj4gPiA+ICAgT25kcmVqIEppcm1hbgo+ID4gPgo+ID4gPiBPbmRyZWogSmlybWFuICgzKToKPiA+ ID4gICBkdC1iaW5kaW5nczogQWRkIGNvbXBhdGlibGUgZm9yIEg2IFJUQwo+ID4gPiAgIHJ0Yzog c3VuNmk6IEFkZCBzdXBwb3J0IGZvciBINiBSVEMKPiA+ID4gICBhcm02NDogZHRzOiBzdW41MGkt aDY6IEFkZCBzdXBwb3J0IGZvciBSVEMgYW5kIGZpeCB0aGUgY2xvY2sgdHJlZQo+ID4gPgo+ID4g PiAgLi4uL2RldmljZXRyZWUvYmluZGluZ3MvcnRjL3N1bjZpLXJ0Yy50eHQgICAgIHwgIDEgKwo+ ID4gPiAgYXJjaC9hcm02NC9ib290L2R0cy9hbGx3aW5uZXIvc3VuNTBpLWg2LmR0c2kgIHwgMzAg KysrKysrKy0tLS0tLS0KPiA+ID4gIGRyaXZlcnMvcnRjL3J0Yy1zdW42aS5jICAgICAgICAgICAg ICAgICAgICAgICB8IDQwICsrKysrKysrKysrKysrKysrKy0KPiA+ID4gIDMgZmlsZXMgY2hhbmdl ZCwgNTUgaW5zZXJ0aW9ucygrKSwgMTYgZGVsZXRpb25zKC0pCj4gPiA+Cj4gPiA+IC0tCj4gPiA+ IDIuMjEuMAo+ID4gPgo+ID4gPiAtLQo+ID4gPiBZb3UgcmVjZWl2ZWQgdGhpcyBtZXNzYWdlIGJl Y2F1c2UgeW91IGFyZSBzdWJzY3JpYmVkIHRvIHRoZSBHb29nbGUgR3JvdXBzICJsaW51eC1zdW54 aSIgZ3JvdXAuCj4gPiA+IFRvIHVuc3Vic2NyaWJlIGZyb20gdGhpcyBncm91cCBhbmQgc3RvcCBy ZWNlaXZpbmcgZW1haWxzIGZyb20gaXQsIHNlbmQgYW4gZW1haWwgdG8gbGludXgtc3VueGkrdW5z dWJzY3JpYmVAZ29vZ2xlZ3JvdXBzLmNvbS4KPiA+ID4gRm9yIG1vcmUgb3B0aW9ucywgdmlzaXQg aHR0cHM6Ly9ncm91cHMuZ29vZ2xlLmNvbS9kL29wdG91dC4KPgo+IC0tCj4gWW91IHJlY2VpdmVk IHRoaXMgbWVzc2FnZSBiZWNhdXNlIHlvdSBhcmUgc3Vic2NyaWJlZCB0byB0aGUgR29vZ2xlIEdy b3VwcyAibGludXgtc3VueGkiIGdyb3VwLgo+IFRvIHVuc3Vic2NyaWJlIGZyb20gdGhpcyBncm91 cCBhbmQgc3RvcCByZWNlaXZpbmcgZW1haWxzIGZyb20gaXQsIHNlbmQgYW4gZW1haWwgdG8gbGlu dXgtc3VueGkrdW5zdWJzY3JpYmVAZ29vZ2xlZ3JvdXBzLmNvbS4KPiBGb3IgbW9yZSBvcHRpb25z LCB2aXNpdCBodHRwczovL2dyb3Vwcy5nb29nbGUuY29tL2Qvb3B0b3V0LgoKX19fX19fX19fX19f X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX18KbGludXgtYXJtLWtlcm5lbCBtYWls aW5nIGxpc3QKbGludXgtYXJtLWtlcm5lbEBsaXN0cy5pbmZyYWRlYWQub3JnCmh0dHA6Ly9saXN0 cy5pbmZyYWRlYWQub3JnL21haWxtYW4vbGlzdGluZm8vbGludXgtYXJtLWtlcm5lbAo=