From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.7 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 438C0C433FF for ; Sat, 27 Jul 2019 14:27:42 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 2E8782087C for ; Sat, 27 Jul 2019 14:27:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728931AbfG0O1l (ORCPT ); Sat, 27 Jul 2019 10:27:41 -0400 Received: from mail-ed1-f67.google.com ([209.85.208.67]:40990 "EHLO mail-ed1-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726370AbfG0O1k (ORCPT ); Sat, 27 Jul 2019 10:27:40 -0400 Received: by mail-ed1-f67.google.com with SMTP id p15so55585610eds.8; Sat, 27 Jul 2019 07:27:39 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=P5LMz+F5HmGiI0OaPOZ+zlAMKqfMWikw1NmVc9ZxKJI=; b=eaM6N5381gjsv+FDW/SVv39i+ZFK2rBVbhukYJCJp7lnR2TFmZ4Na1Xr3RmSXieqkU z+nuOHu6I5XzTJdC/pOggcBk3kmpv2nvYDQc/MbCh2DyL4/cVLRJRa6zRnyfPsFNNKs7 II3jD3ZXhhrT+Yc49YoX9mj4GpIszsL9chPm7P0ogsIv0mERBX02apPX4I2f9vMrlFtc eEQQlQEFcrf0SO0uvWTOnYQJW9WZLYEMuNMw09Gmys8+6nu+uh/bmKcV/xDvDcUScrKy WTWqDP97CEpoPrQ2ugWEzE8G8Pq/7b2gpH6QOPQakBcQdhkfSAd6xONJKpQr6WufCvBB 52nw== X-Gm-Message-State: APjAAAUGPFH2FKoTUW8kQxTb0m0CUMKafO9maud3x5aMFXjRj0pZpv3p SQlNfwLNGPFrjly+Vf8jXKESQPHSvfo= X-Google-Smtp-Source: APXvYqyiwbh05ja7vWezLLE0TLXW6sPR33Ne0kWT6TPD6L3dwLpZBQnXkdqvaVa74bZcsSIdaSDFzA== X-Received: by 2002:a17:906:4582:: with SMTP id t2mr78017594ejq.242.1564237658044; Sat, 27 Jul 2019 07:27:38 -0700 (PDT) Received: from mail-wm1-f47.google.com (mail-wm1-f47.google.com. [209.85.128.47]) by smtp.gmail.com with ESMTPSA id e12sm14671554edb.72.2019.07.27.07.27.36 (version=TLS1_3 cipher=AEAD-AES128-GCM-SHA256 bits=128/128); Sat, 27 Jul 2019 07:27:37 -0700 (PDT) Received: by mail-wm1-f47.google.com with SMTP id a15so50208726wmj.5; Sat, 27 Jul 2019 07:27:36 -0700 (PDT) X-Received: by 2002:a7b:c051:: with SMTP id u17mr88536023wmc.25.1564237656507; Sat, 27 Jul 2019 07:27:36 -0700 (PDT) MIME-Version: 1.0 References: <20190726184045.14669-1-jernej.skrabec@siol.net> <20190726184045.14669-4-jernej.skrabec@siol.net> <20190727104628.jsdvpxvcpzru75v5@flea.home> In-Reply-To: <20190727104628.jsdvpxvcpzru75v5@flea.home> From: Chen-Yu Tsai Date: Sat, 27 Jul 2019 22:27:24 +0800 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH 3/6] pwm: sun4i: Add a quirk for bus clock To: Maxime Ripard Cc: Jernej Skrabec , Thierry Reding , Rob Herring , Mark Rutland , linux-pwm@vger.kernel.org, devicetree , linux-arm-kernel , linux-kernel , linux-sunxi Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Sat, Jul 27, 2019 at 6:46 PM Maxime Ripard wrote: > > Hi, > > On Fri, Jul 26, 2019 at 08:40:42PM +0200, Jernej Skrabec wrote: > > H6 PWM core needs bus clock to be enabled in order to work. > > > > Add a quirk for it. > > > > Signed-off-by: Jernej Skrabec > > --- > > drivers/pwm/pwm-sun4i.c | 15 +++++++++++++++ > > 1 file changed, 15 insertions(+) > > > > diff --git a/drivers/pwm/pwm-sun4i.c b/drivers/pwm/pwm-sun4i.c > > index 1b7be8fbde86..7d3ac3f2dc3f 100644 > > --- a/drivers/pwm/pwm-sun4i.c > > +++ b/drivers/pwm/pwm-sun4i.c > > @@ -72,6 +72,7 @@ static const u32 prescaler_table[] = { > > }; > > > > struct sun4i_pwm_data { > > + bool has_bus_clock; > > bool has_prescaler_bypass; > > bool has_reset; > > unsigned int npwm; > > @@ -79,6 +80,7 @@ struct sun4i_pwm_data { > > > > struct sun4i_pwm_chip { > > struct pwm_chip chip; > > + struct clk *bus_clk; > > struct clk *clk; > > struct reset_control *rst; > > void __iomem *base; > > @@ -382,6 +384,16 @@ static int sun4i_pwm_probe(struct platform_device *pdev) > > reset_control_deassert(pwm->rst); > > } > > > > + if (pwm->data->has_bus_clock) { > > + pwm->bus_clk = devm_clk_get(&pdev->dev, "bus"); > > + if (IS_ERR(pwm->bus_clk)) { > > + ret = PTR_ERR(pwm->bus_clk); > > + goto err_bus; > > + } > > + > > + clk_prepare_enable(pwm->bus_clk); > > + } > > + > > The patch itself looks fine, but you should clarify which clock is > being used by the old driver. > > My guess is that the "new" clock is actually the mod one, while the > old one was both the clock of the register interface (bus) and the > clock of the PWM generation logic (mod). The H6 datasheet explicitly states: The clock source of PWM is OSC24M. The PWM is on APB1 Bus. Ensure that open APB1 Bus gating and de-assert reset signal when accessed to the PWM. Older datasheets do not have anything about bus gating or resets. However with slightly newer ones that have a system bus tree diagram, we can see that PWM is on APB1 (or APB0/APBS for R_PWM). We can assume there is no bus gate and thus it is directly attached to APB1, and that we never modeled this part. So the new clock is definitely the bus gate. You might want to introduce a patch renaming sun4i_pwm_data.clk to sun4i_pwm_data.mod_clk before this one. ChenYu From mboxrd@z Thu Jan 1 00:00:00 1970 From: Chen-Yu Tsai Subject: Re: [PATCH 3/6] pwm: sun4i: Add a quirk for bus clock Date: Sat, 27 Jul 2019 22:27:24 +0800 Message-ID: References: <20190726184045.14669-1-jernej.skrabec@siol.net> <20190726184045.14669-4-jernej.skrabec@siol.net> <20190727104628.jsdvpxvcpzru75v5@flea.home> Reply-To: wens-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org Mime-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Return-path: Sender: linux-sunxi-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org In-Reply-To: <20190727104628.jsdvpxvcpzru75v5-YififvaboMKzQB+pC5nmwQ@public.gmane.org> List-Post: , List-Help: , List-Archive: , List-Unsubscribe: , To: Maxime Ripard Cc: Jernej Skrabec , Thierry Reding , Rob Herring , Mark Rutland , linux-pwm-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, devicetree , linux-arm-kernel , linux-kernel , linux-sunxi List-Id: devicetree@vger.kernel.org On Sat, Jul 27, 2019 at 6:46 PM Maxime Ripard wrote: > > Hi, > > On Fri, Jul 26, 2019 at 08:40:42PM +0200, Jernej Skrabec wrote: > > H6 PWM core needs bus clock to be enabled in order to work. > > > > Add a quirk for it. > > > > Signed-off-by: Jernej Skrabec > > --- > > drivers/pwm/pwm-sun4i.c | 15 +++++++++++++++ > > 1 file changed, 15 insertions(+) > > > > diff --git a/drivers/pwm/pwm-sun4i.c b/drivers/pwm/pwm-sun4i.c > > index 1b7be8fbde86..7d3ac3f2dc3f 100644 > > --- a/drivers/pwm/pwm-sun4i.c > > +++ b/drivers/pwm/pwm-sun4i.c > > @@ -72,6 +72,7 @@ static const u32 prescaler_table[] = { > > }; > > > > struct sun4i_pwm_data { > > + bool has_bus_clock; > > bool has_prescaler_bypass; > > bool has_reset; > > unsigned int npwm; > > @@ -79,6 +80,7 @@ struct sun4i_pwm_data { > > > > struct sun4i_pwm_chip { > > struct pwm_chip chip; > > + struct clk *bus_clk; > > struct clk *clk; > > struct reset_control *rst; > > void __iomem *base; > > @@ -382,6 +384,16 @@ static int sun4i_pwm_probe(struct platform_device *pdev) > > reset_control_deassert(pwm->rst); > > } > > > > + if (pwm->data->has_bus_clock) { > > + pwm->bus_clk = devm_clk_get(&pdev->dev, "bus"); > > + if (IS_ERR(pwm->bus_clk)) { > > + ret = PTR_ERR(pwm->bus_clk); > > + goto err_bus; > > + } > > + > > + clk_prepare_enable(pwm->bus_clk); > > + } > > + > > The patch itself looks fine, but you should clarify which clock is > being used by the old driver. > > My guess is that the "new" clock is actually the mod one, while the > old one was both the clock of the register interface (bus) and the > clock of the PWM generation logic (mod). The H6 datasheet explicitly states: The clock source of PWM is OSC24M. The PWM is on APB1 Bus. Ensure that open APB1 Bus gating and de-assert reset signal when accessed to the PWM. Older datasheets do not have anything about bus gating or resets. However with slightly newer ones that have a system bus tree diagram, we can see that PWM is on APB1 (or APB0/APBS for R_PWM). We can assume there is no bus gate and thus it is directly attached to APB1, and that we never modeled this part. So the new clock is definitely the bus gate. You might want to introduce a patch renaming sun4i_pwm_data.clk to sun4i_pwm_data.mod_clk before this one. ChenYu From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 32247C7618B for ; Sat, 27 Jul 2019 14:28:10 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 092B72087C for ; Sat, 27 Jul 2019 14:28:10 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="QzOcqm41" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 092B72087C Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=csie.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:To:Subject:Message-ID:Date:From: In-Reply-To:References:MIME-Version:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=Fh79j8N/7Y67YfYiogK6+jgTnVCkdTf3bwRA7aLJkVo=; b=QzOcqm41sCjsmg p0YxBXhby/GLGdZTknOL57YDLpHEEJslQFGOW8KJJR2fV0teYF4SD0ecGUgoAN99L3RgmEo66ictn bUl3uAioDd//DrDdxJ9uDdy5iqO6NIQzJl6+1u87ETF6xaSvjF4R6UmPNpiVmU3dZHMjGtzmfo25E dNqL5eVCetFk+HTF52nDApp6ccJTjxVic/Goqp0/9CUn6IExqnuth1CkiFOZF6Q8kETdXm+d1Oebb Xf1efOq22+i4AvTEKGT4Cs/MRjHVBlTVBOX5n3hMe0fLpjFJymcsHwF6a/2uS8IlzJ2TvHL8UxKd1 Fef8LiAbmksCyqJQv7Jw==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92 #3 (Red Hat Linux)) id 1hrNg8-00088t-1I; Sat, 27 Jul 2019 14:28:08 +0000 Received: from mail-ed1-f68.google.com ([209.85.208.68]) by bombadil.infradead.org with esmtps (Exim 4.92 #3 (Red Hat Linux)) id 1hrNfi-00081K-Jl for linux-arm-kernel@lists.infradead.org; Sat, 27 Jul 2019 14:27:48 +0000 Received: by mail-ed1-f68.google.com with SMTP id x19so49692077eda.12 for ; Sat, 27 Jul 2019 07:27:39 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=P5LMz+F5HmGiI0OaPOZ+zlAMKqfMWikw1NmVc9ZxKJI=; b=ID/om/Yc87DaIq2QvBdoOR3t4nC9m84oZbo+BnrBTArDUVT4LTnoQGYWRM9sW9cqzq +amvf9LG3pBtyv9EJ6eP1/GG5b3i2BOmteRJoY4uqhsmf4J1q0YdraXyPq23IIQFFNOh U/BVkyybg2yIfunCpakPQojyu7sJRQxBlMc/OZwhUuds5CevMzF09L9WNfDCgzTNuCkU DWySmlTdJ2+D4r6eQ8iS9R0B/2lYXFypCABSfQcP4apCejOK88Hd3CBubmHk58nHmWBC 3P2uK0fzOI2nudrLezR9eUPwLAHM8ceJuPVH1murZXBF2acrJfMD46ir/EDNI2R9wwiG TZmg== X-Gm-Message-State: APjAAAUn1XlZCrZwjBY+lINzyzYm0myR6Qu0W0BIzVt4IIrXinVmJfgp /DLIii1/wzqz/wcvwmznNSe2+M3cOoU= X-Google-Smtp-Source: APXvYqwdS01ckzMUQjiZ5ZWeih1h3/SZxGu9CAhvneUxpGTNZmy7yxD8wJc5OazpY0bAI/nFGc7PXQ== X-Received: by 2002:a50:fd0c:: with SMTP id i12mr90479499eds.55.1564237658001; Sat, 27 Jul 2019 07:27:38 -0700 (PDT) Received: from mail-wm1-f45.google.com (mail-wm1-f45.google.com. [209.85.128.45]) by smtp.gmail.com with ESMTPSA id c53sm14961492ede.84.2019.07.27.07.27.36 for (version=TLS1_3 cipher=AEAD-AES128-GCM-SHA256 bits=128/128); Sat, 27 Jul 2019 07:27:36 -0700 (PDT) Received: by mail-wm1-f45.google.com with SMTP id a15so50208722wmj.5 for ; Sat, 27 Jul 2019 07:27:36 -0700 (PDT) X-Received: by 2002:a7b:c051:: with SMTP id u17mr88536023wmc.25.1564237656507; Sat, 27 Jul 2019 07:27:36 -0700 (PDT) MIME-Version: 1.0 References: <20190726184045.14669-1-jernej.skrabec@siol.net> <20190726184045.14669-4-jernej.skrabec@siol.net> <20190727104628.jsdvpxvcpzru75v5@flea.home> In-Reply-To: <20190727104628.jsdvpxvcpzru75v5@flea.home> From: Chen-Yu Tsai Date: Sat, 27 Jul 2019 22:27:24 +0800 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH 3/6] pwm: sun4i: Add a quirk for bus clock To: Maxime Ripard X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190727_072743_926870_F3D18D3F X-CRM114-Status: GOOD ( 21.95 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , linux-pwm@vger.kernel.org, Jernej Skrabec , devicetree , linux-kernel , Rob Herring , linux-sunxi , Thierry Reding , linux-arm-kernel Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Sat, Jul 27, 2019 at 6:46 PM Maxime Ripard wrote: > > Hi, > > On Fri, Jul 26, 2019 at 08:40:42PM +0200, Jernej Skrabec wrote: > > H6 PWM core needs bus clock to be enabled in order to work. > > > > Add a quirk for it. > > > > Signed-off-by: Jernej Skrabec > > --- > > drivers/pwm/pwm-sun4i.c | 15 +++++++++++++++ > > 1 file changed, 15 insertions(+) > > > > diff --git a/drivers/pwm/pwm-sun4i.c b/drivers/pwm/pwm-sun4i.c > > index 1b7be8fbde86..7d3ac3f2dc3f 100644 > > --- a/drivers/pwm/pwm-sun4i.c > > +++ b/drivers/pwm/pwm-sun4i.c > > @@ -72,6 +72,7 @@ static const u32 prescaler_table[] = { > > }; > > > > struct sun4i_pwm_data { > > + bool has_bus_clock; > > bool has_prescaler_bypass; > > bool has_reset; > > unsigned int npwm; > > @@ -79,6 +80,7 @@ struct sun4i_pwm_data { > > > > struct sun4i_pwm_chip { > > struct pwm_chip chip; > > + struct clk *bus_clk; > > struct clk *clk; > > struct reset_control *rst; > > void __iomem *base; > > @@ -382,6 +384,16 @@ static int sun4i_pwm_probe(struct platform_device *pdev) > > reset_control_deassert(pwm->rst); > > } > > > > + if (pwm->data->has_bus_clock) { > > + pwm->bus_clk = devm_clk_get(&pdev->dev, "bus"); > > + if (IS_ERR(pwm->bus_clk)) { > > + ret = PTR_ERR(pwm->bus_clk); > > + goto err_bus; > > + } > > + > > + clk_prepare_enable(pwm->bus_clk); > > + } > > + > > The patch itself looks fine, but you should clarify which clock is > being used by the old driver. > > My guess is that the "new" clock is actually the mod one, while the > old one was both the clock of the register interface (bus) and the > clock of the PWM generation logic (mod). The H6 datasheet explicitly states: The clock source of PWM is OSC24M. The PWM is on APB1 Bus. Ensure that open APB1 Bus gating and de-assert reset signal when accessed to the PWM. Older datasheets do not have anything about bus gating or resets. However with slightly newer ones that have a system bus tree diagram, we can see that PWM is on APB1 (or APB0/APBS for R_PWM). We can assume there is no bus gate and thus it is directly attached to APB1, and that we never modeled this part. So the new clock is definitely the bus gate. You might want to introduce a patch renaming sun4i_pwm_data.clk to sun4i_pwm_data.mod_clk before this one. ChenYu _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel