use "ham1" instead "ham1" 1-bit Hamming ecc code "bch4" 4-bit BCH ecc code "bch8" 8-bit BCH ecc code "bch16" 16-bit BCH ECC code Refer below "How to select correct ECC scheme for your device ?" It seems as if this method would be equally applicable to Tegra NAND. Best regards, Benjamin --000000000000ec0670056ceec4ef Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable

Hi Stefan (and all),

First off, I apoloigize in advance if I'm deviating from common= kernel mailing list courtesy -- this is my first time responding. I just h= ave a comment on the NAND driver that I'd like to bring to the public.<= /span>

> +=C2=A0 =C2=A0 =C2=A0 =C2=A0switch (mtd->oobsize) = {
> ...=C2=A0

> +=C2= =A0 =C2=A0 =C2=A0 =C2=A0case 224:
> +=C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0mtd_set_ooblayout(mtd, = &tegra_nand_oob_224_ops);
> +=C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0chip->ecc.strength =3D 8= ;
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0chip->ecc.bytes =3D 18;
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0value |=3D= CFG_ECC_SEL | CFG_TVAL_8;
> +=C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0break;=C2=A0+=C2=A0 =C2=A0 =C2=A0 =C2=A0case 224:

I am not sure how you arrived a= t this oobsize-based inference. I have not seen any explicit relation betwe= en oob size and ECC algorithm used in the reference manual. Indeed, the U-B= oot I was working on (a fork of the Toradex 2015= .04=C2=A0U-Boot) always has oobsize =3D=3D 224 but used either BCH[t= =3D16] or RS[t=3D4]. In fact, we tried choosing RS[t=3D8] in U-Boot but we = failed to make the BootROM decode this at all. So we had to use RS[t=3D4]. = But changing the algorithm did not automatically change the oobsize, at lea= st it didn't for us. So maybe you should consider if this is really the= way to go about deciding which algorithm is used.

Note that we're in fact using this patch set in Linux today, but = we had to remove the oobsize inference part. Currently we're simply har= d coding it to CFG_TVAL_4, but=C2=A0maybe it would be cleaner to add ECC algo as a board config instead, e.g. = in the .dts file or whatever. This seems to be done by other vendors alread= y, see for example excerpt of=C2=A0= Documentation/devicetree/bindings/mtd/gpmc-nand.txt below:

=C2=A0- ti,nand-ecc-opt:= A string setting the ECC layout to use. One of:

<= span style=3D"font-size:12.8px"> &q= uot;sw" 1-bit Hamming ecc code= via software

"hw" <deprecated> use "ham1" instead

= &= quot;hw-romcode" <deprecated= > use "ham1" instead

"ham1" 1-bit Hamming ecc code

&quo= t;bch4" 4-bit BCH ecc code

"bch8" 8-bit= BCH ecc code

"bch16" 16-bit BCH ECC code

Refer below "How to s= elect correct ECC scheme for your device ?"

It seems = as if this method would be equally applicable to Tegra NAND.

Best regards,

Benjamin

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