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From: Oleksandr Suvorov <cryosay@gmail.com>
To: Michal Simek <michal.simek@xilinx.com>
Cc: Oleksandr Suvorov <oleksandr.suvorov@foundries.io>,
	 U-Boot Mailing List <u-boot@lists.denx.de>,
	Adrian Fiergolski <adrian.fiergolski@fastree3d.com>,
	 Jorge Ramirez-Ortiz <jorge@foundries.io>,
	Ricardo Salveti <ricardo@foundries.io>,
	 Igor Opaniuk <igor.opaniuk@foundries.io>,
	Michal Simek <michal.simek@amd.com>
Subject: Re: [PATCH v9 03/13] fpga: xilinx: add bitstream flags to driver desc
Date: Tue, 7 Jun 2022 14:37:09 +0300	[thread overview]
Message-ID: <CAGgjyvFRZA4FJV_vpL3R5A+F65F7wettOgPwQcK-u+CsNR4Y0g@mail.gmail.com> (raw)
In-Reply-To: <7bc55ab5-fe4b-56c8-0c02-9320d8b0a64f@xilinx.com>

Hi Michal,

On Tue, Jun 7, 2022 at 2:32 PM Michal Simek <michal.simek@xilinx.com> wrote:
>
>
>
> On 6/1/22 10:46, Oleksandr Suvorov wrote:
> > Store a set of supported bitstream types in xilinx_desc structure.
> > It will be used to determine whether an FPGA image is able to be
> > loaded with a given driver.
> >
> > Signed-off-by: Oleksandr Suvorov <oleksandr.suvorov@foundries.io>
> > ---
> >
> > (no changes since v1)
> >
> >   include/versalpl.h | 2 +-
> >   include/xilinx.h   | 5 +++++
> >   include/zynqmppl.h | 2 +-
> >   3 files changed, 7 insertions(+), 2 deletions(-)
> >
> > diff --git a/include/versalpl.h b/include/versalpl.h
> > index b94c82e6e66..26f04a2f649 100644
> > --- a/include/versalpl.h
> > +++ b/include/versalpl.h
> > @@ -15,6 +15,6 @@
> >   extern struct xilinx_fpga_op versal_op;
> >
> >   #define XILINX_VERSAL_DESC \
> > -{ xilinx_versal, csu_dma, 1, &versal_op, 0, &versal_op }
> > +{ xilinx_versal, csu_dma, 1, &versal_op, 0, &versal_op, NULL, FPGA_LEGACY }
> >
> >   #endif /* _VERSALPL_H_ */
> > diff --git a/include/xilinx.h b/include/xilinx.h
> > index 362943bc717..91179abe31f 100644
> > --- a/include/xilinx.h
> > +++ b/include/xilinx.h
> > @@ -37,6 +37,9 @@ typedef enum {                      /* typedef xilinx_family */
> >       max_xilinx_type         /* insert all new types before this */
> >   } xilinx_family;            /* end, typedef xilinx_family */
> >
> > +/* FPGA bitstream supported types */
> > +#define FPGA_LEGACY                  BIT(0)
> > +
> >   typedef struct {            /* typedef xilinx_desc */
> >       xilinx_family family;   /* part type */
> >       xilinx_iface iface;     /* interface type */
> > @@ -45,6 +48,7 @@ typedef struct {            /* typedef xilinx_desc */
> >       int cookie;             /* implementation specific cookie */
> >       struct xilinx_fpga_op *operations; /* operations */
> >       char *name;             /* device name in bitstream */
> > +     int flags;              /* compatible flags */
> >   } xilinx_desc;                      /* end, typedef xilinx_desc */
> >
> >   struct xilinx_fpga_op {
> > @@ -56,6 +60,7 @@ struct xilinx_fpga_op {
> >                    struct fpga_secure_info *fpga_sec_info);
> >       int (*dump)(xilinx_desc *desc, const void *buf, size_t bsize);
> >       int (*info)(xilinx_desc *desc);
> > +     int (*str2flag)(xilinx_desc *desc, const char *string);
>
> This should be in 4/13.
>
> M

Thanks, Michal! Agree. I'll post the fixed patchset after receiving
the testing feedback from Ricardo and Adrian.

-- 
Best regards
Oleksandr

Oleksandr Suvorov
cryosay@gmail.com

  reply	other threads:[~2022-06-07 11:37 UTC|newest]

Thread overview: 26+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-06-01  8:46 [PATCH v9 00/13] fpga: zynqmp: Adding support of loading authenticated images Oleksandr Suvorov
2022-06-01  8:46 ` [PATCH v9 01/13] fpga: add option for loading FPGA secure bitstreams Oleksandr Suvorov
2022-06-01  8:46   ` [PATCH v9 02/13] fpga: xilinx: add missed identifier names Oleksandr Suvorov
2022-06-01  8:46     ` [PATCH v9 03/13] fpga: xilinx: add bitstream flags to driver desc Oleksandr Suvorov
2022-06-01  8:46       ` [PATCH v9 04/13] fpga: zynqmp: add str2flags call Oleksandr Suvorov
2022-06-01  8:46         ` [PATCH v9 05/13] fpga: add fpga_compatible2flag Oleksandr Suvorov
2022-06-01  8:46           ` [PATCH v9 06/13] fpga: xilinx: pass compatible flags to xilinx_load() Oleksandr Suvorov
2022-06-01  8:46             ` [PATCH v9 07/13] fpga: pass compatible flags to fpga_load() Oleksandr Suvorov
2022-06-01  8:46               ` [PATCH v9 08/13] spl: fit: pass real " Oleksandr Suvorov
2022-06-01  8:46                 ` [PATCH v9 09/13] fpga: xilinx: pass compatible flags to load() callback Oleksandr Suvorov
2022-06-01  8:46                   ` [PATCH v9 10/13] fpga: zynqmp: optimize zynqmppl_load() code Oleksandr Suvorov
2022-06-01  8:46                     ` [PATCH v9 11/13] fpga: zynqmp: add bitstream compatible checking Oleksandr Suvorov
2022-06-01  8:46                       ` [PATCH v9 12/13] fpga: zynqmp: support loading authenticated images Oleksandr Suvorov
2022-06-01  8:46                         ` [PATCH v9 13/13] fpga: zynqmp: support loading encrypted bitfiles Oleksandr Suvorov
2022-06-07 12:44                         ` [PATCH v9 12/13] fpga: zynqmp: support loading authenticated images Michal Simek
2022-06-07 12:14                 ` [PATCH v9 08/13] spl: fit: pass real compatible flags to fpga_load() Michal Simek
2022-06-07 12:11           ` [PATCH v9 05/13] fpga: add fpga_compatible2flag Michal Simek
2022-06-07 13:14             ` Oleksandr Suvorov
2022-06-07 11:31       ` [PATCH v9 03/13] fpga: xilinx: add bitstream flags to driver desc Michal Simek
2022-06-07 11:37         ` Oleksandr Suvorov [this message]
2022-06-07 12:46           ` Michal Simek
2022-06-07 13:03             ` Oleksandr Suvorov
2022-06-07 11:54       ` Michal Simek
2022-06-02 15:11 ` [PATCH v9 00/13] fpga: zynqmp: Adding support of loading authenticated images Oleksandr Suvorov
2022-06-07 13:01   ` Adrian Fiergolski
2022-06-07 13:11     ` Oleksandr Suvorov

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