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Sun, 21 Nov 2021 20:14:41 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=rfried.dev@gmail.com Received: by mail-oi1-x236.google.com with SMTP id n66so33391169oia.9 for ; Sun, 21 Nov 2021 11:14:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=20Z8D317qzKsVFpPI4Pmatgilu5MXDze/8F5S746loM=; b=gYXOOh2KNc2wxILUnOw0+nRshAF5vMlcxy8N6rJbz/7njBBGSikKl8ei3Uyp8D/8f3 ifpUMnR/5qs8Wy7/ON1ktgLmRxJaakXP5SMZC/F+CbZscImW5oFo5xLr+BqOo0lZ75A0 4kIeyB7AgF7RVTSBu588KRFsnKk4L+4LSeWG1sXxfPkQLySXzIU+5u33qHlLJs/87XoZ cLbFrexIh5NZZ4lbx64W8Xfrb//V5vqaGujKC2buLPJN6jCjWSBS+NqlIOemCxG1lU7q RfDw7O+Okp6iw2z73M4bkYCR8Cc0ZZCwCNJgaxiGho/3qLVXGHE67Dporg5uTIen9u5F mcdw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=20Z8D317qzKsVFpPI4Pmatgilu5MXDze/8F5S746loM=; b=speNIHj7e3GVI9QzfIV+inw5B+8Hjbx4Pcma0hs2vXqPoySy+/0oPxbeRXvZUyNyxk b80iHjTo1ql+xoMk2g1pDUc0mEe1UqMu5xZyLXDncPnv41PWcklIq3AwJE2w7Sfv3kdd 1JHYsA+ko/wWcj/Ctauqxcph6lwi3a1EljmSGIEMTn/9Zw1hO8pt8uHskSUiPz0nd6D5 K9a6+OIuLI8X++9lHIwIg0y9RWnIgxp4uGLmB73WZXDdvFyl2v6DlygcaGTfEFoF5OtC 2/ruzsfe4MB261JfYdtsa9+rFDp8NQCqrIEs3H65xs3GxTm7azqnsCTD0ysQcubWSF33 MzhQ== X-Gm-Message-State: AOAM5320qmhdHftM48PlKXxZ3v4cv0nhYNlSI7HdEYqF2Q4Xa7PHZTQl 1PPmMlDUtyMx5NnSBULR5G+UaiQD0BgvdB45AL+SQSUsoFc= X-Google-Smtp-Source: ABdhPJymtXRIb5Rwj/7rs0GJ0FiCe2DTMnF1VmOd0SKRXFacNVZQ2+vOzwJDtcWz2j5g3R6o5oIvEoR4DMc1gnQCAFk= X-Received: by 2002:a05:6808:bc3:: with SMTP id o3mr15845996oik.151.1637522080086; Sun, 21 Nov 2021 11:14:40 -0800 (PST) MIME-Version: 1.0 References: <880f4d18b3927801577d3c2e4eec128bf3830706.1637285375.git.weijie.gao@mediatek.com> In-Reply-To: <880f4d18b3927801577d3c2e4eec128bf3830706.1637285375.git.weijie.gao@mediatek.com> From: Ramon Fried Date: Sun, 21 Nov 2021 21:14:29 +0200 Message-ID: Subject: Re: [PATCH v2 13/14] net: mediatek: add support for MediaTek MT7621 SoC To: Weijie Gao Cc: U-Boot Mailing List , GSS_MTK_Uboot_upstream , Joe Hershberger Content-Type: text/plain; charset="UTF-8" X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.37 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean On Fri, Nov 19, 2021 at 3:37 AM Weijie Gao wrote: > > This patch adds GMAC support for MediaTek MT7621 SoC. > MT7621 has the same GMAC/Switch configuration as MT7623. > > Signed-off-by: Weijie Gao > --- > v2 changes: none > --- > drivers/net/mtk_eth.c | 27 +++++++++++++++++++++------ > drivers/net/mtk_eth.h | 8 ++++++++ > 2 files changed, 29 insertions(+), 6 deletions(-) > > diff --git a/drivers/net/mtk_eth.c b/drivers/net/mtk_eth.c > index 26f02847a2..3b42c99c2a 100644 > --- a/drivers/net/mtk_eth.c > +++ b/drivers/net/mtk_eth.c > @@ -145,7 +145,8 @@ enum mtk_switch { > enum mtk_soc { > SOC_MT7623, > SOC_MT7629, > - SOC_MT7622 > + SOC_MT7622, > + SOC_MT7621 > }; > > struct mtk_eth_priv { > @@ -669,12 +670,18 @@ static int mt7530_pad_clk_setup(struct mtk_eth_priv *priv, int mode) > static int mt7530_setup(struct mtk_eth_priv *priv) > { > u16 phy_addr, phy_val; > - u32 val; > + u32 val, txdrv; > int i; > > - /* Select 250MHz clk for RGMII mode */ > - mtk_ethsys_rmw(priv, ETHSYS_CLKCFG0_REG, > - ETHSYS_TRGMII_CLK_SEL362_5, 0); > + if (priv->soc != SOC_MT7621) { > + /* Select 250MHz clk for RGMII mode */ > + mtk_ethsys_rmw(priv, ETHSYS_CLKCFG0_REG, > + ETHSYS_TRGMII_CLK_SEL362_5, 0); > + > + txdrv = 8; > + } else { > + txdrv = 4; > + } > > /* Modify HWTRAP first to allow direct access to internal PHYs */ > mt753x_reg_read(priv, HWTRAP_REG, &val); > @@ -732,7 +739,8 @@ static int mt7530_setup(struct mtk_eth_priv *priv) > /* Lower Tx Driving for TRGMII path */ > for (i = 0 ; i < NUM_TRGMII_CTRL ; i++) > mt753x_reg_write(priv, MT7530_TRGMII_TD_ODT(i), > - (8 << TD_DM_DRVP_S) | (8 << TD_DM_DRVN_S)); > + (txdrv << TD_DM_DRVP_S) | > + (txdrv << TD_DM_DRVN_S)); > > for (i = 0 ; i < NUM_TRGMII_CTRL; i++) > mt753x_reg_rmw(priv, MT7530_TRGMII_RD(i), RD_TAP_M, 16); > @@ -1437,6 +1445,12 @@ static int mtk_eth_of_to_plat(struct udevice *dev) > return -ENODEV; > } > > + if (priv->soc == SOC_MT7621) { > + /* ioremap is needed for MIPS platform */ For MIPS ? you need to io map for every platform, some platform just works without it. > + priv->ethsys_base = > + ioremap_nocache((phys_addr_t)priv->ethsys_base, 0x100); > + } > + > /* Reset controllers */ > ret = reset_get_by_name(dev, "fe", &priv->rst_fe); > if (ret) { > @@ -1542,6 +1556,7 @@ static const struct udevice_id mtk_eth_ids[] = { > { .compatible = "mediatek,mt7629-eth", .data = SOC_MT7629 }, > { .compatible = "mediatek,mt7623-eth", .data = SOC_MT7623 }, > { .compatible = "mediatek,mt7622-eth", .data = SOC_MT7622 }, > + { .compatible = "mediatek,mt7621-eth", .data = SOC_MT7621 }, > {} > }; > > diff --git a/drivers/net/mtk_eth.h b/drivers/net/mtk_eth.h > index 057ecfaabf..4a8c66c671 100644 > --- a/drivers/net/mtk_eth.h > +++ b/drivers/net/mtk_eth.h > @@ -412,4 +412,12 @@ > #define PHY_POWER_SAVING_M 0x300 > #define PHY_POWER_SAVING_TX 0x0 > > +#ifndef CONFIG_SYS_NONCACHED_MEMORY > +/* > + * noncached_alloc is provided only for ARM. Add a prototype here for other > + * platforms to suppress compilation warning. > + */ > +phys_addr_t noncached_alloc(size_t size, size_t align); That's not the place for that. I assume that it fails on MIPS, please create a patch for MIPS arch. > +#endif > + > #endif /* _MTK_ETH_H_ */ > -- > 2.17.1 >