From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id CEB9BC48BC2 for ; Sun, 27 Jun 2021 20:01:46 +0000 (UTC) Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 4331E61919 for ; Sun, 27 Jun 2021 20:01:46 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 4331E61919 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id B632D82C7D; Sun, 27 Jun 2021 22:01:44 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="JU7U+1YA"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 80A7482C7E; Sun, 27 Jun 2021 22:01:43 +0200 (CEST) Received: from mail-oi1-x22a.google.com (mail-oi1-x22a.google.com [IPv6:2607:f8b0:4864:20::22a]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id C9AB282C6F for ; Sun, 27 Jun 2021 22:01:39 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=rfried.dev@gmail.com Received: by mail-oi1-x22a.google.com with SMTP id o6so4562375oic.9 for ; Sun, 27 Jun 2021 13:01:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=/gDAH1NHFYhIm6kLniASJ6W/aKhJpTJsX0Hs0HHRTEk=; b=JU7U+1YADxjeiTTiktyDI6YYW5LIy6yKoZXQDpZXvRynhNVMtnLlogtnaw6ZQhRSYG 44/hDtr+9nl5DVfVHgpKFGNCcnLRkMx+rl0fkBtx2QkPCASHpeQ1O5ErfFQsQ7lBDcCT S4SQ/0Fl+16h+VDKmYtpY4gE9gV+0Inuv3oy3NxyJHG0UjuW9a+YVzwZptKP/ZM60VI/ SCaACtEsmXNs1HFYm1cH34fjdlUoEIj0LMjMVI8WlbqkF34XafFhZFB8ettSV4DdKjPC Ykqr+ocyOCbqAqDnp6owaciQozZugjlczqph6mTrQ3hc91e/E+OTbXNXqzNni7BzMyt5 d+Ug== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=/gDAH1NHFYhIm6kLniASJ6W/aKhJpTJsX0Hs0HHRTEk=; b=syESUuTndNX1DdJZEvGi7Q2rG6XiGnhSTxVmAZOMfxCekCjZZ2sD3E//o4P6U3v5q7 che8x9syrwHeBX8MoUCzROm3xd02X+sBVrt/4FZC5Wcf6if3QT9LUMf5XNS6GMDk2pNG jLe9ebvzHUoVdHTYczbKdzFrcZu/KhD4dTLr/McRRqqIpHQZDUm/it4n8cRIxjd1t06N 932TZiA493jyeVniOfyA5im56j/okkC0a3DACy5q3XI1pxVs2AOHebJkShPeNvYKDe7D FggtBLLEWLPRGPGTg81TN1KlilDRRhpBtGnT2W23hyvrRj/Ln58y9QJUq9taNS3/nhOv GG/Q== X-Gm-Message-State: AOAM532lln3syKN4iLH/BF6dSpHnNhmA2sTzMhj6+VcXv0eStUu+pHTW rBt0db5ObqeakwPsvl8xBvzFbF4EdFHh3E4DjYI= X-Google-Smtp-Source: ABdhPJzaugi+rE4lrwi/pLsqjInON2lGmHxhtvnkPW6r5LoTBoXhr81otvcylRzOpboe1N21KXXc7A1Ti3ihuPG8ABw= X-Received: by 2002:a05:6808:1301:: with SMTP id y1mr18630338oiv.92.1624824098645; Sun, 27 Jun 2021 13:01:38 -0700 (PDT) MIME-Version: 1.0 References: <20210624063441.24072-1-ashok.reddy.soma@xilinx.com> <20210624063441.24072-3-ashok.reddy.soma@xilinx.com> In-Reply-To: <20210624063441.24072-3-ashok.reddy.soma@xilinx.com> From: Ramon Fried Date: Sun, 27 Jun 2021 23:01:27 +0300 Message-ID: Subject: Re: [PATCH 2/2] net: xilinx: axi_emac: Add support for 10G/25G AXI ethernet To: Ashok Reddy Soma Cc: U-Boot Mailing List , Joe Hershberger , Michal Simek , git , somaashokreddy@gmail.com, Alessandro Temil Content-Type: text/plain; charset="UTF-8" X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean On Thu, Jun 24, 2021 at 9:35 AM Ashok Reddy Soma wrote: > > Add support for 10G/25G (XXV) high speed ethernet. This Makes use of > the exiting AXI DMA, similar to 1G. > > Signed-off-by: Alessandro Temil > Signed-off-by: Ashok Reddy Soma > --- > > drivers/net/xilinx_axi_emac.c | 162 +++++++++++++++++++++++++--------- > 1 file changed, 118 insertions(+), 44 deletions(-) > > diff --git a/drivers/net/xilinx_axi_emac.c b/drivers/net/xilinx_axi_emac.c > index cfc6082475..2ec76d0f52 100644 > --- a/drivers/net/xilinx_axi_emac.c > +++ b/drivers/net/xilinx_axi_emac.c > @@ -1,5 +1,6 @@ > // SPDX-License-Identifier: GPL-2.0+ > /* > + * Copyright (C) 2021 Waymo LLC > * Copyright (C) 2011 Michal Simek > * Copyright (C) 2011 PetaLogix > * Copyright (C) 2010 Xilinx, Inc. All rights reserved. > @@ -73,9 +74,22 @@ DECLARE_GLOBAL_DATA_PTR; > #define XAXIDMA_BD_CTRL_TXSOF_MASK 0x08000000 /* First tx packet */ > #define XAXIDMA_BD_CTRL_TXEOF_MASK 0x04000000 /* Last tx packet */ > > -#define DMAALIGN 128 > +/* Bitmasks for XXV Ethernet MAC */ > +#define XXV_TC_TX_MASK 0x00000001 > +#define XXV_TC_FCS_MASK 0x00000002 > +#define XXV_RCW1_RX_MASK 0x00000001 > +#define XXV_RCW1_FCS_MASK 0x00000002 > + > +#define DMAALIGN 128 > +#define XXV_MIN_PKT_SIZE 60 > > static u8 rxframe[PKTSIZE_ALIGN] __attribute((aligned(DMAALIGN))); > +static u8 txminframe[XXV_MIN_PKT_SIZE] __attribute((aligned(DMAALIGN))); > + > +enum emac_variant { > + EMAC_1G = 0, > + EMAC_10G_25G = 1, > +}; > > /* Reflect dma offsets */ > struct axidma_reg { > @@ -95,6 +109,7 @@ struct axidma_plat { > int phyaddr; > u8 eth_hasnobuf; > int phy_of_handle; > + enum emac_variant mactype; > }; > > /* Private driver structures */ > @@ -108,6 +123,7 @@ struct axidma_priv { > struct mii_dev *bus; > u8 eth_hasnobuf; > int phy_of_handle; > + enum emac_variant mactype; > }; > > /* BD descriptors */ > @@ -154,6 +170,14 @@ struct axi_regs { > u32 uaw1; /* 0x704: Unicast address word 1 */ > }; > > +struct xxv_axi_regs { > + u32 gt_reset; /* 0x0 */ > + u32 reserved[2]; > + u32 tc; /* 0xC: Tx Configuration */ > + u32 reserved2; > + u32 rcw1; /* 0x14: Rx Configuration Word 1 */ > +}; > + > /* Use MII register 1 (MII status register) to detect PHY */ > #define PHY_DETECT_REG 1 > > @@ -385,6 +409,18 @@ static void axiemac_stop(struct udevice *dev) > debug("axiemac: Halted\n"); > } > > +static int xxv_axi_ethernet_init(struct axidma_priv *priv) > +{ > + struct xxv_axi_regs *regs = (struct xxv_axi_regs *)priv->iobase; > + > + writel(readl(®s->rcw1) | XXV_RCW1_FCS_MASK, ®s->rcw1); > + writel(readl(®s->tc) | XXV_TC_FCS_MASK, ®s->tc); > + writel(readl(®s->tc) | XXV_TC_TX_MASK, ®s->tc); > + writel(readl(®s->rcw1) | XXV_RCW1_RX_MASK, ®s->rcw1); > + > + return 0; > +} > + > static int axi_ethernet_init(struct axidma_priv *priv) > { > struct axi_regs *regs = priv->iobase; > @@ -440,6 +476,9 @@ static int axiemac_write_hwaddr(struct udevice *dev) > struct axidma_priv *priv = dev_get_priv(dev); > struct axi_regs *regs = priv->iobase; > > + if (priv->mactype != EMAC_1G) > + return 0; > + > /* Set the MAC address */ > int val = ((pdata->enetaddr[3] << 24) | (pdata->enetaddr[2] << 16) | > (pdata->enetaddr[1] << 8) | (pdata->enetaddr[0])); > @@ -477,7 +516,6 @@ static void axi_dma_init(struct axidma_priv *priv) > static int axiemac_start(struct udevice *dev) > { > struct axidma_priv *priv = dev_get_priv(dev); > - struct axi_regs *regs = priv->iobase; > u32 temp; > > debug("axiemac: Init started\n"); > @@ -490,8 +528,13 @@ static int axiemac_start(struct udevice *dev) > axi_dma_init(priv); > > /* Initialize AxiEthernet hardware. */ > - if (axi_ethernet_init(priv)) > - return -1; > + if (priv->mactype == EMAC_1G) { > + if (axi_ethernet_init(priv)) > + return -1; > + } else { > + if (xxv_axi_ethernet_init(priv)) > + return -1; > + } > > /* Disable all RX interrupts before RxBD space setup */ > temp = readl(&priv->dmarx->control); > @@ -525,15 +568,25 @@ static int axiemac_start(struct udevice *dev) > /* Rx BD is ready - start */ > axienet_dma_write(&rx_bd, &priv->dmarx->tail); > > - /* Enable TX */ > - writel(XAE_TC_TX_MASK, ®s->tc); > - /* Enable RX */ > - writel(XAE_RCW1_RX_MASK, ®s->rcw1); > + if (priv->mactype == EMAC_1G) { > + struct axi_regs *regs = priv->iobase; > + /* Enable TX */ > + writel(XAE_TC_TX_MASK, ®s->tc); > + /* Enable RX */ > + writel(XAE_RCW1_RX_MASK, ®s->rcw1); > + > + /* PHY setup */ > + if (!setup_phy(dev)) { > + axiemac_stop(dev); > + return -1; > + } > + } else { > + struct xxv_axi_regs *regs = (struct xxv_axi_regs *)priv->iobase; > + /* Enable TX */ > + writel(readl(®s->tc) | XXV_TC_TX_MASK, ®s->tc); > > - /* PHY setup */ > - if (!setup_phy(dev)) { > - axiemac_stop(dev); > - return -1; > + /* Enable RX */ > + writel(readl(®s->rcw1) | XXV_RCW1_RX_MASK, ®s->rcw1); > } > > debug("axiemac: Init complete\n"); > @@ -548,6 +601,14 @@ static int axiemac_send(struct udevice *dev, void *ptr, int len) > if (len > PKTSIZE_ALIGN) > len = PKTSIZE_ALIGN; > > + /* If size is less than min packet size, pad to min size */ > + if (priv->mactype == EMAC_10G_25G && len < XXV_MIN_PKT_SIZE) { > + memset(txminframe, 0, XXV_MIN_PKT_SIZE); > + memcpy(txminframe, ptr, len); > + len = XXV_MIN_PKT_SIZE; > + ptr = txminframe; > + } > + > /* Flush packet to main memory to be trasfered by DMA */ > flush_cache((phys_addr_t)ptr, len); > > @@ -632,7 +693,7 @@ static int axiemac_recv(struct udevice *dev, int flags, uchar **packetp) > temp = readl(&priv->dmarx->control); > temp &= ~XAXIDMA_IRQ_ALL_MASK; > writel(temp, &priv->dmarx->control); > - if (!priv->eth_hasnobuf) > + if (!priv->eth_hasnobuf && priv->mactype == EMAC_1G) > length = rx_bd.app4 & 0xFFFF; /* max length mask */ > else > length = rx_bd.status & XAXIDMA_BD_STS_ACTUAL_LEN_MASK; > @@ -709,21 +770,25 @@ static int axi_emac_probe(struct udevice *dev) > priv->dmatx = plat->dmatx; > /* RX channel offset is 0x30 */ > priv->dmarx = (struct axidma_reg *)((phys_addr_t)priv->dmatx + 0x30); > - priv->eth_hasnobuf = plat->eth_hasnobuf; > - priv->phyaddr = plat->phyaddr; > - priv->phy_of_handle = plat->phy_of_handle; > - priv->interface = pdata->phy_interface; > + priv->mactype = plat->mactype; > + > + if (priv->mactype == EMAC_1G) { > + priv->eth_hasnobuf = plat->eth_hasnobuf; > + priv->phyaddr = plat->phyaddr; > + priv->phy_of_handle = plat->phy_of_handle; > + priv->interface = pdata->phy_interface; > > - priv->bus = mdio_alloc(); > - priv->bus->read = axiemac_miiphy_read; > - priv->bus->write = axiemac_miiphy_write; > - priv->bus->priv = priv; > + priv->bus = mdio_alloc(); > + priv->bus->read = axiemac_miiphy_read; > + priv->bus->write = axiemac_miiphy_write; > + priv->bus->priv = priv; > > - ret = mdio_register_seq(priv->bus, dev_seq(dev)); > - if (ret) > - return ret; > + ret = mdio_register_seq(priv->bus, dev_seq(dev)); > + if (ret) > + return ret; > > - axiemac_phy_init(dev); > + axiemac_phy_init(dev); > + } > > return 0; > } > @@ -732,9 +797,11 @@ static int axi_emac_remove(struct udevice *dev) > { > struct axidma_priv *priv = dev_get_priv(dev); > > - free(priv->phydev); > - mdio_unregister(priv->bus); > - mdio_free(priv->bus); > + if (priv->mactype == EMAC_1G) { > + free(priv->phydev); > + mdio_unregister(priv->bus); > + mdio_free(priv->bus); > + } > > return 0; > } > @@ -757,6 +824,7 @@ static int axi_emac_of_to_plat(struct udevice *dev) > const char *phy_mode; > > pdata->iobase = dev_read_addr(dev); > + plat->mactype = dev_get_driver_data(dev); > > offset = fdtdec_lookup_phandle(gd->fdt_blob, node, > "axistream-connected"); > @@ -771,24 +839,29 @@ static int axi_emac_of_to_plat(struct udevice *dev) > return -EINVAL; > } > > - plat->phyaddr = -1; > + if (plat->mactype == EMAC_1G) { > + plat->phyaddr = -1; > > - offset = fdtdec_lookup_phandle(gd->fdt_blob, node, "phy-handle"); > - if (offset > 0) { > - plat->phyaddr = fdtdec_get_int(gd->fdt_blob, offset, "reg", -1); > - plat->phy_of_handle = offset; > - } > + offset = fdtdec_lookup_phandle(gd->fdt_blob, node, > + "phy-handle"); > + if (offset > 0) { > + plat->phyaddr = fdtdec_get_int(gd->fdt_blob, offset, > + "reg", -1); > + plat->phy_of_handle = offset; > + } > > - phy_mode = fdt_getprop(gd->fdt_blob, node, "phy-mode", NULL); > - if (phy_mode) > - pdata->phy_interface = phy_get_interface_by_name(phy_mode); > - if (pdata->phy_interface == -1) { > - printf("%s: Invalid PHY interface '%s'\n", __func__, phy_mode); > - return -EINVAL; > - } > + phy_mode = fdt_getprop(gd->fdt_blob, node, "phy-mode", NULL); > + if (phy_mode) > + pdata->phy_interface = phy_get_interface_by_name(phy_mode); > + if (pdata->phy_interface == -1) { > + printf("%s: Invalid PHY interface '%s'\n", __func__, > + phy_mode); > + return -EINVAL; > + } > > - plat->eth_hasnobuf = fdtdec_get_bool(gd->fdt_blob, node, > - "xlnx,eth-hasnobuf"); > + plat->eth_hasnobuf = fdtdec_get_bool(gd->fdt_blob, node, > + "xlnx,eth-hasnobuf"); > + } > > printf("AXI EMAC: %lx, phyaddr %d, interface %s\n", (ulong)pdata->iobase, > plat->phyaddr, phy_string_for_interface(pdata->phy_interface)); > @@ -797,7 +870,8 @@ static int axi_emac_of_to_plat(struct udevice *dev) > } > > static const struct udevice_id axi_emac_ids[] = { > - { .compatible = "xlnx,axi-ethernet-1.00.a" }, > + { .compatible = "xlnx,axi-ethernet-1.00.a", .data = (uintptr_t)EMAC_1G }, > + { .compatible = "xlnx,xxv-ethernet-1.0", .data = (uintptr_t)EMAC_10G_25G }, > { } > }; > > -- > 2.17.1 > Reviewed-by: Ramon Fried