From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752550AbbHaDhF (ORCPT ); Sun, 30 Aug 2015 23:37:05 -0400 Received: from mail-oi0-f65.google.com ([209.85.218.65]:33181 "EHLO mail-oi0-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752276AbbHaDhC (ORCPT ); Sun, 30 Aug 2015 23:37:02 -0400 MIME-Version: 1.0 In-Reply-To: References: <1438831173-8761-1-git-send-email-punnaia@xilinx.com> Date: Mon, 31 Aug 2015 09:07:00 +0530 X-Google-Sender-Auth: Arh9LOQCEQ9-Q0DpETvfX-DbwoQ Message-ID: Subject: Re: [PATCH v4 1/2] Documentation: dt: Add Xilinx zynqmp dma device tree binding documentation From: punnaiah choudary kalluri To: Rob Herring Cc: Punnaiah Choudary Kalluri , Rob Herring , Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala , Michal Simek , Vinod Koul , Dan Williams , "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" , Punnaiah Choudary , dmaengine@vger.kernel.org, "linux-arm-kernel@lists.infradead.org" Content-Type: text/plain; charset=UTF-8 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, Aug 25, 2015 at 12:16 PM, punnaiah choudary kalluri wrote: > Hi Rob, > > On Tue, Aug 25, 2015 at 12:23 AM, Rob Herring wrote: >> On Wed, Aug 5, 2015 at 10:19 PM, Punnaiah Choudary Kalluri >> wrote: >>> Device-tree binding documentation for Xilinx zynqmp dma engine used in >>> Zynq UltraScale+ MPSoC. >>> >>> Signed-off-by: Punnaiah Choudary Kalluri >>> --- >>> Changes in v4: >>> - None >>> Changes in v3: >>> - None >>> Changes in v2: >>> - None >>> --- >>> .../devicetree/bindings/dma/xilinx/zynqmp_dma.txt | 61 ++++++++++++++++++++ >>> 1 files changed, 61 insertions(+), 0 deletions(-) >>> create mode 100644 Documentation/devicetree/bindings/dma/xilinx/zynqmp_dma.txt >>> >>> diff --git a/Documentation/devicetree/bindings/dma/xilinx/zynqmp_dma.txt b/Documentation/devicetree/bindings/dma/xilinx/zynqmp_dma.txt >>> new file mode 100644 >>> index 0000000..e4f92b9 >>> --- /dev/null >>> +++ b/Documentation/devicetree/bindings/dma/xilinx/zynqmp_dma.txt >>> @@ -0,0 +1,61 @@ >>> +Xilinx ZynqMP DMA engine, it does support memory to memory transfers, >>> +memory to device and device to memory transfers. It also has flow >>> +control and rate control support for slave/peripheral dma access. >>> + >>> +Required properties: >>> +- compatible: Should be "xlnx,zynqmp-dma-1.0" >>> +- #dma-cells: Should be <1>, a single cell holding a line request number >>> +- reg: Memory map for module access >>> +- interrupt-parent: Interrupt controller the interrupt is routed through >>> +- interrupts: Should contain DMA channel interrupt >>> +- xlnx,bus-width: AXI buswidth in bits. Should contain 128 or 64 >>> + >>> +Optional properties: >>> +- xlnx,include-sg: Indicates the controller to operate in simple or scatter >>> + gather dma mode >>> +- xlnx,ratectrl: Scheduling interval in terms of clock cycles for >>> + source AXI transaction >>> +- xlnx,overfetch: Tells whether the channel is allowed to over fetch the data >>> +- xlnx,src-issue: Number of AXI outstanding transactions on source side >>> +- xlnx,desc-axi-cohrnt: Tells whether the AXI transactions generated for the >>> + descriptor read are marked Non-coherent >>> +- xlnx,src-axi-cohrnt: Tells whether the AXI transactions generated for the >>> + source descriptor payload are marked Non-coherent >>> +- xlnx,dst-axi-cohrnt: Tells whether the AXI transactions generated for the >>> + dst descriptor payload are marked Non-coherent >> >> Do you really need 3? dma-coherent property doesn't work for you? >> >> Not that it should dictate the binding, but the kernel doesn't support >> a device needing both coherent and non-coherent DMA ops. > > I will get back to you shortly on this Yes. dma-coherent property works. I will modify the bindings. Thanks, Punnaiah > >> >>> +- xlnx,desc-axi-qos: AXI QOS bits to be used for descriptor fetch >>> +- xlnx,src-axi-qos: AXI QOS bits to be used for data read >>> +- xlnx,dst-axi-qos: AXI QOS bits to be used for data write >>> +- xlnx,desc-axi-cache: AXI cache bits to be used for descriptor fetch. >>> +- xlnx,desc-axi-cache: AXI cache bits to be used for data read >>> +- xlnx,desc-axi-cache: AXI cache bits to be used for data write >> >> These signals are generally part of the coherent or not setting. This >> allows for potentially invalid combinations. >> >> Plus you have a copy/paste error. > > I will fix this. > > Thanks, > Punnaiah >> >>> +- xlnx,src-burst-len: AXI length for data read. Support only power of 2 values >>> + i.e 1,2,4,8 and 16 >>> +- xlnx,dst-burst-len: AXI length for data write. Support only power of 2 values >>> + i.e 1,2,4,8 and 16 >>> + >>> +Example: >>> +++++++++ >>> +fpd_dma_chan1: dma@FD500000 { >>> + compatible = "xlnx,zynqmp-dma-1.0"; >>> + reg = <0x0 0xFD500000 0x1000>; >>> + #dma_cells = <1>; >>> + interrupt-parent = <&gic>; >>> + interrupts = <0 117 4>; >>> + xlnx,bus-width = <128>; >>> + xlnx,include-sg; >>> + xlnx,overfetch; >>> + xlnx,ratectrl = <0>; >>> + xlnx,src-issue = <16>; >>> + xlnx,desc-axi-cohrnt; >>> + xlnx,src-axi-cohrnt; >>> + xlnx,dst-axi-cohrnt; >>> + xlnx,desc-axi-qos = <0>; >>> + xlnx,desc-axi-cache = <0>; >>> + xlnx,src-axi-qos = <0>; >>> + xlnx,src-axi-cache = <2>; >>> + xlnx,dst-axi-qos = <0>; >>> + xlnx,dst-axi-cache = <2>; >>> + xlnx,src-burst-len = <4>; >>> + xlnx,dst-burst-len = <4>; >>> +}; >>> -- >>> 1.7.4 >>> >>> >>> _______________________________________________ >>> linux-arm-kernel mailing list >>> linux-arm-kernel@lists.infradead.org >>> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel From mboxrd@z Thu Jan 1 00:00:00 1970 From: punnaiah choudary kalluri Subject: Re: [PATCH v4 1/2] Documentation: dt: Add Xilinx zynqmp dma device tree binding documentation Date: Mon, 31 Aug 2015 09:07:00 +0530 Message-ID: References: <1438831173-8761-1-git-send-email-punnaia@xilinx.com> Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Return-path: In-Reply-To: Sender: devicetree-owner-u79uwXL29TY76Z2rM5mHXA@public.gmane.org To: Rob Herring Cc: Punnaiah Choudary Kalluri , Rob Herring , Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala , Michal Simek , Vinod Koul , Dan Williams , "devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org" , "linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org" , Punnaiah Choudary , dmaengine-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, "linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org" List-Id: devicetree@vger.kernel.org On Tue, Aug 25, 2015 at 12:16 PM, punnaiah choudary kalluri wrote: > Hi Rob, > > On Tue, Aug 25, 2015 at 12:23 AM, Rob Herring wrote: >> On Wed, Aug 5, 2015 at 10:19 PM, Punnaiah Choudary Kalluri >> wrote: >>> Device-tree binding documentation for Xilinx zynqmp dma engine used in >>> Zynq UltraScale+ MPSoC. >>> >>> Signed-off-by: Punnaiah Choudary Kalluri >>> --- >>> Changes in v4: >>> - None >>> Changes in v3: >>> - None >>> Changes in v2: >>> - None >>> --- >>> .../devicetree/bindings/dma/xilinx/zynqmp_dma.txt | 61 ++++++++++++++++++++ >>> 1 files changed, 61 insertions(+), 0 deletions(-) >>> create mode 100644 Documentation/devicetree/bindings/dma/xilinx/zynqmp_dma.txt >>> >>> diff --git a/Documentation/devicetree/bindings/dma/xilinx/zynqmp_dma.txt b/Documentation/devicetree/bindings/dma/xilinx/zynqmp_dma.txt >>> new file mode 100644 >>> index 0000000..e4f92b9 >>> --- /dev/null >>> +++ b/Documentation/devicetree/bindings/dma/xilinx/zynqmp_dma.txt >>> @@ -0,0 +1,61 @@ >>> +Xilinx ZynqMP DMA engine, it does support memory to memory transfers, >>> +memory to device and device to memory transfers. It also has flow >>> +control and rate control support for slave/peripheral dma access. >>> + >>> +Required properties: >>> +- compatible: Should be "xlnx,zynqmp-dma-1.0" >>> +- #dma-cells: Should be <1>, a single cell holding a line request number >>> +- reg: Memory map for module access >>> +- interrupt-parent: Interrupt controller the interrupt is routed through >>> +- interrupts: Should contain DMA channel interrupt >>> +- xlnx,bus-width: AXI buswidth in bits. Should contain 128 or 64 >>> + >>> +Optional properties: >>> +- xlnx,include-sg: Indicates the controller to operate in simple or scatter >>> + gather dma mode >>> +- xlnx,ratectrl: Scheduling interval in terms of clock cycles for >>> + source AXI transaction >>> +- xlnx,overfetch: Tells whether the channel is allowed to over fetch the data >>> +- xlnx,src-issue: Number of AXI outstanding transactions on source side >>> +- xlnx,desc-axi-cohrnt: Tells whether the AXI transactions generated for the >>> + descriptor read are marked Non-coherent >>> +- xlnx,src-axi-cohrnt: Tells whether the AXI transactions generated for the >>> + source descriptor payload are marked Non-coherent >>> +- xlnx,dst-axi-cohrnt: Tells whether the AXI transactions generated for the >>> + dst descriptor payload are marked Non-coherent >> >> Do you really need 3? dma-coherent property doesn't work for you? >> >> Not that it should dictate the binding, but the kernel doesn't support >> a device needing both coherent and non-coherent DMA ops. > > I will get back to you shortly on this Yes. dma-coherent property works. I will modify the bindings. Thanks, Punnaiah > >> >>> +- xlnx,desc-axi-qos: AXI QOS bits to be used for descriptor fetch >>> +- xlnx,src-axi-qos: AXI QOS bits to be used for data read >>> +- xlnx,dst-axi-qos: AXI QOS bits to be used for data write >>> +- xlnx,desc-axi-cache: AXI cache bits to be used for descriptor fetch. >>> +- xlnx,desc-axi-cache: AXI cache bits to be used for data read >>> +- xlnx,desc-axi-cache: AXI cache bits to be used for data write >> >> These signals are generally part of the coherent or not setting. This >> allows for potentially invalid combinations. >> >> Plus you have a copy/paste error. > > I will fix this. > > Thanks, > Punnaiah >> >>> +- xlnx,src-burst-len: AXI length for data read. Support only power of 2 values >>> + i.e 1,2,4,8 and 16 >>> +- xlnx,dst-burst-len: AXI length for data write. Support only power of 2 values >>> + i.e 1,2,4,8 and 16 >>> + >>> +Example: >>> +++++++++ >>> +fpd_dma_chan1: dma@FD500000 { >>> + compatible = "xlnx,zynqmp-dma-1.0"; >>> + reg = <0x0 0xFD500000 0x1000>; >>> + #dma_cells = <1>; >>> + interrupt-parent = <&gic>; >>> + interrupts = <0 117 4>; >>> + xlnx,bus-width = <128>; >>> + xlnx,include-sg; >>> + xlnx,overfetch; >>> + xlnx,ratectrl = <0>; >>> + xlnx,src-issue = <16>; >>> + xlnx,desc-axi-cohrnt; >>> + xlnx,src-axi-cohrnt; >>> + xlnx,dst-axi-cohrnt; >>> + xlnx,desc-axi-qos = <0>; >>> + xlnx,desc-axi-cache = <0>; >>> + xlnx,src-axi-qos = <0>; >>> + xlnx,src-axi-cache = <2>; >>> + xlnx,dst-axi-qos = <0>; >>> + xlnx,dst-axi-cache = <2>; >>> + xlnx,src-burst-len = <4>; >>> + xlnx,dst-burst-len = <4>; >>> +}; >>> -- >>> 1.7.4 >>> >>> >>> _______________________________________________ >>> linux-arm-kernel mailing list >>> linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org >>> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html From mboxrd@z Thu Jan 1 00:00:00 1970 From: punnaia@xilinx.com (punnaiah choudary kalluri) Date: Mon, 31 Aug 2015 09:07:00 +0530 Subject: [PATCH v4 1/2] Documentation: dt: Add Xilinx zynqmp dma device tree binding documentation In-Reply-To: References: <1438831173-8761-1-git-send-email-punnaia@xilinx.com> Message-ID: To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On Tue, Aug 25, 2015 at 12:16 PM, punnaiah choudary kalluri wrote: > Hi Rob, > > On Tue, Aug 25, 2015 at 12:23 AM, Rob Herring wrote: >> On Wed, Aug 5, 2015 at 10:19 PM, Punnaiah Choudary Kalluri >> wrote: >>> Device-tree binding documentation for Xilinx zynqmp dma engine used in >>> Zynq UltraScale+ MPSoC. >>> >>> Signed-off-by: Punnaiah Choudary Kalluri >>> --- >>> Changes in v4: >>> - None >>> Changes in v3: >>> - None >>> Changes in v2: >>> - None >>> --- >>> .../devicetree/bindings/dma/xilinx/zynqmp_dma.txt | 61 ++++++++++++++++++++ >>> 1 files changed, 61 insertions(+), 0 deletions(-) >>> create mode 100644 Documentation/devicetree/bindings/dma/xilinx/zynqmp_dma.txt >>> >>> diff --git a/Documentation/devicetree/bindings/dma/xilinx/zynqmp_dma.txt b/Documentation/devicetree/bindings/dma/xilinx/zynqmp_dma.txt >>> new file mode 100644 >>> index 0000000..e4f92b9 >>> --- /dev/null >>> +++ b/Documentation/devicetree/bindings/dma/xilinx/zynqmp_dma.txt >>> @@ -0,0 +1,61 @@ >>> +Xilinx ZynqMP DMA engine, it does support memory to memory transfers, >>> +memory to device and device to memory transfers. It also has flow >>> +control and rate control support for slave/peripheral dma access. >>> + >>> +Required properties: >>> +- compatible: Should be "xlnx,zynqmp-dma-1.0" >>> +- #dma-cells: Should be <1>, a single cell holding a line request number >>> +- reg: Memory map for module access >>> +- interrupt-parent: Interrupt controller the interrupt is routed through >>> +- interrupts: Should contain DMA channel interrupt >>> +- xlnx,bus-width: AXI buswidth in bits. Should contain 128 or 64 >>> + >>> +Optional properties: >>> +- xlnx,include-sg: Indicates the controller to operate in simple or scatter >>> + gather dma mode >>> +- xlnx,ratectrl: Scheduling interval in terms of clock cycles for >>> + source AXI transaction >>> +- xlnx,overfetch: Tells whether the channel is allowed to over fetch the data >>> +- xlnx,src-issue: Number of AXI outstanding transactions on source side >>> +- xlnx,desc-axi-cohrnt: Tells whether the AXI transactions generated for the >>> + descriptor read are marked Non-coherent >>> +- xlnx,src-axi-cohrnt: Tells whether the AXI transactions generated for the >>> + source descriptor payload are marked Non-coherent >>> +- xlnx,dst-axi-cohrnt: Tells whether the AXI transactions generated for the >>> + dst descriptor payload are marked Non-coherent >> >> Do you really need 3? dma-coherent property doesn't work for you? >> >> Not that it should dictate the binding, but the kernel doesn't support >> a device needing both coherent and non-coherent DMA ops. > > I will get back to you shortly on this Yes. dma-coherent property works. I will modify the bindings. Thanks, Punnaiah > >> >>> +- xlnx,desc-axi-qos: AXI QOS bits to be used for descriptor fetch >>> +- xlnx,src-axi-qos: AXI QOS bits to be used for data read >>> +- xlnx,dst-axi-qos: AXI QOS bits to be used for data write >>> +- xlnx,desc-axi-cache: AXI cache bits to be used for descriptor fetch. >>> +- xlnx,desc-axi-cache: AXI cache bits to be used for data read >>> +- xlnx,desc-axi-cache: AXI cache bits to be used for data write >> >> These signals are generally part of the coherent or not setting. This >> allows for potentially invalid combinations. >> >> Plus you have a copy/paste error. > > I will fix this. > > Thanks, > Punnaiah >> >>> +- xlnx,src-burst-len: AXI length for data read. Support only power of 2 values >>> + i.e 1,2,4,8 and 16 >>> +- xlnx,dst-burst-len: AXI length for data write. Support only power of 2 values >>> + i.e 1,2,4,8 and 16 >>> + >>> +Example: >>> +++++++++ >>> +fpd_dma_chan1: dma at FD500000 { >>> + compatible = "xlnx,zynqmp-dma-1.0"; >>> + reg = <0x0 0xFD500000 0x1000>; >>> + #dma_cells = <1>; >>> + interrupt-parent = <&gic>; >>> + interrupts = <0 117 4>; >>> + xlnx,bus-width = <128>; >>> + xlnx,include-sg; >>> + xlnx,overfetch; >>> + xlnx,ratectrl = <0>; >>> + xlnx,src-issue = <16>; >>> + xlnx,desc-axi-cohrnt; >>> + xlnx,src-axi-cohrnt; >>> + xlnx,dst-axi-cohrnt; >>> + xlnx,desc-axi-qos = <0>; >>> + xlnx,desc-axi-cache = <0>; >>> + xlnx,src-axi-qos = <0>; >>> + xlnx,src-axi-cache = <2>; >>> + xlnx,dst-axi-qos = <0>; >>> + xlnx,dst-axi-cache = <2>; >>> + xlnx,src-burst-len = <4>; >>> + xlnx,dst-burst-len = <4>; >>> +}; >>> -- >>> 1.7.4 >>> >>> >>> _______________________________________________ >>> linux-arm-kernel mailing list >>> linux-arm-kernel at lists.infradead.org >>> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel