From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-10.1 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4D4A8C433E1 for ; Fri, 21 Aug 2020 09:59:22 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 1F17D20732 for ; Fri, 21 Aug 2020 09:59:22 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1598003962; bh=6lh8v9cVemjT3jBDnziS64+IY43tdAd2MM8ArvnEnwM=; h=References:In-Reply-To:From:Date:Subject:To:Cc:List-ID:From; b=YKDTHq0w2M+2mpFG3V9vuD6GMmLVUQgPbRF+putSyTtlBDVm7/dbsguLutppvAo5+ oKHlpcEKGvFK1i+SsVb3G64l2QJQFdA1sUezXXiFvdZ295Wb6KdycfSeaY+1sTZ651 +7kp5ljG16mvbX7lu/Q6iv8LprBGT8gYuiIqMVmU= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728004AbgHUJ7V (ORCPT ); Fri, 21 Aug 2020 05:59:21 -0400 Received: from mail.kernel.org ([198.145.29.99]:50508 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727101AbgHUJ7V (ORCPT ); Fri, 21 Aug 2020 05:59:21 -0400 Received: from mail-il1-f171.google.com (mail-il1-f171.google.com [209.85.166.171]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id EE3EB207DE; Fri, 21 Aug 2020 09:59:19 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1598003960; bh=6lh8v9cVemjT3jBDnziS64+IY43tdAd2MM8ArvnEnwM=; h=References:In-Reply-To:From:Date:Subject:To:Cc:From; b=Ev1rZxl06IyNhyRTd512c7nq3kdnBRla8UaI7zrC2WUIRmGGgrMDbwH7srGmRZGH9 aKO0NgPfw7FnEVDbq7DFFz7AcQ4dWx8s4LLiI7zxxMhYHKYMf7U5zDN+b1cxahHNgp evmtydnMCZd6oTiMclBS8UdhVcGEfuaqX5AM591E= Received: by mail-il1-f171.google.com with SMTP id p18so893087ilm.7; Fri, 21 Aug 2020 02:59:19 -0700 (PDT) X-Gm-Message-State: AOAM531UlI5rGo8bExLj5oiBm7RvURW2H8WXrUA02Cgx2b8URYjIXzu/ Yz4NQSyBe5v4vmrIKp38pqQhhfYbiESbzlyCDfg= X-Google-Smtp-Source: ABdhPJziEDnmhrGq8OhVozQdRjzD6EAFpspHY6IqaLQmfT7wM+TItD6CZ20HooROnMXmdFEF8mxdFEgqxtTlvKeOEFM= X-Received: by 2002:a92:db47:: with SMTP id w7mr1978701ilq.264.1598003959218; Fri, 21 Aug 2020 02:59:19 -0700 (PDT) MIME-Version: 1.0 References: <1597739776-15944-1-git-send-email-light.hsieh@mediatek.com> <1597985231.23380.22.camel@mtkswgap22> In-Reply-To: <1597985231.23380.22.camel@mtkswgap22> From: Sean Wang Date: Fri, 21 Aug 2020 02:59:07 -0700 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH v1 1/2] pinctrl: mediatek: support access registers without race-condition To: Light Hsieh Cc: Linus Walleij , "moderated list:ARM/Mediatek SoC support" , "open list:GPIO SUBSYSTEM" , lkml , kuohong.wang@mediatek.com Content-Type: text/plain; charset="UTF-8" Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Hi Light, On Thu, Aug 20, 2020 at 9:47 PM Light Hsieh wrote: > > On Wed, 2020-08-19 at 16:11 -0700, Sean Wang wrote: > > Hi Light, > > > > On Tue, Aug 18, 2020 at 1:36 AM wrote: > > > > > > From: Light Hsieh > > > > > > Some MediaTek SOC provide more control registers other than value register. > > > > s/MT6765/Some MediaTek SoC/ > > > > > Generanll, a value register need read-modify-write is at offset 0xXXXXXXXX0. > > > > s/Generally/Generanll/ > > > > > A corresponding SET register is at offset 0xXXXXXXX4. Write 1s' to some bits > > > of SET register will set same bits in value register. > > > A corresponding CLR register is at offset 0xXXXXXXX8. Write 1s' to some bits > > > of CLR register will clear same bits in value register. > > > For GPIO mode selection, MWR register is provided at offset 0xXXXXXXXC. > > > With MWR, the MSBit of GPIO mode selection field is for modification-enable, > > > not for GPIO mode selection, and the remaining LSBits are for mode > > > selection. > > > Take mode selection field with 4-bits as example, to select mode 0~7 via > > > MWR register, 8~15 (instead of 0~7) shall be written to corresponding mode > > > selection field. > > > When using SET/CLR/MWR registers, read-modify-write of value register is not > > > necessary. This can prevent from race condition when multiple bus masters > > > concurrently read-modify-write the same value register for setting different > > > fields of the same value register. > > > > > > Signed-off-by: Light Hsieh > > > --- > > > drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c | 69 ++++++++++++++++++++++-- > > > drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h | 2 + > > > 2 files changed, 67 insertions(+), 4 deletions(-) > > > > > > diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c > > > index b77b18f..51f0b53 100644 > > > --- a/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c > > > +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c > > > @@ -18,6 +18,29 @@ > > > #include "mtk-eint.h" > > > #include "pinctrl-mtk-common-v2.h" > > > > > > +/* Some MediaTek SOC provide more control registers other than value register. > > > > s/MT6765/Some MediaTek SoC/ > > Not only MT6765 provides such control registers. > Actually, many (but not all) MediaTek SoC support. > Other MediaTek SoC can enable such control according to its HW support. > > > > > > + * Generanll, a value register need read-modify-write is at offset 0xXXXXXXXX0. > > > > s/Generally/Generanll/ > > > > > + * A corresponding SET register is at offset 0xXXXXXXX4. Write 1s' to some bits > > > + * of SET register will set same bits in value register. > > > + * A corresponding CLR register is at offset 0xXXXXXXX8. Write 1s' to some bits > > > + * of CLR register will clear same bits in value register. > > > + * For GPIO mode selection, MWR register is provided at offset 0xXXXXXXXC. > > > + * With MWR, the MSBit of GPIO mode selection field is for modification-enable, > > > + * not for GPIO mode selection, and the remaining LSBits are for mode > > > + * selection. > > > + * Take mode selection field with 4-bits as example, to select mode 0~7 via > > > + * MWR register, 8~15 (instead of 0~7) shall be written to corresponding mode > > > + * selection field. > > > + * When using SET/CLR/MWR registers, read-modify-write of value register is not > > > + * necessary. This can prevent from race condition when multiple bus masters > > > + * concurrently read-modify-write the same value register for setting different > > > + * fields of the same value register. > > > + */ > > > + > > > +#define SET_OFFSET 0x4 > > > +#define CLR_OFFSET 0x8 > > > > can set/clr offset work for mode register? > > Yes. However, use set/clr to change mode require 2 register access when > target mode is not all 0's or all 1's. DRV/TDSEL and RDSEL register might have value not all 0's or all 1's. That seems to be we still require two steps register access for such fields, right? > The mwr HW support is not available on mode register. if I understand correctly, that seems to be a typo, MWR should be only available on mode register > > > > > > +#define MWR_OFFSET 0xC > > > + > > > /** > > > * struct mtk_drive_desc - the structure that holds the information > > > * of the driving current > > > @@ -64,6 +87,38 @@ void mtk_rmw(struct mtk_pinctrl *pctl, u8 i, u32 reg, u32 mask, u32 set) > > > mtk_w32(pctl, i, reg, val); > > > } > > > > > > + > > > +static void mtk_hw_set_value_race_free(struct mtk_pinctrl *pctl, > > > + struct mtk_pin_field *pf, u32 value) > > > > s/mtk_hw_set_value_race_free/mtk_hw_w1sc/ to explictly indicate > > write-one ethier set or clear operation supported by hw > > > > > +{ > > > + unsigned int set, clr; > > > + > > > + set = value & pf->mask; > > > + clr = (~set) & pf->mask; > > > + > > > + if (set) > > > + mtk_w32(pctl, pf->index, pf->offset + SET_OFFSET, > > > + set << pf->bitpos); > > > + if (clr) > > > + mtk_w32(pctl, pf->index, pf->offset + CLR_OFFSET, > > > + clr << pf->bitpos); > > > +} > > > + > > > +static void mtk_hw_set_mode_race_free(struct mtk_pinctrl *pctl, > > > + struct mtk_pin_field *pf, u32 value) > > > > s/mtk_hw_set_mode_race_free/mtk_hw_mwr/ > > > > > +{ > > > + unsigned int value_new; > > > + > > > + /* MSB of mask is modification-enable bit, set this bit */ > > > + value_new = (1 << (pctl->soc->mwr_field_width - 1)) | value; > > > > it seems to be we can use fls(pf->mask) to replace ctl->soc->mwr_field_width > > > > pf->mask cannot be used direct. It needs conversion.For example: > pf->mask: 0x1f -> value_new = (1 << 4) | value; > pf->mask: 0xf -> value_new = (1 << 3) | value; > pf->mask: 0x7 -> value_new = (1 << 2) | value; > > The code size of perform conversion is greater than using a direct > mwr_field_width field. > using pf->mask can allow MWR supports any field that can support MWR to be generic. that would be a mess when there are more fields relying on MWR on certain SoC someday. > > > > + if (value_new == value) > > > + dev_notice(pctl->dev, > > > + "invalid mode 0x%x, use it by ignoring MSBit!\n", > > > + value); > > > + mtk_w32(pctl, pf->index, pf->offset + MWR_OFFSET, > > > + value_new << pf->bitpos); > > > +} > > > + > > > static int mtk_hw_pin_field_lookup(struct mtk_pinctrl *hw, > > > const struct mtk_pin_desc *desc, > > > int field, struct mtk_pin_field *pfd) > > > @@ -197,10 +252,16 @@ int mtk_hw_set_value(struct mtk_pinctrl *hw, const struct mtk_pin_desc *desc, > > > if (value < 0 || value > pf.mask) > > > return -EINVAL; > > > > > > - if (!pf.next) > > > - mtk_rmw(hw, pf.index, pf.offset, pf.mask << pf.bitpos, > > > - (value & pf.mask) << pf.bitpos); > > > - else > > > + if (!pf.next) { > > > + if (hw->soc->race_free_access) { > > > > let's create an extra flags caps under hw->soc and the SoC capability > > check, something like hw->soc->caps & MTK_HW_CAPS_RMW_ATOMIC to easily > > extend various things for future SoC > > > > > + if (field == PINCTRL_PIN_REG_MODE) > > > + mtk_hw_set_mode_race_free(hw, &pf, value); > > > + else > > > + mtk_hw_set_value_race_free(hw, &pf, value); > > > + } > > > > let's create a function holding that specific hardware stuff (at least > > currently it look like), something like > > > > static void mtk_hw_rmw(struct mtk_pinctrl *pctl, struct mtk_pin_field *pf) > > { > > if (pf->field == PINCTRL_PIN_REG_MODE) /* create a member field for pf */ > > mtk_hw_mwr(...); > > else > > mtk_hw_w1sc(...); > > } > > > > Sine there is no member 'field' in struct mtk_pin_field, pf->field > cannot be used. > Therefore an extra function parameter is required if you want to use a > standalone function mtk_hw_rmw. Like this: > > void mtk_hw_rmw(struct mtk_pinctrl *pctl, struct mtk_pin_field *pf, > int field, u32 value) > { > if (field == PINCTRL_PIN_REG_MODE) > mtk_hw_set_mode_race_free(hw, &pf, value); > else > mtk_hw_set_value_race_free(hw, &pf, value); > } > > I wonder the necessity/efficiency of such extra intermediate function > with many function parameters. holding it in a separate function is for that operation is not generic enough for the moment. > > > > > + mtk_rmw(hw, pf.index, pf.offset, pf.mask << pf.bitpos, > > > + (value & pf.mask) << pf.bitpos); > > > + } else > > > mtk_hw_write_cross_field(hw, &pf, value); > > > > > > return 0; > > > diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h > > > index 27df087..95fb329 100644 > > > --- a/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h > > > +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h > > > @@ -203,6 +203,8 @@ struct mtk_pin_soc { > > > /* Specific parameters per SoC */ > > > u8 gpio_m; > > > bool ies_present; > > > + bool race_free_access; > > > + unsigned int mwr_field_width; > > > const char * const *base_names; > > > unsigned int nbase_names; > > > > > > -- > > > 1.8.1.1.dirty > From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-10.0 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C432FC433E1 for ; Fri, 21 Aug 2020 09:59:32 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 8544F20732 for ; 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Fri, 21 Aug 2020 09:59:19 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1598003960; bh=6lh8v9cVemjT3jBDnziS64+IY43tdAd2MM8ArvnEnwM=; h=References:In-Reply-To:From:Date:Subject:To:Cc:From; b=Ev1rZxl06IyNhyRTd512c7nq3kdnBRla8UaI7zrC2WUIRmGGgrMDbwH7srGmRZGH9 aKO0NgPfw7FnEVDbq7DFFz7AcQ4dWx8s4LLiI7zxxMhYHKYMf7U5zDN+b1cxahHNgp evmtydnMCZd6oTiMclBS8UdhVcGEfuaqX5AM591E= Received: by mail-il1-f169.google.com with SMTP id f12so896340ils.6 for ; Fri, 21 Aug 2020 02:59:19 -0700 (PDT) X-Gm-Message-State: AOAM533n862Afc/RWpIJGi0q1YD+QnCYEIi14Rs/lu2LZNV79o71KdDk e+LD+r0Xyilt/7t6pkZg/SJrb1V3niR1+N2IgzI= X-Google-Smtp-Source: ABdhPJziEDnmhrGq8OhVozQdRjzD6EAFpspHY6IqaLQmfT7wM+TItD6CZ20HooROnMXmdFEF8mxdFEgqxtTlvKeOEFM= X-Received: by 2002:a92:db47:: with SMTP id w7mr1978701ilq.264.1598003959218; Fri, 21 Aug 2020 02:59:19 -0700 (PDT) MIME-Version: 1.0 References: <1597739776-15944-1-git-send-email-light.hsieh@mediatek.com> <1597985231.23380.22.camel@mtkswgap22> In-Reply-To: <1597985231.23380.22.camel@mtkswgap22> From: Sean Wang Date: Fri, 21 Aug 2020 02:59:07 -0700 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH v1 1/2] pinctrl: mediatek: support access registers without race-condition To: Light Hsieh X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200821_055921_685763_34A4C976 X-CRM114-Status: GOOD ( 41.20 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "open list:GPIO SUBSYSTEM" , Linus Walleij , "moderated list:ARM/Mediatek SoC support" , lkml , kuohong.wang@mediatek.com Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org Hi Light, On Thu, Aug 20, 2020 at 9:47 PM Light Hsieh wrote: > > On Wed, 2020-08-19 at 16:11 -0700, Sean Wang wrote: > > Hi Light, > > > > On Tue, Aug 18, 2020 at 1:36 AM wrote: > > > > > > From: Light Hsieh > > > > > > Some MediaTek SOC provide more control registers other than value register. > > > > s/MT6765/Some MediaTek SoC/ > > > > > Generanll, a value register need read-modify-write is at offset 0xXXXXXXXX0. > > > > s/Generally/Generanll/ > > > > > A corresponding SET register is at offset 0xXXXXXXX4. Write 1s' to some bits > > > of SET register will set same bits in value register. > > > A corresponding CLR register is at offset 0xXXXXXXX8. Write 1s' to some bits > > > of CLR register will clear same bits in value register. > > > For GPIO mode selection, MWR register is provided at offset 0xXXXXXXXC. > > > With MWR, the MSBit of GPIO mode selection field is for modification-enable, > > > not for GPIO mode selection, and the remaining LSBits are for mode > > > selection. > > > Take mode selection field with 4-bits as example, to select mode 0~7 via > > > MWR register, 8~15 (instead of 0~7) shall be written to corresponding mode > > > selection field. > > > When using SET/CLR/MWR registers, read-modify-write of value register is not > > > necessary. This can prevent from race condition when multiple bus masters > > > concurrently read-modify-write the same value register for setting different > > > fields of the same value register. > > > > > > Signed-off-by: Light Hsieh > > > --- > > > drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c | 69 ++++++++++++++++++++++-- > > > drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h | 2 + > > > 2 files changed, 67 insertions(+), 4 deletions(-) > > > > > > diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c > > > index b77b18f..51f0b53 100644 > > > --- a/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c > > > +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c > > > @@ -18,6 +18,29 @@ > > > #include "mtk-eint.h" > > > #include "pinctrl-mtk-common-v2.h" > > > > > > +/* Some MediaTek SOC provide more control registers other than value register. > > > > s/MT6765/Some MediaTek SoC/ > > Not only MT6765 provides such control registers. > Actually, many (but not all) MediaTek SoC support. > Other MediaTek SoC can enable such control according to its HW support. > > > > > > + * Generanll, a value register need read-modify-write is at offset 0xXXXXXXXX0. > > > > s/Generally/Generanll/ > > > > > + * A corresponding SET register is at offset 0xXXXXXXX4. Write 1s' to some bits > > > + * of SET register will set same bits in value register. > > > + * A corresponding CLR register is at offset 0xXXXXXXX8. Write 1s' to some bits > > > + * of CLR register will clear same bits in value register. > > > + * For GPIO mode selection, MWR register is provided at offset 0xXXXXXXXC. > > > + * With MWR, the MSBit of GPIO mode selection field is for modification-enable, > > > + * not for GPIO mode selection, and the remaining LSBits are for mode > > > + * selection. > > > + * Take mode selection field with 4-bits as example, to select mode 0~7 via > > > + * MWR register, 8~15 (instead of 0~7) shall be written to corresponding mode > > > + * selection field. > > > + * When using SET/CLR/MWR registers, read-modify-write of value register is not > > > + * necessary. This can prevent from race condition when multiple bus masters > > > + * concurrently read-modify-write the same value register for setting different > > > + * fields of the same value register. > > > + */ > > > + > > > +#define SET_OFFSET 0x4 > > > +#define CLR_OFFSET 0x8 > > > > can set/clr offset work for mode register? > > Yes. However, use set/clr to change mode require 2 register access when > target mode is not all 0's or all 1's. DRV/TDSEL and RDSEL register might have value not all 0's or all 1's. That seems to be we still require two steps register access for such fields, right? > The mwr HW support is not available on mode register. if I understand correctly, that seems to be a typo, MWR should be only available on mode register > > > > > > +#define MWR_OFFSET 0xC > > > + > > > /** > > > * struct mtk_drive_desc - the structure that holds the information > > > * of the driving current > > > @@ -64,6 +87,38 @@ void mtk_rmw(struct mtk_pinctrl *pctl, u8 i, u32 reg, u32 mask, u32 set) > > > mtk_w32(pctl, i, reg, val); > > > } > > > > > > + > > > +static void mtk_hw_set_value_race_free(struct mtk_pinctrl *pctl, > > > + struct mtk_pin_field *pf, u32 value) > > > > s/mtk_hw_set_value_race_free/mtk_hw_w1sc/ to explictly indicate > > write-one ethier set or clear operation supported by hw > > > > > +{ > > > + unsigned int set, clr; > > > + > > > + set = value & pf->mask; > > > + clr = (~set) & pf->mask; > > > + > > > + if (set) > > > + mtk_w32(pctl, pf->index, pf->offset + SET_OFFSET, > > > + set << pf->bitpos); > > > + if (clr) > > > + mtk_w32(pctl, pf->index, pf->offset + CLR_OFFSET, > > > + clr << pf->bitpos); > > > +} > > > + > > > +static void mtk_hw_set_mode_race_free(struct mtk_pinctrl *pctl, > > > + struct mtk_pin_field *pf, u32 value) > > > > s/mtk_hw_set_mode_race_free/mtk_hw_mwr/ > > > > > +{ > > > + unsigned int value_new; > > > + > > > + /* MSB of mask is modification-enable bit, set this bit */ > > > + value_new = (1 << (pctl->soc->mwr_field_width - 1)) | value; > > > > it seems to be we can use fls(pf->mask) to replace ctl->soc->mwr_field_width > > > > pf->mask cannot be used direct. It needs conversion.For example: > pf->mask: 0x1f -> value_new = (1 << 4) | value; > pf->mask: 0xf -> value_new = (1 << 3) | value; > pf->mask: 0x7 -> value_new = (1 << 2) | value; > > The code size of perform conversion is greater than using a direct > mwr_field_width field. > using pf->mask can allow MWR supports any field that can support MWR to be generic. that would be a mess when there are more fields relying on MWR on certain SoC someday. > > > > + if (value_new == value) > > > + dev_notice(pctl->dev, > > > + "invalid mode 0x%x, use it by ignoring MSBit!\n", > > > + value); > > > + mtk_w32(pctl, pf->index, pf->offset + MWR_OFFSET, > > > + value_new << pf->bitpos); > > > +} > > > + > > > static int mtk_hw_pin_field_lookup(struct mtk_pinctrl *hw, > > > const struct mtk_pin_desc *desc, > > > int field, struct mtk_pin_field *pfd) > > > @@ -197,10 +252,16 @@ int mtk_hw_set_value(struct mtk_pinctrl *hw, const struct mtk_pin_desc *desc, > > > if (value < 0 || value > pf.mask) > > > return -EINVAL; > > > > > > - if (!pf.next) > > > - mtk_rmw(hw, pf.index, pf.offset, pf.mask << pf.bitpos, > > > - (value & pf.mask) << pf.bitpos); > > > - else > > > + if (!pf.next) { > > > + if (hw->soc->race_free_access) { > > > > let's create an extra flags caps under hw->soc and the SoC capability > > check, something like hw->soc->caps & MTK_HW_CAPS_RMW_ATOMIC to easily > > extend various things for future SoC > > > > > + if (field == PINCTRL_PIN_REG_MODE) > > > + mtk_hw_set_mode_race_free(hw, &pf, value); > > > + else > > > + mtk_hw_set_value_race_free(hw, &pf, value); > > > + } > > > > let's create a function holding that specific hardware stuff (at least > > currently it look like), something like > > > > static void mtk_hw_rmw(struct mtk_pinctrl *pctl, struct mtk_pin_field *pf) > > { > > if (pf->field == PINCTRL_PIN_REG_MODE) /* create a member field for pf */ > > mtk_hw_mwr(...); > > else > > mtk_hw_w1sc(...); > > } > > > > Sine there is no member 'field' in struct mtk_pin_field, pf->field > cannot be used. > Therefore an extra function parameter is required if you want to use a > standalone function mtk_hw_rmw. Like this: > > void mtk_hw_rmw(struct mtk_pinctrl *pctl, struct mtk_pin_field *pf, > int field, u32 value) > { > if (field == PINCTRL_PIN_REG_MODE) > mtk_hw_set_mode_race_free(hw, &pf, value); > else > mtk_hw_set_value_race_free(hw, &pf, value); > } > > I wonder the necessity/efficiency of such extra intermediate function > with many function parameters. holding it in a separate function is for that operation is not generic enough for the moment. > > > > > + mtk_rmw(hw, pf.index, pf.offset, pf.mask << pf.bitpos, > > > + (value & pf.mask) << pf.bitpos); > > > + } else > > > mtk_hw_write_cross_field(hw, &pf, value); > > > > > > return 0; > > > diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h > > > index 27df087..95fb329 100644 > > > --- a/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h > > > +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h > > > @@ -203,6 +203,8 @@ struct mtk_pin_soc { > > > /* Specific parameters per SoC */ > > > u8 gpio_m; > > > bool ies_present; > > > + bool race_free_access; > > > + unsigned int mwr_field_width; > > > const char * const *base_names; > > > unsigned int nbase_names; > > > > > > -- > > > 1.8.1.1.dirty > _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek