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* [PATCH 0/5] pinctrl/gpio: remove obsolete drivers
@ 2021-01-20 13:20 ` Arnd Bergmann
  0 siblings, 0 replies; 22+ messages in thread
From: Arnd Bergmann @ 2021-01-20 13:20 UTC (permalink / raw)
  To: linux-arm-kernel, linux-kernel, linux-gpio, Linus Walleij
  Cc: Bartosz Golaszewski, Arnd Bergmann

From: Arnd Bergmann <arnd@arndb.de>

A few Arm platforms are getting removed in v5.12, this removes
the corresponding gpio and pinctrl drivers.

Link: https://lore.kernel.org/linux-arm-kernel/20210120124812.2800027-1-arnd@kernel.org/T/

Arnd Bergmann (5):
  gpio: remove zte zx driver
  pinctrl: remove zte zx driver
  pinctrl: remove sirf atlas/prima drivers
  pinctrl: remove coh901 driver
  pinctrl: remove ste u300 driver

 .../devicetree/bindings/gpio/gpio-atlas7.txt  |   50 -
 .../bindings/gpio/gpio-stericsson-coh901.txt  |    7 -
 .../bindings/gpio/zx296702-gpio.txt           |   24 -
 .../bindings/pinctrl/pinctrl-atlas7.txt       |  109 -
 .../bindings/pinctrl/pinctrl-zx.txt           |   84 -
 drivers/gpio/Kconfig                          |    7 -
 drivers/gpio/Makefile                         |    1 -
 drivers/gpio/gpio-zx.c                        |  289 -
 drivers/pinctrl/Kconfig                       |   25 -
 drivers/pinctrl/Makefile                      |    4 -
 drivers/pinctrl/pinctrl-coh901.c              |  774 ---
 drivers/pinctrl/pinctrl-coh901.h              |    6 -
 drivers/pinctrl/pinctrl-u300.c                | 1111 ---
 drivers/pinctrl/sirf/Makefile                 |    7 -
 drivers/pinctrl/sirf/pinctrl-atlas6.c         | 1137 ---
 drivers/pinctrl/sirf/pinctrl-atlas7.c         | 6157 -----------------
 drivers/pinctrl/sirf/pinctrl-prima2.c         | 1131 ---
 drivers/pinctrl/sirf/pinctrl-sirf.c           |  894 ---
 drivers/pinctrl/sirf/pinctrl-sirf.h           |  116 -
 drivers/pinctrl/zte/Kconfig                   |   14 -
 drivers/pinctrl/zte/Makefile                  |    3 -
 drivers/pinctrl/zte/pinctrl-zx.c              |  445 --
 drivers/pinctrl/zte/pinctrl-zx.h              |  102 -
 drivers/pinctrl/zte/pinctrl-zx296718.c        | 1024 ---
 24 files changed, 13521 deletions(-)
 delete mode 100644 Documentation/devicetree/bindings/gpio/gpio-atlas7.txt
 delete mode 100644 Documentation/devicetree/bindings/gpio/gpio-stericsson-coh901.txt
 delete mode 100644 Documentation/devicetree/bindings/gpio/zx296702-gpio.txt
 delete mode 100644 Documentation/devicetree/bindings/pinctrl/pinctrl-atlas7.txt
 delete mode 100644 Documentation/devicetree/bindings/pinctrl/pinctrl-zx.txt
 delete mode 100644 drivers/gpio/gpio-zx.c
 delete mode 100644 drivers/pinctrl/pinctrl-coh901.c
 delete mode 100644 drivers/pinctrl/pinctrl-coh901.h
 delete mode 100644 drivers/pinctrl/pinctrl-u300.c
 delete mode 100644 drivers/pinctrl/sirf/Makefile
 delete mode 100644 drivers/pinctrl/sirf/pinctrl-atlas6.c
 delete mode 100644 drivers/pinctrl/sirf/pinctrl-atlas7.c
 delete mode 100644 drivers/pinctrl/sirf/pinctrl-prima2.c
 delete mode 100644 drivers/pinctrl/sirf/pinctrl-sirf.c
 delete mode 100644 drivers/pinctrl/sirf/pinctrl-sirf.h
 delete mode 100644 drivers/pinctrl/zte/Kconfig
 delete mode 100644 drivers/pinctrl/zte/Makefile
 delete mode 100644 drivers/pinctrl/zte/pinctrl-zx.c
 delete mode 100644 drivers/pinctrl/zte/pinctrl-zx.h
 delete mode 100644 drivers/pinctrl/zte/pinctrl-zx296718.c

-- 
2.29.2


^ permalink raw reply	[flat|nested] 22+ messages in thread

* [PATCH 0/5] pinctrl/gpio: remove obsolete drivers
@ 2021-01-20 13:20 ` Arnd Bergmann
  0 siblings, 0 replies; 22+ messages in thread
From: Arnd Bergmann @ 2021-01-20 13:20 UTC (permalink / raw)
  To: linux-arm-kernel, linux-kernel, linux-gpio, Linus Walleij
  Cc: Bartosz Golaszewski, Arnd Bergmann

From: Arnd Bergmann <arnd@arndb.de>

A few Arm platforms are getting removed in v5.12, this removes
the corresponding gpio and pinctrl drivers.

Link: https://lore.kernel.org/linux-arm-kernel/20210120124812.2800027-1-arnd@kernel.org/T/

Arnd Bergmann (5):
  gpio: remove zte zx driver
  pinctrl: remove zte zx driver
  pinctrl: remove sirf atlas/prima drivers
  pinctrl: remove coh901 driver
  pinctrl: remove ste u300 driver

 .../devicetree/bindings/gpio/gpio-atlas7.txt  |   50 -
 .../bindings/gpio/gpio-stericsson-coh901.txt  |    7 -
 .../bindings/gpio/zx296702-gpio.txt           |   24 -
 .../bindings/pinctrl/pinctrl-atlas7.txt       |  109 -
 .../bindings/pinctrl/pinctrl-zx.txt           |   84 -
 drivers/gpio/Kconfig                          |    7 -
 drivers/gpio/Makefile                         |    1 -
 drivers/gpio/gpio-zx.c                        |  289 -
 drivers/pinctrl/Kconfig                       |   25 -
 drivers/pinctrl/Makefile                      |    4 -
 drivers/pinctrl/pinctrl-coh901.c              |  774 ---
 drivers/pinctrl/pinctrl-coh901.h              |    6 -
 drivers/pinctrl/pinctrl-u300.c                | 1111 ---
 drivers/pinctrl/sirf/Makefile                 |    7 -
 drivers/pinctrl/sirf/pinctrl-atlas6.c         | 1137 ---
 drivers/pinctrl/sirf/pinctrl-atlas7.c         | 6157 -----------------
 drivers/pinctrl/sirf/pinctrl-prima2.c         | 1131 ---
 drivers/pinctrl/sirf/pinctrl-sirf.c           |  894 ---
 drivers/pinctrl/sirf/pinctrl-sirf.h           |  116 -
 drivers/pinctrl/zte/Kconfig                   |   14 -
 drivers/pinctrl/zte/Makefile                  |    3 -
 drivers/pinctrl/zte/pinctrl-zx.c              |  445 --
 drivers/pinctrl/zte/pinctrl-zx.h              |  102 -
 drivers/pinctrl/zte/pinctrl-zx296718.c        | 1024 ---
 24 files changed, 13521 deletions(-)
 delete mode 100644 Documentation/devicetree/bindings/gpio/gpio-atlas7.txt
 delete mode 100644 Documentation/devicetree/bindings/gpio/gpio-stericsson-coh901.txt
 delete mode 100644 Documentation/devicetree/bindings/gpio/zx296702-gpio.txt
 delete mode 100644 Documentation/devicetree/bindings/pinctrl/pinctrl-atlas7.txt
 delete mode 100644 Documentation/devicetree/bindings/pinctrl/pinctrl-zx.txt
 delete mode 100644 drivers/gpio/gpio-zx.c
 delete mode 100644 drivers/pinctrl/pinctrl-coh901.c
 delete mode 100644 drivers/pinctrl/pinctrl-coh901.h
 delete mode 100644 drivers/pinctrl/pinctrl-u300.c
 delete mode 100644 drivers/pinctrl/sirf/Makefile
 delete mode 100644 drivers/pinctrl/sirf/pinctrl-atlas6.c
 delete mode 100644 drivers/pinctrl/sirf/pinctrl-atlas7.c
 delete mode 100644 drivers/pinctrl/sirf/pinctrl-prima2.c
 delete mode 100644 drivers/pinctrl/sirf/pinctrl-sirf.c
 delete mode 100644 drivers/pinctrl/sirf/pinctrl-sirf.h
 delete mode 100644 drivers/pinctrl/zte/Kconfig
 delete mode 100644 drivers/pinctrl/zte/Makefile
 delete mode 100644 drivers/pinctrl/zte/pinctrl-zx.c
 delete mode 100644 drivers/pinctrl/zte/pinctrl-zx.h
 delete mode 100644 drivers/pinctrl/zte/pinctrl-zx296718.c

-- 
2.29.2


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 22+ messages in thread

* [PATCH 1/5] gpio: remove zte zx driver
  2021-01-20 13:20 ` Arnd Bergmann
@ 2021-01-20 13:20   ` Arnd Bergmann
  -1 siblings, 0 replies; 22+ messages in thread
From: Arnd Bergmann @ 2021-01-20 13:20 UTC (permalink / raw)
  To: linux-arm-kernel, linux-kernel, linux-gpio, Linus Walleij
  Cc: Bartosz Golaszewski, Arnd Bergmann, Jun Nie, Shawn Guo

From: Arnd Bergmann <arnd@arndb.de>

The zte zx platform is getting removed, so this driver is no
longer needed.

Cc: Jun Nie <jun.nie@linaro.org>
Cc: Shawn Guo <shawnguo@kernel.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
---
 .../bindings/gpio/zx296702-gpio.txt           |  24 --
 drivers/gpio/Kconfig                          |   7 -
 drivers/gpio/Makefile                         |   1 -
 drivers/gpio/gpio-zx.c                        | 289 ------------------
 4 files changed, 321 deletions(-)
 delete mode 100644 Documentation/devicetree/bindings/gpio/zx296702-gpio.txt
 delete mode 100644 drivers/gpio/gpio-zx.c

diff --git a/Documentation/devicetree/bindings/gpio/zx296702-gpio.txt b/Documentation/devicetree/bindings/gpio/zx296702-gpio.txt
deleted file mode 100644
index 0dab156fcf41..000000000000
--- a/Documentation/devicetree/bindings/gpio/zx296702-gpio.txt
+++ /dev/null
@@ -1,24 +0,0 @@
-ZTE ZX296702 GPIO controller
-
-Required properties:
-- compatible : "zte,zx296702-gpio"
-- #gpio-cells : Should be two. The first cell is the pin number and the
-  second cell is used to specify optional parameters:
-  - bit 0 specifies polarity (0 for normal, 1 for inverted)
-- gpio-controller : Marks the device node as a GPIO controller.
-- interrupts : Interrupt mapping for GPIO IRQ.
-- gpio-ranges : Interaction with the PINCTRL subsystem.
-
-gpio1: gpio@b008040 {
-	compatible = "zte,zx296702-gpio";
-	reg = <0xb008040 0x40>;
-	gpio-controller;
-	#gpio-cells = <2>;
-	gpio-ranges = < &pmx0 0 54 2 &pmx0 2 59 14>;
-	interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
-	interrupt-parent = <&intc>;
-	interrupt-controller;
-	#interrupt-cells = <2>;
-	clock-names = "gpio_pclk";
-	clocks = <&lsp0clk ZX296702_GPIO_CLK>;
-};
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index c70f46e80a3b..e4f6dfefa9df 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -727,13 +727,6 @@ config GPIO_ZYNQ
 	help
 	  Say yes here to support Xilinx Zynq GPIO controller.
 
-config GPIO_ZX
-	bool "ZTE ZX GPIO support"
-	depends on ARCH_ZX || COMPILE_TEST
-	select GPIOLIB_IRQCHIP
-	help
-	  Say yes here to support the GPIO device on ZTE ZX SoCs.
-
 config GPIO_LOONGSON1
 	tristate "Loongson1 GPIO support"
 	depends on MACH_LOONGSON32
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index 35e3b6026665..db72ebc7b387 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -180,5 +180,4 @@ obj-$(CONFIG_GPIO_XLP)			+= gpio-xlp.o
 obj-$(CONFIG_GPIO_XRA1403)		+= gpio-xra1403.o
 obj-$(CONFIG_GPIO_XTENSA)		+= gpio-xtensa.o
 obj-$(CONFIG_GPIO_ZEVIO)		+= gpio-zevio.o
-obj-$(CONFIG_GPIO_ZX)			+= gpio-zx.o
 obj-$(CONFIG_GPIO_ZYNQ)			+= gpio-zynq.o
diff --git a/drivers/gpio/gpio-zx.c b/drivers/gpio/gpio-zx.c
deleted file mode 100644
index 64bfb722756a..000000000000
--- a/drivers/gpio/gpio-zx.c
+++ /dev/null
@@ -1,289 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * ZTE ZX296702 GPIO driver
- *
- * Author: Jun Nie <jun.nie@linaro.org>
- *
- * Copyright (C) 2015 Linaro Ltd.
- */
-#include <linux/bitops.h>
-#include <linux/device.h>
-#include <linux/errno.h>
-#include <linux/gpio/driver.h>
-#include <linux/irqchip/chained_irq.h>
-#include <linux/init.h>
-#include <linux/of.h>
-#include <linux/pinctrl/consumer.h>
-#include <linux/platform_device.h>
-#include <linux/pm.h>
-#include <linux/slab.h>
-#include <linux/spinlock.h>
-
-#define ZX_GPIO_DIR	0x00
-#define ZX_GPIO_IVE	0x04
-#define ZX_GPIO_IV	0x08
-#define ZX_GPIO_IEP	0x0C
-#define ZX_GPIO_IEN	0x10
-#define ZX_GPIO_DI	0x14
-#define ZX_GPIO_DO1	0x18
-#define ZX_GPIO_DO0	0x1C
-#define ZX_GPIO_DO	0x20
-
-#define ZX_GPIO_IM	0x28
-#define ZX_GPIO_IE	0x2C
-
-#define ZX_GPIO_MIS	0x30
-#define ZX_GPIO_IC	0x34
-
-#define ZX_GPIO_NR	16
-
-struct zx_gpio {
-	raw_spinlock_t		lock;
-
-	void __iomem		*base;
-	struct gpio_chip	gc;
-};
-
-static int zx_direction_input(struct gpio_chip *gc, unsigned offset)
-{
-	struct zx_gpio *chip = gpiochip_get_data(gc);
-	unsigned long flags;
-	u16 gpiodir;
-
-	if (offset >= gc->ngpio)
-		return -EINVAL;
-
-	raw_spin_lock_irqsave(&chip->lock, flags);
-	gpiodir = readw_relaxed(chip->base + ZX_GPIO_DIR);
-	gpiodir &= ~BIT(offset);
-	writew_relaxed(gpiodir, chip->base + ZX_GPIO_DIR);
-	raw_spin_unlock_irqrestore(&chip->lock, flags);
-
-	return 0;
-}
-
-static int zx_direction_output(struct gpio_chip *gc, unsigned offset,
-		int value)
-{
-	struct zx_gpio *chip = gpiochip_get_data(gc);
-	unsigned long flags;
-	u16 gpiodir;
-
-	if (offset >= gc->ngpio)
-		return -EINVAL;
-
-	raw_spin_lock_irqsave(&chip->lock, flags);
-	gpiodir = readw_relaxed(chip->base + ZX_GPIO_DIR);
-	gpiodir |= BIT(offset);
-	writew_relaxed(gpiodir, chip->base + ZX_GPIO_DIR);
-
-	if (value)
-		writew_relaxed(BIT(offset), chip->base + ZX_GPIO_DO1);
-	else
-		writew_relaxed(BIT(offset), chip->base + ZX_GPIO_DO0);
-	raw_spin_unlock_irqrestore(&chip->lock, flags);
-
-	return 0;
-}
-
-static int zx_get_value(struct gpio_chip *gc, unsigned offset)
-{
-	struct zx_gpio *chip = gpiochip_get_data(gc);
-
-	return !!(readw_relaxed(chip->base + ZX_GPIO_DI) & BIT(offset));
-}
-
-static void zx_set_value(struct gpio_chip *gc, unsigned offset, int value)
-{
-	struct zx_gpio *chip = gpiochip_get_data(gc);
-
-	if (value)
-		writew_relaxed(BIT(offset), chip->base + ZX_GPIO_DO1);
-	else
-		writew_relaxed(BIT(offset), chip->base + ZX_GPIO_DO0);
-}
-
-static int zx_irq_type(struct irq_data *d, unsigned trigger)
-{
-	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
-	struct zx_gpio *chip = gpiochip_get_data(gc);
-	int offset = irqd_to_hwirq(d);
-	unsigned long flags;
-	u16 gpiois, gpioi_epos, gpioi_eneg, gpioiev;
-	u16 bit = BIT(offset);
-
-	if (offset < 0 || offset >= ZX_GPIO_NR)
-		return -EINVAL;
-
-	raw_spin_lock_irqsave(&chip->lock, flags);
-
-	gpioiev = readw_relaxed(chip->base + ZX_GPIO_IV);
-	gpiois = readw_relaxed(chip->base + ZX_GPIO_IVE);
-	gpioi_epos = readw_relaxed(chip->base + ZX_GPIO_IEP);
-	gpioi_eneg = readw_relaxed(chip->base + ZX_GPIO_IEN);
-
-	if (trigger & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
-		gpiois |= bit;
-		if (trigger & IRQ_TYPE_LEVEL_HIGH)
-			gpioiev |= bit;
-		else
-			gpioiev &= ~bit;
-	} else
-		gpiois &= ~bit;
-
-	if ((trigger & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) {
-		gpioi_epos |= bit;
-		gpioi_eneg |= bit;
-	} else {
-		if (trigger & IRQ_TYPE_EDGE_RISING) {
-			gpioi_epos |= bit;
-			gpioi_eneg &= ~bit;
-		} else if (trigger & IRQ_TYPE_EDGE_FALLING) {
-			gpioi_eneg |= bit;
-			gpioi_epos &= ~bit;
-		}
-	}
-
-	writew_relaxed(gpiois, chip->base + ZX_GPIO_IVE);
-	writew_relaxed(gpioi_epos, chip->base + ZX_GPIO_IEP);
-	writew_relaxed(gpioi_eneg, chip->base + ZX_GPIO_IEN);
-	writew_relaxed(gpioiev, chip->base + ZX_GPIO_IV);
-	raw_spin_unlock_irqrestore(&chip->lock, flags);
-
-	return 0;
-}
-
-static void zx_irq_handler(struct irq_desc *desc)
-{
-	unsigned long pending;
-	int offset;
-	struct gpio_chip *gc = irq_desc_get_handler_data(desc);
-	struct zx_gpio *chip = gpiochip_get_data(gc);
-	struct irq_chip *irqchip = irq_desc_get_chip(desc);
-
-	chained_irq_enter(irqchip, desc);
-
-	pending = readw_relaxed(chip->base + ZX_GPIO_MIS);
-	writew_relaxed(pending, chip->base + ZX_GPIO_IC);
-	if (pending) {
-		for_each_set_bit(offset, &pending, ZX_GPIO_NR)
-			generic_handle_irq(irq_find_mapping(gc->irq.domain,
-							    offset));
-	}
-
-	chained_irq_exit(irqchip, desc);
-}
-
-static void zx_irq_mask(struct irq_data *d)
-{
-	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
-	struct zx_gpio *chip = gpiochip_get_data(gc);
-	u16 mask = BIT(irqd_to_hwirq(d) % ZX_GPIO_NR);
-	u16 gpioie;
-
-	raw_spin_lock(&chip->lock);
-	gpioie = readw_relaxed(chip->base + ZX_GPIO_IM) | mask;
-	writew_relaxed(gpioie, chip->base + ZX_GPIO_IM);
-	gpioie = readw_relaxed(chip->base + ZX_GPIO_IE) & ~mask;
-	writew_relaxed(gpioie, chip->base + ZX_GPIO_IE);
-	raw_spin_unlock(&chip->lock);
-}
-
-static void zx_irq_unmask(struct irq_data *d)
-{
-	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
-	struct zx_gpio *chip = gpiochip_get_data(gc);
-	u16 mask = BIT(irqd_to_hwirq(d) % ZX_GPIO_NR);
-	u16 gpioie;
-
-	raw_spin_lock(&chip->lock);
-	gpioie = readw_relaxed(chip->base + ZX_GPIO_IM) & ~mask;
-	writew_relaxed(gpioie, chip->base + ZX_GPIO_IM);
-	gpioie = readw_relaxed(chip->base + ZX_GPIO_IE) | mask;
-	writew_relaxed(gpioie, chip->base + ZX_GPIO_IE);
-	raw_spin_unlock(&chip->lock);
-}
-
-static struct irq_chip zx_irqchip = {
-	.name		= "zx-gpio",
-	.irq_mask	= zx_irq_mask,
-	.irq_unmask	= zx_irq_unmask,
-	.irq_set_type	= zx_irq_type,
-};
-
-static int zx_gpio_probe(struct platform_device *pdev)
-{
-	struct device *dev = &pdev->dev;
-	struct zx_gpio *chip;
-	struct gpio_irq_chip *girq;
-	int irq, id, ret;
-
-	chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
-	if (!chip)
-		return -ENOMEM;
-
-	chip->base = devm_platform_ioremap_resource(pdev, 0);
-	if (IS_ERR(chip->base))
-		return PTR_ERR(chip->base);
-
-	id = of_alias_get_id(dev->of_node, "gpio");
-
-	raw_spin_lock_init(&chip->lock);
-	chip->gc.request = gpiochip_generic_request;
-	chip->gc.free = gpiochip_generic_free;
-	chip->gc.direction_input = zx_direction_input;
-	chip->gc.direction_output = zx_direction_output;
-	chip->gc.get = zx_get_value;
-	chip->gc.set = zx_set_value;
-	chip->gc.base = ZX_GPIO_NR * id;
-	chip->gc.ngpio = ZX_GPIO_NR;
-	chip->gc.label = dev_name(dev);
-	chip->gc.parent = dev;
-	chip->gc.owner = THIS_MODULE;
-
-	/*
-	 * irq_chip support
-	 */
-	writew_relaxed(0xffff, chip->base + ZX_GPIO_IM);
-	writew_relaxed(0, chip->base + ZX_GPIO_IE);
-	irq = platform_get_irq(pdev, 0);
-	if (irq < 0)
-		return irq;
-	girq = &chip->gc.irq;
-	girq->chip = &zx_irqchip;
-	girq->parent_handler = zx_irq_handler;
-	girq->num_parents = 1;
-	girq->parents = devm_kcalloc(&pdev->dev, 1,
-				     sizeof(*girq->parents),
-				     GFP_KERNEL);
-	if (!girq->parents)
-		return -ENOMEM;
-	girq->parents[0] = irq;
-	girq->default_type = IRQ_TYPE_NONE;
-	girq->handler = handle_simple_irq;
-
-	ret = gpiochip_add_data(&chip->gc, chip);
-	if (ret)
-		return ret;
-
-	platform_set_drvdata(pdev, chip);
-	dev_info(dev, "ZX GPIO chip registered\n");
-
-	return 0;
-}
-
-static const struct of_device_id zx_gpio_match[] = {
-	{
-		.compatible = "zte,zx296702-gpio",
-	},
-	{ },
-};
-
-static struct platform_driver zx_gpio_driver = {
-	.probe		= zx_gpio_probe,
-	.driver = {
-		.name	= "zx_gpio",
-		.of_match_table = of_match_ptr(zx_gpio_match),
-	},
-};
-builtin_platform_driver(zx_gpio_driver)
-- 
2.29.2


^ permalink raw reply related	[flat|nested] 22+ messages in thread

* [PATCH 1/5] gpio: remove zte zx driver
@ 2021-01-20 13:20   ` Arnd Bergmann
  0 siblings, 0 replies; 22+ messages in thread
From: Arnd Bergmann @ 2021-01-20 13:20 UTC (permalink / raw)
  To: linux-arm-kernel, linux-kernel, linux-gpio, Linus Walleij
  Cc: Bartosz Golaszewski, Jun Nie, Shawn Guo, Arnd Bergmann

From: Arnd Bergmann <arnd@arndb.de>

The zte zx platform is getting removed, so this driver is no
longer needed.

Cc: Jun Nie <jun.nie@linaro.org>
Cc: Shawn Guo <shawnguo@kernel.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
---
 .../bindings/gpio/zx296702-gpio.txt           |  24 --
 drivers/gpio/Kconfig                          |   7 -
 drivers/gpio/Makefile                         |   1 -
 drivers/gpio/gpio-zx.c                        | 289 ------------------
 4 files changed, 321 deletions(-)
 delete mode 100644 Documentation/devicetree/bindings/gpio/zx296702-gpio.txt
 delete mode 100644 drivers/gpio/gpio-zx.c

diff --git a/Documentation/devicetree/bindings/gpio/zx296702-gpio.txt b/Documentation/devicetree/bindings/gpio/zx296702-gpio.txt
deleted file mode 100644
index 0dab156fcf41..000000000000
--- a/Documentation/devicetree/bindings/gpio/zx296702-gpio.txt
+++ /dev/null
@@ -1,24 +0,0 @@
-ZTE ZX296702 GPIO controller
-
-Required properties:
-- compatible : "zte,zx296702-gpio"
-- #gpio-cells : Should be two. The first cell is the pin number and the
-  second cell is used to specify optional parameters:
-  - bit 0 specifies polarity (0 for normal, 1 for inverted)
-- gpio-controller : Marks the device node as a GPIO controller.
-- interrupts : Interrupt mapping for GPIO IRQ.
-- gpio-ranges : Interaction with the PINCTRL subsystem.
-
-gpio1: gpio@b008040 {
-	compatible = "zte,zx296702-gpio";
-	reg = <0xb008040 0x40>;
-	gpio-controller;
-	#gpio-cells = <2>;
-	gpio-ranges = < &pmx0 0 54 2 &pmx0 2 59 14>;
-	interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
-	interrupt-parent = <&intc>;
-	interrupt-controller;
-	#interrupt-cells = <2>;
-	clock-names = "gpio_pclk";
-	clocks = <&lsp0clk ZX296702_GPIO_CLK>;
-};
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index c70f46e80a3b..e4f6dfefa9df 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -727,13 +727,6 @@ config GPIO_ZYNQ
 	help
 	  Say yes here to support Xilinx Zynq GPIO controller.
 
-config GPIO_ZX
-	bool "ZTE ZX GPIO support"
-	depends on ARCH_ZX || COMPILE_TEST
-	select GPIOLIB_IRQCHIP
-	help
-	  Say yes here to support the GPIO device on ZTE ZX SoCs.
-
 config GPIO_LOONGSON1
 	tristate "Loongson1 GPIO support"
 	depends on MACH_LOONGSON32
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index 35e3b6026665..db72ebc7b387 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -180,5 +180,4 @@ obj-$(CONFIG_GPIO_XLP)			+= gpio-xlp.o
 obj-$(CONFIG_GPIO_XRA1403)		+= gpio-xra1403.o
 obj-$(CONFIG_GPIO_XTENSA)		+= gpio-xtensa.o
 obj-$(CONFIG_GPIO_ZEVIO)		+= gpio-zevio.o
-obj-$(CONFIG_GPIO_ZX)			+= gpio-zx.o
 obj-$(CONFIG_GPIO_ZYNQ)			+= gpio-zynq.o
diff --git a/drivers/gpio/gpio-zx.c b/drivers/gpio/gpio-zx.c
deleted file mode 100644
index 64bfb722756a..000000000000
--- a/drivers/gpio/gpio-zx.c
+++ /dev/null
@@ -1,289 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * ZTE ZX296702 GPIO driver
- *
- * Author: Jun Nie <jun.nie@linaro.org>
- *
- * Copyright (C) 2015 Linaro Ltd.
- */
-#include <linux/bitops.h>
-#include <linux/device.h>
-#include <linux/errno.h>
-#include <linux/gpio/driver.h>
-#include <linux/irqchip/chained_irq.h>
-#include <linux/init.h>
-#include <linux/of.h>
-#include <linux/pinctrl/consumer.h>
-#include <linux/platform_device.h>
-#include <linux/pm.h>
-#include <linux/slab.h>
-#include <linux/spinlock.h>
-
-#define ZX_GPIO_DIR	0x00
-#define ZX_GPIO_IVE	0x04
-#define ZX_GPIO_IV	0x08
-#define ZX_GPIO_IEP	0x0C
-#define ZX_GPIO_IEN	0x10
-#define ZX_GPIO_DI	0x14
-#define ZX_GPIO_DO1	0x18
-#define ZX_GPIO_DO0	0x1C
-#define ZX_GPIO_DO	0x20
-
-#define ZX_GPIO_IM	0x28
-#define ZX_GPIO_IE	0x2C
-
-#define ZX_GPIO_MIS	0x30
-#define ZX_GPIO_IC	0x34
-
-#define ZX_GPIO_NR	16
-
-struct zx_gpio {
-	raw_spinlock_t		lock;
-
-	void __iomem		*base;
-	struct gpio_chip	gc;
-};
-
-static int zx_direction_input(struct gpio_chip *gc, unsigned offset)
-{
-	struct zx_gpio *chip = gpiochip_get_data(gc);
-	unsigned long flags;
-	u16 gpiodir;
-
-	if (offset >= gc->ngpio)
-		return -EINVAL;
-
-	raw_spin_lock_irqsave(&chip->lock, flags);
-	gpiodir = readw_relaxed(chip->base + ZX_GPIO_DIR);
-	gpiodir &= ~BIT(offset);
-	writew_relaxed(gpiodir, chip->base + ZX_GPIO_DIR);
-	raw_spin_unlock_irqrestore(&chip->lock, flags);
-
-	return 0;
-}
-
-static int zx_direction_output(struct gpio_chip *gc, unsigned offset,
-		int value)
-{
-	struct zx_gpio *chip = gpiochip_get_data(gc);
-	unsigned long flags;
-	u16 gpiodir;
-
-	if (offset >= gc->ngpio)
-		return -EINVAL;
-
-	raw_spin_lock_irqsave(&chip->lock, flags);
-	gpiodir = readw_relaxed(chip->base + ZX_GPIO_DIR);
-	gpiodir |= BIT(offset);
-	writew_relaxed(gpiodir, chip->base + ZX_GPIO_DIR);
-
-	if (value)
-		writew_relaxed(BIT(offset), chip->base + ZX_GPIO_DO1);
-	else
-		writew_relaxed(BIT(offset), chip->base + ZX_GPIO_DO0);
-	raw_spin_unlock_irqrestore(&chip->lock, flags);
-
-	return 0;
-}
-
-static int zx_get_value(struct gpio_chip *gc, unsigned offset)
-{
-	struct zx_gpio *chip = gpiochip_get_data(gc);
-
-	return !!(readw_relaxed(chip->base + ZX_GPIO_DI) & BIT(offset));
-}
-
-static void zx_set_value(struct gpio_chip *gc, unsigned offset, int value)
-{
-	struct zx_gpio *chip = gpiochip_get_data(gc);
-
-	if (value)
-		writew_relaxed(BIT(offset), chip->base + ZX_GPIO_DO1);
-	else
-		writew_relaxed(BIT(offset), chip->base + ZX_GPIO_DO0);
-}
-
-static int zx_irq_type(struct irq_data *d, unsigned trigger)
-{
-	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
-	struct zx_gpio *chip = gpiochip_get_data(gc);
-	int offset = irqd_to_hwirq(d);
-	unsigned long flags;
-	u16 gpiois, gpioi_epos, gpioi_eneg, gpioiev;
-	u16 bit = BIT(offset);
-
-	if (offset < 0 || offset >= ZX_GPIO_NR)
-		return -EINVAL;
-
-	raw_spin_lock_irqsave(&chip->lock, flags);
-
-	gpioiev = readw_relaxed(chip->base + ZX_GPIO_IV);
-	gpiois = readw_relaxed(chip->base + ZX_GPIO_IVE);
-	gpioi_epos = readw_relaxed(chip->base + ZX_GPIO_IEP);
-	gpioi_eneg = readw_relaxed(chip->base + ZX_GPIO_IEN);
-
-	if (trigger & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
-		gpiois |= bit;
-		if (trigger & IRQ_TYPE_LEVEL_HIGH)
-			gpioiev |= bit;
-		else
-			gpioiev &= ~bit;
-	} else
-		gpiois &= ~bit;
-
-	if ((trigger & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) {
-		gpioi_epos |= bit;
-		gpioi_eneg |= bit;
-	} else {
-		if (trigger & IRQ_TYPE_EDGE_RISING) {
-			gpioi_epos |= bit;
-			gpioi_eneg &= ~bit;
-		} else if (trigger & IRQ_TYPE_EDGE_FALLING) {
-			gpioi_eneg |= bit;
-			gpioi_epos &= ~bit;
-		}
-	}
-
-	writew_relaxed(gpiois, chip->base + ZX_GPIO_IVE);
-	writew_relaxed(gpioi_epos, chip->base + ZX_GPIO_IEP);
-	writew_relaxed(gpioi_eneg, chip->base + ZX_GPIO_IEN);
-	writew_relaxed(gpioiev, chip->base + ZX_GPIO_IV);
-	raw_spin_unlock_irqrestore(&chip->lock, flags);
-
-	return 0;
-}
-
-static void zx_irq_handler(struct irq_desc *desc)
-{
-	unsigned long pending;
-	int offset;
-	struct gpio_chip *gc = irq_desc_get_handler_data(desc);
-	struct zx_gpio *chip = gpiochip_get_data(gc);
-	struct irq_chip *irqchip = irq_desc_get_chip(desc);
-
-	chained_irq_enter(irqchip, desc);
-
-	pending = readw_relaxed(chip->base + ZX_GPIO_MIS);
-	writew_relaxed(pending, chip->base + ZX_GPIO_IC);
-	if (pending) {
-		for_each_set_bit(offset, &pending, ZX_GPIO_NR)
-			generic_handle_irq(irq_find_mapping(gc->irq.domain,
-							    offset));
-	}
-
-	chained_irq_exit(irqchip, desc);
-}
-
-static void zx_irq_mask(struct irq_data *d)
-{
-	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
-	struct zx_gpio *chip = gpiochip_get_data(gc);
-	u16 mask = BIT(irqd_to_hwirq(d) % ZX_GPIO_NR);
-	u16 gpioie;
-
-	raw_spin_lock(&chip->lock);
-	gpioie = readw_relaxed(chip->base + ZX_GPIO_IM) | mask;
-	writew_relaxed(gpioie, chip->base + ZX_GPIO_IM);
-	gpioie = readw_relaxed(chip->base + ZX_GPIO_IE) & ~mask;
-	writew_relaxed(gpioie, chip->base + ZX_GPIO_IE);
-	raw_spin_unlock(&chip->lock);
-}
-
-static void zx_irq_unmask(struct irq_data *d)
-{
-	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
-	struct zx_gpio *chip = gpiochip_get_data(gc);
-	u16 mask = BIT(irqd_to_hwirq(d) % ZX_GPIO_NR);
-	u16 gpioie;
-
-	raw_spin_lock(&chip->lock);
-	gpioie = readw_relaxed(chip->base + ZX_GPIO_IM) & ~mask;
-	writew_relaxed(gpioie, chip->base + ZX_GPIO_IM);
-	gpioie = readw_relaxed(chip->base + ZX_GPIO_IE) | mask;
-	writew_relaxed(gpioie, chip->base + ZX_GPIO_IE);
-	raw_spin_unlock(&chip->lock);
-}
-
-static struct irq_chip zx_irqchip = {
-	.name		= "zx-gpio",
-	.irq_mask	= zx_irq_mask,
-	.irq_unmask	= zx_irq_unmask,
-	.irq_set_type	= zx_irq_type,
-};
-
-static int zx_gpio_probe(struct platform_device *pdev)
-{
-	struct device *dev = &pdev->dev;
-	struct zx_gpio *chip;
-	struct gpio_irq_chip *girq;
-	int irq, id, ret;
-
-	chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
-	if (!chip)
-		return -ENOMEM;
-
-	chip->base = devm_platform_ioremap_resource(pdev, 0);
-	if (IS_ERR(chip->base))
-		return PTR_ERR(chip->base);
-
-	id = of_alias_get_id(dev->of_node, "gpio");
-
-	raw_spin_lock_init(&chip->lock);
-	chip->gc.request = gpiochip_generic_request;
-	chip->gc.free = gpiochip_generic_free;
-	chip->gc.direction_input = zx_direction_input;
-	chip->gc.direction_output = zx_direction_output;
-	chip->gc.get = zx_get_value;
-	chip->gc.set = zx_set_value;
-	chip->gc.base = ZX_GPIO_NR * id;
-	chip->gc.ngpio = ZX_GPIO_NR;
-	chip->gc.label = dev_name(dev);
-	chip->gc.parent = dev;
-	chip->gc.owner = THIS_MODULE;
-
-	/*
-	 * irq_chip support
-	 */
-	writew_relaxed(0xffff, chip->base + ZX_GPIO_IM);
-	writew_relaxed(0, chip->base + ZX_GPIO_IE);
-	irq = platform_get_irq(pdev, 0);
-	if (irq < 0)
-		return irq;
-	girq = &chip->gc.irq;
-	girq->chip = &zx_irqchip;
-	girq->parent_handler = zx_irq_handler;
-	girq->num_parents = 1;
-	girq->parents = devm_kcalloc(&pdev->dev, 1,
-				     sizeof(*girq->parents),
-				     GFP_KERNEL);
-	if (!girq->parents)
-		return -ENOMEM;
-	girq->parents[0] = irq;
-	girq->default_type = IRQ_TYPE_NONE;
-	girq->handler = handle_simple_irq;
-
-	ret = gpiochip_add_data(&chip->gc, chip);
-	if (ret)
-		return ret;
-
-	platform_set_drvdata(pdev, chip);
-	dev_info(dev, "ZX GPIO chip registered\n");
-
-	return 0;
-}
-
-static const struct of_device_id zx_gpio_match[] = {
-	{
-		.compatible = "zte,zx296702-gpio",
-	},
-	{ },
-};
-
-static struct platform_driver zx_gpio_driver = {
-	.probe		= zx_gpio_probe,
-	.driver = {
-		.name	= "zx_gpio",
-		.of_match_table = of_match_ptr(zx_gpio_match),
-	},
-};
-builtin_platform_driver(zx_gpio_driver)
-- 
2.29.2


_______________________________________________
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^ permalink raw reply related	[flat|nested] 22+ messages in thread

* [PATCH 2/5] pinctrl: remove zte zx driver
  2021-01-20 13:20 ` Arnd Bergmann
@ 2021-01-20 13:20   ` Arnd Bergmann
  -1 siblings, 0 replies; 22+ messages in thread
From: Arnd Bergmann @ 2021-01-20 13:20 UTC (permalink / raw)
  To: linux-arm-kernel, linux-kernel, linux-gpio, Linus Walleij
  Cc: Bartosz Golaszewski, Arnd Bergmann, Jun Nie, Shawn Guo

From: Arnd Bergmann <arnd@arndb.de>

The zte zx platform is getting removed, so this driver is no
longer needed.

Cc: Jun Nie <jun.nie@linaro.org>
Cc: Shawn Guo <shawnguo@kernel.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
---
 .../bindings/pinctrl/pinctrl-zx.txt           |   84 --
 drivers/pinctrl/Kconfig                       |    1 -
 drivers/pinctrl/Makefile                      |    1 -
 drivers/pinctrl/zte/Kconfig                   |   14 -
 drivers/pinctrl/zte/Makefile                  |    3 -
 drivers/pinctrl/zte/pinctrl-zx.c              |  445 -------
 drivers/pinctrl/zte/pinctrl-zx.h              |  102 --
 drivers/pinctrl/zte/pinctrl-zx296718.c        | 1024 -----------------
 8 files changed, 1674 deletions(-)
 delete mode 100644 Documentation/devicetree/bindings/pinctrl/pinctrl-zx.txt
 delete mode 100644 drivers/pinctrl/zte/Kconfig
 delete mode 100644 drivers/pinctrl/zte/Makefile
 delete mode 100644 drivers/pinctrl/zte/pinctrl-zx.c
 delete mode 100644 drivers/pinctrl/zte/pinctrl-zx.h
 delete mode 100644 drivers/pinctrl/zte/pinctrl-zx296718.c

diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-zx.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-zx.txt
deleted file mode 100644
index 39170f372599..000000000000
--- a/Documentation/devicetree/bindings/pinctrl/pinctrl-zx.txt
+++ /dev/null
@@ -1,84 +0,0 @@
-* ZTE ZX Pin Controller
-
-The pin controller on ZTE ZX platforms is kinda of hybrid.  It consists of
-a main controller and an auxiliary one.  For example, on ZX296718 SoC, the
-main controller is TOP_PMM and the auxiliary one is AON_IOCFG.  Both
-controllers work together to control pin multiplexing and configuration in
-the way illustrated as below.
-
-
-           GMII_RXD3 ---+
-                        |
-             DVI1_HS ---+----------------------------- GMII_RXD3 (TOP pin)
-                        |
-             BGPIO16 ---+                               ^
-                                                        | pinconf
-                        ^                               |
-                        | pinmux                        |
-                        |                               |
-
-                   TOP_PMM (main)           AON_IOCFG (aux)
-
-                        |                       |       |
-                        |                pinmux |       |
-                        | pinmux                v       |
-                        v                               | pinconf
-                                    KEY_ROW2 ---+       v
-        PORT1_LCD_TE ---+                       |
-                        |            AGPIO10 ---+------ KEY_ROW2 (AON pin)
-          I2S0_DOUT3 ---+                       |
-                        |-----------------------+
-            PWM_OUT3 ---+
-                        |
-             VGA_VS1 ---+
-
-
-For most of pins like GMII_RXD3 in the figure, the pinmux function is
-controlled by TOP_PMM block only, and this type of pins are meant by term
-'TOP pins'.  For pins like KEY_ROW2, the pinmux is controlled by both
-TOP_PMM and AON_IOCFG blocks, as the available multiplexing functions for
-the pin spread in both controllers.  This type of pins are called 'AON pins'.
-Though pinmux implementation is quite different, pinconf is same for both
-types of pins.  Both are controlled by auxiliary controller, i.e. AON_IOCFG
-on ZX296718.
-
-Required properties:
-- compatible: should be "zte,zx296718-pmm".
-- reg: the register physical address and length.
-- zte,auxiliary-controller: phandle to the auxiliary pin controller which
-  implements pinmux for AON pins and pinconf for all pins.
-
-The following pin configuration are supported. Please refer to
-pinctrl-bindings.txt in this directory for more details of the common
-pinctrl bindings used by client devices.
-
-- bias-pull-up
-- bias-pull-down
-- drive-strength
-- input-enable
-- slew-rate
-
-Examples:
-
-iocfg: pin-controller@119000 {
-	compatible = "zte,zx296718-iocfg";
-	reg = <0x119000 0x1000>;
-};
-
-pmm: pin-controller@1462000 {
-	compatible = "zte,zx296718-pmm";
-	reg = <0x1462000 0x1000>;
-	zte,auxiliary-controller = <&iocfg>;
-};
-
-&pmm {
-	vga_pins: vga {
-		pins = "KEY_COL1", "KEY_COL2", "KEY_ROW1", "KEY_ROW2";
-		function = "VGA";
-	};
-};
-
-&vga {
-	pinctrl-names = "default";
-	pinctrl-0 = <&vga_pins>;
-};
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index d4b2f2e2ed75..1c1fa681b96d 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -417,7 +417,6 @@ source "drivers/pinctrl/ti/Kconfig"
 source "drivers/pinctrl/uniphier/Kconfig"
 source "drivers/pinctrl/vt8500/Kconfig"
 source "drivers/pinctrl/mediatek/Kconfig"
-source "drivers/pinctrl/zte/Kconfig"
 source "drivers/pinctrl/meson/Kconfig"
 source "drivers/pinctrl/cirrus/Kconfig"
 source "drivers/pinctrl/visconti/Kconfig"
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index 5bb9bb6cc3ce..fef92794900d 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -71,6 +71,5 @@ obj-y				+= ti/
 obj-$(CONFIG_PINCTRL_UNIPHIER)	+= uniphier/
 obj-$(CONFIG_ARCH_VT8500)	+= vt8500/
 obj-y				+= mediatek/
-obj-$(CONFIG_PINCTRL_ZX)	+= zte/
 obj-y				+= cirrus/
 obj-$(CONFIG_PINCTRL_VISCONTI)	+= visconti/
diff --git a/drivers/pinctrl/zte/Kconfig b/drivers/pinctrl/zte/Kconfig
deleted file mode 100644
index 4fdc70511034..000000000000
--- a/drivers/pinctrl/zte/Kconfig
+++ /dev/null
@@ -1,14 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-only
-config PINCTRL_ZX
-	bool
-	select PINMUX
-	select GENERIC_PINCONF
-	select GENERIC_PINCTRL_GROUPS
-	select GENERIC_PINMUX_FUNCTIONS
-
-config PINCTRL_ZX296718
-	bool "ZTE ZX296718 pinctrl driver"
-	depends on OF && ARCH_ZX
-	select PINCTRL_ZX
-	help
-	  Say Y here to enable the ZX296718 pinctrl driver
diff --git a/drivers/pinctrl/zte/Makefile b/drivers/pinctrl/zte/Makefile
deleted file mode 100644
index 2084c7810f96..000000000000
--- a/drivers/pinctrl/zte/Makefile
+++ /dev/null
@@ -1,3 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-only
-obj-$(CONFIG_PINCTRL_ZX)	+= pinctrl-zx.o
-obj-$(CONFIG_PINCTRL_ZX296718)	+= pinctrl-zx296718.o
diff --git a/drivers/pinctrl/zte/pinctrl-zx.c b/drivers/pinctrl/zte/pinctrl-zx.c
deleted file mode 100644
index 80d00ab8c110..000000000000
--- a/drivers/pinctrl/zte/pinctrl-zx.c
+++ /dev/null
@@ -1,445 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Copyright (C) 2017 Sanechips Technology Co., Ltd.
- * Copyright 2017 Linaro Ltd.
- */
-
-#include <linux/io.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-#include <linux/of_device.h>
-#include <linux/pinctrl/pinctrl.h>
-#include <linux/pinctrl/pinconf-generic.h>
-#include <linux/pinctrl/pinmux.h>
-#include <linux/platform_device.h>
-#include <linux/slab.h>
-
-#include "../core.h"
-#include "../pinctrl-utils.h"
-#include "../pinmux.h"
-#include "pinctrl-zx.h"
-
-#define ZX_PULL_DOWN		BIT(0)
-#define ZX_PULL_UP		BIT(1)
-#define ZX_INPUT_ENABLE		BIT(3)
-#define ZX_DS_SHIFT		4
-#define ZX_DS_MASK		(0x7 << ZX_DS_SHIFT)
-#define ZX_DS_VALUE(x)		(((x) << ZX_DS_SHIFT) & ZX_DS_MASK)
-#define ZX_SLEW			BIT(8)
-
-struct zx_pinctrl {
-	struct pinctrl_dev *pctldev;
-	struct device *dev;
-	void __iomem *base;
-	void __iomem *aux_base;
-	spinlock_t lock;
-	struct zx_pinctrl_soc_info *info;
-};
-
-static int zx_dt_node_to_map(struct pinctrl_dev *pctldev,
-			     struct device_node *np_config,
-			     struct pinctrl_map **map, u32 *num_maps)
-{
-	return pinconf_generic_dt_node_to_map(pctldev, np_config, map,
-					      num_maps, PIN_MAP_TYPE_INVALID);
-}
-
-static const struct pinctrl_ops zx_pinctrl_ops = {
-	.dt_node_to_map = zx_dt_node_to_map,
-	.dt_free_map = pinctrl_utils_free_map,
-	.get_groups_count = pinctrl_generic_get_group_count,
-	.get_group_name = pinctrl_generic_get_group_name,
-	.get_group_pins = pinctrl_generic_get_group_pins,
-};
-
-#define NONAON_MVAL 2
-
-static int zx_set_mux(struct pinctrl_dev *pctldev, unsigned int func_selector,
-		      unsigned int group_selector)
-{
-	struct zx_pinctrl *zpctl = pinctrl_dev_get_drvdata(pctldev);
-	struct zx_pinctrl_soc_info *info = zpctl->info;
-	const struct pinctrl_pin_desc *pindesc = info->pins + group_selector;
-	struct zx_pin_data *data = pindesc->drv_data;
-	struct zx_mux_desc *mux;
-	u32 mask, offset, bitpos;
-	struct function_desc *func;
-	unsigned long flags;
-	u32 val, mval;
-
-	/* Skip reserved pin */
-	if (!data)
-		return -EINVAL;
-
-	mux = data->muxes;
-	mask = (1 << data->width) - 1;
-	offset = data->offset;
-	bitpos = data->bitpos;
-
-	func = pinmux_generic_get_function(pctldev, func_selector);
-	if (!func)
-		return -EINVAL;
-
-	while (mux->name) {
-		if (strcmp(mux->name, func->name) == 0)
-			break;
-		mux++;
-	}
-
-	/* Found mux value to be written */
-	mval = mux->muxval;
-
-	spin_lock_irqsave(&zpctl->lock, flags);
-
-	if (data->aon_pin) {
-		/*
-		 * It's an AON pin, whose mux register offset and bit position
-		 * can be calculated from pin number.  Each register covers 16
-		 * pins, and each pin occupies 2 bits.
-		 */
-		u16 aoffset = pindesc->number / 16 * 4;
-		u16 abitpos = (pindesc->number % 16) * 2;
-
-		if (mval & AON_MUX_FLAG) {
-			/*
-			 * This is a mux value that needs to be written into
-			 * AON pinmux register.  Write it and then we're done.
-			 */
-			val = readl(zpctl->aux_base + aoffset);
-			val &= ~(0x3 << abitpos);
-			val |= (mval & 0x3) << abitpos;
-			writel(val, zpctl->aux_base + aoffset);
-		} else {
-			/*
-			 * It's a mux value that needs to be written into TOP
-			 * pinmux register.
-			 */
-			val = readl(zpctl->base + offset);
-			val &= ~(mask << bitpos);
-			val |= (mval & mask) << bitpos;
-			writel(val, zpctl->base + offset);
-
-			/*
-			 * In this case, the AON pinmux register needs to be
-			 * set up to select non-AON function.
-			 */
-			val = readl(zpctl->aux_base + aoffset);
-			val &= ~(0x3 << abitpos);
-			val |= NONAON_MVAL << abitpos;
-			writel(val, zpctl->aux_base + aoffset);
-		}
-
-	} else {
-		/*
-		 * This is a TOP pin, and we only need to set up TOP pinmux
-		 * register and then we're done with it.
-		 */
-		val = readl(zpctl->base + offset);
-		val &= ~(mask << bitpos);
-		val |= (mval & mask) << bitpos;
-		writel(val, zpctl->base + offset);
-	}
-
-	spin_unlock_irqrestore(&zpctl->lock, flags);
-
-	return 0;
-}
-
-static const struct pinmux_ops zx_pinmux_ops = {
-	.get_functions_count = pinmux_generic_get_function_count,
-	.get_function_name = pinmux_generic_get_function_name,
-	.get_function_groups = pinmux_generic_get_function_groups,
-	.set_mux = zx_set_mux,
-};
-
-static int zx_pin_config_get(struct pinctrl_dev *pctldev, unsigned int pin,
-			     unsigned long *config)
-{
-	struct zx_pinctrl *zpctl = pinctrl_dev_get_drvdata(pctldev);
-	struct zx_pinctrl_soc_info *info = zpctl->info;
-	const struct pinctrl_pin_desc *pindesc = info->pins + pin;
-	struct zx_pin_data *data = pindesc->drv_data;
-	enum pin_config_param param = pinconf_to_config_param(*config);
-	u32 val;
-
-	/* Skip reserved pin */
-	if (!data)
-		return -EINVAL;
-
-	val = readl(zpctl->aux_base + data->coffset);
-	val = val >> data->cbitpos;
-
-	switch (param) {
-	case PIN_CONFIG_BIAS_PULL_DOWN:
-		val &= ZX_PULL_DOWN;
-		val = !!val;
-		if (val == 0)
-			return -EINVAL;
-		break;
-	case PIN_CONFIG_BIAS_PULL_UP:
-		val &= ZX_PULL_UP;
-		val = !!val;
-		if (val == 0)
-			return -EINVAL;
-		break;
-	case PIN_CONFIG_INPUT_ENABLE:
-		val &= ZX_INPUT_ENABLE;
-		val = !!val;
-		if (val == 0)
-			return -EINVAL;
-		break;
-	case PIN_CONFIG_DRIVE_STRENGTH:
-		val &= ZX_DS_MASK;
-		val = val >> ZX_DS_SHIFT;
-		break;
-	case PIN_CONFIG_SLEW_RATE:
-		val &= ZX_SLEW;
-		val = !!val;
-		break;
-	default:
-		return -ENOTSUPP;
-	}
-
-	*config = pinconf_to_config_packed(param, val);
-
-	return 0;
-}
-
-static int zx_pin_config_set(struct pinctrl_dev *pctldev, unsigned int pin,
-			     unsigned long *configs, unsigned int num_configs)
-{
-	struct zx_pinctrl *zpctl = pinctrl_dev_get_drvdata(pctldev);
-	struct zx_pinctrl_soc_info *info = zpctl->info;
-	const struct pinctrl_pin_desc *pindesc = info->pins + pin;
-	struct zx_pin_data *data = pindesc->drv_data;
-	enum pin_config_param param;
-	u32 val, arg;
-	int i;
-
-	/* Skip reserved pin */
-	if (!data)
-		return -EINVAL;
-
-	val = readl(zpctl->aux_base + data->coffset);
-
-	for (i = 0; i < num_configs; i++) {
-		param = pinconf_to_config_param(configs[i]);
-		arg = pinconf_to_config_argument(configs[i]);
-
-		switch (param) {
-		case PIN_CONFIG_BIAS_PULL_DOWN:
-			val |= ZX_PULL_DOWN << data->cbitpos;
-			break;
-		case PIN_CONFIG_BIAS_PULL_UP:
-			val |= ZX_PULL_UP << data->cbitpos;
-			break;
-		case PIN_CONFIG_INPUT_ENABLE:
-			val |= ZX_INPUT_ENABLE << data->cbitpos;
-			break;
-		case PIN_CONFIG_DRIVE_STRENGTH:
-			val &= ~(ZX_DS_MASK << data->cbitpos);
-			val |= ZX_DS_VALUE(arg) << data->cbitpos;
-			break;
-		case PIN_CONFIG_SLEW_RATE:
-			if (arg)
-				val |= ZX_SLEW << data->cbitpos;
-			else
-				val &= ~ZX_SLEW << data->cbitpos;
-			break;
-		default:
-			return -ENOTSUPP;
-		}
-	}
-
-	writel(val, zpctl->aux_base + data->coffset);
-	return 0;
-}
-
-static const struct pinconf_ops zx_pinconf_ops = {
-	.pin_config_set = zx_pin_config_set,
-	.pin_config_get = zx_pin_config_get,
-	.is_generic = true,
-};
-
-static int zx_pinctrl_build_state(struct platform_device *pdev)
-{
-	struct zx_pinctrl *zpctl = platform_get_drvdata(pdev);
-	struct zx_pinctrl_soc_info *info = zpctl->info;
-	struct pinctrl_dev *pctldev = zpctl->pctldev;
-	struct function_desc *functions;
-	int nfunctions;
-	struct group_desc *groups;
-	int ngroups;
-	int i;
-
-	/* Every single pin composes a group */
-	ngroups = info->npins;
-	groups = devm_kcalloc(&pdev->dev, ngroups, sizeof(*groups),
-			      GFP_KERNEL);
-	if (!groups)
-		return -ENOMEM;
-
-	for (i = 0; i < ngroups; i++) {
-		const struct pinctrl_pin_desc *pindesc = info->pins + i;
-		struct group_desc *group = groups + i;
-
-		group->name = pindesc->name;
-		group->pins = (int *) &pindesc->number;
-		group->num_pins = 1;
-		radix_tree_insert(&pctldev->pin_group_tree, i, group);
-	}
-
-	pctldev->num_groups = ngroups;
-
-	/* Build function list from pin mux functions */
-	functions = kcalloc(info->npins, sizeof(*functions), GFP_KERNEL);
-	if (!functions)
-		return -ENOMEM;
-
-	nfunctions = 0;
-	for (i = 0; i < info->npins; i++) {
-		const struct pinctrl_pin_desc *pindesc = info->pins + i;
-		struct zx_pin_data *data = pindesc->drv_data;
-		struct zx_mux_desc *mux;
-
-		/* Reserved pins do not have a drv_data at all */
-		if (!data)
-			continue;
-
-		/* Loop over all muxes for the pin */
-		mux = data->muxes;
-		while (mux->name) {
-			struct function_desc *func = functions;
-
-			/* Search function list for given mux */
-			while (func->name) {
-				if (strcmp(mux->name, func->name) == 0) {
-					/* Function exists */
-					func->num_group_names++;
-					break;
-				}
-				func++;
-			}
-
-			if (!func->name) {
-				/* New function */
-				func->name = mux->name;
-				func->num_group_names = 1;
-				radix_tree_insert(&pctldev->pin_function_tree,
-						  nfunctions++, func);
-			}
-
-			mux++;
-		}
-	}
-
-	pctldev->num_functions = nfunctions;
-	functions = krealloc(functions, nfunctions * sizeof(*functions),
-			     GFP_KERNEL);
-
-	/* Find pin groups for every single function */
-	for (i = 0; i < info->npins; i++) {
-		const struct pinctrl_pin_desc *pindesc = info->pins + i;
-		struct zx_pin_data *data = pindesc->drv_data;
-		struct zx_mux_desc *mux;
-
-		if (!data)
-			continue;
-
-		mux = data->muxes;
-		while (mux->name) {
-			struct function_desc *func;
-			const char **group;
-			int j;
-
-			/* Find function for given mux */
-			for (j = 0; j < nfunctions; j++)
-				if (strcmp(functions[j].name, mux->name) == 0)
-					break;
-
-			func = functions + j;
-			if (!func->group_names) {
-				func->group_names = devm_kcalloc(&pdev->dev,
-						func->num_group_names,
-						sizeof(*func->group_names),
-						GFP_KERNEL);
-				if (!func->group_names) {
-					kfree(functions);
-					return -ENOMEM;
-				}
-			}
-
-			group = func->group_names;
-			while (*group)
-				group++;
-			*group = pindesc->name;
-
-			mux++;
-		}
-	}
-
-	return 0;
-}
-
-int zx_pinctrl_init(struct platform_device *pdev,
-		    struct zx_pinctrl_soc_info *info)
-{
-	struct pinctrl_desc *pctldesc;
-	struct zx_pinctrl *zpctl;
-	struct device_node *np;
-	int ret;
-
-	zpctl = devm_kzalloc(&pdev->dev, sizeof(*zpctl), GFP_KERNEL);
-	if (!zpctl)
-		return -ENOMEM;
-
-	spin_lock_init(&zpctl->lock);
-
-	zpctl->base = devm_platform_ioremap_resource(pdev, 0);
-	if (IS_ERR(zpctl->base))
-		return PTR_ERR(zpctl->base);
-
-	np = of_parse_phandle(pdev->dev.of_node, "zte,auxiliary-controller", 0);
-	if (!np) {
-		dev_err(&pdev->dev, "failed to find auxiliary controller\n");
-		return -ENODEV;
-	}
-
-	zpctl->aux_base = of_iomap(np, 0);
-	of_node_put(np);
-	if (!zpctl->aux_base)
-		return -ENOMEM;
-
-	zpctl->dev = &pdev->dev;
-	zpctl->info = info;
-
-	pctldesc = devm_kzalloc(&pdev->dev, sizeof(*pctldesc), GFP_KERNEL);
-	if (!pctldesc)
-		return -ENOMEM;
-
-	pctldesc->name = dev_name(&pdev->dev);
-	pctldesc->owner = THIS_MODULE;
-	pctldesc->pins = info->pins;
-	pctldesc->npins = info->npins;
-	pctldesc->pctlops = &zx_pinctrl_ops;
-	pctldesc->pmxops = &zx_pinmux_ops;
-	pctldesc->confops = &zx_pinconf_ops;
-
-	zpctl->pctldev = devm_pinctrl_register(&pdev->dev, pctldesc, zpctl);
-	if (IS_ERR(zpctl->pctldev)) {
-		ret = PTR_ERR(zpctl->pctldev);
-		dev_err(&pdev->dev, "failed to register pinctrl: %d\n", ret);
-		return ret;
-	}
-
-	platform_set_drvdata(pdev, zpctl);
-
-	ret = zx_pinctrl_build_state(pdev);
-	if (ret) {
-		dev_err(&pdev->dev, "failed to build state: %d\n", ret);
-		return ret;
-	}
-
-	dev_info(&pdev->dev, "initialized pinctrl driver\n");
-	return 0;
-}
diff --git a/drivers/pinctrl/zte/pinctrl-zx.h b/drivers/pinctrl/zte/pinctrl-zx.h
deleted file mode 100644
index a0692e2e9012..000000000000
--- a/drivers/pinctrl/zte/pinctrl-zx.h
+++ /dev/null
@@ -1,102 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * Copyright (C) 2017 Sanechips Technology Co., Ltd.
- * Copyright 2017 Linaro Ltd.
- */
-
-#ifndef __PINCTRL_ZX_H
-#define __PINCTRL_ZX_H
-
-/**
- * struct zx_mux_desc - hardware mux descriptor
- * @name: mux function name
- * @muxval: mux register bit value
- */
-struct zx_mux_desc {
-	const char *name;
-	u8 muxval;
-};
-
-/**
- * struct zx_pin_data - hardware per-pin data
- * @aon_pin: whether it's an AON pin
- * @offset: register offset within TOP pinmux controller
- * @bitpos: bit position within TOP pinmux register
- * @width: bit width within TOP pinmux register
- * @coffset: pinconf register offset within AON controller
- * @cbitpos: pinconf bit position within AON register
- * @muxes: available mux function names and corresponding register values
- *
- * Unlike TOP pinmux and AON pinconf registers which are arranged pretty
- * arbitrarily, AON pinmux register bits are well organized per pin id, and
- * each pin occupies two bits, so that we can calculate the AON register offset
- * and bit position from pin id.  Thus, we only need to define TOP pinmux and
- * AON pinconf register data for the pin.
- */
-struct zx_pin_data {
-	bool aon_pin;
-	u16 offset;
-	u16 bitpos;
-	u16 width;
-	u16 coffset;
-	u16 cbitpos;
-	struct zx_mux_desc *muxes;
-};
-
-struct zx_pinctrl_soc_info {
-	const struct pinctrl_pin_desc *pins;
-	unsigned int npins;
-};
-
-#define TOP_PIN(pin, off, bp, wd, coff, cbp, ...) {		\
-	.number = pin,						\
-	.name = #pin,						\
-	.drv_data = &(struct zx_pin_data) {			\
-		.aon_pin = false,				\
-		.offset = off,					\
-		.bitpos = bp,					\
-		.width = wd,					\
-		.coffset = coff,				\
-		.cbitpos = cbp,					\
-		.muxes = (struct zx_mux_desc[]) {		\
-			 __VA_ARGS__, { } },			\
-	},							\
-}
-
-#define AON_PIN(pin, off, bp, wd, coff, cbp, ...) {		\
-	.number = pin,						\
-	.name = #pin,						\
-	.drv_data = &(struct zx_pin_data) {			\
-		.aon_pin = true,				\
-		.offset = off,					\
-		.bitpos = bp,					\
-		.width = wd,					\
-		.coffset = coff,				\
-		.cbitpos = cbp,					\
-		.muxes = (struct zx_mux_desc[]) {		\
-			 __VA_ARGS__, { } },			\
-	},							\
-}
-
-#define ZX_RESERVED(pin) PINCTRL_PIN(pin, #pin)
-
-#define TOP_MUX(_val, _name) {					\
-	.name = _name,						\
-	.muxval = _val,						\
-}
-
-/*
- * When the flag is set, it's a mux configuration for an AON pin that sits in
- * AON register.  Otherwise, it's one for AON pin but sitting in TOP register.
- */
-#define AON_MUX_FLAG BIT(7)
-
-#define AON_MUX(_val, _name) {					\
-	.name = _name,						\
-	.muxval = _val | AON_MUX_FLAG,				\
-}
-
-int zx_pinctrl_init(struct platform_device *pdev,
-		    struct zx_pinctrl_soc_info *info);
-
-#endif /* __PINCTRL_ZX_H */
diff --git a/drivers/pinctrl/zte/pinctrl-zx296718.c b/drivers/pinctrl/zte/pinctrl-zx296718.c
deleted file mode 100644
index c980aecb6f2f..000000000000
--- a/drivers/pinctrl/zte/pinctrl-zx296718.c
+++ /dev/null
@@ -1,1024 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Copyright (C) 2017 Sanechips Technology Co., Ltd.
- * Copyright 2017 Linaro Ltd.
- */
-
-#include <linux/module.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-#include <linux/of_device.h>
-#include <linux/pinctrl/pinctrl.h>
-#include <linux/platform_device.h>
-
-#include "pinctrl-zx.h"
-
-#define TOP_REG0	0x00
-#define TOP_REG1	0x04
-#define TOP_REG2	0x08
-#define TOP_REG3	0x0c
-#define TOP_REG4	0x10
-#define TOP_REG5	0x14
-#define TOP_REG6	0x18
-#define TOP_REG7	0x1c
-#define TOP_REG8	0x20
-
-/*
- * The pin numbering starts from AON pins with reserved ones included,
- * so that register data like offset and bit position for AON pins can
- * be calculated from pin number.
- */
-enum zx296718_pin {
-	/* aon_pmm_reg_0 */
-	I2C3_SCL = 0,
-	I2C3_SDA = 1,
-	AON_RESERVED0 = 2,
-	AON_RESERVED1 = 3,
-	SEC_EN = 4,
-	UART0_RXD = 5,
-	UART0_TXD = 6,
-	IR_IN = 7,
-	SPI0_CLK = 8,
-	SPI0_CS = 9,
-	SPI0_TXD = 10,
-	SPI0_RXD = 11,
-	KEY_COL0 = 12,
-	KEY_COL1 = 13,
-	KEY_COL2 = 14,
-	KEY_ROW0 = 15,
-
-	/* aon_pmm_reg_1 */
-	KEY_ROW1 = 16,
-	KEY_ROW2 = 17,
-	HDMI_SCL = 18,
-	HDMI_SDA = 19,
-	JTAG_TCK = 20,
-	JTAG_TRSTN = 21,
-	JTAG_TMS = 22,
-	JTAG_TDI = 23,
-	JTAG_TDO = 24,
-	I2C0_SCL = 25,
-	I2C0_SDA = 26,
-	I2C1_SCL = 27,
-	I2C1_SDA = 28,
-	AON_RESERVED2 = 29,
-	AON_RESERVED3 = 30,
-	AON_RESERVED4 = 31,
-
-	/* aon_pmm_reg_2 */
-	SPI1_CLK = 32,
-	SPI1_CS = 33,
-	SPI1_TXD = 34,
-	SPI1_RXD = 35,
-	AON_RESERVED5 = 36,
-	AON_RESERVED6 = 37,
-	AUDIO_DET = 38,
-	SPDIF_OUT = 39,
-	HDMI_CEC = 40,
-	HDMI_HPD = 41,
-	GMAC_25M_OUT = 42,
-	BOOT_SEL0 = 43,
-	BOOT_SEL1 = 44,
-	BOOT_SEL2 = 45,
-	DEEP_SLEEP_OUT_N = 46,
-	AON_RESERVED7 = 47,
-
-	/* top_pmm_reg_0 */
-	GMII_GTX_CLK = 48,
-	GMII_TX_CLK = 49,
-	GMII_TXD0 = 50,
-	GMII_TXD1 = 51,
-	GMII_TXD2 = 52,
-	GMII_TXD3 = 53,
-	GMII_TXD4 = 54,
-	GMII_TXD5 = 55,
-	GMII_TXD6 = 56,
-	GMII_TXD7 = 57,
-	GMII_TX_ER = 58,
-	GMII_TX_EN = 59,
-	GMII_RX_CLK = 60,
-	GMII_RXD0 = 61,
-	GMII_RXD1 = 62,
-	GMII_RXD2 = 63,
-
-	/* top_pmm_reg_1 */
-	GMII_RXD3 = 64,
-	GMII_RXD4 = 65,
-	GMII_RXD5 = 66,
-	GMII_RXD6 = 67,
-	GMII_RXD7 = 68,
-	GMII_RX_ER = 69,
-	GMII_RX_DV = 70,
-	GMII_COL = 71,
-	GMII_CRS = 72,
-	GMII_MDC = 73,
-	GMII_MDIO = 74,
-	SDIO1_CLK = 75,
-	SDIO1_CMD = 76,
-	SDIO1_DATA0 = 77,
-	SDIO1_DATA1 = 78,
-	SDIO1_DATA2 = 79,
-
-	/* top_pmm_reg_2 */
-	SDIO1_DATA3 = 80,
-	SDIO1_CD = 81,
-	SDIO1_WP = 82,
-	USIM1_CD = 83,
-	USIM1_CLK = 84,
-	USIM1_RST = 85,
-
-	/* top_pmm_reg_3 */
-	USIM1_DATA = 86,
-	SDIO0_CLK = 87,
-	SDIO0_CMD = 88,
-	SDIO0_DATA0 = 89,
-	SDIO0_DATA1 = 90,
-	SDIO0_DATA2 = 91,
-	SDIO0_DATA3 = 92,
-	SDIO0_CD = 93,
-	SDIO0_WP = 94,
-
-	/* top_pmm_reg_4 */
-	TSI0_DATA0 = 95,
-	SPINOR_CLK = 96,
-	TSI2_DATA = 97,
-	TSI2_CLK = 98,
-	TSI2_SYNC = 99,
-	TSI2_VALID = 100,
-	SPINOR_CS = 101,
-	SPINOR_DQ0 = 102,
-	SPINOR_DQ1 = 103,
-	SPINOR_DQ2 = 104,
-	SPINOR_DQ3 = 105,
-	VGA_HS = 106,
-	VGA_VS = 107,
-	TSI3_DATA = 108,
-
-	/* top_pmm_reg_5 */
-	TSI3_CLK = 109,
-	TSI3_SYNC = 110,
-	TSI3_VALID = 111,
-	I2S1_WS = 112,
-	I2S1_BCLK = 113,
-	I2S1_MCLK = 114,
-	I2S1_DIN0 = 115,
-	I2S1_DOUT0 = 116,
-	SPI3_CLK = 117,
-	SPI3_CS = 118,
-	SPI3_TXD = 119,
-	NAND_LDO_MS18_SEL = 120,
-
-	/* top_pmm_reg_6 */
-	SPI3_RXD = 121,
-	I2S0_MCLK = 122,
-	I2S0_BCLK = 123,
-	I2S0_WS = 124,
-	I2S0_DIN0 = 125,
-	I2S0_DOUT0 = 126,
-	I2C5_SCL = 127,
-	I2C5_SDA = 128,
-	SPI2_CLK = 129,
-	SPI2_CS = 130,
-	SPI2_TXD = 131,
-
-	/* top_pmm_reg_7 */
-	SPI2_RXD = 132,
-	NAND_WP_N = 133,
-	NAND_PAGE_SIZE0 = 134,
-	NAND_PAGE_SIZE1 = 135,
-	NAND_ADDR_CYCLE = 136,
-	NAND_RB0 = 137,
-	NAND_RB1 = 138,
-	NAND_RB2 = 139,
-	NAND_RB3 = 140,
-
-	/* top_pmm_reg_8 */
-	GMAC_125M_IN = 141,
-	GMAC_50M_OUT = 142,
-	SPINOR_SSCLK_LOOPBACK = 143,
-	SPINOR_SDIO1CLK_LOOPBACK = 144,
-};
-
-static const struct pinctrl_pin_desc zx296718_pins[] = {
-	/* aon_pmm_reg_0 */
-	AON_PIN(I2C3_SCL, TOP_REG2, 18, 2, 0x48, 0,
-		AON_MUX(0x0, "ANMI"),		/* anmi */
-		AON_MUX(0x1, "AGPIO"),		/* agpio29 */
-		AON_MUX(0x2, "nonAON"),		/* pin0 */
-		AON_MUX(0x3, "EXT_INT"),	/* int4 */
-		TOP_MUX(0x0, "I2C3"),		/* scl */
-		TOP_MUX(0x1, "SPI2"),		/* txd */
-		TOP_MUX(0x2, "I2S1")),		/* din0 */
-	AON_PIN(I2C3_SDA, TOP_REG2, 20, 2, 0x48, 9,
-		AON_MUX(0x0, "WD"),		/* rst_b */
-		AON_MUX(0x1, "AGPIO"),		/* agpio30 */
-		AON_MUX(0x2, "nonAON"),		/* pin1 */
-		AON_MUX(0x3, "EXT_INT"),	/* int5 */
-		TOP_MUX(0x0, "I2C3"),		/* sda */
-		TOP_MUX(0x1, "SPI2"),		/* rxd */
-		TOP_MUX(0x2, "I2S0")),		/* mclk */
-	ZX_RESERVED(AON_RESERVED0),
-	ZX_RESERVED(AON_RESERVED1),
-	AON_PIN(SEC_EN, TOP_REG3, 5, 1, 0x50, 0,
-		AON_MUX(0x0, "SEC"),		/* en */
-		AON_MUX(0x1, "AGPIO"),		/* agpio28 */
-		AON_MUX(0x2, "nonAON"),		/* pin3 */
-		AON_MUX(0x3, "EXT_INT"),	/* int7 */
-		TOP_MUX(0x0, "I2C2"),		/* sda */
-		TOP_MUX(0x1, "SPI2")),		/* cs */
-	AON_PIN(UART0_RXD, 0, 0, 0, 0x50, 9,
-		AON_MUX(0x0, "UART0"),		/* rxd */
-		AON_MUX(0x1, "AGPIO"),		/* agpio20 */
-		AON_MUX(0x2, "nonAON")),	/* pin34 */
-	AON_PIN(UART0_TXD, 0, 0, 0, 0x50, 18,
-		AON_MUX(0x0, "UART0"),		/* txd */
-		AON_MUX(0x1, "AGPIO"),		/* agpio21 */
-		AON_MUX(0x2, "nonAON")),	/* pin32 */
-	AON_PIN(IR_IN, 0, 0, 0, 0x64, 0,
-		AON_MUX(0x0, "IR"),		/* in */
-		AON_MUX(0x1, "AGPIO"),		/* agpio0 */
-		AON_MUX(0x2, "nonAON")),	/* pin27 */
-	AON_PIN(SPI0_CLK, TOP_REG3, 16, 1, 0x64, 9,
-		AON_MUX(0x0, "EXT_INT"),	/* int0 */
-		AON_MUX(0x1, "AGPIO"),		/* agpio23 */
-		AON_MUX(0x2, "nonAON"),		/* pin5 */
-		AON_MUX(0x3, "PCU"),		/* test6 */
-		TOP_MUX(0x0, "SPI0"),		/* clk */
-		TOP_MUX(0x1, "ISP")),		/* flash_trig */
-	AON_PIN(SPI0_CS, TOP_REG3, 17, 1, 0x64, 18,
-		AON_MUX(0x0, "EXT_INT"),	/* int1 */
-		AON_MUX(0x1, "AGPIO"),		/* agpio24 */
-		AON_MUX(0x2, "nonAON"),		/* pin6 */
-		AON_MUX(0x3, "PCU"),		/* test0 */
-		TOP_MUX(0x0, "SPI0"),		/* cs */
-		TOP_MUX(0x1, "ISP")),		/* prelight_trig */
-	AON_PIN(SPI0_TXD, TOP_REG3, 18, 1, 0x68, 0,
-		AON_MUX(0x0, "EXT_INT"),	/* int2 */
-		AON_MUX(0x1, "AGPIO"),		/* agpio25 */
-		AON_MUX(0x2, "nonAON"),		/* pin7 */
-		AON_MUX(0x3, "PCU"),		/* test1 */
-		TOP_MUX(0x0, "SPI0"),		/* txd */
-		TOP_MUX(0x1, "ISP")),		/* shutter_trig */
-	AON_PIN(SPI0_RXD, TOP_REG3, 19, 1, 0x68, 9,
-		AON_MUX(0x0, "EXT_INT"),	/* int3 */
-		AON_MUX(0x1, "AGPIO"),		/* agpio26 */
-		AON_MUX(0x2, "nonAON"),		/* pin8 */
-		AON_MUX(0x3, "PCU"),		/* test2 */
-		TOP_MUX(0x0, "SPI0"),		/* rxd */
-		TOP_MUX(0x1, "ISP")),		/* shutter_open */
-	AON_PIN(KEY_COL0, TOP_REG3, 20, 1, 0x68, 18,
-		AON_MUX(0x0, "KEY"),		/* col0 */
-		AON_MUX(0x1, "AGPIO"),		/* agpio5 */
-		AON_MUX(0x2, "nonAON"),		/* pin9 */
-		AON_MUX(0x3, "PCU"),		/* test3 */
-		TOP_MUX(0x0, "UART3"),		/* rxd */
-		TOP_MUX(0x1, "I2S0")),		/* din1 */
-	AON_PIN(KEY_COL1, TOP_REG3, 21, 2, 0x6c, 0,
-		AON_MUX(0x0, "KEY"),		/* col1 */
-		AON_MUX(0x1, "AGPIO"),		/* agpio6 */
-		AON_MUX(0x2, "nonAON"),		/* pin10 */
-		TOP_MUX(0x0, "UART3"),		/* txd */
-		TOP_MUX(0x1, "I2S0"),		/* din2 */
-		TOP_MUX(0x2, "VGA")),		/* scl */
-	AON_PIN(KEY_COL2, TOP_REG3, 23, 2, 0x6c, 9,
-		AON_MUX(0x0, "KEY"),		/* col2 */
-		AON_MUX(0x1, "AGPIO"),		/* agpio7 */
-		AON_MUX(0x2, "nonAON"),		/* pin11 */
-		TOP_MUX(0x0, "PWM"),		/* out1 */
-		TOP_MUX(0x1, "I2S0"),		/* din3 */
-		TOP_MUX(0x2, "VGA")),		/* sda */
-	AON_PIN(KEY_ROW0, 0, 0, 0, 0x6c, 18,
-		AON_MUX(0x0, "KEY"),		/* row0 */
-		AON_MUX(0x1, "AGPIO"),		/* agpio8 */
-		AON_MUX(0x2, "nonAON"),		/* pin33 */
-		AON_MUX(0x3, "WD")),		/* rst_b */
-
-	/* aon_pmm_reg_1 */
-	AON_PIN(KEY_ROW1, TOP_REG3, 25, 2, 0x70, 0,
-		AON_MUX(0x0, "KEY"),		/* row1 */
-		AON_MUX(0x1, "AGPIO"),		/* agpio9 */
-		AON_MUX(0x2, "nonAON"),		/* pin12 */
-		TOP_MUX(0x0, "LCD"),		/* port0 lcd_te */
-		TOP_MUX(0x1, "I2S0"),		/* dout2 */
-		TOP_MUX(0x2, "PWM"),		/* out2 */
-		TOP_MUX(0x3, "VGA")),		/* hs1 */
-	AON_PIN(KEY_ROW2, TOP_REG3, 27, 2, 0x70, 9,
-		AON_MUX(0x0, "KEY"),		/* row2 */
-		AON_MUX(0x1, "AGPIO"),		/* agpio10 */
-		AON_MUX(0x2, "nonAON"),		/* pin13 */
-		TOP_MUX(0x0, "LCD"),		/* port1 lcd_te */
-		TOP_MUX(0x1, "I2S0"),		/* dout3 */
-		TOP_MUX(0x2, "PWM"),		/* out3 */
-		TOP_MUX(0x3, "VGA")),		/* vs1 */
-	AON_PIN(HDMI_SCL, TOP_REG3, 29, 1, 0x70, 18,
-		AON_MUX(0x0, "PCU"),		/* test7 */
-		AON_MUX(0x1, "AGPIO"),		/* agpio3 */
-		AON_MUX(0x2, "nonAON"),		/* pin14 */
-		TOP_MUX(0x0, "HDMI"),		/* scl */
-		TOP_MUX(0x1, "UART3")),		/* rxd */
-	AON_PIN(HDMI_SDA, TOP_REG3, 30, 1, 0x74, 0,
-		AON_MUX(0x0, "PCU"),		/* test8 */
-		AON_MUX(0x1, "AGPIO"),		/* agpio4 */
-		AON_MUX(0x2, "nonAON"),		/* pin15 */
-		TOP_MUX(0x0, "HDMI"),		/* sda */
-		TOP_MUX(0x1, "UART3")),		/* txd */
-	AON_PIN(JTAG_TCK, TOP_REG7, 3, 1, 0x78, 18,
-		AON_MUX(0x0, "JTAG"),		/* tck */
-		AON_MUX(0x1, "AGPIO"),		/* agpio11 */
-		AON_MUX(0x2, "nonAON"),		/* pin22 */
-		AON_MUX(0x3, "EXT_INT"),	/* int4 */
-		TOP_MUX(0x0, "SPI4"),		/* clk */
-		TOP_MUX(0x1, "UART1")),		/* rxd */
-	AON_PIN(JTAG_TRSTN, TOP_REG7, 4, 1, 0xac, 0,
-		AON_MUX(0x0, "JTAG"),		/* trstn */
-		AON_MUX(0x1, "AGPIO"),		/* agpio12 */
-		AON_MUX(0x2, "nonAON"),		/* pin23 */
-		AON_MUX(0x3, "EXT_INT"),	/* int5 */
-		TOP_MUX(0x0, "SPI4"),		/* cs */
-		TOP_MUX(0x1, "UART1")),		/* txd */
-	AON_PIN(JTAG_TMS, TOP_REG7, 5, 1, 0xac, 9,
-		AON_MUX(0x0, "JTAG"),		/* tms */
-		AON_MUX(0x1, "AGPIO"),		/* agpio13 */
-		AON_MUX(0x2, "nonAON"),		/* pin24 */
-		AON_MUX(0x3, "EXT_INT"),	/* int6 */
-		TOP_MUX(0x0, "SPI4"),		/* txd */
-		TOP_MUX(0x1, "UART2")),		/* rxd */
-	AON_PIN(JTAG_TDI, TOP_REG7, 6, 1, 0xac, 18,
-		AON_MUX(0x0, "JTAG"),		/* tdi */
-		AON_MUX(0x1, "AGPIO"),		/* agpio14 */
-		AON_MUX(0x2, "nonAON"),		/* pin25 */
-		AON_MUX(0x3, "EXT_INT"),	/* int7 */
-		TOP_MUX(0x0, "SPI4"),		/* rxd */
-		TOP_MUX(0x1, "UART2")),		/* txd */
-	AON_PIN(JTAG_TDO, 0, 0, 0, 0xb0, 0,
-		AON_MUX(0x0, "JTAG"),		/* tdo */
-		AON_MUX(0x1, "AGPIO"),		/* agpio15 */
-		AON_MUX(0x2, "nonAON")),	/* pin26 */
-	AON_PIN(I2C0_SCL, 0, 0, 0, 0xb0, 9,
-		AON_MUX(0x0, "I2C0"),		/* scl */
-		AON_MUX(0x1, "AGPIO"),		/* agpio16 */
-		AON_MUX(0x2, "nonAON")),	/* pin28 */
-	AON_PIN(I2C0_SDA, 0, 0, 0, 0xb0, 18,
-		AON_MUX(0x0, "I2C0"),		/* sda */
-		AON_MUX(0x1, "AGPIO"),		/* agpio17 */
-		AON_MUX(0x2, "nonAON")),	/* pin29 */
-	AON_PIN(I2C1_SCL, TOP_REG8, 4, 1, 0xb4, 0,
-		AON_MUX(0x0, "I2C1"),		/* scl */
-		AON_MUX(0x1, "AGPIO"),		/* agpio18 */
-		AON_MUX(0x2, "nonAON"),		/* pin30 */
-		TOP_MUX(0x0, "LCD")),		/* port0 lcd_te */
-	AON_PIN(I2C1_SDA, TOP_REG8, 5, 1, 0xb4, 9,
-		AON_MUX(0x0, "I2C1"),		/* sda */
-		AON_MUX(0x1, "AGPIO"),		/* agpio19 */
-		AON_MUX(0x2, "nonAON"),		/* pin31 */
-		TOP_MUX(0x0, "LCD")),		/* port1 lcd_te */
-	ZX_RESERVED(AON_RESERVED2),
-	ZX_RESERVED(AON_RESERVED3),
-	ZX_RESERVED(AON_RESERVED4),
-
-	/* aon_pmm_reg_2 */
-	AON_PIN(SPI1_CLK, TOP_REG2, 6, 3, 0x40, 9,
-		AON_MUX(0x0, "EXT_INT"),	/* int0 */
-		AON_MUX(0x1, "PCU"),		/* test12 */
-		AON_MUX(0x2, "nonAON"),		/* pin39 */
-		TOP_MUX(0x0, "SPI1"),		/* clk */
-		TOP_MUX(0x1, "PCM"),		/* clk */
-		TOP_MUX(0x2, "BGPIO"),		/* gpio35 */
-		TOP_MUX(0x3, "I2C4"),		/* scl */
-		TOP_MUX(0x4, "I2S1"),		/* mclk */
-		TOP_MUX(0x5, "ISP")),		/* flash_trig */
-	AON_PIN(SPI1_CS, TOP_REG2, 9, 3, 0x40, 18,
-		AON_MUX(0x0, "EXT_INT"),	/* int1 */
-		AON_MUX(0x1, "PCU"),		/* test13 */
-		AON_MUX(0x2, "nonAON"),		/* pin40 */
-		TOP_MUX(0x0, "SPI1"),		/* cs */
-		TOP_MUX(0x1, "PCM"),		/* fs */
-		TOP_MUX(0x2, "BGPIO"),		/* gpio36 */
-		TOP_MUX(0x3, "I2C4"),		/* sda */
-		TOP_MUX(0x4, "I2S1"),		/* bclk */
-		TOP_MUX(0x5, "ISP")),		/* prelight_trig */
-	AON_PIN(SPI1_TXD, TOP_REG2, 12, 3, 0x44, 0,
-		AON_MUX(0x0, "EXT_INT"),	/* int2 */
-		AON_MUX(0x1, "PCU"),		/* test14 */
-		AON_MUX(0x2, "nonAON"),		/* pin41 */
-		TOP_MUX(0x0, "SPI1"),		/* txd */
-		TOP_MUX(0x1, "PCM"),		/* txd */
-		TOP_MUX(0x2, "BGPIO"),		/* gpio37 */
-		TOP_MUX(0x3, "UART5"),		/* rxd */
-		TOP_MUX(0x4, "I2S1"),		/* ws */
-		TOP_MUX(0x5, "ISP")),		/* shutter_trig */
-	AON_PIN(SPI1_RXD, TOP_REG2, 15, 3, 0x44, 9,
-		AON_MUX(0x0, "EXT_INT"),	/* int3 */
-		AON_MUX(0x1, "PCU"),		/* test15 */
-		AON_MUX(0x2, "nonAON"),		/* pin42 */
-		TOP_MUX(0x0, "SPI1"),		/* rxd */
-		TOP_MUX(0x1, "PCM"),		/* rxd */
-		TOP_MUX(0x2, "BGPIO"),		/* gpio38 */
-		TOP_MUX(0x3, "UART5"),		/* txd */
-		TOP_MUX(0x4, "I2S1"),		/* dout0 */
-		TOP_MUX(0x5, "ISP")),		/* shutter_open */
-	ZX_RESERVED(AON_RESERVED5),
-	ZX_RESERVED(AON_RESERVED6),
-	AON_PIN(AUDIO_DET, TOP_REG3, 3, 2, 0x48, 18,
-		AON_MUX(0x0, "PCU"),		/* test4 */
-		AON_MUX(0x1, "AGPIO"),		/* agpio27 */
-		AON_MUX(0x2, "nonAON"),		/* pin2 */
-		AON_MUX(0x3, "EXT_INT"),	/* int16 */
-		TOP_MUX(0x0, "AUDIO"),		/* detect */
-		TOP_MUX(0x1, "I2C2"),		/* scl */
-		TOP_MUX(0x2, "SPI2")),		/* clk */
-	AON_PIN(SPDIF_OUT, TOP_REG3, 14, 2, 0x78, 9,
-		AON_MUX(0x0, "PCU"),		/* test5 */
-		AON_MUX(0x1, "AGPIO"),		/* agpio22 */
-		AON_MUX(0x2, "nonAON"),		/* pin4 */
-		TOP_MUX(0x0, "SPDIF"),		/* out */
-		TOP_MUX(0x1, "PWM"),		/* out0 */
-		TOP_MUX(0x2, "ISP")),		/* fl_trig */
-	AON_PIN(HDMI_CEC, 0, 0, 0, 0x74, 9,
-		AON_MUX(0x0, "PCU"),		/* test9 */
-		AON_MUX(0x1, "AGPIO"),		/* agpio1 */
-		AON_MUX(0x2, "nonAON")),	/* pin16 */
-	AON_PIN(HDMI_HPD, 0, 0, 0, 0x74, 18,
-		AON_MUX(0x0, "PCU"),		/* test10 */
-		AON_MUX(0x1, "AGPIO"),		/* agpio2 */
-		AON_MUX(0x2, "nonAON")),	/* pin17 */
-	AON_PIN(GMAC_25M_OUT, 0, 0, 0, 0x78, 0,
-		AON_MUX(0x0, "PCU"),		/* test11 */
-		AON_MUX(0x1, "AGPIO"),		/* agpio31 */
-		AON_MUX(0x2, "nonAON")),	/* pin43 */
-	AON_PIN(BOOT_SEL0, 0, 0, 0, 0xc0, 9,
-		AON_MUX(0x0, "BOOT"),		/* sel0 */
-		AON_MUX(0x1, "AGPIO"),		/* agpio18 */
-		AON_MUX(0x2, "nonAON")),	/* pin18 */
-	AON_PIN(BOOT_SEL1, 0, 0, 0, 0xc0, 18,
-		AON_MUX(0x0, "BOOT"),		/* sel1 */
-		AON_MUX(0x1, "AGPIO"),		/* agpio19 */
-		AON_MUX(0x2, "nonAON")),	/* pin19 */
-	AON_PIN(BOOT_SEL2, 0, 0, 0, 0xc4, 0,
-		AON_MUX(0x0, "BOOT"),		/* sel2 */
-		AON_MUX(0x1, "AGPIO"),		/* agpio20 */
-		AON_MUX(0x2, "nonAON")),	/* pin20 */
-	AON_PIN(DEEP_SLEEP_OUT_N, 0, 0, 0, 0xc4, 9,
-		AON_MUX(0x0, "DEEPSLP"),	/* deep sleep out_n */
-		AON_MUX(0x1, "AGPIO"),		/* agpio21 */
-		AON_MUX(0x2, "nonAON")),	/* pin21 */
-	ZX_RESERVED(AON_RESERVED7),
-
-	/* top_pmm_reg_0 */
-	TOP_PIN(GMII_GTX_CLK, TOP_REG0, 0, 2, 0x10, 0,
-		TOP_MUX(0x0, "GMII"),		/* gtx_clk */
-		TOP_MUX(0x1, "DVI0"),		/* clk */
-		TOP_MUX(0x2, "BGPIO")),		/* gpio0 */
-	TOP_PIN(GMII_TX_CLK, TOP_REG0, 2, 2, 0x10, 9,
-		TOP_MUX(0x0, "GMII"),		/* tx_clk */
-		TOP_MUX(0x1, "DVI0"),		/* vs */
-		TOP_MUX(0x2, "BGPIO")),		/* gpio1 */
-	TOP_PIN(GMII_TXD0, TOP_REG0, 4, 2, 0x10, 18,
-		TOP_MUX(0x0, "GMII"),		/* txd0 */
-		TOP_MUX(0x1, "DVI0"),		/* hs */
-		TOP_MUX(0x2, "BGPIO")),		/* gpio2 */
-	TOP_PIN(GMII_TXD1, TOP_REG0, 6, 2, 0x14, 0,
-		TOP_MUX(0x0, "GMII"),		/* txd1 */
-		TOP_MUX(0x1, "DVI0"),		/* d0 */
-		TOP_MUX(0x2, "BGPIO")),		/* gpio3 */
-	TOP_PIN(GMII_TXD2, TOP_REG0, 8, 2, 0x14, 9,
-		TOP_MUX(0x0, "GMII"),		/* txd2 */
-		TOP_MUX(0x1, "DVI0"),		/* d1 */
-		TOP_MUX(0x2, "BGPIO")),		/* gpio4 */
-	TOP_PIN(GMII_TXD3, TOP_REG0, 10, 2, 0x14, 18,
-		TOP_MUX(0x0, "GMII"),		/* txd3 */
-		TOP_MUX(0x1, "DVI0"),		/* d2 */
-		TOP_MUX(0x2, "BGPIO")),		/* gpio5 */
-	TOP_PIN(GMII_TXD4, TOP_REG0, 12, 2, 0x18, 0,
-		TOP_MUX(0x0, "GMII"),		/* txd4 */
-		TOP_MUX(0x1, "DVI0"),		/* d3 */
-		TOP_MUX(0x2, "BGPIO")),		/* gpio6 */
-	TOP_PIN(GMII_TXD5, TOP_REG0, 14, 2, 0x18, 9,
-		TOP_MUX(0x0, "GMII"),		/* txd5 */
-		TOP_MUX(0x1, "DVI0"),		/* d4 */
-		TOP_MUX(0x2, "BGPIO")),		/* gpio7 */
-	TOP_PIN(GMII_TXD6, TOP_REG0, 16, 2, 0x18, 18,
-		TOP_MUX(0x0, "GMII"),		/* txd6 */
-		TOP_MUX(0x1, "DVI0"),		/* d5 */
-		TOP_MUX(0x2, "BGPIO")),		/* gpio8 */
-	TOP_PIN(GMII_TXD7, TOP_REG0, 18, 2, 0x1c, 0,
-		TOP_MUX(0x0, "GMII"),		/* txd7 */
-		TOP_MUX(0x1, "DVI0"),		/* d6 */
-		TOP_MUX(0x2, "BGPIO")),		/* gpio9 */
-	TOP_PIN(GMII_TX_ER, TOP_REG0, 20, 2, 0x1c, 9,
-		TOP_MUX(0x0, "GMII"),		/* tx_er */
-		TOP_MUX(0x1, "DVI0"),		/* d7 */
-		TOP_MUX(0x2, "BGPIO")),		/* gpio10 */
-	TOP_PIN(GMII_TX_EN, TOP_REG0, 22, 2, 0x1c, 18,
-		TOP_MUX(0x0, "GMII"),		/* tx_en */
-		TOP_MUX(0x1, "DVI0"),		/* d8 */
-		TOP_MUX(0x3, "BGPIO")),		/* gpio11 */
-	TOP_PIN(GMII_RX_CLK, TOP_REG0, 24, 2, 0x20, 0,
-		TOP_MUX(0x0, "GMII"),		/* rx_clk */
-		TOP_MUX(0x1, "DVI0"),		/* d9 */
-		TOP_MUX(0x3, "BGPIO")),		/* gpio12 */
-	TOP_PIN(GMII_RXD0, TOP_REG0, 26, 2, 0x20, 9,
-		TOP_MUX(0x0, "GMII"),		/* rxd0 */
-		TOP_MUX(0x1, "DVI0"),		/* d10 */
-		TOP_MUX(0x3, "BGPIO")),		/* gpio13 */
-	TOP_PIN(GMII_RXD1, TOP_REG0, 28, 2, 0x20, 18,
-		TOP_MUX(0x0, "GMII"),		/* rxd1 */
-		TOP_MUX(0x1, "DVI0"),		/* d11 */
-		TOP_MUX(0x2, "BGPIO")),		/* gpio14 */
-	TOP_PIN(GMII_RXD2, TOP_REG0, 30, 2, 0x24, 0,
-		TOP_MUX(0x0, "GMII"),		/* rxd2 */
-		TOP_MUX(0x1, "DVI1"),		/* clk */
-		TOP_MUX(0x2, "BGPIO")),		/* gpio15 */
-
-	/* top_pmm_reg_1 */
-	TOP_PIN(GMII_RXD3, TOP_REG1, 0, 2, 0x24, 9,
-		TOP_MUX(0x0, "GMII"),		/* rxd3 */
-		TOP_MUX(0x1, "DVI1"),		/* hs */
-		TOP_MUX(0x2, "BGPIO")),		/* gpio16 */
-	TOP_PIN(GMII_RXD4, TOP_REG1, 2, 2, 0x24, 18,
-		TOP_MUX(0x0, "GMII"),		/* rxd4 */
-		TOP_MUX(0x1, "DVI1"),		/* vs */
-		TOP_MUX(0x2, "BGPIO")),		/* gpio17 */
-	TOP_PIN(GMII_RXD5, TOP_REG1, 4, 2, 0x28, 0,
-		TOP_MUX(0x0, "GMII"),		/* rxd5 */
-		TOP_MUX(0x1, "DVI1"),		/* d0 */
-		TOP_MUX(0x2, "BGPIO"),		/* gpio18 */
-		TOP_MUX(0x3, "TSI0")),		/* dat0 */
-	TOP_PIN(GMII_RXD6, TOP_REG1, 6, 2, 0x28, 9,
-		TOP_MUX(0x0, "GMII"),		/* rxd6 */
-		TOP_MUX(0x1, "DVI1"),		/* d1 */
-		TOP_MUX(0x2, "BGPIO"),		/* gpio19 */
-		TOP_MUX(0x3, "TSI0")),		/* clk */
-	TOP_PIN(GMII_RXD7, TOP_REG1, 8, 2, 0x28, 18,
-		TOP_MUX(0x0, "GMII"),		/* rxd7 */
-		TOP_MUX(0x1, "DVI1"),		/* d2 */
-		TOP_MUX(0x2, "BGPIO"),		/* gpio20 */
-		TOP_MUX(0x3, "TSI0")),		/* sync */
-	TOP_PIN(GMII_RX_ER, TOP_REG1, 10, 2, 0x2c, 0,
-		TOP_MUX(0x0, "GMII"),		/* rx_er */
-		TOP_MUX(0x1, "DVI1"),		/* d3 */
-		TOP_MUX(0x2, "BGPIO"),		/* gpio21 */
-		TOP_MUX(0x3, "TSI0")),		/* valid */
-	TOP_PIN(GMII_RX_DV, TOP_REG1, 12, 2, 0x2c, 9,
-		TOP_MUX(0x0, "GMII"),		/* rx_dv */
-		TOP_MUX(0x1, "DVI1"),		/* d4 */
-		TOP_MUX(0x2, "BGPIO"),		/* gpio22 */
-		TOP_MUX(0x3, "TSI1")),		/* dat0 */
-	TOP_PIN(GMII_COL, TOP_REG1, 14, 2, 0x2c, 18,
-		TOP_MUX(0x0, "GMII"),		/* col */
-		TOP_MUX(0x1, "DVI1"),		/* d5 */
-		TOP_MUX(0x2, "BGPIO"),		/* gpio23 */
-		TOP_MUX(0x3, "TSI1")),		/* clk */
-	TOP_PIN(GMII_CRS, TOP_REG1, 16, 2, 0x30, 0,
-		TOP_MUX(0x0, "GMII"),		/* crs */
-		TOP_MUX(0x1, "DVI1"),		/* d6 */
-		TOP_MUX(0x2, "BGPIO"),		/* gpio24 */
-		TOP_MUX(0x3, "TSI1")),		/* sync */
-	TOP_PIN(GMII_MDC, TOP_REG1, 18, 2, 0x30, 9,
-		TOP_MUX(0x0, "GMII"),		/* mdc */
-		TOP_MUX(0x1, "DVI1"),		/* d7 */
-		TOP_MUX(0x2, "BGPIO"),		/* gpio25 */
-		TOP_MUX(0x3, "TSI1")),		/* valid */
-	TOP_PIN(GMII_MDIO, TOP_REG1, 20, 1, 0x30, 18,
-		TOP_MUX(0x0, "GMII"),		/* mdio */
-		TOP_MUX(0x2, "BGPIO")),		/* gpio26 */
-	TOP_PIN(SDIO1_CLK, TOP_REG1, 21, 2, 0x34, 18,
-		TOP_MUX(0x0, "SDIO1"),		/* clk */
-		TOP_MUX(0x1, "USIM0"),		/* clk */
-		TOP_MUX(0x2, "BGPIO"),		/* gpio27 */
-		TOP_MUX(0x3, "SPINOR")),	/* clk */
-	TOP_PIN(SDIO1_CMD, TOP_REG1, 23, 2, 0x38, 0,
-		TOP_MUX(0x0, "SDIO1"),		/* cmd */
-		TOP_MUX(0x1, "USIM0"),		/* cd */
-		TOP_MUX(0x2, "BGPIO"),		/* gpio28 */
-		TOP_MUX(0x3, "SPINOR")),	/* cs */
-	TOP_PIN(SDIO1_DATA0, TOP_REG1, 25, 2, 0x38, 9,
-		TOP_MUX(0x0, "SDIO1"),		/* dat0 */
-		TOP_MUX(0x1, "USIM0"),		/* rst */
-		TOP_MUX(0x2, "BGPIO"),		/* gpio29 */
-		TOP_MUX(0x3, "SPINOR")),	/* dq0 */
-	TOP_PIN(SDIO1_DATA1, TOP_REG1, 27, 2, 0x38, 18,
-		TOP_MUX(0x0, "SDIO1"),		/* dat1 */
-		TOP_MUX(0x1, "USIM0"),		/* data */
-		TOP_MUX(0x2, "BGPIO"),		/* gpio30 */
-		TOP_MUX(0x3, "SPINOR")),	/* dq1 */
-	TOP_PIN(SDIO1_DATA2, TOP_REG1, 29, 2, 0x3c, 0,
-		TOP_MUX(0x0, "SDIO1"),		/* dat2 */
-		TOP_MUX(0x1, "BGPIO"),		/* gpio31 */
-		TOP_MUX(0x2, "SPINOR")),	/* dq2 */
-
-	/* top_pmm_reg_2 */
-	TOP_PIN(SDIO1_DATA3, TOP_REG2, 0, 2, 0x3c, 9,
-		TOP_MUX(0x0, "SDIO1"),		/* dat3 */
-		TOP_MUX(0x1, "BGPIO"),		/* gpio32 */
-		TOP_MUX(0x2, "SPINOR")),	/* dq3 */
-	TOP_PIN(SDIO1_CD, TOP_REG2, 2, 2, 0x3c, 18,
-		TOP_MUX(0x0, "SDIO1"),		/* cd */
-		TOP_MUX(0x1, "BGPIO"),		/* gpio33 */
-		TOP_MUX(0x2, "ISP")),		/* fl_trig */
-	TOP_PIN(SDIO1_WP, TOP_REG2, 4, 2, 0x40, 0,
-		TOP_MUX(0x0, "SDIO1"),		/* wp */
-		TOP_MUX(0x1, "BGPIO"),		/* gpio34 */
-		TOP_MUX(0x2, "ISP")),		/* ref_clk */
-	TOP_PIN(USIM1_CD, TOP_REG2, 22, 3, 0x44, 18,
-		TOP_MUX(0x0, "USIM1"),		/* cd */
-		TOP_MUX(0x1, "UART4"),		/* rxd */
-		TOP_MUX(0x2, "BGPIO"),		/* gpio39 */
-		TOP_MUX(0x3, "SPI3"),		/* clk */
-		TOP_MUX(0x4, "I2S0"),		/* bclk */
-		TOP_MUX(0x5, "B_DVI0")),	/* d8 */
-	TOP_PIN(USIM1_CLK, TOP_REG2, 25, 3, 0x4c, 18,
-		TOP_MUX(0x0, "USIM1"),		/* clk */
-		TOP_MUX(0x1, "UART4"),		/* txd */
-		TOP_MUX(0x2, "BGPIO"),		/* gpio40 */
-		TOP_MUX(0x3, "SPI3"),		/* cs */
-		TOP_MUX(0x4, "I2S0"),		/* ws */
-		TOP_MUX(0x5, "B_DVI0")),	/* d9 */
-	TOP_PIN(USIM1_RST, TOP_REG2, 28, 3, 0x4c, 0,
-		TOP_MUX(0x0, "USIM1"),		/* rst */
-		TOP_MUX(0x1, "UART4"),		/* cts */
-		TOP_MUX(0x2, "BGPIO"),		/* gpio41 */
-		TOP_MUX(0x3, "SPI3"),		/* txd */
-		TOP_MUX(0x4, "I2S0"),		/* dout0 */
-		TOP_MUX(0x5, "B_DVI0")),	/* d10 */
-
-	/* top_pmm_reg_3 */
-	TOP_PIN(USIM1_DATA, TOP_REG3, 0, 3, 0x4c, 9,
-		TOP_MUX(0x0, "USIM1"),		/* dat */
-		TOP_MUX(0x1, "UART4"),		/* rst */
-		TOP_MUX(0x2, "BGPIO"),		/* gpio42 */
-		TOP_MUX(0x3, "SPI3"),		/* rxd */
-		TOP_MUX(0x4, "I2S0"),		/* din0 */
-		TOP_MUX(0x5, "B_DVI0")),	/* d11 */
-	TOP_PIN(SDIO0_CLK, TOP_REG3, 6, 1, 0x58, 0,
-		TOP_MUX(0x0, "SDIO0"),		/* clk */
-		TOP_MUX(0x1, "GPIO")),		/* gpio43 */
-	TOP_PIN(SDIO0_CMD, TOP_REG3, 7, 1, 0x58, 9,
-		TOP_MUX(0x0, "SDIO0"),		/* cmd */
-		TOP_MUX(0x1, "GPIO")),		/* gpio44 */
-	TOP_PIN(SDIO0_DATA0, TOP_REG3, 8, 1, 0x58, 18,
-		TOP_MUX(0x0, "SDIO0"),		/* dat0 */
-		TOP_MUX(0x1, "GPIO")),		/* gpio45 */
-	TOP_PIN(SDIO0_DATA1, TOP_REG3, 9, 1, 0x5c, 0,
-		TOP_MUX(0x0, "SDIO0"),		/* dat1 */
-		TOP_MUX(0x1, "GPIO")),		/* gpio46 */
-	TOP_PIN(SDIO0_DATA2, TOP_REG3, 10, 1, 0x5c, 9,
-		TOP_MUX(0x0, "SDIO0"),		/* dat2 */
-		TOP_MUX(0x1, "GPIO")),		/* gpio47 */
-	TOP_PIN(SDIO0_DATA3, TOP_REG3, 11, 1, 0x5c, 18,
-		TOP_MUX(0x0, "SDIO0"),		/* dat3 */
-		TOP_MUX(0x1, "GPIO")),		/* gpio48 */
-	TOP_PIN(SDIO0_CD, TOP_REG3, 12, 1, 0x60, 0,
-		TOP_MUX(0x0, "SDIO0"),		/* cd */
-		TOP_MUX(0x1, "GPIO")),		/* gpio49 */
-	TOP_PIN(SDIO0_WP, TOP_REG3, 13, 1, 0x60, 9,
-		TOP_MUX(0x0, "SDIO0"),		/* wp */
-		TOP_MUX(0x1, "GPIO")),		/* gpio50 */
-
-	/* top_pmm_reg_4 */
-	TOP_PIN(TSI0_DATA0, TOP_REG4, 0, 2, 0x60, 18,
-		TOP_MUX(0x0, "TSI0"),		/* dat0 */
-		TOP_MUX(0x1, "LCD"),		/* clk */
-		TOP_MUX(0x2, "BGPIO")),		/* gpio51 */
-	TOP_PIN(SPINOR_CLK, TOP_REG4, 2, 2, 0xa8, 18,
-		TOP_MUX(0x0, "SPINOR"),		/* clk */
-		TOP_MUX(0x1, "TSI0"),		/* dat1 */
-		TOP_MUX(0x2, "LCD"),		/* dat0 */
-		TOP_MUX(0x3, "BGPIO")),		/* gpio52 */
-	TOP_PIN(TSI2_DATA, TOP_REG4, 4, 2, 0x7c, 0,
-		TOP_MUX(0x0, "TSI2"),		/* dat */
-		TOP_MUX(0x1, "TSI0"),		/* dat2 */
-		TOP_MUX(0x2, "LCD"),		/* dat1 */
-		TOP_MUX(0x3, "BGPIO")),		/* gpio53 */
-	TOP_PIN(TSI2_CLK, TOP_REG4, 6, 2, 0x7c, 9,
-		TOP_MUX(0x0, "TSI2"),		/* clk */
-		TOP_MUX(0x1, "TSI0"),		/* dat3 */
-		TOP_MUX(0x2, "LCD"),		/* dat2 */
-		TOP_MUX(0x3, "BGPIO")),		/* gpio54 */
-	TOP_PIN(TSI2_SYNC, TOP_REG4, 8, 2, 0x7c, 18,
-		TOP_MUX(0x0, "TSI2"),		/* sync */
-		TOP_MUX(0x1, "TSI0"),		/* dat4 */
-		TOP_MUX(0x2, "LCD"),		/* dat3 */
-		TOP_MUX(0x3, "BGPIO")),		/* gpio55 */
-	TOP_PIN(TSI2_VALID, TOP_REG4, 10, 2, 0x80, 0,
-		TOP_MUX(0x0, "TSI2"),		/* valid */
-		TOP_MUX(0x1, "TSI0"),		/* dat5 */
-		TOP_MUX(0x2, "LCD"),		/* dat4 */
-		TOP_MUX(0x3, "BGPIO")),		/* gpio56 */
-	TOP_PIN(SPINOR_CS, TOP_REG4, 12, 2, 0x80, 9,
-		TOP_MUX(0x0, "SPINOR"),		/* cs */
-		TOP_MUX(0x1, "TSI0"),		/* dat6 */
-		TOP_MUX(0x2, "LCD"),		/* dat5 */
-		TOP_MUX(0x3, "BGPIO")),		/* gpio57 */
-	TOP_PIN(SPINOR_DQ0, TOP_REG4, 14, 2, 0x80, 18,
-		TOP_MUX(0x0, "SPINOR"),		/* dq0 */
-		TOP_MUX(0x1, "TSI0"),		/* dat7 */
-		TOP_MUX(0x2, "LCD"),		/* dat6 */
-		TOP_MUX(0x3, "BGPIO")),		/* gpio58 */
-	TOP_PIN(SPINOR_DQ1, TOP_REG4, 16, 2, 0x84, 0,
-		TOP_MUX(0x0, "SPINOR"),		/* dq1 */
-		TOP_MUX(0x1, "TSI0"),		/* clk */
-		TOP_MUX(0x2, "LCD"),		/* dat7 */
-		TOP_MUX(0x3, "BGPIO")),		/* gpio59 */
-	TOP_PIN(SPINOR_DQ2, TOP_REG4, 18, 2, 0x84, 9,
-		TOP_MUX(0x0, "SPINOR"),		/* dq2 */
-		TOP_MUX(0x1, "TSI0"),		/* sync */
-		TOP_MUX(0x2, "LCD"),		/* dat8 */
-		TOP_MUX(0x3, "BGPIO")),		/* gpio60 */
-	TOP_PIN(SPINOR_DQ3, TOP_REG4, 20, 2, 0x84, 18,
-		TOP_MUX(0x0, "SPINOR"),		/* dq3 */
-		TOP_MUX(0x1, "TSI0"),		/* valid */
-		TOP_MUX(0x2, "LCD"),		/* dat9 */
-		TOP_MUX(0x3, "BGPIO")),		/* gpio61 */
-	TOP_PIN(VGA_HS, TOP_REG4, 22, 3, 0x88, 0,
-		TOP_MUX(0x0, "VGA"),		/* hs */
-		TOP_MUX(0x1, "TSI1"),		/* dat0 */
-		TOP_MUX(0x2, "LCD"),		/* dat10 */
-		TOP_MUX(0x3, "BGPIO"),		/* gpio62 */
-		TOP_MUX(0x4, "I2S1"),		/* din1 */
-		TOP_MUX(0x5, "B_DVI0")),	/* clk */
-	TOP_PIN(VGA_VS, TOP_REG4, 25, 3, 0x88, 9,
-		TOP_MUX(0x0, "VGA"),		/* vs0 */
-		TOP_MUX(0x1, "TSI1"),		/* dat1 */
-		TOP_MUX(0x2, "LCD"),		/* dat11 */
-		TOP_MUX(0x3, "BGPIO"),		/* gpio63 */
-		TOP_MUX(0x4, "I2S1"),		/* din2 */
-		TOP_MUX(0x5, "B_DVI0")),	/* vs */
-	TOP_PIN(TSI3_DATA, TOP_REG4, 28, 3, 0x88, 18,
-		TOP_MUX(0x0, "TSI3"),		/* dat */
-		TOP_MUX(0x1, "TSI1"),		/* dat2 */
-		TOP_MUX(0x2, "LCD"),		/* dat12 */
-		TOP_MUX(0x3, "BGPIO"),		/* gpio64 */
-		TOP_MUX(0x4, "I2S1"),		/* din3 */
-		TOP_MUX(0x5, "B_DVI0")),	/* hs */
-
-	/* top_pmm_reg_5 */
-	TOP_PIN(TSI3_CLK, TOP_REG5, 0, 3, 0x8c, 0,
-		TOP_MUX(0x0, "TSI3"),		/* clk */
-		TOP_MUX(0x1, "TSI1"),		/* dat3 */
-		TOP_MUX(0x2, "LCD"),		/* dat13 */
-		TOP_MUX(0x3, "BGPIO"),		/* gpio65 */
-		TOP_MUX(0x4, "I2S1"),		/* dout1 */
-		TOP_MUX(0x5, "B_DVI0")),	/* d0 */
-	TOP_PIN(TSI3_SYNC, TOP_REG5, 3, 3, 0x8c, 9,
-		TOP_MUX(0x0, "TSI3"),		/* sync */
-		TOP_MUX(0x1, "TSI1"),		/* dat4 */
-		TOP_MUX(0x2, "LCD"),		/* dat14 */
-		TOP_MUX(0x3, "BGPIO"),		/* gpio66 */
-		TOP_MUX(0x4, "I2S1"),		/* dout2 */
-		TOP_MUX(0x5, "B_DVI0")),	/* d1 */
-	TOP_PIN(TSI3_VALID, TOP_REG5, 6, 3, 0x8c, 18,
-		TOP_MUX(0x0, "TSI3"),		/* valid */
-		TOP_MUX(0x1, "TSI1"),		/* dat5 */
-		TOP_MUX(0x2, "LCD"),		/* dat15 */
-		TOP_MUX(0x3, "BGPIO"),		/* gpio67 */
-		TOP_MUX(0x4, "I2S1"),		/* dout3 */
-		TOP_MUX(0x5, "B_DVI0")),	/* d2 */
-	TOP_PIN(I2S1_WS, TOP_REG5, 9, 3, 0x90, 0,
-		TOP_MUX(0x0, "I2S1"),		/* ws */
-		TOP_MUX(0x1, "TSI1"),		/* dat6 */
-		TOP_MUX(0x2, "LCD"),		/* dat16 */
-		TOP_MUX(0x3, "BGPIO"),		/* gpio68 */
-		TOP_MUX(0x4, "VGA"),		/* scl */
-		TOP_MUX(0x5, "B_DVI0")),	/* d3 */
-	TOP_PIN(I2S1_BCLK, TOP_REG5, 12, 3, 0x90, 9,
-		TOP_MUX(0x0, "I2S1"),		/* bclk */
-		TOP_MUX(0x1, "TSI1"),		/* dat7 */
-		TOP_MUX(0x2, "LCD"),		/* dat17 */
-		TOP_MUX(0x3, "BGPIO"),		/* gpio69 */
-		TOP_MUX(0x4, "VGA"),		/* sda */
-		TOP_MUX(0x5, "B_DVI0")),	/* d4 */
-	TOP_PIN(I2S1_MCLK, TOP_REG5, 15, 2, 0x90, 18,
-		TOP_MUX(0x0, "I2S1"),		/* mclk */
-		TOP_MUX(0x1, "TSI1"),		/* clk */
-		TOP_MUX(0x2, "LCD"),		/* dat18 */
-		TOP_MUX(0x3, "BGPIO")),		/* gpio70 */
-	TOP_PIN(I2S1_DIN0, TOP_REG5, 17, 2, 0x94, 0,
-		TOP_MUX(0x0, "I2S1"),		/* din0 */
-		TOP_MUX(0x1, "TSI1"),		/* sync */
-		TOP_MUX(0x2, "LCD"),		/* dat19 */
-		TOP_MUX(0x3, "BGPIO")),		/* gpio71 */
-	TOP_PIN(I2S1_DOUT0, TOP_REG5, 19, 2, 0x94, 9,
-		TOP_MUX(0x0, "I2S1"),		/* dout0 */
-		TOP_MUX(0x1, "TSI1"),		/* valid */
-		TOP_MUX(0x2, "LCD"),		/* dat20 */
-		TOP_MUX(0x3, "BGPIO")),		/* gpio72 */
-	TOP_PIN(SPI3_CLK, TOP_REG5, 21, 3, 0x94, 18,
-		TOP_MUX(0x0, "SPI3"),		/* clk */
-		TOP_MUX(0x1, "TSO1"),		/* clk */
-		TOP_MUX(0x2, "LCD"),		/* dat21 */
-		TOP_MUX(0x3, "BGPIO"),		/* gpio73 */
-		TOP_MUX(0x4, "UART5"),		/* rxd */
-		TOP_MUX(0x5, "PCM"),		/* fs */
-		TOP_MUX(0x6, "I2S0"),		/* din1 */
-		TOP_MUX(0x7, "B_DVI0")),	/* d5 */
-	TOP_PIN(SPI3_CS, TOP_REG5, 24, 3, 0x98, 0,
-		TOP_MUX(0x0, "SPI3"),		/* cs */
-		TOP_MUX(0x1, "TSO1"),		/* dat0 */
-		TOP_MUX(0x2, "LCD"),		/* dat22 */
-		TOP_MUX(0x3, "BGPIO"),		/* gpio74 */
-		TOP_MUX(0x4, "UART5"),		/* txd */
-		TOP_MUX(0x5, "PCM"),		/* clk */
-		TOP_MUX(0x6, "I2S0"),		/* din2 */
-		TOP_MUX(0x7, "B_DVI0")),	/* d6 */
-	TOP_PIN(SPI3_TXD, TOP_REG5, 27, 3, 0x98, 9,
-		TOP_MUX(0x0, "SPI3"),		/* txd */
-		TOP_MUX(0x1, "TSO1"),		/* dat1 */
-		TOP_MUX(0x2, "LCD"),		/* dat23 */
-		TOP_MUX(0x3, "BGPIO"),		/* gpio75 */
-		TOP_MUX(0x4, "UART5"),		/* cts */
-		TOP_MUX(0x5, "PCM"),		/* txd */
-		TOP_MUX(0x6, "I2S0"),		/* din3 */
-		TOP_MUX(0x7, "B_DVI0")),	/* d7 */
-	TOP_PIN(NAND_LDO_MS18_SEL, TOP_REG5, 30, 1, 0xe4, 0,
-		TOP_MUX(0x0, "NAND"),		/* ldo_ms18_sel */
-		TOP_MUX(0x1, "BGPIO")),		/* gpio99 */
-
-	/* top_pmm_reg_6 */
-	TOP_PIN(SPI3_RXD, TOP_REG6, 0, 3, 0x98, 18,
-		TOP_MUX(0x0, "SPI3"),		/* rxd */
-		TOP_MUX(0x1, "TSO1"),		/* dat2 */
-		TOP_MUX(0x2, "LCD"),		/* stvu_vsync */
-		TOP_MUX(0x3, "BGPIO"),		/* gpio76 */
-		TOP_MUX(0x4, "UART5"),		/* rts */
-		TOP_MUX(0x5, "PCM"),		/* rxd */
-		TOP_MUX(0x6, "I2S0"),		/* dout1 */
-		TOP_MUX(0x7, "B_DVI1")),	/* clk */
-	TOP_PIN(I2S0_MCLK, TOP_REG6, 3, 3, 0x9c, 0,
-		TOP_MUX(0x0, "I2S0"),		/* mclk */
-		TOP_MUX(0x1, "TSO1"),		/* dat3 */
-		TOP_MUX(0x2, "LCD"),		/* stvd */
-		TOP_MUX(0x3, "BGPIO"),		/* gpio77 */
-		TOP_MUX(0x4, "USIM0"),		/* cd */
-		TOP_MUX(0x5, "B_DVI1")),	/* vs */
-	TOP_PIN(I2S0_BCLK, TOP_REG6, 6, 3, 0x9c, 9,
-		TOP_MUX(0x0, "I2S0"),		/* bclk */
-		TOP_MUX(0x1, "TSO1"),		/* dat4 */
-		TOP_MUX(0x2, "LCD"),		/* sthl_hsync */
-		TOP_MUX(0x3, "BGPIO"),		/* gpio78 */
-		TOP_MUX(0x4, "USIM0"),		/* clk */
-		TOP_MUX(0x5, "B_DVI1")),	/* hs */
-	TOP_PIN(I2S0_WS, TOP_REG6, 9, 3, 0x9c, 18,
-		TOP_MUX(0x0, "I2S0"),		/* ws */
-		TOP_MUX(0x1, "TSO1"),		/* dat5 */
-		TOP_MUX(0x2, "LCD"),		/* sthr */
-		TOP_MUX(0x3, "BGPIO"),		/* gpio79 */
-		TOP_MUX(0x4, "USIM0"),		/* rst */
-		TOP_MUX(0x5, "B_DVI1")),	/* d0 */
-	TOP_PIN(I2S0_DIN0, TOP_REG6, 12, 3, 0xa0, 0,
-		TOP_MUX(0x0, "I2S0"),		/* din0 */
-		TOP_MUX(0x1, "TSO1"),		/* dat6 */
-		TOP_MUX(0x2, "LCD"),		/* oev_dataen */
-		TOP_MUX(0x3, "BGPIO"),		/* gpio80 */
-		TOP_MUX(0x4, "USIM0"),		/* dat */
-		TOP_MUX(0x5, "B_DVI1")),	/* d1 */
-	TOP_PIN(I2S0_DOUT0, TOP_REG6, 15, 2, 0xa0, 9,
-		TOP_MUX(0x0, "I2S0"),		/* dout0 */
-		TOP_MUX(0x1, "TSO1"),		/* dat7 */
-		TOP_MUX(0x2, "LCD"),		/* ckv */
-		TOP_MUX(0x3, "BGPIO")),		/* gpio81 */
-	TOP_PIN(I2C5_SCL, TOP_REG6, 17, 3, 0xa0, 18,
-		TOP_MUX(0x0, "I2C5"),		/* scl */
-		TOP_MUX(0x1, "TSO1"),		/* sync */
-		TOP_MUX(0x2, "LCD"),		/* ld */
-		TOP_MUX(0x3, "BGPIO"),		/* gpio82 */
-		TOP_MUX(0x4, "PWM"),		/* out2 */
-		TOP_MUX(0x5, "I2S0"),		/* dout2 */
-		TOP_MUX(0x6, "B_DVI1")),	/* d2 */
-	TOP_PIN(I2C5_SDA, TOP_REG6, 20, 3, 0xa4, 0,
-		TOP_MUX(0x0, "I2C5"),		/* sda */
-		TOP_MUX(0x1, "TSO1"),		/* vld */
-		TOP_MUX(0x2, "LCD"),		/* pol */
-		TOP_MUX(0x3, "BGPIO"),		/* gpio83 */
-		TOP_MUX(0x4, "PWM"),		/* out3 */
-		TOP_MUX(0x5, "I2S0"),		/* dout3 */
-		TOP_MUX(0x6, "B_DVI1")),	/* d3 */
-	TOP_PIN(SPI2_CLK, TOP_REG6, 23, 3, 0xa4, 9,
-		TOP_MUX(0x0, "SPI2"),		/* clk */
-		TOP_MUX(0x1, "TSO0"),		/* clk */
-		TOP_MUX(0x2, "LCD"),		/* degsl */
-		TOP_MUX(0x3, "BGPIO"),		/* gpio84 */
-		TOP_MUX(0x4, "I2C4"),		/* scl */
-		TOP_MUX(0x5, "B_DVI1")),	/* d4 */
-	TOP_PIN(SPI2_CS, TOP_REG6, 26, 3, 0xa4, 18,
-		TOP_MUX(0x0, "SPI2"),		/* cs */
-		TOP_MUX(0x1, "TSO0"),		/* data */
-		TOP_MUX(0x2, "LCD"),		/* rev */
-		TOP_MUX(0x3, "BGPIO"),		/* gpio85 */
-		TOP_MUX(0x4, "I2C4"),		/* sda */
-		TOP_MUX(0x5, "B_DVI1")),	/* d5 */
-	TOP_PIN(SPI2_TXD, TOP_REG6, 29, 3, 0xa8, 0,
-		TOP_MUX(0x0, "SPI2"),		/* txd */
-		TOP_MUX(0x1, "TSO0"),		/* sync */
-		TOP_MUX(0x2, "LCD"),		/* u_d */
-		TOP_MUX(0x3, "BGPIO"),		/* gpio86 */
-		TOP_MUX(0x4, "I2C4"),		/* scl */
-		TOP_MUX(0x5, "B_DVI1")),	/* d6 */
-
-	/* top_pmm_reg_7 */
-	TOP_PIN(SPI2_RXD, TOP_REG7, 0, 3, 0xa8, 9,
-		TOP_MUX(0x0, "SPI2"),		/* rxd */
-		TOP_MUX(0x1, "TSO0"),		/* vld */
-		TOP_MUX(0x2, "LCD"),		/* r_l */
-		TOP_MUX(0x3, "BGPIO"),		/* gpio87 */
-		TOP_MUX(0x4, "I2C3"),		/* sda */
-		TOP_MUX(0x5, "B_DVI1")),	/* d7 */
-	TOP_PIN(NAND_WP_N, TOP_REG7, 7, 3, 0x54, 9,
-		TOP_MUX(0x0, "NAND"),		/* wp */
-		TOP_MUX(0x1, "PWM"),		/* out2 */
-		TOP_MUX(0x2, "SPI2"),		/* clk */
-		TOP_MUX(0x3, "BGPIO"),		/* gpio88 */
-		TOP_MUX(0x4, "TSI0"),		/* dat0 */
-		TOP_MUX(0x5, "I2S1")),		/* din1 */
-	TOP_PIN(NAND_PAGE_SIZE0, TOP_REG7, 10, 3, 0xb8, 0,
-		TOP_MUX(0x0, "NAND"),		/* boot_pagesize0 */
-		TOP_MUX(0x1, "PWM"),		/* out3 */
-		TOP_MUX(0x2, "SPI2"),		/* cs */
-		TOP_MUX(0x3, "BGPIO"),		/* gpio89 */
-		TOP_MUX(0x4, "TSI0"),		/* clk */
-		TOP_MUX(0x5, "I2S1")),		/* din2 */
-	TOP_PIN(NAND_PAGE_SIZE1, TOP_REG7, 13, 3, 0xb8, 9,
-		TOP_MUX(0x0, "NAND"),		/* boot_pagesize1 */
-		TOP_MUX(0x1, "I2C4"),		/* scl */
-		TOP_MUX(0x2, "SPI2"),		/* txd */
-		TOP_MUX(0x3, "BGPIO"),		/* gpio90 */
-		TOP_MUX(0x4, "TSI0"),		/* sync */
-		TOP_MUX(0x5, "I2S1")),		/* din3 */
-	TOP_PIN(NAND_ADDR_CYCLE, TOP_REG7, 16, 3, 0xb8, 18,
-		TOP_MUX(0x0, "NAND"),		/* boot_addr_cycles */
-		TOP_MUX(0x1, "I2C4"),		/* sda */
-		TOP_MUX(0x2, "SPI2"),		/* rxd */
-		TOP_MUX(0x3, "BGPIO"),		/* gpio91 */
-		TOP_MUX(0x4, "TSI0"),		/* valid */
-		TOP_MUX(0x5, "I2S1")),		/* dout1 */
-	TOP_PIN(NAND_RB0, TOP_REG7, 19, 3, 0xbc, 0,
-		TOP_MUX(0x0, "NAND"),		/* rdy_busy0 */
-		TOP_MUX(0x1, "I2C2"),		/* scl */
-		TOP_MUX(0x2, "USIM0"),		/* cd */
-		TOP_MUX(0x3, "BGPIO"),		/* gpio92 */
-		TOP_MUX(0x4, "TSI1")),		/* data0 */
-	TOP_PIN(NAND_RB1, TOP_REG7, 22, 3, 0xbc, 9,
-		TOP_MUX(0x0, "NAND"),		/* rdy_busy1 */
-		TOP_MUX(0x1, "I2C2"),		/* sda */
-		TOP_MUX(0x2, "USIM0"),		/* clk */
-		TOP_MUX(0x3, "BGPIO"),		/* gpio93 */
-		TOP_MUX(0x4, "TSI1")),		/* clk */
-	TOP_PIN(NAND_RB2, TOP_REG7, 25, 3, 0xbc, 18,
-		TOP_MUX(0x0, "NAND"),		/* rdy_busy2 */
-		TOP_MUX(0x1, "UART5"),		/* rxd */
-		TOP_MUX(0x2, "USIM0"),		/* rst */
-		TOP_MUX(0x3, "BGPIO"),		/* gpio94 */
-		TOP_MUX(0x4, "TSI1"),		/* sync */
-		TOP_MUX(0x4, "I2S1")),		/* dout2 */
-	TOP_PIN(NAND_RB3, TOP_REG7, 28, 3, 0x54, 18,
-		TOP_MUX(0x0, "NAND"),		/* rdy_busy3 */
-		TOP_MUX(0x1, "UART5"),		/* txd */
-		TOP_MUX(0x2, "USIM0"),		/* dat */
-		TOP_MUX(0x3, "BGPIO"),		/* gpio95 */
-		TOP_MUX(0x4, "TSI1"),		/* valid */
-		TOP_MUX(0x4, "I2S1")),		/* dout3 */
-
-	/* top_pmm_reg_8 */
-	TOP_PIN(GMAC_125M_IN, TOP_REG8, 0, 2, 0x34, 0,
-		TOP_MUX(0x0, "GMII"),		/* 125m_in */
-		TOP_MUX(0x1, "USB2"),		/* 0_drvvbus */
-		TOP_MUX(0x2, "ISP"),		/* ref_clk */
-		TOP_MUX(0x3, "BGPIO")),		/* gpio96 */
-	TOP_PIN(GMAC_50M_OUT, TOP_REG8, 2, 2, 0x34, 9,
-		TOP_MUX(0x0, "GMII"),		/* 50m_out */
-		TOP_MUX(0x1, "USB2"),		/* 1_drvvbus */
-		TOP_MUX(0x2, "BGPIO"),		/* gpio97 */
-		TOP_MUX(0x3, "USB2")),		/* 0_drvvbus */
-	TOP_PIN(SPINOR_SSCLK_LOOPBACK, TOP_REG8, 6, 1, 0xc8, 9,
-		TOP_MUX(0x0, "SPINOR")),	/* sdio1_clk_i */
-	TOP_PIN(SPINOR_SDIO1CLK_LOOPBACK, TOP_REG8, 7, 1, 0xc8, 18,
-		TOP_MUX(0x0, "SPINOR")),	/* ssclk_i */
-};
-
-static struct zx_pinctrl_soc_info zx296718_pinctrl_info = {
-	.pins = zx296718_pins,
-	.npins = ARRAY_SIZE(zx296718_pins),
-};
-
-static int zx296718_pinctrl_probe(struct platform_device *pdev)
-{
-	return zx_pinctrl_init(pdev, &zx296718_pinctrl_info);
-}
-
-static const struct of_device_id zx296718_pinctrl_match[] = {
-	{ .compatible = "zte,zx296718-pmm", },
-	{}
-};
-MODULE_DEVICE_TABLE(of, zx296718_pinctrl_match);
-
-static struct platform_driver zx296718_pinctrl_driver = {
-	.probe  = zx296718_pinctrl_probe,
-	.driver = {
-		.name = "zx296718-pinctrl",
-		.of_match_table = zx296718_pinctrl_match,
-	},
-};
-builtin_platform_driver(zx296718_pinctrl_driver);
-
-MODULE_DESCRIPTION("ZTE ZX296718 pinctrl driver");
-MODULE_LICENSE("GPL");
-- 
2.29.2


^ permalink raw reply related	[flat|nested] 22+ messages in thread

* [PATCH 2/5] pinctrl: remove zte zx driver
@ 2021-01-20 13:20   ` Arnd Bergmann
  0 siblings, 0 replies; 22+ messages in thread
From: Arnd Bergmann @ 2021-01-20 13:20 UTC (permalink / raw)
  To: linux-arm-kernel, linux-kernel, linux-gpio, Linus Walleij
  Cc: Bartosz Golaszewski, Jun Nie, Shawn Guo, Arnd Bergmann

From: Arnd Bergmann <arnd@arndb.de>

The zte zx platform is getting removed, so this driver is no
longer needed.

Cc: Jun Nie <jun.nie@linaro.org>
Cc: Shawn Guo <shawnguo@kernel.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
---
 .../bindings/pinctrl/pinctrl-zx.txt           |   84 --
 drivers/pinctrl/Kconfig                       |    1 -
 drivers/pinctrl/Makefile                      |    1 -
 drivers/pinctrl/zte/Kconfig                   |   14 -
 drivers/pinctrl/zte/Makefile                  |    3 -
 drivers/pinctrl/zte/pinctrl-zx.c              |  445 -------
 drivers/pinctrl/zte/pinctrl-zx.h              |  102 --
 drivers/pinctrl/zte/pinctrl-zx296718.c        | 1024 -----------------
 8 files changed, 1674 deletions(-)
 delete mode 100644 Documentation/devicetree/bindings/pinctrl/pinctrl-zx.txt
 delete mode 100644 drivers/pinctrl/zte/Kconfig
 delete mode 100644 drivers/pinctrl/zte/Makefile
 delete mode 100644 drivers/pinctrl/zte/pinctrl-zx.c
 delete mode 100644 drivers/pinctrl/zte/pinctrl-zx.h
 delete mode 100644 drivers/pinctrl/zte/pinctrl-zx296718.c

diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-zx.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-zx.txt
deleted file mode 100644
index 39170f372599..000000000000
--- a/Documentation/devicetree/bindings/pinctrl/pinctrl-zx.txt
+++ /dev/null
@@ -1,84 +0,0 @@
-* ZTE ZX Pin Controller
-
-The pin controller on ZTE ZX platforms is kinda of hybrid.  It consists of
-a main controller and an auxiliary one.  For example, on ZX296718 SoC, the
-main controller is TOP_PMM and the auxiliary one is AON_IOCFG.  Both
-controllers work together to control pin multiplexing and configuration in
-the way illustrated as below.
-
-
-           GMII_RXD3 ---+
-                        |
-             DVI1_HS ---+----------------------------- GMII_RXD3 (TOP pin)
-                        |
-             BGPIO16 ---+                               ^
-                                                        | pinconf
-                        ^                               |
-                        | pinmux                        |
-                        |                               |
-
-                   TOP_PMM (main)           AON_IOCFG (aux)
-
-                        |                       |       |
-                        |                pinmux |       |
-                        | pinmux                v       |
-                        v                               | pinconf
-                                    KEY_ROW2 ---+       v
-        PORT1_LCD_TE ---+                       |
-                        |            AGPIO10 ---+------ KEY_ROW2 (AON pin)
-          I2S0_DOUT3 ---+                       |
-                        |-----------------------+
-            PWM_OUT3 ---+
-                        |
-             VGA_VS1 ---+
-
-
-For most of pins like GMII_RXD3 in the figure, the pinmux function is
-controlled by TOP_PMM block only, and this type of pins are meant by term
-'TOP pins'.  For pins like KEY_ROW2, the pinmux is controlled by both
-TOP_PMM and AON_IOCFG blocks, as the available multiplexing functions for
-the pin spread in both controllers.  This type of pins are called 'AON pins'.
-Though pinmux implementation is quite different, pinconf is same for both
-types of pins.  Both are controlled by auxiliary controller, i.e. AON_IOCFG
-on ZX296718.
-
-Required properties:
-- compatible: should be "zte,zx296718-pmm".
-- reg: the register physical address and length.
-- zte,auxiliary-controller: phandle to the auxiliary pin controller which
-  implements pinmux for AON pins and pinconf for all pins.
-
-The following pin configuration are supported. Please refer to
-pinctrl-bindings.txt in this directory for more details of the common
-pinctrl bindings used by client devices.
-
-- bias-pull-up
-- bias-pull-down
-- drive-strength
-- input-enable
-- slew-rate
-
-Examples:
-
-iocfg: pin-controller@119000 {
-	compatible = "zte,zx296718-iocfg";
-	reg = <0x119000 0x1000>;
-};
-
-pmm: pin-controller@1462000 {
-	compatible = "zte,zx296718-pmm";
-	reg = <0x1462000 0x1000>;
-	zte,auxiliary-controller = <&iocfg>;
-};
-
-&pmm {
-	vga_pins: vga {
-		pins = "KEY_COL1", "KEY_COL2", "KEY_ROW1", "KEY_ROW2";
-		function = "VGA";
-	};
-};
-
-&vga {
-	pinctrl-names = "default";
-	pinctrl-0 = <&vga_pins>;
-};
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index d4b2f2e2ed75..1c1fa681b96d 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -417,7 +417,6 @@ source "drivers/pinctrl/ti/Kconfig"
 source "drivers/pinctrl/uniphier/Kconfig"
 source "drivers/pinctrl/vt8500/Kconfig"
 source "drivers/pinctrl/mediatek/Kconfig"
-source "drivers/pinctrl/zte/Kconfig"
 source "drivers/pinctrl/meson/Kconfig"
 source "drivers/pinctrl/cirrus/Kconfig"
 source "drivers/pinctrl/visconti/Kconfig"
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index 5bb9bb6cc3ce..fef92794900d 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -71,6 +71,5 @@ obj-y				+= ti/
 obj-$(CONFIG_PINCTRL_UNIPHIER)	+= uniphier/
 obj-$(CONFIG_ARCH_VT8500)	+= vt8500/
 obj-y				+= mediatek/
-obj-$(CONFIG_PINCTRL_ZX)	+= zte/
 obj-y				+= cirrus/
 obj-$(CONFIG_PINCTRL_VISCONTI)	+= visconti/
diff --git a/drivers/pinctrl/zte/Kconfig b/drivers/pinctrl/zte/Kconfig
deleted file mode 100644
index 4fdc70511034..000000000000
--- a/drivers/pinctrl/zte/Kconfig
+++ /dev/null
@@ -1,14 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-only
-config PINCTRL_ZX
-	bool
-	select PINMUX
-	select GENERIC_PINCONF
-	select GENERIC_PINCTRL_GROUPS
-	select GENERIC_PINMUX_FUNCTIONS
-
-config PINCTRL_ZX296718
-	bool "ZTE ZX296718 pinctrl driver"
-	depends on OF && ARCH_ZX
-	select PINCTRL_ZX
-	help
-	  Say Y here to enable the ZX296718 pinctrl driver
diff --git a/drivers/pinctrl/zte/Makefile b/drivers/pinctrl/zte/Makefile
deleted file mode 100644
index 2084c7810f96..000000000000
--- a/drivers/pinctrl/zte/Makefile
+++ /dev/null
@@ -1,3 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-only
-obj-$(CONFIG_PINCTRL_ZX)	+= pinctrl-zx.o
-obj-$(CONFIG_PINCTRL_ZX296718)	+= pinctrl-zx296718.o
diff --git a/drivers/pinctrl/zte/pinctrl-zx.c b/drivers/pinctrl/zte/pinctrl-zx.c
deleted file mode 100644
index 80d00ab8c110..000000000000
--- a/drivers/pinctrl/zte/pinctrl-zx.c
+++ /dev/null
@@ -1,445 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Copyright (C) 2017 Sanechips Technology Co., Ltd.
- * Copyright 2017 Linaro Ltd.
- */
-
-#include <linux/io.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-#include <linux/of_device.h>
-#include <linux/pinctrl/pinctrl.h>
-#include <linux/pinctrl/pinconf-generic.h>
-#include <linux/pinctrl/pinmux.h>
-#include <linux/platform_device.h>
-#include <linux/slab.h>
-
-#include "../core.h"
-#include "../pinctrl-utils.h"
-#include "../pinmux.h"
-#include "pinctrl-zx.h"
-
-#define ZX_PULL_DOWN		BIT(0)
-#define ZX_PULL_UP		BIT(1)
-#define ZX_INPUT_ENABLE		BIT(3)
-#define ZX_DS_SHIFT		4
-#define ZX_DS_MASK		(0x7 << ZX_DS_SHIFT)
-#define ZX_DS_VALUE(x)		(((x) << ZX_DS_SHIFT) & ZX_DS_MASK)
-#define ZX_SLEW			BIT(8)
-
-struct zx_pinctrl {
-	struct pinctrl_dev *pctldev;
-	struct device *dev;
-	void __iomem *base;
-	void __iomem *aux_base;
-	spinlock_t lock;
-	struct zx_pinctrl_soc_info *info;
-};
-
-static int zx_dt_node_to_map(struct pinctrl_dev *pctldev,
-			     struct device_node *np_config,
-			     struct pinctrl_map **map, u32 *num_maps)
-{
-	return pinconf_generic_dt_node_to_map(pctldev, np_config, map,
-					      num_maps, PIN_MAP_TYPE_INVALID);
-}
-
-static const struct pinctrl_ops zx_pinctrl_ops = {
-	.dt_node_to_map = zx_dt_node_to_map,
-	.dt_free_map = pinctrl_utils_free_map,
-	.get_groups_count = pinctrl_generic_get_group_count,
-	.get_group_name = pinctrl_generic_get_group_name,
-	.get_group_pins = pinctrl_generic_get_group_pins,
-};
-
-#define NONAON_MVAL 2
-
-static int zx_set_mux(struct pinctrl_dev *pctldev, unsigned int func_selector,
-		      unsigned int group_selector)
-{
-	struct zx_pinctrl *zpctl = pinctrl_dev_get_drvdata(pctldev);
-	struct zx_pinctrl_soc_info *info = zpctl->info;
-	const struct pinctrl_pin_desc *pindesc = info->pins + group_selector;
-	struct zx_pin_data *data = pindesc->drv_data;
-	struct zx_mux_desc *mux;
-	u32 mask, offset, bitpos;
-	struct function_desc *func;
-	unsigned long flags;
-	u32 val, mval;
-
-	/* Skip reserved pin */
-	if (!data)
-		return -EINVAL;
-
-	mux = data->muxes;
-	mask = (1 << data->width) - 1;
-	offset = data->offset;
-	bitpos = data->bitpos;
-
-	func = pinmux_generic_get_function(pctldev, func_selector);
-	if (!func)
-		return -EINVAL;
-
-	while (mux->name) {
-		if (strcmp(mux->name, func->name) == 0)
-			break;
-		mux++;
-	}
-
-	/* Found mux value to be written */
-	mval = mux->muxval;
-
-	spin_lock_irqsave(&zpctl->lock, flags);
-
-	if (data->aon_pin) {
-		/*
-		 * It's an AON pin, whose mux register offset and bit position
-		 * can be calculated from pin number.  Each register covers 16
-		 * pins, and each pin occupies 2 bits.
-		 */
-		u16 aoffset = pindesc->number / 16 * 4;
-		u16 abitpos = (pindesc->number % 16) * 2;
-
-		if (mval & AON_MUX_FLAG) {
-			/*
-			 * This is a mux value that needs to be written into
-			 * AON pinmux register.  Write it and then we're done.
-			 */
-			val = readl(zpctl->aux_base + aoffset);
-			val &= ~(0x3 << abitpos);
-			val |= (mval & 0x3) << abitpos;
-			writel(val, zpctl->aux_base + aoffset);
-		} else {
-			/*
-			 * It's a mux value that needs to be written into TOP
-			 * pinmux register.
-			 */
-			val = readl(zpctl->base + offset);
-			val &= ~(mask << bitpos);
-			val |= (mval & mask) << bitpos;
-			writel(val, zpctl->base + offset);
-
-			/*
-			 * In this case, the AON pinmux register needs to be
-			 * set up to select non-AON function.
-			 */
-			val = readl(zpctl->aux_base + aoffset);
-			val &= ~(0x3 << abitpos);
-			val |= NONAON_MVAL << abitpos;
-			writel(val, zpctl->aux_base + aoffset);
-		}
-
-	} else {
-		/*
-		 * This is a TOP pin, and we only need to set up TOP pinmux
-		 * register and then we're done with it.
-		 */
-		val = readl(zpctl->base + offset);
-		val &= ~(mask << bitpos);
-		val |= (mval & mask) << bitpos;
-		writel(val, zpctl->base + offset);
-	}
-
-	spin_unlock_irqrestore(&zpctl->lock, flags);
-
-	return 0;
-}
-
-static const struct pinmux_ops zx_pinmux_ops = {
-	.get_functions_count = pinmux_generic_get_function_count,
-	.get_function_name = pinmux_generic_get_function_name,
-	.get_function_groups = pinmux_generic_get_function_groups,
-	.set_mux = zx_set_mux,
-};
-
-static int zx_pin_config_get(struct pinctrl_dev *pctldev, unsigned int pin,
-			     unsigned long *config)
-{
-	struct zx_pinctrl *zpctl = pinctrl_dev_get_drvdata(pctldev);
-	struct zx_pinctrl_soc_info *info = zpctl->info;
-	const struct pinctrl_pin_desc *pindesc = info->pins + pin;
-	struct zx_pin_data *data = pindesc->drv_data;
-	enum pin_config_param param = pinconf_to_config_param(*config);
-	u32 val;
-
-	/* Skip reserved pin */
-	if (!data)
-		return -EINVAL;
-
-	val = readl(zpctl->aux_base + data->coffset);
-	val = val >> data->cbitpos;
-
-	switch (param) {
-	case PIN_CONFIG_BIAS_PULL_DOWN:
-		val &= ZX_PULL_DOWN;
-		val = !!val;
-		if (val == 0)
-			return -EINVAL;
-		break;
-	case PIN_CONFIG_BIAS_PULL_UP:
-		val &= ZX_PULL_UP;
-		val = !!val;
-		if (val == 0)
-			return -EINVAL;
-		break;
-	case PIN_CONFIG_INPUT_ENABLE:
-		val &= ZX_INPUT_ENABLE;
-		val = !!val;
-		if (val == 0)
-			return -EINVAL;
-		break;
-	case PIN_CONFIG_DRIVE_STRENGTH:
-		val &= ZX_DS_MASK;
-		val = val >> ZX_DS_SHIFT;
-		break;
-	case PIN_CONFIG_SLEW_RATE:
-		val &= ZX_SLEW;
-		val = !!val;
-		break;
-	default:
-		return -ENOTSUPP;
-	}
-
-	*config = pinconf_to_config_packed(param, val);
-
-	return 0;
-}
-
-static int zx_pin_config_set(struct pinctrl_dev *pctldev, unsigned int pin,
-			     unsigned long *configs, unsigned int num_configs)
-{
-	struct zx_pinctrl *zpctl = pinctrl_dev_get_drvdata(pctldev);
-	struct zx_pinctrl_soc_info *info = zpctl->info;
-	const struct pinctrl_pin_desc *pindesc = info->pins + pin;
-	struct zx_pin_data *data = pindesc->drv_data;
-	enum pin_config_param param;
-	u32 val, arg;
-	int i;
-
-	/* Skip reserved pin */
-	if (!data)
-		return -EINVAL;
-
-	val = readl(zpctl->aux_base + data->coffset);
-
-	for (i = 0; i < num_configs; i++) {
-		param = pinconf_to_config_param(configs[i]);
-		arg = pinconf_to_config_argument(configs[i]);
-
-		switch (param) {
-		case PIN_CONFIG_BIAS_PULL_DOWN:
-			val |= ZX_PULL_DOWN << data->cbitpos;
-			break;
-		case PIN_CONFIG_BIAS_PULL_UP:
-			val |= ZX_PULL_UP << data->cbitpos;
-			break;
-		case PIN_CONFIG_INPUT_ENABLE:
-			val |= ZX_INPUT_ENABLE << data->cbitpos;
-			break;
-		case PIN_CONFIG_DRIVE_STRENGTH:
-			val &= ~(ZX_DS_MASK << data->cbitpos);
-			val |= ZX_DS_VALUE(arg) << data->cbitpos;
-			break;
-		case PIN_CONFIG_SLEW_RATE:
-			if (arg)
-				val |= ZX_SLEW << data->cbitpos;
-			else
-				val &= ~ZX_SLEW << data->cbitpos;
-			break;
-		default:
-			return -ENOTSUPP;
-		}
-	}
-
-	writel(val, zpctl->aux_base + data->coffset);
-	return 0;
-}
-
-static const struct pinconf_ops zx_pinconf_ops = {
-	.pin_config_set = zx_pin_config_set,
-	.pin_config_get = zx_pin_config_get,
-	.is_generic = true,
-};
-
-static int zx_pinctrl_build_state(struct platform_device *pdev)
-{
-	struct zx_pinctrl *zpctl = platform_get_drvdata(pdev);
-	struct zx_pinctrl_soc_info *info = zpctl->info;
-	struct pinctrl_dev *pctldev = zpctl->pctldev;
-	struct function_desc *functions;
-	int nfunctions;
-	struct group_desc *groups;
-	int ngroups;
-	int i;
-
-	/* Every single pin composes a group */
-	ngroups = info->npins;
-	groups = devm_kcalloc(&pdev->dev, ngroups, sizeof(*groups),
-			      GFP_KERNEL);
-	if (!groups)
-		return -ENOMEM;
-
-	for (i = 0; i < ngroups; i++) {
-		const struct pinctrl_pin_desc *pindesc = info->pins + i;
-		struct group_desc *group = groups + i;
-
-		group->name = pindesc->name;
-		group->pins = (int *) &pindesc->number;
-		group->num_pins = 1;
-		radix_tree_insert(&pctldev->pin_group_tree, i, group);
-	}
-
-	pctldev->num_groups = ngroups;
-
-	/* Build function list from pin mux functions */
-	functions = kcalloc(info->npins, sizeof(*functions), GFP_KERNEL);
-	if (!functions)
-		return -ENOMEM;
-
-	nfunctions = 0;
-	for (i = 0; i < info->npins; i++) {
-		const struct pinctrl_pin_desc *pindesc = info->pins + i;
-		struct zx_pin_data *data = pindesc->drv_data;
-		struct zx_mux_desc *mux;
-
-		/* Reserved pins do not have a drv_data at all */
-		if (!data)
-			continue;
-
-		/* Loop over all muxes for the pin */
-		mux = data->muxes;
-		while (mux->name) {
-			struct function_desc *func = functions;
-
-			/* Search function list for given mux */
-			while (func->name) {
-				if (strcmp(mux->name, func->name) == 0) {
-					/* Function exists */
-					func->num_group_names++;
-					break;
-				}
-				func++;
-			}
-
-			if (!func->name) {
-				/* New function */
-				func->name = mux->name;
-				func->num_group_names = 1;
-				radix_tree_insert(&pctldev->pin_function_tree,
-						  nfunctions++, func);
-			}
-
-			mux++;
-		}
-	}
-
-	pctldev->num_functions = nfunctions;
-	functions = krealloc(functions, nfunctions * sizeof(*functions),
-			     GFP_KERNEL);
-
-	/* Find pin groups for every single function */
-	for (i = 0; i < info->npins; i++) {
-		const struct pinctrl_pin_desc *pindesc = info->pins + i;
-		struct zx_pin_data *data = pindesc->drv_data;
-		struct zx_mux_desc *mux;
-
-		if (!data)
-			continue;
-
-		mux = data->muxes;
-		while (mux->name) {
-			struct function_desc *func;
-			const char **group;
-			int j;
-
-			/* Find function for given mux */
-			for (j = 0; j < nfunctions; j++)
-				if (strcmp(functions[j].name, mux->name) == 0)
-					break;
-
-			func = functions + j;
-			if (!func->group_names) {
-				func->group_names = devm_kcalloc(&pdev->dev,
-						func->num_group_names,
-						sizeof(*func->group_names),
-						GFP_KERNEL);
-				if (!func->group_names) {
-					kfree(functions);
-					return -ENOMEM;
-				}
-			}
-
-			group = func->group_names;
-			while (*group)
-				group++;
-			*group = pindesc->name;
-
-			mux++;
-		}
-	}
-
-	return 0;
-}
-
-int zx_pinctrl_init(struct platform_device *pdev,
-		    struct zx_pinctrl_soc_info *info)
-{
-	struct pinctrl_desc *pctldesc;
-	struct zx_pinctrl *zpctl;
-	struct device_node *np;
-	int ret;
-
-	zpctl = devm_kzalloc(&pdev->dev, sizeof(*zpctl), GFP_KERNEL);
-	if (!zpctl)
-		return -ENOMEM;
-
-	spin_lock_init(&zpctl->lock);
-
-	zpctl->base = devm_platform_ioremap_resource(pdev, 0);
-	if (IS_ERR(zpctl->base))
-		return PTR_ERR(zpctl->base);
-
-	np = of_parse_phandle(pdev->dev.of_node, "zte,auxiliary-controller", 0);
-	if (!np) {
-		dev_err(&pdev->dev, "failed to find auxiliary controller\n");
-		return -ENODEV;
-	}
-
-	zpctl->aux_base = of_iomap(np, 0);
-	of_node_put(np);
-	if (!zpctl->aux_base)
-		return -ENOMEM;
-
-	zpctl->dev = &pdev->dev;
-	zpctl->info = info;
-
-	pctldesc = devm_kzalloc(&pdev->dev, sizeof(*pctldesc), GFP_KERNEL);
-	if (!pctldesc)
-		return -ENOMEM;
-
-	pctldesc->name = dev_name(&pdev->dev);
-	pctldesc->owner = THIS_MODULE;
-	pctldesc->pins = info->pins;
-	pctldesc->npins = info->npins;
-	pctldesc->pctlops = &zx_pinctrl_ops;
-	pctldesc->pmxops = &zx_pinmux_ops;
-	pctldesc->confops = &zx_pinconf_ops;
-
-	zpctl->pctldev = devm_pinctrl_register(&pdev->dev, pctldesc, zpctl);
-	if (IS_ERR(zpctl->pctldev)) {
-		ret = PTR_ERR(zpctl->pctldev);
-		dev_err(&pdev->dev, "failed to register pinctrl: %d\n", ret);
-		return ret;
-	}
-
-	platform_set_drvdata(pdev, zpctl);
-
-	ret = zx_pinctrl_build_state(pdev);
-	if (ret) {
-		dev_err(&pdev->dev, "failed to build state: %d\n", ret);
-		return ret;
-	}
-
-	dev_info(&pdev->dev, "initialized pinctrl driver\n");
-	return 0;
-}
diff --git a/drivers/pinctrl/zte/pinctrl-zx.h b/drivers/pinctrl/zte/pinctrl-zx.h
deleted file mode 100644
index a0692e2e9012..000000000000
--- a/drivers/pinctrl/zte/pinctrl-zx.h
+++ /dev/null
@@ -1,102 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * Copyright (C) 2017 Sanechips Technology Co., Ltd.
- * Copyright 2017 Linaro Ltd.
- */
-
-#ifndef __PINCTRL_ZX_H
-#define __PINCTRL_ZX_H
-
-/**
- * struct zx_mux_desc - hardware mux descriptor
- * @name: mux function name
- * @muxval: mux register bit value
- */
-struct zx_mux_desc {
-	const char *name;
-	u8 muxval;
-};
-
-/**
- * struct zx_pin_data - hardware per-pin data
- * @aon_pin: whether it's an AON pin
- * @offset: register offset within TOP pinmux controller
- * @bitpos: bit position within TOP pinmux register
- * @width: bit width within TOP pinmux register
- * @coffset: pinconf register offset within AON controller
- * @cbitpos: pinconf bit position within AON register
- * @muxes: available mux function names and corresponding register values
- *
- * Unlike TOP pinmux and AON pinconf registers which are arranged pretty
- * arbitrarily, AON pinmux register bits are well organized per pin id, and
- * each pin occupies two bits, so that we can calculate the AON register offset
- * and bit position from pin id.  Thus, we only need to define TOP pinmux and
- * AON pinconf register data for the pin.
- */
-struct zx_pin_data {
-	bool aon_pin;
-	u16 offset;
-	u16 bitpos;
-	u16 width;
-	u16 coffset;
-	u16 cbitpos;
-	struct zx_mux_desc *muxes;
-};
-
-struct zx_pinctrl_soc_info {
-	const struct pinctrl_pin_desc *pins;
-	unsigned int npins;
-};
-
-#define TOP_PIN(pin, off, bp, wd, coff, cbp, ...) {		\
-	.number = pin,						\
-	.name = #pin,						\
-	.drv_data = &(struct zx_pin_data) {			\
-		.aon_pin = false,				\
-		.offset = off,					\
-		.bitpos = bp,					\
-		.width = wd,					\
-		.coffset = coff,				\
-		.cbitpos = cbp,					\
-		.muxes = (struct zx_mux_desc[]) {		\
-			 __VA_ARGS__, { } },			\
-	},							\
-}
-
-#define AON_PIN(pin, off, bp, wd, coff, cbp, ...) {		\
-	.number = pin,						\
-	.name = #pin,						\
-	.drv_data = &(struct zx_pin_data) {			\
-		.aon_pin = true,				\
-		.offset = off,					\
-		.bitpos = bp,					\
-		.width = wd,					\
-		.coffset = coff,				\
-		.cbitpos = cbp,					\
-		.muxes = (struct zx_mux_desc[]) {		\
-			 __VA_ARGS__, { } },			\
-	},							\
-}
-
-#define ZX_RESERVED(pin) PINCTRL_PIN(pin, #pin)
-
-#define TOP_MUX(_val, _name) {					\
-	.name = _name,						\
-	.muxval = _val,						\
-}
-
-/*
- * When the flag is set, it's a mux configuration for an AON pin that sits in
- * AON register.  Otherwise, it's one for AON pin but sitting in TOP register.
- */
-#define AON_MUX_FLAG BIT(7)
-
-#define AON_MUX(_val, _name) {					\
-	.name = _name,						\
-	.muxval = _val | AON_MUX_FLAG,				\
-}
-
-int zx_pinctrl_init(struct platform_device *pdev,
-		    struct zx_pinctrl_soc_info *info);
-
-#endif /* __PINCTRL_ZX_H */
diff --git a/drivers/pinctrl/zte/pinctrl-zx296718.c b/drivers/pinctrl/zte/pinctrl-zx296718.c
deleted file mode 100644
index c980aecb6f2f..000000000000
--- a/drivers/pinctrl/zte/pinctrl-zx296718.c
+++ /dev/null
@@ -1,1024 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Copyright (C) 2017 Sanechips Technology Co., Ltd.
- * Copyright 2017 Linaro Ltd.
- */
-
-#include <linux/module.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-#include <linux/of_device.h>
-#include <linux/pinctrl/pinctrl.h>
-#include <linux/platform_device.h>
-
-#include "pinctrl-zx.h"
-
-#define TOP_REG0	0x00
-#define TOP_REG1	0x04
-#define TOP_REG2	0x08
-#define TOP_REG3	0x0c
-#define TOP_REG4	0x10
-#define TOP_REG5	0x14
-#define TOP_REG6	0x18
-#define TOP_REG7	0x1c
-#define TOP_REG8	0x20
-
-/*
- * The pin numbering starts from AON pins with reserved ones included,
- * so that register data like offset and bit position for AON pins can
- * be calculated from pin number.
- */
-enum zx296718_pin {
-	/* aon_pmm_reg_0 */
-	I2C3_SCL = 0,
-	I2C3_SDA = 1,
-	AON_RESERVED0 = 2,
-	AON_RESERVED1 = 3,
-	SEC_EN = 4,
-	UART0_RXD = 5,
-	UART0_TXD = 6,
-	IR_IN = 7,
-	SPI0_CLK = 8,
-	SPI0_CS = 9,
-	SPI0_TXD = 10,
-	SPI0_RXD = 11,
-	KEY_COL0 = 12,
-	KEY_COL1 = 13,
-	KEY_COL2 = 14,
-	KEY_ROW0 = 15,
-
-	/* aon_pmm_reg_1 */
-	KEY_ROW1 = 16,
-	KEY_ROW2 = 17,
-	HDMI_SCL = 18,
-	HDMI_SDA = 19,
-	JTAG_TCK = 20,
-	JTAG_TRSTN = 21,
-	JTAG_TMS = 22,
-	JTAG_TDI = 23,
-	JTAG_TDO = 24,
-	I2C0_SCL = 25,
-	I2C0_SDA = 26,
-	I2C1_SCL = 27,
-	I2C1_SDA = 28,
-	AON_RESERVED2 = 29,
-	AON_RESERVED3 = 30,
-	AON_RESERVED4 = 31,
-
-	/* aon_pmm_reg_2 */
-	SPI1_CLK = 32,
-	SPI1_CS = 33,
-	SPI1_TXD = 34,
-	SPI1_RXD = 35,
-	AON_RESERVED5 = 36,
-	AON_RESERVED6 = 37,
-	AUDIO_DET = 38,
-	SPDIF_OUT = 39,
-	HDMI_CEC = 40,
-	HDMI_HPD = 41,
-	GMAC_25M_OUT = 42,
-	BOOT_SEL0 = 43,
-	BOOT_SEL1 = 44,
-	BOOT_SEL2 = 45,
-	DEEP_SLEEP_OUT_N = 46,
-	AON_RESERVED7 = 47,
-
-	/* top_pmm_reg_0 */
-	GMII_GTX_CLK = 48,
-	GMII_TX_CLK = 49,
-	GMII_TXD0 = 50,
-	GMII_TXD1 = 51,
-	GMII_TXD2 = 52,
-	GMII_TXD3 = 53,
-	GMII_TXD4 = 54,
-	GMII_TXD5 = 55,
-	GMII_TXD6 = 56,
-	GMII_TXD7 = 57,
-	GMII_TX_ER = 58,
-	GMII_TX_EN = 59,
-	GMII_RX_CLK = 60,
-	GMII_RXD0 = 61,
-	GMII_RXD1 = 62,
-	GMII_RXD2 = 63,
-
-	/* top_pmm_reg_1 */
-	GMII_RXD3 = 64,
-	GMII_RXD4 = 65,
-	GMII_RXD5 = 66,
-	GMII_RXD6 = 67,
-	GMII_RXD7 = 68,
-	GMII_RX_ER = 69,
-	GMII_RX_DV = 70,
-	GMII_COL = 71,
-	GMII_CRS = 72,
-	GMII_MDC = 73,
-	GMII_MDIO = 74,
-	SDIO1_CLK = 75,
-	SDIO1_CMD = 76,
-	SDIO1_DATA0 = 77,
-	SDIO1_DATA1 = 78,
-	SDIO1_DATA2 = 79,
-
-	/* top_pmm_reg_2 */
-	SDIO1_DATA3 = 80,
-	SDIO1_CD = 81,
-	SDIO1_WP = 82,
-	USIM1_CD = 83,
-	USIM1_CLK = 84,
-	USIM1_RST = 85,
-
-	/* top_pmm_reg_3 */
-	USIM1_DATA = 86,
-	SDIO0_CLK = 87,
-	SDIO0_CMD = 88,
-	SDIO0_DATA0 = 89,
-	SDIO0_DATA1 = 90,
-	SDIO0_DATA2 = 91,
-	SDIO0_DATA3 = 92,
-	SDIO0_CD = 93,
-	SDIO0_WP = 94,
-
-	/* top_pmm_reg_4 */
-	TSI0_DATA0 = 95,
-	SPINOR_CLK = 96,
-	TSI2_DATA = 97,
-	TSI2_CLK = 98,
-	TSI2_SYNC = 99,
-	TSI2_VALID = 100,
-	SPINOR_CS = 101,
-	SPINOR_DQ0 = 102,
-	SPINOR_DQ1 = 103,
-	SPINOR_DQ2 = 104,
-	SPINOR_DQ3 = 105,
-	VGA_HS = 106,
-	VGA_VS = 107,
-	TSI3_DATA = 108,
-
-	/* top_pmm_reg_5 */
-	TSI3_CLK = 109,
-	TSI3_SYNC = 110,
-	TSI3_VALID = 111,
-	I2S1_WS = 112,
-	I2S1_BCLK = 113,
-	I2S1_MCLK = 114,
-	I2S1_DIN0 = 115,
-	I2S1_DOUT0 = 116,
-	SPI3_CLK = 117,
-	SPI3_CS = 118,
-	SPI3_TXD = 119,
-	NAND_LDO_MS18_SEL = 120,
-
-	/* top_pmm_reg_6 */
-	SPI3_RXD = 121,
-	I2S0_MCLK = 122,
-	I2S0_BCLK = 123,
-	I2S0_WS = 124,
-	I2S0_DIN0 = 125,
-	I2S0_DOUT0 = 126,
-	I2C5_SCL = 127,
-	I2C5_SDA = 128,
-	SPI2_CLK = 129,
-	SPI2_CS = 130,
-	SPI2_TXD = 131,
-
-	/* top_pmm_reg_7 */
-	SPI2_RXD = 132,
-	NAND_WP_N = 133,
-	NAND_PAGE_SIZE0 = 134,
-	NAND_PAGE_SIZE1 = 135,
-	NAND_ADDR_CYCLE = 136,
-	NAND_RB0 = 137,
-	NAND_RB1 = 138,
-	NAND_RB2 = 139,
-	NAND_RB3 = 140,
-
-	/* top_pmm_reg_8 */
-	GMAC_125M_IN = 141,
-	GMAC_50M_OUT = 142,
-	SPINOR_SSCLK_LOOPBACK = 143,
-	SPINOR_SDIO1CLK_LOOPBACK = 144,
-};
-
-static const struct pinctrl_pin_desc zx296718_pins[] = {
-	/* aon_pmm_reg_0 */
-	AON_PIN(I2C3_SCL, TOP_REG2, 18, 2, 0x48, 0,
-		AON_MUX(0x0, "ANMI"),		/* anmi */
-		AON_MUX(0x1, "AGPIO"),		/* agpio29 */
-		AON_MUX(0x2, "nonAON"),		/* pin0 */
-		AON_MUX(0x3, "EXT_INT"),	/* int4 */
-		TOP_MUX(0x0, "I2C3"),		/* scl */
-		TOP_MUX(0x1, "SPI2"),		/* txd */
-		TOP_MUX(0x2, "I2S1")),		/* din0 */
-	AON_PIN(I2C3_SDA, TOP_REG2, 20, 2, 0x48, 9,
-		AON_MUX(0x0, "WD"),		/* rst_b */
-		AON_MUX(0x1, "AGPIO"),		/* agpio30 */
-		AON_MUX(0x2, "nonAON"),		/* pin1 */
-		AON_MUX(0x3, "EXT_INT"),	/* int5 */
-		TOP_MUX(0x0, "I2C3"),		/* sda */
-		TOP_MUX(0x1, "SPI2"),		/* rxd */
-		TOP_MUX(0x2, "I2S0")),		/* mclk */
-	ZX_RESERVED(AON_RESERVED0),
-	ZX_RESERVED(AON_RESERVED1),
-	AON_PIN(SEC_EN, TOP_REG3, 5, 1, 0x50, 0,
-		AON_MUX(0x0, "SEC"),		/* en */
-		AON_MUX(0x1, "AGPIO"),		/* agpio28 */
-		AON_MUX(0x2, "nonAON"),		/* pin3 */
-		AON_MUX(0x3, "EXT_INT"),	/* int7 */
-		TOP_MUX(0x0, "I2C2"),		/* sda */
-		TOP_MUX(0x1, "SPI2")),		/* cs */
-	AON_PIN(UART0_RXD, 0, 0, 0, 0x50, 9,
-		AON_MUX(0x0, "UART0"),		/* rxd */
-		AON_MUX(0x1, "AGPIO"),		/* agpio20 */
-		AON_MUX(0x2, "nonAON")),	/* pin34 */
-	AON_PIN(UART0_TXD, 0, 0, 0, 0x50, 18,
-		AON_MUX(0x0, "UART0"),		/* txd */
-		AON_MUX(0x1, "AGPIO"),		/* agpio21 */
-		AON_MUX(0x2, "nonAON")),	/* pin32 */
-	AON_PIN(IR_IN, 0, 0, 0, 0x64, 0,
-		AON_MUX(0x0, "IR"),		/* in */
-		AON_MUX(0x1, "AGPIO"),		/* agpio0 */
-		AON_MUX(0x2, "nonAON")),	/* pin27 */
-	AON_PIN(SPI0_CLK, TOP_REG3, 16, 1, 0x64, 9,
-		AON_MUX(0x0, "EXT_INT"),	/* int0 */
-		AON_MUX(0x1, "AGPIO"),		/* agpio23 */
-		AON_MUX(0x2, "nonAON"),		/* pin5 */
-		AON_MUX(0x3, "PCU"),		/* test6 */
-		TOP_MUX(0x0, "SPI0"),		/* clk */
-		TOP_MUX(0x1, "ISP")),		/* flash_trig */
-	AON_PIN(SPI0_CS, TOP_REG3, 17, 1, 0x64, 18,
-		AON_MUX(0x0, "EXT_INT"),	/* int1 */
-		AON_MUX(0x1, "AGPIO"),		/* agpio24 */
-		AON_MUX(0x2, "nonAON"),		/* pin6 */
-		AON_MUX(0x3, "PCU"),		/* test0 */
-		TOP_MUX(0x0, "SPI0"),		/* cs */
-		TOP_MUX(0x1, "ISP")),		/* prelight_trig */
-	AON_PIN(SPI0_TXD, TOP_REG3, 18, 1, 0x68, 0,
-		AON_MUX(0x0, "EXT_INT"),	/* int2 */
-		AON_MUX(0x1, "AGPIO"),		/* agpio25 */
-		AON_MUX(0x2, "nonAON"),		/* pin7 */
-		AON_MUX(0x3, "PCU"),		/* test1 */
-		TOP_MUX(0x0, "SPI0"),		/* txd */
-		TOP_MUX(0x1, "ISP")),		/* shutter_trig */
-	AON_PIN(SPI0_RXD, TOP_REG3, 19, 1, 0x68, 9,
-		AON_MUX(0x0, "EXT_INT"),	/* int3 */
-		AON_MUX(0x1, "AGPIO"),		/* agpio26 */
-		AON_MUX(0x2, "nonAON"),		/* pin8 */
-		AON_MUX(0x3, "PCU"),		/* test2 */
-		TOP_MUX(0x0, "SPI0"),		/* rxd */
-		TOP_MUX(0x1, "ISP")),		/* shutter_open */
-	AON_PIN(KEY_COL0, TOP_REG3, 20, 1, 0x68, 18,
-		AON_MUX(0x0, "KEY"),		/* col0 */
-		AON_MUX(0x1, "AGPIO"),		/* agpio5 */
-		AON_MUX(0x2, "nonAON"),		/* pin9 */
-		AON_MUX(0x3, "PCU"),		/* test3 */
-		TOP_MUX(0x0, "UART3"),		/* rxd */
-		TOP_MUX(0x1, "I2S0")),		/* din1 */
-	AON_PIN(KEY_COL1, TOP_REG3, 21, 2, 0x6c, 0,
-		AON_MUX(0x0, "KEY"),		/* col1 */
-		AON_MUX(0x1, "AGPIO"),		/* agpio6 */
-		AON_MUX(0x2, "nonAON"),		/* pin10 */
-		TOP_MUX(0x0, "UART3"),		/* txd */
-		TOP_MUX(0x1, "I2S0"),		/* din2 */
-		TOP_MUX(0x2, "VGA")),		/* scl */
-	AON_PIN(KEY_COL2, TOP_REG3, 23, 2, 0x6c, 9,
-		AON_MUX(0x0, "KEY"),		/* col2 */
-		AON_MUX(0x1, "AGPIO"),		/* agpio7 */
-		AON_MUX(0x2, "nonAON"),		/* pin11 */
-		TOP_MUX(0x0, "PWM"),		/* out1 */
-		TOP_MUX(0x1, "I2S0"),		/* din3 */
-		TOP_MUX(0x2, "VGA")),		/* sda */
-	AON_PIN(KEY_ROW0, 0, 0, 0, 0x6c, 18,
-		AON_MUX(0x0, "KEY"),		/* row0 */
-		AON_MUX(0x1, "AGPIO"),		/* agpio8 */
-		AON_MUX(0x2, "nonAON"),		/* pin33 */
-		AON_MUX(0x3, "WD")),		/* rst_b */
-
-	/* aon_pmm_reg_1 */
-	AON_PIN(KEY_ROW1, TOP_REG3, 25, 2, 0x70, 0,
-		AON_MUX(0x0, "KEY"),		/* row1 */
-		AON_MUX(0x1, "AGPIO"),		/* agpio9 */
-		AON_MUX(0x2, "nonAON"),		/* pin12 */
-		TOP_MUX(0x0, "LCD"),		/* port0 lcd_te */
-		TOP_MUX(0x1, "I2S0"),		/* dout2 */
-		TOP_MUX(0x2, "PWM"),		/* out2 */
-		TOP_MUX(0x3, "VGA")),		/* hs1 */
-	AON_PIN(KEY_ROW2, TOP_REG3, 27, 2, 0x70, 9,
-		AON_MUX(0x0, "KEY"),		/* row2 */
-		AON_MUX(0x1, "AGPIO"),		/* agpio10 */
-		AON_MUX(0x2, "nonAON"),		/* pin13 */
-		TOP_MUX(0x0, "LCD"),		/* port1 lcd_te */
-		TOP_MUX(0x1, "I2S0"),		/* dout3 */
-		TOP_MUX(0x2, "PWM"),		/* out3 */
-		TOP_MUX(0x3, "VGA")),		/* vs1 */
-	AON_PIN(HDMI_SCL, TOP_REG3, 29, 1, 0x70, 18,
-		AON_MUX(0x0, "PCU"),		/* test7 */
-		AON_MUX(0x1, "AGPIO"),		/* agpio3 */
-		AON_MUX(0x2, "nonAON"),		/* pin14 */
-		TOP_MUX(0x0, "HDMI"),		/* scl */
-		TOP_MUX(0x1, "UART3")),		/* rxd */
-	AON_PIN(HDMI_SDA, TOP_REG3, 30, 1, 0x74, 0,
-		AON_MUX(0x0, "PCU"),		/* test8 */
-		AON_MUX(0x1, "AGPIO"),		/* agpio4 */
-		AON_MUX(0x2, "nonAON"),		/* pin15 */
-		TOP_MUX(0x0, "HDMI"),		/* sda */
-		TOP_MUX(0x1, "UART3")),		/* txd */
-	AON_PIN(JTAG_TCK, TOP_REG7, 3, 1, 0x78, 18,
-		AON_MUX(0x0, "JTAG"),		/* tck */
-		AON_MUX(0x1, "AGPIO"),		/* agpio11 */
-		AON_MUX(0x2, "nonAON"),		/* pin22 */
-		AON_MUX(0x3, "EXT_INT"),	/* int4 */
-		TOP_MUX(0x0, "SPI4"),		/* clk */
-		TOP_MUX(0x1, "UART1")),		/* rxd */
-	AON_PIN(JTAG_TRSTN, TOP_REG7, 4, 1, 0xac, 0,
-		AON_MUX(0x0, "JTAG"),		/* trstn */
-		AON_MUX(0x1, "AGPIO"),		/* agpio12 */
-		AON_MUX(0x2, "nonAON"),		/* pin23 */
-		AON_MUX(0x3, "EXT_INT"),	/* int5 */
-		TOP_MUX(0x0, "SPI4"),		/* cs */
-		TOP_MUX(0x1, "UART1")),		/* txd */
-	AON_PIN(JTAG_TMS, TOP_REG7, 5, 1, 0xac, 9,
-		AON_MUX(0x0, "JTAG"),		/* tms */
-		AON_MUX(0x1, "AGPIO"),		/* agpio13 */
-		AON_MUX(0x2, "nonAON"),		/* pin24 */
-		AON_MUX(0x3, "EXT_INT"),	/* int6 */
-		TOP_MUX(0x0, "SPI4"),		/* txd */
-		TOP_MUX(0x1, "UART2")),		/* rxd */
-	AON_PIN(JTAG_TDI, TOP_REG7, 6, 1, 0xac, 18,
-		AON_MUX(0x0, "JTAG"),		/* tdi */
-		AON_MUX(0x1, "AGPIO"),		/* agpio14 */
-		AON_MUX(0x2, "nonAON"),		/* pin25 */
-		AON_MUX(0x3, "EXT_INT"),	/* int7 */
-		TOP_MUX(0x0, "SPI4"),		/* rxd */
-		TOP_MUX(0x1, "UART2")),		/* txd */
-	AON_PIN(JTAG_TDO, 0, 0, 0, 0xb0, 0,
-		AON_MUX(0x0, "JTAG"),		/* tdo */
-		AON_MUX(0x1, "AGPIO"),		/* agpio15 */
-		AON_MUX(0x2, "nonAON")),	/* pin26 */
-	AON_PIN(I2C0_SCL, 0, 0, 0, 0xb0, 9,
-		AON_MUX(0x0, "I2C0"),		/* scl */
-		AON_MUX(0x1, "AGPIO"),		/* agpio16 */
-		AON_MUX(0x2, "nonAON")),	/* pin28 */
-	AON_PIN(I2C0_SDA, 0, 0, 0, 0xb0, 18,
-		AON_MUX(0x0, "I2C0"),		/* sda */
-		AON_MUX(0x1, "AGPIO"),		/* agpio17 */
-		AON_MUX(0x2, "nonAON")),	/* pin29 */
-	AON_PIN(I2C1_SCL, TOP_REG8, 4, 1, 0xb4, 0,
-		AON_MUX(0x0, "I2C1"),		/* scl */
-		AON_MUX(0x1, "AGPIO"),		/* agpio18 */
-		AON_MUX(0x2, "nonAON"),		/* pin30 */
-		TOP_MUX(0x0, "LCD")),		/* port0 lcd_te */
-	AON_PIN(I2C1_SDA, TOP_REG8, 5, 1, 0xb4, 9,
-		AON_MUX(0x0, "I2C1"),		/* sda */
-		AON_MUX(0x1, "AGPIO"),		/* agpio19 */
-		AON_MUX(0x2, "nonAON"),		/* pin31 */
-		TOP_MUX(0x0, "LCD")),		/* port1 lcd_te */
-	ZX_RESERVED(AON_RESERVED2),
-	ZX_RESERVED(AON_RESERVED3),
-	ZX_RESERVED(AON_RESERVED4),
-
-	/* aon_pmm_reg_2 */
-	AON_PIN(SPI1_CLK, TOP_REG2, 6, 3, 0x40, 9,
-		AON_MUX(0x0, "EXT_INT"),	/* int0 */
-		AON_MUX(0x1, "PCU"),		/* test12 */
-		AON_MUX(0x2, "nonAON"),		/* pin39 */
-		TOP_MUX(0x0, "SPI1"),		/* clk */
-		TOP_MUX(0x1, "PCM"),		/* clk */
-		TOP_MUX(0x2, "BGPIO"),		/* gpio35 */
-		TOP_MUX(0x3, "I2C4"),		/* scl */
-		TOP_MUX(0x4, "I2S1"),		/* mclk */
-		TOP_MUX(0x5, "ISP")),		/* flash_trig */
-	AON_PIN(SPI1_CS, TOP_REG2, 9, 3, 0x40, 18,
-		AON_MUX(0x0, "EXT_INT"),	/* int1 */
-		AON_MUX(0x1, "PCU"),		/* test13 */
-		AON_MUX(0x2, "nonAON"),		/* pin40 */
-		TOP_MUX(0x0, "SPI1"),		/* cs */
-		TOP_MUX(0x1, "PCM"),		/* fs */
-		TOP_MUX(0x2, "BGPIO"),		/* gpio36 */
-		TOP_MUX(0x3, "I2C4"),		/* sda */
-		TOP_MUX(0x4, "I2S1"),		/* bclk */
-		TOP_MUX(0x5, "ISP")),		/* prelight_trig */
-	AON_PIN(SPI1_TXD, TOP_REG2, 12, 3, 0x44, 0,
-		AON_MUX(0x0, "EXT_INT"),	/* int2 */
-		AON_MUX(0x1, "PCU"),		/* test14 */
-		AON_MUX(0x2, "nonAON"),		/* pin41 */
-		TOP_MUX(0x0, "SPI1"),		/* txd */
-		TOP_MUX(0x1, "PCM"),		/* txd */
-		TOP_MUX(0x2, "BGPIO"),		/* gpio37 */
-		TOP_MUX(0x3, "UART5"),		/* rxd */
-		TOP_MUX(0x4, "I2S1"),		/* ws */
-		TOP_MUX(0x5, "ISP")),		/* shutter_trig */
-	AON_PIN(SPI1_RXD, TOP_REG2, 15, 3, 0x44, 9,
-		AON_MUX(0x0, "EXT_INT"),	/* int3 */
-		AON_MUX(0x1, "PCU"),		/* test15 */
-		AON_MUX(0x2, "nonAON"),		/* pin42 */
-		TOP_MUX(0x0, "SPI1"),		/* rxd */
-		TOP_MUX(0x1, "PCM"),		/* rxd */
-		TOP_MUX(0x2, "BGPIO"),		/* gpio38 */
-		TOP_MUX(0x3, "UART5"),		/* txd */
-		TOP_MUX(0x4, "I2S1"),		/* dout0 */
-		TOP_MUX(0x5, "ISP")),		/* shutter_open */
-	ZX_RESERVED(AON_RESERVED5),
-	ZX_RESERVED(AON_RESERVED6),
-	AON_PIN(AUDIO_DET, TOP_REG3, 3, 2, 0x48, 18,
-		AON_MUX(0x0, "PCU"),		/* test4 */
-		AON_MUX(0x1, "AGPIO"),		/* agpio27 */
-		AON_MUX(0x2, "nonAON"),		/* pin2 */
-		AON_MUX(0x3, "EXT_INT"),	/* int16 */
-		TOP_MUX(0x0, "AUDIO"),		/* detect */
-		TOP_MUX(0x1, "I2C2"),		/* scl */
-		TOP_MUX(0x2, "SPI2")),		/* clk */
-	AON_PIN(SPDIF_OUT, TOP_REG3, 14, 2, 0x78, 9,
-		AON_MUX(0x0, "PCU"),		/* test5 */
-		AON_MUX(0x1, "AGPIO"),		/* agpio22 */
-		AON_MUX(0x2, "nonAON"),		/* pin4 */
-		TOP_MUX(0x0, "SPDIF"),		/* out */
-		TOP_MUX(0x1, "PWM"),		/* out0 */
-		TOP_MUX(0x2, "ISP")),		/* fl_trig */
-	AON_PIN(HDMI_CEC, 0, 0, 0, 0x74, 9,
-		AON_MUX(0x0, "PCU"),		/* test9 */
-		AON_MUX(0x1, "AGPIO"),		/* agpio1 */
-		AON_MUX(0x2, "nonAON")),	/* pin16 */
-	AON_PIN(HDMI_HPD, 0, 0, 0, 0x74, 18,
-		AON_MUX(0x0, "PCU"),		/* test10 */
-		AON_MUX(0x1, "AGPIO"),		/* agpio2 */
-		AON_MUX(0x2, "nonAON")),	/* pin17 */
-	AON_PIN(GMAC_25M_OUT, 0, 0, 0, 0x78, 0,
-		AON_MUX(0x0, "PCU"),		/* test11 */
-		AON_MUX(0x1, "AGPIO"),		/* agpio31 */
-		AON_MUX(0x2, "nonAON")),	/* pin43 */
-	AON_PIN(BOOT_SEL0, 0, 0, 0, 0xc0, 9,
-		AON_MUX(0x0, "BOOT"),		/* sel0 */
-		AON_MUX(0x1, "AGPIO"),		/* agpio18 */
-		AON_MUX(0x2, "nonAON")),	/* pin18 */
-	AON_PIN(BOOT_SEL1, 0, 0, 0, 0xc0, 18,
-		AON_MUX(0x0, "BOOT"),		/* sel1 */
-		AON_MUX(0x1, "AGPIO"),		/* agpio19 */
-		AON_MUX(0x2, "nonAON")),	/* pin19 */
-	AON_PIN(BOOT_SEL2, 0, 0, 0, 0xc4, 0,
-		AON_MUX(0x0, "BOOT"),		/* sel2 */
-		AON_MUX(0x1, "AGPIO"),		/* agpio20 */
-		AON_MUX(0x2, "nonAON")),	/* pin20 */
-	AON_PIN(DEEP_SLEEP_OUT_N, 0, 0, 0, 0xc4, 9,
-		AON_MUX(0x0, "DEEPSLP"),	/* deep sleep out_n */
-		AON_MUX(0x1, "AGPIO"),		/* agpio21 */
-		AON_MUX(0x2, "nonAON")),	/* pin21 */
-	ZX_RESERVED(AON_RESERVED7),
-
-	/* top_pmm_reg_0 */
-	TOP_PIN(GMII_GTX_CLK, TOP_REG0, 0, 2, 0x10, 0,
-		TOP_MUX(0x0, "GMII"),		/* gtx_clk */
-		TOP_MUX(0x1, "DVI0"),		/* clk */
-		TOP_MUX(0x2, "BGPIO")),		/* gpio0 */
-	TOP_PIN(GMII_TX_CLK, TOP_REG0, 2, 2, 0x10, 9,
-		TOP_MUX(0x0, "GMII"),		/* tx_clk */
-		TOP_MUX(0x1, "DVI0"),		/* vs */
-		TOP_MUX(0x2, "BGPIO")),		/* gpio1 */
-	TOP_PIN(GMII_TXD0, TOP_REG0, 4, 2, 0x10, 18,
-		TOP_MUX(0x0, "GMII"),		/* txd0 */
-		TOP_MUX(0x1, "DVI0"),		/* hs */
-		TOP_MUX(0x2, "BGPIO")),		/* gpio2 */
-	TOP_PIN(GMII_TXD1, TOP_REG0, 6, 2, 0x14, 0,
-		TOP_MUX(0x0, "GMII"),		/* txd1 */
-		TOP_MUX(0x1, "DVI0"),		/* d0 */
-		TOP_MUX(0x2, "BGPIO")),		/* gpio3 */
-	TOP_PIN(GMII_TXD2, TOP_REG0, 8, 2, 0x14, 9,
-		TOP_MUX(0x0, "GMII"),		/* txd2 */
-		TOP_MUX(0x1, "DVI0"),		/* d1 */
-		TOP_MUX(0x2, "BGPIO")),		/* gpio4 */
-	TOP_PIN(GMII_TXD3, TOP_REG0, 10, 2, 0x14, 18,
-		TOP_MUX(0x0, "GMII"),		/* txd3 */
-		TOP_MUX(0x1, "DVI0"),		/* d2 */
-		TOP_MUX(0x2, "BGPIO")),		/* gpio5 */
-	TOP_PIN(GMII_TXD4, TOP_REG0, 12, 2, 0x18, 0,
-		TOP_MUX(0x0, "GMII"),		/* txd4 */
-		TOP_MUX(0x1, "DVI0"),		/* d3 */
-		TOP_MUX(0x2, "BGPIO")),		/* gpio6 */
-	TOP_PIN(GMII_TXD5, TOP_REG0, 14, 2, 0x18, 9,
-		TOP_MUX(0x0, "GMII"),		/* txd5 */
-		TOP_MUX(0x1, "DVI0"),		/* d4 */
-		TOP_MUX(0x2, "BGPIO")),		/* gpio7 */
-	TOP_PIN(GMII_TXD6, TOP_REG0, 16, 2, 0x18, 18,
-		TOP_MUX(0x0, "GMII"),		/* txd6 */
-		TOP_MUX(0x1, "DVI0"),		/* d5 */
-		TOP_MUX(0x2, "BGPIO")),		/* gpio8 */
-	TOP_PIN(GMII_TXD7, TOP_REG0, 18, 2, 0x1c, 0,
-		TOP_MUX(0x0, "GMII"),		/* txd7 */
-		TOP_MUX(0x1, "DVI0"),		/* d6 */
-		TOP_MUX(0x2, "BGPIO")),		/* gpio9 */
-	TOP_PIN(GMII_TX_ER, TOP_REG0, 20, 2, 0x1c, 9,
-		TOP_MUX(0x0, "GMII"),		/* tx_er */
-		TOP_MUX(0x1, "DVI0"),		/* d7 */
-		TOP_MUX(0x2, "BGPIO")),		/* gpio10 */
-	TOP_PIN(GMII_TX_EN, TOP_REG0, 22, 2, 0x1c, 18,
-		TOP_MUX(0x0, "GMII"),		/* tx_en */
-		TOP_MUX(0x1, "DVI0"),		/* d8 */
-		TOP_MUX(0x3, "BGPIO")),		/* gpio11 */
-	TOP_PIN(GMII_RX_CLK, TOP_REG0, 24, 2, 0x20, 0,
-		TOP_MUX(0x0, "GMII"),		/* rx_clk */
-		TOP_MUX(0x1, "DVI0"),		/* d9 */
-		TOP_MUX(0x3, "BGPIO")),		/* gpio12 */
-	TOP_PIN(GMII_RXD0, TOP_REG0, 26, 2, 0x20, 9,
-		TOP_MUX(0x0, "GMII"),		/* rxd0 */
-		TOP_MUX(0x1, "DVI0"),		/* d10 */
-		TOP_MUX(0x3, "BGPIO")),		/* gpio13 */
-	TOP_PIN(GMII_RXD1, TOP_REG0, 28, 2, 0x20, 18,
-		TOP_MUX(0x0, "GMII"),		/* rxd1 */
-		TOP_MUX(0x1, "DVI0"),		/* d11 */
-		TOP_MUX(0x2, "BGPIO")),		/* gpio14 */
-	TOP_PIN(GMII_RXD2, TOP_REG0, 30, 2, 0x24, 0,
-		TOP_MUX(0x0, "GMII"),		/* rxd2 */
-		TOP_MUX(0x1, "DVI1"),		/* clk */
-		TOP_MUX(0x2, "BGPIO")),		/* gpio15 */
-
-	/* top_pmm_reg_1 */
-	TOP_PIN(GMII_RXD3, TOP_REG1, 0, 2, 0x24, 9,
-		TOP_MUX(0x0, "GMII"),		/* rxd3 */
-		TOP_MUX(0x1, "DVI1"),		/* hs */
-		TOP_MUX(0x2, "BGPIO")),		/* gpio16 */
-	TOP_PIN(GMII_RXD4, TOP_REG1, 2, 2, 0x24, 18,
-		TOP_MUX(0x0, "GMII"),		/* rxd4 */
-		TOP_MUX(0x1, "DVI1"),		/* vs */
-		TOP_MUX(0x2, "BGPIO")),		/* gpio17 */
-	TOP_PIN(GMII_RXD5, TOP_REG1, 4, 2, 0x28, 0,
-		TOP_MUX(0x0, "GMII"),		/* rxd5 */
-		TOP_MUX(0x1, "DVI1"),		/* d0 */
-		TOP_MUX(0x2, "BGPIO"),		/* gpio18 */
-		TOP_MUX(0x3, "TSI0")),		/* dat0 */
-	TOP_PIN(GMII_RXD6, TOP_REG1, 6, 2, 0x28, 9,
-		TOP_MUX(0x0, "GMII"),		/* rxd6 */
-		TOP_MUX(0x1, "DVI1"),		/* d1 */
-		TOP_MUX(0x2, "BGPIO"),		/* gpio19 */
-		TOP_MUX(0x3, "TSI0")),		/* clk */
-	TOP_PIN(GMII_RXD7, TOP_REG1, 8, 2, 0x28, 18,
-		TOP_MUX(0x0, "GMII"),		/* rxd7 */
-		TOP_MUX(0x1, "DVI1"),		/* d2 */
-		TOP_MUX(0x2, "BGPIO"),		/* gpio20 */
-		TOP_MUX(0x3, "TSI0")),		/* sync */
-	TOP_PIN(GMII_RX_ER, TOP_REG1, 10, 2, 0x2c, 0,
-		TOP_MUX(0x0, "GMII"),		/* rx_er */
-		TOP_MUX(0x1, "DVI1"),		/* d3 */
-		TOP_MUX(0x2, "BGPIO"),		/* gpio21 */
-		TOP_MUX(0x3, "TSI0")),		/* valid */
-	TOP_PIN(GMII_RX_DV, TOP_REG1, 12, 2, 0x2c, 9,
-		TOP_MUX(0x0, "GMII"),		/* rx_dv */
-		TOP_MUX(0x1, "DVI1"),		/* d4 */
-		TOP_MUX(0x2, "BGPIO"),		/* gpio22 */
-		TOP_MUX(0x3, "TSI1")),		/* dat0 */
-	TOP_PIN(GMII_COL, TOP_REG1, 14, 2, 0x2c, 18,
-		TOP_MUX(0x0, "GMII"),		/* col */
-		TOP_MUX(0x1, "DVI1"),		/* d5 */
-		TOP_MUX(0x2, "BGPIO"),		/* gpio23 */
-		TOP_MUX(0x3, "TSI1")),		/* clk */
-	TOP_PIN(GMII_CRS, TOP_REG1, 16, 2, 0x30, 0,
-		TOP_MUX(0x0, "GMII"),		/* crs */
-		TOP_MUX(0x1, "DVI1"),		/* d6 */
-		TOP_MUX(0x2, "BGPIO"),		/* gpio24 */
-		TOP_MUX(0x3, "TSI1")),		/* sync */
-	TOP_PIN(GMII_MDC, TOP_REG1, 18, 2, 0x30, 9,
-		TOP_MUX(0x0, "GMII"),		/* mdc */
-		TOP_MUX(0x1, "DVI1"),		/* d7 */
-		TOP_MUX(0x2, "BGPIO"),		/* gpio25 */
-		TOP_MUX(0x3, "TSI1")),		/* valid */
-	TOP_PIN(GMII_MDIO, TOP_REG1, 20, 1, 0x30, 18,
-		TOP_MUX(0x0, "GMII"),		/* mdio */
-		TOP_MUX(0x2, "BGPIO")),		/* gpio26 */
-	TOP_PIN(SDIO1_CLK, TOP_REG1, 21, 2, 0x34, 18,
-		TOP_MUX(0x0, "SDIO1"),		/* clk */
-		TOP_MUX(0x1, "USIM0"),		/* clk */
-		TOP_MUX(0x2, "BGPIO"),		/* gpio27 */
-		TOP_MUX(0x3, "SPINOR")),	/* clk */
-	TOP_PIN(SDIO1_CMD, TOP_REG1, 23, 2, 0x38, 0,
-		TOP_MUX(0x0, "SDIO1"),		/* cmd */
-		TOP_MUX(0x1, "USIM0"),		/* cd */
-		TOP_MUX(0x2, "BGPIO"),		/* gpio28 */
-		TOP_MUX(0x3, "SPINOR")),	/* cs */
-	TOP_PIN(SDIO1_DATA0, TOP_REG1, 25, 2, 0x38, 9,
-		TOP_MUX(0x0, "SDIO1"),		/* dat0 */
-		TOP_MUX(0x1, "USIM0"),		/* rst */
-		TOP_MUX(0x2, "BGPIO"),		/* gpio29 */
-		TOP_MUX(0x3, "SPINOR")),	/* dq0 */
-	TOP_PIN(SDIO1_DATA1, TOP_REG1, 27, 2, 0x38, 18,
-		TOP_MUX(0x0, "SDIO1"),		/* dat1 */
-		TOP_MUX(0x1, "USIM0"),		/* data */
-		TOP_MUX(0x2, "BGPIO"),		/* gpio30 */
-		TOP_MUX(0x3, "SPINOR")),	/* dq1 */
-	TOP_PIN(SDIO1_DATA2, TOP_REG1, 29, 2, 0x3c, 0,
-		TOP_MUX(0x0, "SDIO1"),		/* dat2 */
-		TOP_MUX(0x1, "BGPIO"),		/* gpio31 */
-		TOP_MUX(0x2, "SPINOR")),	/* dq2 */
-
-	/* top_pmm_reg_2 */
-	TOP_PIN(SDIO1_DATA3, TOP_REG2, 0, 2, 0x3c, 9,
-		TOP_MUX(0x0, "SDIO1"),		/* dat3 */
-		TOP_MUX(0x1, "BGPIO"),		/* gpio32 */
-		TOP_MUX(0x2, "SPINOR")),	/* dq3 */
-	TOP_PIN(SDIO1_CD, TOP_REG2, 2, 2, 0x3c, 18,
-		TOP_MUX(0x0, "SDIO1"),		/* cd */
-		TOP_MUX(0x1, "BGPIO"),		/* gpio33 */
-		TOP_MUX(0x2, "ISP")),		/* fl_trig */
-	TOP_PIN(SDIO1_WP, TOP_REG2, 4, 2, 0x40, 0,
-		TOP_MUX(0x0, "SDIO1"),		/* wp */
-		TOP_MUX(0x1, "BGPIO"),		/* gpio34 */
-		TOP_MUX(0x2, "ISP")),		/* ref_clk */
-	TOP_PIN(USIM1_CD, TOP_REG2, 22, 3, 0x44, 18,
-		TOP_MUX(0x0, "USIM1"),		/* cd */
-		TOP_MUX(0x1, "UART4"),		/* rxd */
-		TOP_MUX(0x2, "BGPIO"),		/* gpio39 */
-		TOP_MUX(0x3, "SPI3"),		/* clk */
-		TOP_MUX(0x4, "I2S0"),		/* bclk */
-		TOP_MUX(0x5, "B_DVI0")),	/* d8 */
-	TOP_PIN(USIM1_CLK, TOP_REG2, 25, 3, 0x4c, 18,
-		TOP_MUX(0x0, "USIM1"),		/* clk */
-		TOP_MUX(0x1, "UART4"),		/* txd */
-		TOP_MUX(0x2, "BGPIO"),		/* gpio40 */
-		TOP_MUX(0x3, "SPI3"),		/* cs */
-		TOP_MUX(0x4, "I2S0"),		/* ws */
-		TOP_MUX(0x5, "B_DVI0")),	/* d9 */
-	TOP_PIN(USIM1_RST, TOP_REG2, 28, 3, 0x4c, 0,
-		TOP_MUX(0x0, "USIM1"),		/* rst */
-		TOP_MUX(0x1, "UART4"),		/* cts */
-		TOP_MUX(0x2, "BGPIO"),		/* gpio41 */
-		TOP_MUX(0x3, "SPI3"),		/* txd */
-		TOP_MUX(0x4, "I2S0"),		/* dout0 */
-		TOP_MUX(0x5, "B_DVI0")),	/* d10 */
-
-	/* top_pmm_reg_3 */
-	TOP_PIN(USIM1_DATA, TOP_REG3, 0, 3, 0x4c, 9,
-		TOP_MUX(0x0, "USIM1"),		/* dat */
-		TOP_MUX(0x1, "UART4"),		/* rst */
-		TOP_MUX(0x2, "BGPIO"),		/* gpio42 */
-		TOP_MUX(0x3, "SPI3"),		/* rxd */
-		TOP_MUX(0x4, "I2S0"),		/* din0 */
-		TOP_MUX(0x5, "B_DVI0")),	/* d11 */
-	TOP_PIN(SDIO0_CLK, TOP_REG3, 6, 1, 0x58, 0,
-		TOP_MUX(0x0, "SDIO0"),		/* clk */
-		TOP_MUX(0x1, "GPIO")),		/* gpio43 */
-	TOP_PIN(SDIO0_CMD, TOP_REG3, 7, 1, 0x58, 9,
-		TOP_MUX(0x0, "SDIO0"),		/* cmd */
-		TOP_MUX(0x1, "GPIO")),		/* gpio44 */
-	TOP_PIN(SDIO0_DATA0, TOP_REG3, 8, 1, 0x58, 18,
-		TOP_MUX(0x0, "SDIO0"),		/* dat0 */
-		TOP_MUX(0x1, "GPIO")),		/* gpio45 */
-	TOP_PIN(SDIO0_DATA1, TOP_REG3, 9, 1, 0x5c, 0,
-		TOP_MUX(0x0, "SDIO0"),		/* dat1 */
-		TOP_MUX(0x1, "GPIO")),		/* gpio46 */
-	TOP_PIN(SDIO0_DATA2, TOP_REG3, 10, 1, 0x5c, 9,
-		TOP_MUX(0x0, "SDIO0"),		/* dat2 */
-		TOP_MUX(0x1, "GPIO")),		/* gpio47 */
-	TOP_PIN(SDIO0_DATA3, TOP_REG3, 11, 1, 0x5c, 18,
-		TOP_MUX(0x0, "SDIO0"),		/* dat3 */
-		TOP_MUX(0x1, "GPIO")),		/* gpio48 */
-	TOP_PIN(SDIO0_CD, TOP_REG3, 12, 1, 0x60, 0,
-		TOP_MUX(0x0, "SDIO0"),		/* cd */
-		TOP_MUX(0x1, "GPIO")),		/* gpio49 */
-	TOP_PIN(SDIO0_WP, TOP_REG3, 13, 1, 0x60, 9,
-		TOP_MUX(0x0, "SDIO0"),		/* wp */
-		TOP_MUX(0x1, "GPIO")),		/* gpio50 */
-
-	/* top_pmm_reg_4 */
-	TOP_PIN(TSI0_DATA0, TOP_REG4, 0, 2, 0x60, 18,
-		TOP_MUX(0x0, "TSI0"),		/* dat0 */
-		TOP_MUX(0x1, "LCD"),		/* clk */
-		TOP_MUX(0x2, "BGPIO")),		/* gpio51 */
-	TOP_PIN(SPINOR_CLK, TOP_REG4, 2, 2, 0xa8, 18,
-		TOP_MUX(0x0, "SPINOR"),		/* clk */
-		TOP_MUX(0x1, "TSI0"),		/* dat1 */
-		TOP_MUX(0x2, "LCD"),		/* dat0 */
-		TOP_MUX(0x3, "BGPIO")),		/* gpio52 */
-	TOP_PIN(TSI2_DATA, TOP_REG4, 4, 2, 0x7c, 0,
-		TOP_MUX(0x0, "TSI2"),		/* dat */
-		TOP_MUX(0x1, "TSI0"),		/* dat2 */
-		TOP_MUX(0x2, "LCD"),		/* dat1 */
-		TOP_MUX(0x3, "BGPIO")),		/* gpio53 */
-	TOP_PIN(TSI2_CLK, TOP_REG4, 6, 2, 0x7c, 9,
-		TOP_MUX(0x0, "TSI2"),		/* clk */
-		TOP_MUX(0x1, "TSI0"),		/* dat3 */
-		TOP_MUX(0x2, "LCD"),		/* dat2 */
-		TOP_MUX(0x3, "BGPIO")),		/* gpio54 */
-	TOP_PIN(TSI2_SYNC, TOP_REG4, 8, 2, 0x7c, 18,
-		TOP_MUX(0x0, "TSI2"),		/* sync */
-		TOP_MUX(0x1, "TSI0"),		/* dat4 */
-		TOP_MUX(0x2, "LCD"),		/* dat3 */
-		TOP_MUX(0x3, "BGPIO")),		/* gpio55 */
-	TOP_PIN(TSI2_VALID, TOP_REG4, 10, 2, 0x80, 0,
-		TOP_MUX(0x0, "TSI2"),		/* valid */
-		TOP_MUX(0x1, "TSI0"),		/* dat5 */
-		TOP_MUX(0x2, "LCD"),		/* dat4 */
-		TOP_MUX(0x3, "BGPIO")),		/* gpio56 */
-	TOP_PIN(SPINOR_CS, TOP_REG4, 12, 2, 0x80, 9,
-		TOP_MUX(0x0, "SPINOR"),		/* cs */
-		TOP_MUX(0x1, "TSI0"),		/* dat6 */
-		TOP_MUX(0x2, "LCD"),		/* dat5 */
-		TOP_MUX(0x3, "BGPIO")),		/* gpio57 */
-	TOP_PIN(SPINOR_DQ0, TOP_REG4, 14, 2, 0x80, 18,
-		TOP_MUX(0x0, "SPINOR"),		/* dq0 */
-		TOP_MUX(0x1, "TSI0"),		/* dat7 */
-		TOP_MUX(0x2, "LCD"),		/* dat6 */
-		TOP_MUX(0x3, "BGPIO")),		/* gpio58 */
-	TOP_PIN(SPINOR_DQ1, TOP_REG4, 16, 2, 0x84, 0,
-		TOP_MUX(0x0, "SPINOR"),		/* dq1 */
-		TOP_MUX(0x1, "TSI0"),		/* clk */
-		TOP_MUX(0x2, "LCD"),		/* dat7 */
-		TOP_MUX(0x3, "BGPIO")),		/* gpio59 */
-	TOP_PIN(SPINOR_DQ2, TOP_REG4, 18, 2, 0x84, 9,
-		TOP_MUX(0x0, "SPINOR"),		/* dq2 */
-		TOP_MUX(0x1, "TSI0"),		/* sync */
-		TOP_MUX(0x2, "LCD"),		/* dat8 */
-		TOP_MUX(0x3, "BGPIO")),		/* gpio60 */
-	TOP_PIN(SPINOR_DQ3, TOP_REG4, 20, 2, 0x84, 18,
-		TOP_MUX(0x0, "SPINOR"),		/* dq3 */
-		TOP_MUX(0x1, "TSI0"),		/* valid */
-		TOP_MUX(0x2, "LCD"),		/* dat9 */
-		TOP_MUX(0x3, "BGPIO")),		/* gpio61 */
-	TOP_PIN(VGA_HS, TOP_REG4, 22, 3, 0x88, 0,
-		TOP_MUX(0x0, "VGA"),		/* hs */
-		TOP_MUX(0x1, "TSI1"),		/* dat0 */
-		TOP_MUX(0x2, "LCD"),		/* dat10 */
-		TOP_MUX(0x3, "BGPIO"),		/* gpio62 */
-		TOP_MUX(0x4, "I2S1"),		/* din1 */
-		TOP_MUX(0x5, "B_DVI0")),	/* clk */
-	TOP_PIN(VGA_VS, TOP_REG4, 25, 3, 0x88, 9,
-		TOP_MUX(0x0, "VGA"),		/* vs0 */
-		TOP_MUX(0x1, "TSI1"),		/* dat1 */
-		TOP_MUX(0x2, "LCD"),		/* dat11 */
-		TOP_MUX(0x3, "BGPIO"),		/* gpio63 */
-		TOP_MUX(0x4, "I2S1"),		/* din2 */
-		TOP_MUX(0x5, "B_DVI0")),	/* vs */
-	TOP_PIN(TSI3_DATA, TOP_REG4, 28, 3, 0x88, 18,
-		TOP_MUX(0x0, "TSI3"),		/* dat */
-		TOP_MUX(0x1, "TSI1"),		/* dat2 */
-		TOP_MUX(0x2, "LCD"),		/* dat12 */
-		TOP_MUX(0x3, "BGPIO"),		/* gpio64 */
-		TOP_MUX(0x4, "I2S1"),		/* din3 */
-		TOP_MUX(0x5, "B_DVI0")),	/* hs */
-
-	/* top_pmm_reg_5 */
-	TOP_PIN(TSI3_CLK, TOP_REG5, 0, 3, 0x8c, 0,
-		TOP_MUX(0x0, "TSI3"),		/* clk */
-		TOP_MUX(0x1, "TSI1"),		/* dat3 */
-		TOP_MUX(0x2, "LCD"),		/* dat13 */
-		TOP_MUX(0x3, "BGPIO"),		/* gpio65 */
-		TOP_MUX(0x4, "I2S1"),		/* dout1 */
-		TOP_MUX(0x5, "B_DVI0")),	/* d0 */
-	TOP_PIN(TSI3_SYNC, TOP_REG5, 3, 3, 0x8c, 9,
-		TOP_MUX(0x0, "TSI3"),		/* sync */
-		TOP_MUX(0x1, "TSI1"),		/* dat4 */
-		TOP_MUX(0x2, "LCD"),		/* dat14 */
-		TOP_MUX(0x3, "BGPIO"),		/* gpio66 */
-		TOP_MUX(0x4, "I2S1"),		/* dout2 */
-		TOP_MUX(0x5, "B_DVI0")),	/* d1 */
-	TOP_PIN(TSI3_VALID, TOP_REG5, 6, 3, 0x8c, 18,
-		TOP_MUX(0x0, "TSI3"),		/* valid */
-		TOP_MUX(0x1, "TSI1"),		/* dat5 */
-		TOP_MUX(0x2, "LCD"),		/* dat15 */
-		TOP_MUX(0x3, "BGPIO"),		/* gpio67 */
-		TOP_MUX(0x4, "I2S1"),		/* dout3 */
-		TOP_MUX(0x5, "B_DVI0")),	/* d2 */
-	TOP_PIN(I2S1_WS, TOP_REG5, 9, 3, 0x90, 0,
-		TOP_MUX(0x0, "I2S1"),		/* ws */
-		TOP_MUX(0x1, "TSI1"),		/* dat6 */
-		TOP_MUX(0x2, "LCD"),		/* dat16 */
-		TOP_MUX(0x3, "BGPIO"),		/* gpio68 */
-		TOP_MUX(0x4, "VGA"),		/* scl */
-		TOP_MUX(0x5, "B_DVI0")),	/* d3 */
-	TOP_PIN(I2S1_BCLK, TOP_REG5, 12, 3, 0x90, 9,
-		TOP_MUX(0x0, "I2S1"),		/* bclk */
-		TOP_MUX(0x1, "TSI1"),		/* dat7 */
-		TOP_MUX(0x2, "LCD"),		/* dat17 */
-		TOP_MUX(0x3, "BGPIO"),		/* gpio69 */
-		TOP_MUX(0x4, "VGA"),		/* sda */
-		TOP_MUX(0x5, "B_DVI0")),	/* d4 */
-	TOP_PIN(I2S1_MCLK, TOP_REG5, 15, 2, 0x90, 18,
-		TOP_MUX(0x0, "I2S1"),		/* mclk */
-		TOP_MUX(0x1, "TSI1"),		/* clk */
-		TOP_MUX(0x2, "LCD"),		/* dat18 */
-		TOP_MUX(0x3, "BGPIO")),		/* gpio70 */
-	TOP_PIN(I2S1_DIN0, TOP_REG5, 17, 2, 0x94, 0,
-		TOP_MUX(0x0, "I2S1"),		/* din0 */
-		TOP_MUX(0x1, "TSI1"),		/* sync */
-		TOP_MUX(0x2, "LCD"),		/* dat19 */
-		TOP_MUX(0x3, "BGPIO")),		/* gpio71 */
-	TOP_PIN(I2S1_DOUT0, TOP_REG5, 19, 2, 0x94, 9,
-		TOP_MUX(0x0, "I2S1"),		/* dout0 */
-		TOP_MUX(0x1, "TSI1"),		/* valid */
-		TOP_MUX(0x2, "LCD"),		/* dat20 */
-		TOP_MUX(0x3, "BGPIO")),		/* gpio72 */
-	TOP_PIN(SPI3_CLK, TOP_REG5, 21, 3, 0x94, 18,
-		TOP_MUX(0x0, "SPI3"),		/* clk */
-		TOP_MUX(0x1, "TSO1"),		/* clk */
-		TOP_MUX(0x2, "LCD"),		/* dat21 */
-		TOP_MUX(0x3, "BGPIO"),		/* gpio73 */
-		TOP_MUX(0x4, "UART5"),		/* rxd */
-		TOP_MUX(0x5, "PCM"),		/* fs */
-		TOP_MUX(0x6, "I2S0"),		/* din1 */
-		TOP_MUX(0x7, "B_DVI0")),	/* d5 */
-	TOP_PIN(SPI3_CS, TOP_REG5, 24, 3, 0x98, 0,
-		TOP_MUX(0x0, "SPI3"),		/* cs */
-		TOP_MUX(0x1, "TSO1"),		/* dat0 */
-		TOP_MUX(0x2, "LCD"),		/* dat22 */
-		TOP_MUX(0x3, "BGPIO"),		/* gpio74 */
-		TOP_MUX(0x4, "UART5"),		/* txd */
-		TOP_MUX(0x5, "PCM"),		/* clk */
-		TOP_MUX(0x6, "I2S0"),		/* din2 */
-		TOP_MUX(0x7, "B_DVI0")),	/* d6 */
-	TOP_PIN(SPI3_TXD, TOP_REG5, 27, 3, 0x98, 9,
-		TOP_MUX(0x0, "SPI3"),		/* txd */
-		TOP_MUX(0x1, "TSO1"),		/* dat1 */
-		TOP_MUX(0x2, "LCD"),		/* dat23 */
-		TOP_MUX(0x3, "BGPIO"),		/* gpio75 */
-		TOP_MUX(0x4, "UART5"),		/* cts */
-		TOP_MUX(0x5, "PCM"),		/* txd */
-		TOP_MUX(0x6, "I2S0"),		/* din3 */
-		TOP_MUX(0x7, "B_DVI0")),	/* d7 */
-	TOP_PIN(NAND_LDO_MS18_SEL, TOP_REG5, 30, 1, 0xe4, 0,
-		TOP_MUX(0x0, "NAND"),		/* ldo_ms18_sel */
-		TOP_MUX(0x1, "BGPIO")),		/* gpio99 */
-
-	/* top_pmm_reg_6 */
-	TOP_PIN(SPI3_RXD, TOP_REG6, 0, 3, 0x98, 18,
-		TOP_MUX(0x0, "SPI3"),		/* rxd */
-		TOP_MUX(0x1, "TSO1"),		/* dat2 */
-		TOP_MUX(0x2, "LCD"),		/* stvu_vsync */
-		TOP_MUX(0x3, "BGPIO"),		/* gpio76 */
-		TOP_MUX(0x4, "UART5"),		/* rts */
-		TOP_MUX(0x5, "PCM"),		/* rxd */
-		TOP_MUX(0x6, "I2S0"),		/* dout1 */
-		TOP_MUX(0x7, "B_DVI1")),	/* clk */
-	TOP_PIN(I2S0_MCLK, TOP_REG6, 3, 3, 0x9c, 0,
-		TOP_MUX(0x0, "I2S0"),		/* mclk */
-		TOP_MUX(0x1, "TSO1"),		/* dat3 */
-		TOP_MUX(0x2, "LCD"),		/* stvd */
-		TOP_MUX(0x3, "BGPIO"),		/* gpio77 */
-		TOP_MUX(0x4, "USIM0"),		/* cd */
-		TOP_MUX(0x5, "B_DVI1")),	/* vs */
-	TOP_PIN(I2S0_BCLK, TOP_REG6, 6, 3, 0x9c, 9,
-		TOP_MUX(0x0, "I2S0"),		/* bclk */
-		TOP_MUX(0x1, "TSO1"),		/* dat4 */
-		TOP_MUX(0x2, "LCD"),		/* sthl_hsync */
-		TOP_MUX(0x3, "BGPIO"),		/* gpio78 */
-		TOP_MUX(0x4, "USIM0"),		/* clk */
-		TOP_MUX(0x5, "B_DVI1")),	/* hs */
-	TOP_PIN(I2S0_WS, TOP_REG6, 9, 3, 0x9c, 18,
-		TOP_MUX(0x0, "I2S0"),		/* ws */
-		TOP_MUX(0x1, "TSO1"),		/* dat5 */
-		TOP_MUX(0x2, "LCD"),		/* sthr */
-		TOP_MUX(0x3, "BGPIO"),		/* gpio79 */
-		TOP_MUX(0x4, "USIM0"),		/* rst */
-		TOP_MUX(0x5, "B_DVI1")),	/* d0 */
-	TOP_PIN(I2S0_DIN0, TOP_REG6, 12, 3, 0xa0, 0,
-		TOP_MUX(0x0, "I2S0"),		/* din0 */
-		TOP_MUX(0x1, "TSO1"),		/* dat6 */
-		TOP_MUX(0x2, "LCD"),		/* oev_dataen */
-		TOP_MUX(0x3, "BGPIO"),		/* gpio80 */
-		TOP_MUX(0x4, "USIM0"),		/* dat */
-		TOP_MUX(0x5, "B_DVI1")),	/* d1 */
-	TOP_PIN(I2S0_DOUT0, TOP_REG6, 15, 2, 0xa0, 9,
-		TOP_MUX(0x0, "I2S0"),		/* dout0 */
-		TOP_MUX(0x1, "TSO1"),		/* dat7 */
-		TOP_MUX(0x2, "LCD"),		/* ckv */
-		TOP_MUX(0x3, "BGPIO")),		/* gpio81 */
-	TOP_PIN(I2C5_SCL, TOP_REG6, 17, 3, 0xa0, 18,
-		TOP_MUX(0x0, "I2C5"),		/* scl */
-		TOP_MUX(0x1, "TSO1"),		/* sync */
-		TOP_MUX(0x2, "LCD"),		/* ld */
-		TOP_MUX(0x3, "BGPIO"),		/* gpio82 */
-		TOP_MUX(0x4, "PWM"),		/* out2 */
-		TOP_MUX(0x5, "I2S0"),		/* dout2 */
-		TOP_MUX(0x6, "B_DVI1")),	/* d2 */
-	TOP_PIN(I2C5_SDA, TOP_REG6, 20, 3, 0xa4, 0,
-		TOP_MUX(0x0, "I2C5"),		/* sda */
-		TOP_MUX(0x1, "TSO1"),		/* vld */
-		TOP_MUX(0x2, "LCD"),		/* pol */
-		TOP_MUX(0x3, "BGPIO"),		/* gpio83 */
-		TOP_MUX(0x4, "PWM"),		/* out3 */
-		TOP_MUX(0x5, "I2S0"),		/* dout3 */
-		TOP_MUX(0x6, "B_DVI1")),	/* d3 */
-	TOP_PIN(SPI2_CLK, TOP_REG6, 23, 3, 0xa4, 9,
-		TOP_MUX(0x0, "SPI2"),		/* clk */
-		TOP_MUX(0x1, "TSO0"),		/* clk */
-		TOP_MUX(0x2, "LCD"),		/* degsl */
-		TOP_MUX(0x3, "BGPIO"),		/* gpio84 */
-		TOP_MUX(0x4, "I2C4"),		/* scl */
-		TOP_MUX(0x5, "B_DVI1")),	/* d4 */
-	TOP_PIN(SPI2_CS, TOP_REG6, 26, 3, 0xa4, 18,
-		TOP_MUX(0x0, "SPI2"),		/* cs */
-		TOP_MUX(0x1, "TSO0"),		/* data */
-		TOP_MUX(0x2, "LCD"),		/* rev */
-		TOP_MUX(0x3, "BGPIO"),		/* gpio85 */
-		TOP_MUX(0x4, "I2C4"),		/* sda */
-		TOP_MUX(0x5, "B_DVI1")),	/* d5 */
-	TOP_PIN(SPI2_TXD, TOP_REG6, 29, 3, 0xa8, 0,
-		TOP_MUX(0x0, "SPI2"),		/* txd */
-		TOP_MUX(0x1, "TSO0"),		/* sync */
-		TOP_MUX(0x2, "LCD"),		/* u_d */
-		TOP_MUX(0x3, "BGPIO"),		/* gpio86 */
-		TOP_MUX(0x4, "I2C4"),		/* scl */
-		TOP_MUX(0x5, "B_DVI1")),	/* d6 */
-
-	/* top_pmm_reg_7 */
-	TOP_PIN(SPI2_RXD, TOP_REG7, 0, 3, 0xa8, 9,
-		TOP_MUX(0x0, "SPI2"),		/* rxd */
-		TOP_MUX(0x1, "TSO0"),		/* vld */
-		TOP_MUX(0x2, "LCD"),		/* r_l */
-		TOP_MUX(0x3, "BGPIO"),		/* gpio87 */
-		TOP_MUX(0x4, "I2C3"),		/* sda */
-		TOP_MUX(0x5, "B_DVI1")),	/* d7 */
-	TOP_PIN(NAND_WP_N, TOP_REG7, 7, 3, 0x54, 9,
-		TOP_MUX(0x0, "NAND"),		/* wp */
-		TOP_MUX(0x1, "PWM"),		/* out2 */
-		TOP_MUX(0x2, "SPI2"),		/* clk */
-		TOP_MUX(0x3, "BGPIO"),		/* gpio88 */
-		TOP_MUX(0x4, "TSI0"),		/* dat0 */
-		TOP_MUX(0x5, "I2S1")),		/* din1 */
-	TOP_PIN(NAND_PAGE_SIZE0, TOP_REG7, 10, 3, 0xb8, 0,
-		TOP_MUX(0x0, "NAND"),		/* boot_pagesize0 */
-		TOP_MUX(0x1, "PWM"),		/* out3 */
-		TOP_MUX(0x2, "SPI2"),		/* cs */
-		TOP_MUX(0x3, "BGPIO"),		/* gpio89 */
-		TOP_MUX(0x4, "TSI0"),		/* clk */
-		TOP_MUX(0x5, "I2S1")),		/* din2 */
-	TOP_PIN(NAND_PAGE_SIZE1, TOP_REG7, 13, 3, 0xb8, 9,
-		TOP_MUX(0x0, "NAND"),		/* boot_pagesize1 */
-		TOP_MUX(0x1, "I2C4"),		/* scl */
-		TOP_MUX(0x2, "SPI2"),		/* txd */
-		TOP_MUX(0x3, "BGPIO"),		/* gpio90 */
-		TOP_MUX(0x4, "TSI0"),		/* sync */
-		TOP_MUX(0x5, "I2S1")),		/* din3 */
-	TOP_PIN(NAND_ADDR_CYCLE, TOP_REG7, 16, 3, 0xb8, 18,
-		TOP_MUX(0x0, "NAND"),		/* boot_addr_cycles */
-		TOP_MUX(0x1, "I2C4"),		/* sda */
-		TOP_MUX(0x2, "SPI2"),		/* rxd */
-		TOP_MUX(0x3, "BGPIO"),		/* gpio91 */
-		TOP_MUX(0x4, "TSI0"),		/* valid */
-		TOP_MUX(0x5, "I2S1")),		/* dout1 */
-	TOP_PIN(NAND_RB0, TOP_REG7, 19, 3, 0xbc, 0,
-		TOP_MUX(0x0, "NAND"),		/* rdy_busy0 */
-		TOP_MUX(0x1, "I2C2"),		/* scl */
-		TOP_MUX(0x2, "USIM0"),		/* cd */
-		TOP_MUX(0x3, "BGPIO"),		/* gpio92 */
-		TOP_MUX(0x4, "TSI1")),		/* data0 */
-	TOP_PIN(NAND_RB1, TOP_REG7, 22, 3, 0xbc, 9,
-		TOP_MUX(0x0, "NAND"),		/* rdy_busy1 */
-		TOP_MUX(0x1, "I2C2"),		/* sda */
-		TOP_MUX(0x2, "USIM0"),		/* clk */
-		TOP_MUX(0x3, "BGPIO"),		/* gpio93 */
-		TOP_MUX(0x4, "TSI1")),		/* clk */
-	TOP_PIN(NAND_RB2, TOP_REG7, 25, 3, 0xbc, 18,
-		TOP_MUX(0x0, "NAND"),		/* rdy_busy2 */
-		TOP_MUX(0x1, "UART5"),		/* rxd */
-		TOP_MUX(0x2, "USIM0"),		/* rst */
-		TOP_MUX(0x3, "BGPIO"),		/* gpio94 */
-		TOP_MUX(0x4, "TSI1"),		/* sync */
-		TOP_MUX(0x4, "I2S1")),		/* dout2 */
-	TOP_PIN(NAND_RB3, TOP_REG7, 28, 3, 0x54, 18,
-		TOP_MUX(0x0, "NAND"),		/* rdy_busy3 */
-		TOP_MUX(0x1, "UART5"),		/* txd */
-		TOP_MUX(0x2, "USIM0"),		/* dat */
-		TOP_MUX(0x3, "BGPIO"),		/* gpio95 */
-		TOP_MUX(0x4, "TSI1"),		/* valid */
-		TOP_MUX(0x4, "I2S1")),		/* dout3 */
-
-	/* top_pmm_reg_8 */
-	TOP_PIN(GMAC_125M_IN, TOP_REG8, 0, 2, 0x34, 0,
-		TOP_MUX(0x0, "GMII"),		/* 125m_in */
-		TOP_MUX(0x1, "USB2"),		/* 0_drvvbus */
-		TOP_MUX(0x2, "ISP"),		/* ref_clk */
-		TOP_MUX(0x3, "BGPIO")),		/* gpio96 */
-	TOP_PIN(GMAC_50M_OUT, TOP_REG8, 2, 2, 0x34, 9,
-		TOP_MUX(0x0, "GMII"),		/* 50m_out */
-		TOP_MUX(0x1, "USB2"),		/* 1_drvvbus */
-		TOP_MUX(0x2, "BGPIO"),		/* gpio97 */
-		TOP_MUX(0x3, "USB2")),		/* 0_drvvbus */
-	TOP_PIN(SPINOR_SSCLK_LOOPBACK, TOP_REG8, 6, 1, 0xc8, 9,
-		TOP_MUX(0x0, "SPINOR")),	/* sdio1_clk_i */
-	TOP_PIN(SPINOR_SDIO1CLK_LOOPBACK, TOP_REG8, 7, 1, 0xc8, 18,
-		TOP_MUX(0x0, "SPINOR")),	/* ssclk_i */
-};
-
-static struct zx_pinctrl_soc_info zx296718_pinctrl_info = {
-	.pins = zx296718_pins,
-	.npins = ARRAY_SIZE(zx296718_pins),
-};
-
-static int zx296718_pinctrl_probe(struct platform_device *pdev)
-{
-	return zx_pinctrl_init(pdev, &zx296718_pinctrl_info);
-}
-
-static const struct of_device_id zx296718_pinctrl_match[] = {
-	{ .compatible = "zte,zx296718-pmm", },
-	{}
-};
-MODULE_DEVICE_TABLE(of, zx296718_pinctrl_match);
-
-static struct platform_driver zx296718_pinctrl_driver = {
-	.probe  = zx296718_pinctrl_probe,
-	.driver = {
-		.name = "zx296718-pinctrl",
-		.of_match_table = zx296718_pinctrl_match,
-	},
-};
-builtin_platform_driver(zx296718_pinctrl_driver);
-
-MODULE_DESCRIPTION("ZTE ZX296718 pinctrl driver");
-MODULE_LICENSE("GPL");
-- 
2.29.2


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^ permalink raw reply related	[flat|nested] 22+ messages in thread

* [PATCH 3/5] pinctrl: remove sirf atlas/prima drivers
  2021-01-20 13:20 ` Arnd Bergmann
                   ` (2 preceding siblings ...)
  (?)
@ 2021-01-20 13:20 ` Arnd Bergmann
  2021-01-20 21:30   ` Barry Song
  -1 siblings, 1 reply; 22+ messages in thread
From: Arnd Bergmann @ 2021-01-20 13:20 UTC (permalink / raw)
  To: linux-arm-kernel, linux-kernel, linux-gpio, Linus Walleij
  Cc: Bartosz Golaszewski, Arnd Bergmann, Barry Song

From: Arnd Bergmann <arnd@arndb.de>

The CSR SiRF prima2/atlas platforms are getting removed, so this driver
is no longer needed.

Cc: Barry Song <baohua@kernel.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
---
 .../devicetree/bindings/gpio/gpio-atlas7.txt  |   50 -
 .../bindings/pinctrl/pinctrl-atlas7.txt       |  109 -
 drivers/pinctrl/Kconfig                       |    8 -
 drivers/pinctrl/Makefile                      |    1 -
 drivers/pinctrl/sirf/Makefile                 |    7 -
 drivers/pinctrl/sirf/pinctrl-atlas6.c         | 1137 ---
 drivers/pinctrl/sirf/pinctrl-atlas7.c         | 6157 -----------------
 drivers/pinctrl/sirf/pinctrl-prima2.c         | 1131 ---
 drivers/pinctrl/sirf/pinctrl-sirf.c           |  894 ---
 drivers/pinctrl/sirf/pinctrl-sirf.h           |  116 -
 10 files changed, 9610 deletions(-)
 delete mode 100644 Documentation/devicetree/bindings/gpio/gpio-atlas7.txt
 delete mode 100644 Documentation/devicetree/bindings/pinctrl/pinctrl-atlas7.txt
 delete mode 100644 drivers/pinctrl/sirf/Makefile
 delete mode 100644 drivers/pinctrl/sirf/pinctrl-atlas6.c
 delete mode 100644 drivers/pinctrl/sirf/pinctrl-atlas7.c
 delete mode 100644 drivers/pinctrl/sirf/pinctrl-prima2.c
 delete mode 100644 drivers/pinctrl/sirf/pinctrl-sirf.c
 delete mode 100644 drivers/pinctrl/sirf/pinctrl-sirf.h

diff --git a/Documentation/devicetree/bindings/gpio/gpio-atlas7.txt b/Documentation/devicetree/bindings/gpio/gpio-atlas7.txt
deleted file mode 100644
index d7e123fc90b5..000000000000
--- a/Documentation/devicetree/bindings/gpio/gpio-atlas7.txt
+++ /dev/null
@@ -1,50 +0,0 @@
-CSR SiRFatlas7 GPIO controller bindings
-
-Required properties:
-- compatible	: "sirf,atlas7-gpio"
-- reg		: Address range of the pinctrl registers
-- interrupts	: Interrupts used by every GPIO group
-- gpio-banks	: How many gpio banks on this controller
-- gpio-controller : Indicates this device is a GPIO controller
-- interrupt-controller  : Marks the device node as an interrupt controller
-
-The GPIO controller also acts as an interrupt controller. It uses the default
-two cells specifier as described in Documentation/devicetree/bindings/
-interrupt-controller/interrupts.txt.
-
-Example:
-
-	gpio_0: gpio_mediam@17040000 {
-		compatible = "sirf,atlas7-gpio";
-		reg = <0x17040000 0x1000>;
-		interrupts = <0 13 0>, <0 14 0>;
-
-		#gpio-cells = <2>;
-		#interrupt-cells = <2>;
-
-		gpio-controller;
-		interrupt-controller;
-
-		gpio-banks = <2>;
-		gpio-ranges = <&pinctrl 0 0 0>,
-				<&pinctrl 32 0 0>;
-		gpio-ranges-group-names = "lvds_gpio_grp",
-					"uart_nand_gpio_grp";
-	};
-
-	leds {
-		compatible = "gpio-leds";
-
-		led1 {
-			gpios = <&gpio_1 15 0>;
-			...
-		};
-
-		led2 {
-			gpios = <&gpio_2 34 0>;
-			...
-		};
-	};
-
-Please refer to gpio.txt in this directory for details of the common
-gpio properties used by devices.
diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-atlas7.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-atlas7.txt
deleted file mode 100644
index fbdd1a716a1e..000000000000
--- a/Documentation/devicetree/bindings/pinctrl/pinctrl-atlas7.txt
+++ /dev/null
@@ -1,109 +0,0 @@
-CSR SiRFatlas7 pinmux controller
-
-Required properties:
-- compatible	: "sirf,atlas7-ioc"
-- reg		: Address range of the pinctrl registers
-
-For example, pinctrl might have properties like the following:
-	pinctrl: ioc@18880000 {
-			compatible = "sirf,atlas7-ioc";
-			reg = <0x18880000 0x1000>;
-
-			a_ac97_pmx: ac97@0 {
-				ac97 {
-					groups = "audio_ac97_grp";
-					function = "audio_ac97";
-				};
-			};
-
-			...
-
-			sd2_pmx: sd2@0 {
-				sd2 {
-					groups = "sd2_grp0";
-					function = "sd2";
-				};
-			};
-
-			...
-
-
-			sample0_cfg: sample0@0 {
-				sample0 {
-					pins = "ldd_0", "ldd_1";
-					bias-pull-up;
-				};
-			};
-
-			sample1_cfg: sample1@0 {
-				sample1 {
-					pins = "ldd_2", "ldd_3";
-					input-schmitt-enable;
-				};
-			};
-
-			sample2_cfg: sample2@0 {
-				sample2 {
-					groups = "uart4_nopause_grp";
-					bias-pull-down;
-				};
-			};
-
-			sample3_cfg: sample3@0 {
-				sample3 {
-					pins = "ldd_4", "ldd_5";
-					drive-strength = <2>;
-				};
-			};
-	};
-
-Please refer to pinctrl-bindings.txt in this directory for details of the common
-pinctrl bindings used by client devices.
-
-SiRFatlas7's pinmux nodes act as a container for an arbitrary number of subnodes.
-Each of these subnodes represents some desired configuration for a group of pins.
-
-Required subnode-properties:
-- groups : An array of strings. Each string contains the name of a group.
-- function: A string containing the name of the function to mux to the
-  group.
-
-  Valid values for group and function names can be found from looking at the
-  group and function arrays in driver files:
-  drivers/pinctrl/pinctrl-sirf.c
-
-For example, pinctrl might have subnodes like the following:
-	sd0_pmx: sd0@0 {
-		sd0 {
-			groups = "sd0_grp";
-			function = "sd0";
-		};
-	};
-
-	sd1_pmx0: sd1@0 {
-		sd1 {
-			groups = "sd1_grp0";
-			function = "sd1_m0";
-		};
-	};
-
-	sd1_pmx1: sd1@1 {
-		sd1 {
-			groups = "sd1_grp1";
-			function = "sd1_m1";
-		};
-	};
-
-For a specific board, if it wants to use sd1,
-it can add the following to its board-specific .dts file.
-sd1: sd@12340000 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&sd1_pmx0>;
-}
-
-or
-
-sd1: sd@12340000 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&sd1_pmx1>;
-}
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index 1c1fa681b96d..e176137dbf29 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -226,14 +226,6 @@ config PINCTRL_SINGLE
 	help
 	  This selects the device tree based generic pinctrl driver.
 
-config PINCTRL_SIRF
-	bool "CSR SiRFprimaII pin controller driver"
-	depends on ARCH_SIRF
-	select PINMUX
-	select PINCONF
-	select GENERIC_PINCONF
-	select GPIOLIB_IRQCHIP
-
 config PINCTRL_SX150X
 	bool "Semtech SX150x I2C GPIO expander pinctrl driver"
 	depends on I2C=y
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index fef92794900d..f414846abe2d 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -31,7 +31,6 @@ obj-$(CONFIG_PINCTRL_PIC32)	+= pinctrl-pic32.o
 obj-$(CONFIG_PINCTRL_PISTACHIO)	+= pinctrl-pistachio.o
 obj-$(CONFIG_PINCTRL_ROCKCHIP)	+= pinctrl-rockchip.o
 obj-$(CONFIG_PINCTRL_SINGLE)	+= pinctrl-single.o
-obj-$(CONFIG_PINCTRL_SIRF)	+= sirf/
 obj-$(CONFIG_PINCTRL_SX150X)	+= pinctrl-sx150x.o
 obj-$(CONFIG_ARCH_TEGRA)	+= tegra/
 obj-$(CONFIG_PINCTRL_U300)	+= pinctrl-u300.o
diff --git a/drivers/pinctrl/sirf/Makefile b/drivers/pinctrl/sirf/Makefile
deleted file mode 100644
index 1ab0742075f6..000000000000
--- a/drivers/pinctrl/sirf/Makefile
+++ /dev/null
@@ -1,7 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-only
-# CSR SiRFsoc pinmux support
-
-obj-y	+= pinctrl-sirf.o
-obj-y	+= pinctrl-prima2.o
-obj-y	+= pinctrl-atlas6.o
-obj-y	+= pinctrl-atlas7.o
diff --git a/drivers/pinctrl/sirf/pinctrl-atlas6.c b/drivers/pinctrl/sirf/pinctrl-atlas6.c
deleted file mode 100644
index ab35d59bfa04..000000000000
--- a/drivers/pinctrl/sirf/pinctrl-atlas6.c
+++ /dev/null
@@ -1,1137 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-/*
- * pinctrl pads, groups, functions for CSR SiRFatlasVI
- *
- * Copyright (c) 2011 - 2014 Cambridge Silicon Radio Limited, a CSR plc group
- * company.
- */
-
-#include <linux/pinctrl/pinctrl.h>
-#include <linux/bitops.h>
-
-#include "pinctrl-sirf.h"
-
-/*
- * pad list for the pinmux subsystem
- * refer to atlasVI_io_table_v0.93.xls
- */
-static const struct pinctrl_pin_desc sirfsoc_pads[] = {
-	PINCTRL_PIN(0, "gpio0-0"),
-	PINCTRL_PIN(1, "gpio0-1"),
-	PINCTRL_PIN(2, "gpio0-2"),
-	PINCTRL_PIN(3, "gpio0-3"),
-	PINCTRL_PIN(4, "pwm0"),
-	PINCTRL_PIN(5, "pwm1"),
-	PINCTRL_PIN(6, "pwm2"),
-	PINCTRL_PIN(7, "pwm3"),
-	PINCTRL_PIN(8, "warm_rst_b"),
-	PINCTRL_PIN(9, "odo_0"),
-	PINCTRL_PIN(10, "odo_1"),
-	PINCTRL_PIN(11, "dr_dir"),
-	PINCTRL_PIN(12, "rts_0"),
-	PINCTRL_PIN(13, "scl_1"),
-	PINCTRL_PIN(14, "ntrst"),
-	PINCTRL_PIN(15, "sda_1"),
-	PINCTRL_PIN(16, "x_ldd[16]"),
-	PINCTRL_PIN(17, "x_ldd[17]"),
-	PINCTRL_PIN(18, "x_ldd[18]"),
-	PINCTRL_PIN(19, "x_ldd[19]"),
-	PINCTRL_PIN(20, "x_ldd[20]"),
-	PINCTRL_PIN(21, "x_ldd[21]"),
-	PINCTRL_PIN(22, "x_ldd[22]"),
-	PINCTRL_PIN(23, "x_ldd[23]"),
-	PINCTRL_PIN(24, "gps_sgn"),
-	PINCTRL_PIN(25, "gps_mag"),
-	PINCTRL_PIN(26, "gps_clk"),
-	PINCTRL_PIN(27,	"sd_cd_b_2"),
-	PINCTRL_PIN(28, "sd_vcc_on_2"),
-	PINCTRL_PIN(29, "sd_wp_b_2"),
-	PINCTRL_PIN(30, "sd_clk_3"),
-	PINCTRL_PIN(31, "sd_cmd_3"),
-
-	PINCTRL_PIN(32, "x_sd_dat_3[0]"),
-	PINCTRL_PIN(33, "x_sd_dat_3[1]"),
-	PINCTRL_PIN(34, "x_sd_dat_3[2]"),
-	PINCTRL_PIN(35, "x_sd_dat_3[3]"),
-	PINCTRL_PIN(36, "usb_clk"),
-	PINCTRL_PIN(37, "usb_dir"),
-	PINCTRL_PIN(38, "usb_nxt"),
-	PINCTRL_PIN(39, "usb_stp"),
-	PINCTRL_PIN(40, "usb_dat[7]"),
-	PINCTRL_PIN(41, "usb_dat[6]"),
-	PINCTRL_PIN(42, "x_cko_1"),
-	PINCTRL_PIN(43, "spi_clk_1"),
-	PINCTRL_PIN(44, "spi_dout_1"),
-	PINCTRL_PIN(45, "spi_din_1"),
-	PINCTRL_PIN(46, "spi_en_1"),
-	PINCTRL_PIN(47, "x_txd_1"),
-	PINCTRL_PIN(48, "x_txd_2"),
-	PINCTRL_PIN(49, "x_rxd_1"),
-	PINCTRL_PIN(50, "x_rxd_2"),
-	PINCTRL_PIN(51, "x_usclk_0"),
-	PINCTRL_PIN(52, "x_utxd_0"),
-	PINCTRL_PIN(53, "x_urxd_0"),
-	PINCTRL_PIN(54, "x_utfs_0"),
-	PINCTRL_PIN(55, "x_urfs_0"),
-	PINCTRL_PIN(56, "usb_dat5"),
-	PINCTRL_PIN(57, "usb_dat4"),
-	PINCTRL_PIN(58, "usb_dat3"),
-	PINCTRL_PIN(59, "usb_dat2"),
-	PINCTRL_PIN(60, "usb_dat1"),
-	PINCTRL_PIN(61, "usb_dat0"),
-	PINCTRL_PIN(62, "x_ldd[14]"),
-	PINCTRL_PIN(63, "x_ldd[15]"),
-
-	PINCTRL_PIN(64, "x_gps_gpio"),
-	PINCTRL_PIN(65, "x_ldd[13]"),
-	PINCTRL_PIN(66, "x_df_we_b"),
-	PINCTRL_PIN(67, "x_df_re_b"),
-	PINCTRL_PIN(68, "x_txd_0"),
-	PINCTRL_PIN(69, "x_rxd_0"),
-	PINCTRL_PIN(70, "x_l_lck"),
-	PINCTRL_PIN(71, "x_l_fck"),
-	PINCTRL_PIN(72, "x_l_de"),
-	PINCTRL_PIN(73, "x_ldd[0]"),
-	PINCTRL_PIN(74, "x_ldd[1]"),
-	PINCTRL_PIN(75, "x_ldd[2]"),
-	PINCTRL_PIN(76, "x_ldd[3]"),
-	PINCTRL_PIN(77, "x_ldd[4]"),
-	PINCTRL_PIN(78, "x_cko_0"),
-	PINCTRL_PIN(79, "x_ldd[5]"),
-	PINCTRL_PIN(80, "x_ldd[6]"),
-	PINCTRL_PIN(81, "x_ldd[7]"),
-	PINCTRL_PIN(82, "x_ldd[8]"),
-	PINCTRL_PIN(83, "x_ldd[9]"),
-	PINCTRL_PIN(84, "x_ldd[10]"),
-	PINCTRL_PIN(85, "x_ldd[11]"),
-	PINCTRL_PIN(86, "x_ldd[12]"),
-	PINCTRL_PIN(87, "x_vip_vsync"),
-	PINCTRL_PIN(88, "x_vip_hsync"),
-	PINCTRL_PIN(89, "x_vip_pxclk"),
-	PINCTRL_PIN(90, "x_sda_0"),
-	PINCTRL_PIN(91, "x_scl_0"),
-	PINCTRL_PIN(92, "x_df_ry_by"),
-	PINCTRL_PIN(93, "x_df_cs_b[1]"),
-	PINCTRL_PIN(94, "x_df_cs_b[0]"),
-	PINCTRL_PIN(95, "x_l_pclk"),
-
-	PINCTRL_PIN(96, "x_df_dqs"),
-	PINCTRL_PIN(97, "x_df_wp_b"),
-	PINCTRL_PIN(98, "ac97_sync"),
-	PINCTRL_PIN(99, "ac97_bit_clk "),
-	PINCTRL_PIN(100, "ac97_dout"),
-	PINCTRL_PIN(101, "ac97_din"),
-	PINCTRL_PIN(102, "x_rtc_io"),
-
-	PINCTRL_PIN(103, "x_usb1_dp"),
-	PINCTRL_PIN(104, "x_usb1_dn"),
-};
-
-static const struct sirfsoc_muxmask lcd_16bits_sirfsoc_muxmask[] = {
-	{
-		.group = 1,
-		.mask = BIT(30) | BIT(31),
-	}, {
-		.group = 2,
-		.mask = BIT(1) | BIT(6) | BIT(7) | BIT(8) | BIT(9) |
-			BIT(10) | BIT(11) | BIT(12) | BIT(13) | BIT(15) |
-			BIT(16) | BIT(17) | BIT(18) | BIT(19) |
-			BIT(20) | BIT(21) | BIT(22) | BIT(31),
-	},
-};
-
-static const struct sirfsoc_padmux lcd_16bits_padmux = {
-	.muxmask_counts = ARRAY_SIZE(lcd_16bits_sirfsoc_muxmask),
-	.muxmask = lcd_16bits_sirfsoc_muxmask,
-	.ctrlreg = SIRFSOC_RSC_PIN_MUX,
-	.funcmask = BIT(4),
-	.funcval = 0,
-};
-
-static const unsigned lcd_16bits_pins[] = { 62, 63, 65, 70, 71, 72, 73, 74, 75,
-	76, 77, 79, 80, 81, 82, 83, 84, 85, 86, 95 };
-
-static const struct sirfsoc_muxmask lcd_18bits_muxmask[] = {
-	{
-		.group = 2,
-		.mask = BIT(1) | BIT(6) | BIT(7) | BIT(8) | BIT(9) |
-			BIT(10) | BIT(11) | BIT(12) | BIT(13) | BIT(15) |
-			BIT(16) | BIT(17) | BIT(18) | BIT(19) |
-			BIT(20) | BIT(21) | BIT(22) | BIT(31),
-	}, {
-		.group = 1,
-		.mask = BIT(30) | BIT(31),
-	}, {
-		.group = 0,
-		.mask = BIT(16) | BIT(17),
-	},
-};
-
-static const struct sirfsoc_padmux lcd_18bits_padmux = {
-	.muxmask_counts = ARRAY_SIZE(lcd_18bits_muxmask),
-	.muxmask = lcd_18bits_muxmask,
-	.ctrlreg = SIRFSOC_RSC_PIN_MUX,
-	.funcmask = BIT(4) | BIT(15),
-	.funcval = 0,
-};
-
-static const unsigned lcd_18bits_pins[] = { 16, 17, 62, 63, 65, 70, 71, 72, 73,
-	74, 75, 76, 77, 79, 80, 81, 82, 83, 84, 85, 86, 95 };
-
-static const struct sirfsoc_muxmask lcd_24bits_muxmask[] = {
-	{
-		.group = 2,
-		.mask = BIT(1) | BIT(6) | BIT(7) | BIT(8) | BIT(9) |
-			BIT(10) | BIT(11) | BIT(12) | BIT(13) | BIT(15) |
-			BIT(16) | BIT(17) | BIT(18) | BIT(19) |
-			BIT(20) | BIT(21) | BIT(22) | BIT(31),
-	}, {
-		.group = 1,
-		.mask = BIT(30) | BIT(31),
-	}, {
-		.group = 0,
-		.mask = BIT(16) | BIT(17) | BIT(18) | BIT(19) | BIT(20) |
-			BIT(21) | BIT(22) | BIT(23),
-	},
-};
-
-static const struct sirfsoc_padmux lcd_24bits_padmux = {
-	.muxmask_counts = ARRAY_SIZE(lcd_24bits_muxmask),
-	.muxmask = lcd_24bits_muxmask,
-	.ctrlreg = SIRFSOC_RSC_PIN_MUX,
-	.funcmask = BIT(4) | BIT(15),
-	.funcval = 0,
-};
-
-static const unsigned lcd_24bits_pins[] = { 16, 17, 18, 19, 20, 21, 22, 23, 62,
-	63, 65, 70, 71, 72, 73, 74, 75, 76, 77, 79, 80, 81, 82, 83, 84,
-	85, 86, 95};
-
-static const struct sirfsoc_muxmask lcdrom_muxmask[] = {
-	{
-		.group = 2,
-		.mask = BIT(1) | BIT(6) | BIT(7) | BIT(8) | BIT(9) | BIT(10) |
-			BIT(11) | BIT(12) | BIT(13) | BIT(15) | BIT(16) |
-			BIT(17) | BIT(18) | BIT(19) |
-			BIT(20) | BIT(21) | BIT(22) | BIT(31),
-	}, {
-		.group = 1,
-		.mask = BIT(30) | BIT(31),
-	}, {
-		.group = 0,
-		.mask = BIT(8),
-	},
-};
-
-static const struct sirfsoc_padmux lcdrom_padmux = {
-	.muxmask_counts = ARRAY_SIZE(lcdrom_muxmask),
-	.muxmask = lcdrom_muxmask,
-	.ctrlreg = SIRFSOC_RSC_PIN_MUX,
-	.funcmask = BIT(4),
-	.funcval = BIT(4),
-};
-
-static const unsigned lcdrom_pins[] = { 8, 62, 63, 65, 70, 71, 72, 73, 74, 75,
-	76, 77, 79, 80, 81, 82, 83, 84, 85, 86, 95};
-
-static const struct sirfsoc_muxmask uart0_muxmask[] = {
-	{
-		.group = 0,
-		.mask = BIT(12),
-	}, {
-		.group = 1,
-		.mask = BIT(23),
-	}, {
-		.group = 2,
-		.mask = BIT(4) | BIT(5),
-	},
-};
-
-static const struct sirfsoc_padmux uart0_padmux = {
-	.muxmask_counts = ARRAY_SIZE(uart0_muxmask),
-	.muxmask = uart0_muxmask,
-	.ctrlreg = SIRFSOC_RSC_PIN_MUX,
-	.funcmask = BIT(9),
-	.funcval = BIT(9),
-};
-
-static const unsigned uart0_pins[] = { 12, 55, 68, 69 };
-
-static const struct sirfsoc_muxmask uart0_nostreamctrl_muxmask[] = {
-	{
-		.group = 2,
-		.mask = BIT(4) | BIT(5),
-	},
-};
-
-static const struct sirfsoc_padmux uart0_nostreamctrl_padmux = {
-	.muxmask_counts = ARRAY_SIZE(uart0_nostreamctrl_muxmask),
-	.muxmask = uart0_nostreamctrl_muxmask,
-};
-
-static const unsigned uart0_nostreamctrl_pins[] = { 68, 69 };
-
-static const struct sirfsoc_muxmask uart1_muxmask[] = {
-	{
-		.group = 1,
-		.mask = BIT(15) | BIT(17),
-	},
-};
-
-static const struct sirfsoc_padmux uart1_padmux = {
-	.muxmask_counts = ARRAY_SIZE(uart1_muxmask),
-	.muxmask = uart1_muxmask,
-};
-
-static const unsigned uart1_pins[] = { 47, 49 };
-
-static const struct sirfsoc_muxmask uart2_muxmask[] = {
-	{
-		.group = 0,
-		.mask = BIT(10) | BIT(14),
-	}, {
-		.group = 1,
-		.mask = BIT(16) | BIT(18),
-	},
-};
-
-static const struct sirfsoc_padmux uart2_padmux = {
-	.muxmask_counts = ARRAY_SIZE(uart2_muxmask),
-	.muxmask = uart2_muxmask,
-	.ctrlreg = SIRFSOC_RSC_PIN_MUX,
-	.funcmask = BIT(10),
-	.funcval = BIT(10),
-};
-
-static const unsigned uart2_pins[] = { 10, 14, 48, 50 };
-
-static const struct sirfsoc_muxmask uart2_nostreamctrl_muxmask[] = {
-	{
-		.group = 1,
-		.mask = BIT(16) | BIT(18),
-	},
-};
-
-static const struct sirfsoc_padmux uart2_nostreamctrl_padmux = {
-	.muxmask_counts = ARRAY_SIZE(uart2_nostreamctrl_muxmask),
-	.muxmask = uart2_nostreamctrl_muxmask,
-};
-
-static const unsigned uart2_nostreamctrl_pins[] = { 48, 50 };
-
-static const struct sirfsoc_muxmask sdmmc3_muxmask[] = {
-	{
-		.group = 0,
-		.mask = BIT(30) | BIT(31),
-	}, {
-		.group = 1,
-		.mask = BIT(0) | BIT(1) | BIT(2) | BIT(3),
-	},
-};
-
-static const struct sirfsoc_padmux sdmmc3_padmux = {
-	.muxmask_counts = ARRAY_SIZE(sdmmc3_muxmask),
-	.muxmask = sdmmc3_muxmask,
-	.ctrlreg = SIRFSOC_RSC_PIN_MUX,
-	.funcmask = BIT(7),
-	.funcval = 0,
-};
-
-static const unsigned sdmmc3_pins[] = { 30, 31, 32, 33, 34, 35 };
-
-static const struct sirfsoc_muxmask spi0_muxmask[] = {
-	{
-		.group = 0,
-		.mask = BIT(30),
-	}, {
-		.group = 1,
-		.mask = BIT(0) | BIT(2) | BIT(3),
-	},
-};
-
-static const struct sirfsoc_padmux spi0_padmux = {
-	.muxmask_counts = ARRAY_SIZE(spi0_muxmask),
-	.muxmask = spi0_muxmask,
-	.ctrlreg = SIRFSOC_RSC_PIN_MUX,
-	.funcmask = BIT(7),
-	.funcval = BIT(7),
-};
-
-static const unsigned spi0_pins[] = { 30, 32, 34, 35 };
-
-static const struct sirfsoc_muxmask cko1_muxmask[] = {
-	{
-		.group = 1,
-		.mask = BIT(10),
-	},
-};
-
-static const struct sirfsoc_padmux cko1_padmux = {
-	.muxmask_counts = ARRAY_SIZE(cko1_muxmask),
-	.muxmask = cko1_muxmask,
-	.ctrlreg = SIRFSOC_RSC_PIN_MUX,
-	.funcmask = BIT(3),
-	.funcval = 0,
-};
-
-static const unsigned cko1_pins[] = { 42 };
-
-static const struct sirfsoc_muxmask i2s_mclk_muxmask[] = {
-	{
-		.group = 1,
-		.mask = BIT(10),
-	},
-};
-
-static const struct sirfsoc_padmux i2s_mclk_padmux = {
-	.muxmask_counts = ARRAY_SIZE(i2s_mclk_muxmask),
-	.muxmask = i2s_mclk_muxmask,
-	.ctrlreg = SIRFSOC_RSC_PIN_MUX,
-	.funcmask = BIT(3),
-	.funcval = BIT(3),
-};
-
-static const unsigned i2s_mclk_pins[] = { 42 };
-
-static const struct sirfsoc_muxmask i2s_ext_clk_input_muxmask[] = {
-	{
-		.group = 1,
-		.mask = BIT(19),
-	},
-};
-
-static const struct sirfsoc_padmux i2s_ext_clk_input_padmux = {
-	.muxmask_counts = ARRAY_SIZE(i2s_ext_clk_input_muxmask),
-	.muxmask = i2s_ext_clk_input_muxmask,
-	.ctrlreg = SIRFSOC_RSC_PIN_MUX,
-	.funcmask = BIT(2),
-	.funcval = BIT(2),
-};
-
-static const unsigned i2s_ext_clk_input_pins[] = { 51 };
-
-static const struct sirfsoc_muxmask i2s_muxmask[] = {
-	{
-		.group = 3,
-		.mask = BIT(2) | BIT(3) | BIT(4) | BIT(5),
-	},
-};
-
-static const struct sirfsoc_padmux i2s_padmux = {
-	.muxmask_counts = ARRAY_SIZE(i2s_muxmask),
-	.muxmask = i2s_muxmask,
-	.ctrlreg = SIRFSOC_RSC_PIN_MUX,
-};
-
-static const unsigned i2s_pins[] = { 98, 99, 100, 101 };
-
-static const struct sirfsoc_muxmask i2s_no_din_muxmask[] = {
-	{
-		.group = 3,
-		.mask = BIT(2) | BIT(3) | BIT(4),
-	},
-};
-
-static const struct sirfsoc_padmux i2s_no_din_padmux = {
-	.muxmask_counts = ARRAY_SIZE(i2s_no_din_muxmask),
-	.muxmask = i2s_no_din_muxmask,
-	.ctrlreg = SIRFSOC_RSC_PIN_MUX,
-};
-
-static const unsigned i2s_no_din_pins[] = { 98, 99, 100 };
-
-static const struct sirfsoc_muxmask i2s_6chn_muxmask[] = {
-	{
-		.group = 3,
-		.mask = BIT(2) | BIT(3) | BIT(4) | BIT(5),
-	},
-};
-
-static const struct sirfsoc_padmux i2s_6chn_padmux = {
-	.muxmask_counts = ARRAY_SIZE(i2s_6chn_muxmask),
-	.muxmask = i2s_6chn_muxmask,
-	.ctrlreg = SIRFSOC_RSC_PIN_MUX,
-	.funcmask = BIT(1) | BIT(9),
-	.funcval = BIT(1) | BIT(9),
-};
-
-static const unsigned i2s_6chn_pins[] = { 52, 55, 98, 99, 100, 101 };
-
-static const struct sirfsoc_muxmask ac97_muxmask[] = {
-	{
-		.group = 3,
-		.mask = BIT(2) | BIT(3) | BIT(4) | BIT(5),
-	},
-};
-
-static const struct sirfsoc_padmux ac97_padmux = {
-	.muxmask_counts = ARRAY_SIZE(ac97_muxmask),
-	.muxmask = ac97_muxmask,
-};
-
-static const unsigned ac97_pins[] = { 98, 99, 100, 101 };
-
-static const struct sirfsoc_muxmask spi1_muxmask[] = {
-	{
-		.group = 1,
-		.mask = BIT(11) | BIT(12) | BIT(13) | BIT(14),
-	},
-};
-
-static const struct sirfsoc_padmux spi1_padmux = {
-	.muxmask_counts = ARRAY_SIZE(spi1_muxmask),
-	.muxmask = spi1_muxmask,
-	.ctrlreg = SIRFSOC_RSC_PIN_MUX,
-	.funcmask = BIT(16),
-	.funcval = 0,
-};
-
-static const unsigned spi1_pins[] = { 43, 44, 45, 46 };
-
-static const struct sirfsoc_muxmask sdmmc1_muxmask[] = {
-	{
-		.group = 2,
-		.mask = BIT(2) | BIT(3),
-	},
-};
-
-static const struct sirfsoc_padmux sdmmc1_padmux = {
-	.muxmask_counts = ARRAY_SIZE(sdmmc1_muxmask),
-	.muxmask = sdmmc1_muxmask,
-	.ctrlreg = SIRFSOC_RSC_PIN_MUX,
-	.funcmask = BIT(5),
-	.funcval = BIT(5),
-};
-
-static const unsigned sdmmc1_pins[] = { 66, 67 };
-
-static const struct sirfsoc_muxmask gps_muxmask[] = {
-	{
-		.group = 0,
-		.mask = BIT(24) | BIT(25) | BIT(26),
-	},
-};
-
-static const struct sirfsoc_padmux gps_padmux = {
-	.muxmask_counts = ARRAY_SIZE(gps_muxmask),
-	.muxmask = gps_muxmask,
-	.ctrlreg = SIRFSOC_RSC_PIN_MUX,
-	.funcmask = BIT(13),
-	.funcval = 0,
-};
-
-static const unsigned gps_pins[] = { 24, 25, 26 };
-
-static const struct sirfsoc_muxmask sdmmc5_muxmask[] = {
-	{
-		.group = 0,
-		.mask = BIT(24) | BIT(25) | BIT(26),
-	},
-};
-
-static const struct sirfsoc_padmux sdmmc5_padmux = {
-	.muxmask_counts = ARRAY_SIZE(sdmmc5_muxmask),
-	.muxmask = sdmmc5_muxmask,
-	.ctrlreg = SIRFSOC_RSC_PIN_MUX,
-	.funcmask = BIT(13),
-	.funcval = BIT(13),
-};
-
-static const unsigned sdmmc5_pins[] = { 24, 25, 26 };
-
-static const struct sirfsoc_muxmask usp0_muxmask[] = {
-	{
-		.group = 1,
-		.mask = BIT(19) | BIT(20) | BIT(21) | BIT(22) | BIT(23),
-	},
-};
-
-static const struct sirfsoc_padmux usp0_padmux = {
-	.muxmask_counts = ARRAY_SIZE(usp0_muxmask),
-	.muxmask = usp0_muxmask,
-	.ctrlreg = SIRFSOC_RSC_PIN_MUX,
-	.funcmask = BIT(1) | BIT(2) | BIT(9),
-	.funcval = 0,
-};
-
-static const unsigned usp0_pins[] = { 51, 52, 53, 54, 55 };
-
-static const struct sirfsoc_muxmask usp0_only_utfs_muxmask[] = {
-	{
-		.group = 1,
-		.mask = BIT(19) | BIT(20) | BIT(21) | BIT(22),
-	},
-};
-
-static const struct sirfsoc_padmux usp0_only_utfs_padmux = {
-	.muxmask_counts = ARRAY_SIZE(usp0_only_utfs_muxmask),
-	.muxmask = usp0_only_utfs_muxmask,
-	.ctrlreg = SIRFSOC_RSC_PIN_MUX,
-	.funcmask = BIT(1) | BIT(2) | BIT(6),
-	.funcval = 0,
-};
-
-static const unsigned usp0_only_utfs_pins[] = { 51, 52, 53, 54 };
-
-static const struct sirfsoc_muxmask usp0_only_urfs_muxmask[] = {
-	{
-		.group = 1,
-		.mask = BIT(19) | BIT(20) | BIT(21) | BIT(23),
-	},
-};
-
-static const struct sirfsoc_padmux usp0_only_urfs_padmux = {
-	.muxmask_counts = ARRAY_SIZE(usp0_only_urfs_muxmask),
-	.muxmask = usp0_only_urfs_muxmask,
-	.ctrlreg = SIRFSOC_RSC_PIN_MUX,
-	.funcmask = BIT(1) | BIT(2) | BIT(9),
-	.funcval = 0,
-};
-
-static const unsigned usp0_only_urfs_pins[] = { 51, 52, 53, 55 };
-
-static const struct sirfsoc_muxmask usp0_uart_nostreamctrl_muxmask[] = {
-	{
-		.group = 1,
-		.mask = BIT(20) | BIT(21),
-	},
-};
-
-static const struct sirfsoc_padmux usp0_uart_nostreamctrl_padmux = {
-	.muxmask_counts = ARRAY_SIZE(usp0_uart_nostreamctrl_muxmask),
-	.muxmask = usp0_uart_nostreamctrl_muxmask,
-};
-
-static const unsigned usp0_uart_nostreamctrl_pins[] = { 52, 53 };
-static const struct sirfsoc_muxmask usp1_muxmask[] = {
-	{
-		.group = 0,
-		.mask = BIT(15),
-	}, {
-		.group = 1,
-		.mask = BIT(11) | BIT(12) | BIT(13) | BIT(14),
-	},
-};
-
-static const struct sirfsoc_padmux usp1_padmux = {
-	.muxmask_counts = ARRAY_SIZE(usp1_muxmask),
-	.muxmask = usp1_muxmask,
-	.ctrlreg = SIRFSOC_RSC_PIN_MUX,
-	.funcmask = BIT(16),
-	.funcval = BIT(16),
-};
-
-static const unsigned usp1_pins[] = { 15, 43, 44, 45, 46 };
-
-static const struct sirfsoc_muxmask usp1_uart_nostreamctrl_muxmask[] = {
-	{
-		.group = 1,
-		.mask = BIT(12) | BIT(13),
-	},
-};
-
-static const struct sirfsoc_padmux usp1_uart_nostreamctrl_padmux = {
-	.muxmask_counts = ARRAY_SIZE(usp1_uart_nostreamctrl_muxmask),
-	.muxmask = usp1_uart_nostreamctrl_muxmask,
-	.ctrlreg = SIRFSOC_RSC_PIN_MUX,
-	.funcmask = BIT(16),
-	.funcval = BIT(16),
-};
-
-static const unsigned usp1_uart_nostreamctrl_pins[] = { 44, 45 };
-
-static const struct sirfsoc_muxmask nand_muxmask[] = {
-	{
-		.group = 2,
-		.mask = BIT(2) | BIT(3) | BIT(28) | BIT(29) | BIT(30),
-	}, {
-		.group = 3,
-		.mask = BIT(0) | BIT(1),
-	},
-};
-
-static const struct sirfsoc_padmux nand_padmux = {
-	.muxmask_counts = ARRAY_SIZE(nand_muxmask),
-	.muxmask = nand_muxmask,
-	.ctrlreg = SIRFSOC_RSC_PIN_MUX,
-	.funcmask = BIT(5) | BIT(19),
-	.funcval = 0,
-};
-
-static const unsigned nand_pins[] = { 66, 67, 92, 93, 94, 96, 97 };
-
-static const struct sirfsoc_muxmask sdmmc0_muxmask[] = {
-	{
-		.group = 3,
-		.mask = BIT(1),
-	},
-};
-
-static const struct sirfsoc_padmux sdmmc0_padmux = {
-	.muxmask_counts = ARRAY_SIZE(sdmmc0_muxmask),
-	.muxmask = sdmmc0_muxmask,
-	.ctrlreg = SIRFSOC_RSC_PIN_MUX,
-	.funcmask = BIT(5) | BIT(19),
-	.funcval = BIT(19),
-};
-
-static const unsigned sdmmc0_pins[] = { 97 };
-
-static const struct sirfsoc_muxmask sdmmc2_muxmask[] = {
-	{
-		.group = 0,
-		.mask = BIT(27) | BIT(28) | BIT(29),
-	},
-};
-
-static const struct sirfsoc_padmux sdmmc2_padmux = {
-	.muxmask_counts = ARRAY_SIZE(sdmmc2_muxmask),
-	.muxmask = sdmmc2_muxmask,
-	.ctrlreg = SIRFSOC_RSC_PIN_MUX,
-	.funcmask = BIT(11),
-	.funcval = 0,
-};
-
-static const unsigned sdmmc2_pins[] = { 27, 28, 29 };
-
-static const struct sirfsoc_muxmask sdmmc2_nowp_muxmask[] = {
-	{
-		.group = 0,
-		.mask = BIT(27) | BIT(28),
-	},
-};
-
-static const struct sirfsoc_padmux sdmmc2_nowp_padmux = {
-	.muxmask_counts = ARRAY_SIZE(sdmmc2_nowp_muxmask),
-	.muxmask = sdmmc2_nowp_muxmask,
-	.ctrlreg = SIRFSOC_RSC_PIN_MUX,
-	.funcmask = BIT(11),
-	.funcval = 0,
-};
-
-static const unsigned sdmmc2_nowp_pins[] = { 27, 28 };
-
-static const struct sirfsoc_muxmask cko0_muxmask[] = {
-	{
-		.group = 2,
-		.mask = BIT(14),
-	},
-};
-
-static const struct sirfsoc_padmux cko0_padmux = {
-	.muxmask_counts = ARRAY_SIZE(cko0_muxmask),
-	.muxmask = cko0_muxmask,
-};
-
-static const unsigned cko0_pins[] = { 78 };
-
-static const struct sirfsoc_muxmask vip_muxmask[] = {
-	{
-		.group = 1,
-		.mask = BIT(4) | BIT(5) | BIT(6) | BIT(8) | BIT(9)
-			| BIT(24) | BIT(25) | BIT(26) | BIT(27) | BIT(28) |
-			BIT(29),
-	},
-};
-
-static const struct sirfsoc_padmux vip_padmux = {
-	.muxmask_counts = ARRAY_SIZE(vip_muxmask),
-	.muxmask = vip_muxmask,
-	.ctrlreg = SIRFSOC_RSC_PIN_MUX,
-	.funcmask = BIT(18),
-	.funcval = BIT(18),
-};
-
-static const unsigned vip_pins[] = { 36, 37, 38, 40, 41, 56, 57, 58, 59,
-	60, 61 };
-
-static const struct sirfsoc_muxmask vip_noupli_muxmask[] = {
-	{
-		.group = 0,
-		.mask = BIT(16) | BIT(17) | BIT(18) | BIT(19) | BIT(20)
-			| BIT(21) | BIT(22) | BIT(23),
-	}, {
-		.group = 2,
-		.mask = BIT(23) | BIT(24) | BIT(25),
-	},
-};
-
-static const struct sirfsoc_padmux vip_noupli_padmux = {
-	.muxmask_counts = ARRAY_SIZE(vip_noupli_muxmask),
-	.muxmask = vip_noupli_muxmask,
-	.ctrlreg = SIRFSOC_RSC_PIN_MUX,
-	.funcmask = BIT(15),
-	.funcval = BIT(15),
-};
-
-static const unsigned vip_noupli_pins[] = { 16, 17, 18, 19, 20, 21, 22, 23,
-	87, 88, 89 };
-
-static const struct sirfsoc_muxmask i2c0_muxmask[] = {
-	{
-		.group = 2,
-		.mask = BIT(26) | BIT(27),
-	},
-};
-
-static const struct sirfsoc_padmux i2c0_padmux = {
-	.muxmask_counts = ARRAY_SIZE(i2c0_muxmask),
-	.muxmask = i2c0_muxmask,
-};
-
-static const unsigned i2c0_pins[] = { 90, 91 };
-
-static const struct sirfsoc_muxmask i2c1_muxmask[] = {
-	{
-		.group = 0,
-		.mask = BIT(13) | BIT(15),
-	},
-};
-
-static const struct sirfsoc_padmux i2c1_padmux = {
-	.muxmask_counts = ARRAY_SIZE(i2c1_muxmask),
-	.muxmask = i2c1_muxmask,
-	.ctrlreg = SIRFSOC_RSC_PIN_MUX,
-	.funcmask = BIT(16),
-	.funcval = 0,
-};
-
-static const unsigned i2c1_pins[] = { 13, 15 };
-
-static const struct sirfsoc_muxmask pwm0_muxmask[] = {
-	{
-		.group = 0,
-		.mask = BIT(4),
-	},
-};
-
-static const struct sirfsoc_padmux pwm0_padmux = {
-	.muxmask_counts = ARRAY_SIZE(pwm0_muxmask),
-	.muxmask = pwm0_muxmask,
-	.ctrlreg = SIRFSOC_RSC_PIN_MUX,
-	.funcmask = BIT(12),
-	.funcval = 0,
-};
-
-static const unsigned pwm0_pins[] = { 4 };
-
-static const struct sirfsoc_muxmask pwm1_muxmask[] = {
-	{
-		.group = 0,
-		.mask = BIT(5),
-	},
-};
-
-static const struct sirfsoc_padmux pwm1_padmux = {
-	.muxmask_counts = ARRAY_SIZE(pwm1_muxmask),
-	.muxmask = pwm1_muxmask,
-};
-
-static const unsigned pwm1_pins[] = { 5 };
-
-static const struct sirfsoc_muxmask pwm2_muxmask[] = {
-	{
-		.group = 0,
-		.mask = BIT(6),
-	},
-};
-
-static const struct sirfsoc_padmux pwm2_padmux = {
-	.muxmask_counts = ARRAY_SIZE(pwm2_muxmask),
-	.muxmask = pwm2_muxmask,
-};
-
-static const unsigned pwm2_pins[] = { 6 };
-
-static const struct sirfsoc_muxmask pwm3_muxmask[] = {
-	{
-		.group = 0,
-		.mask = BIT(7),
-	},
-};
-
-static const struct sirfsoc_padmux pwm3_padmux = {
-	.muxmask_counts = ARRAY_SIZE(pwm3_muxmask),
-	.muxmask = pwm3_muxmask,
-};
-
-static const unsigned pwm3_pins[] = { 7 };
-
-static const struct sirfsoc_muxmask pwm4_muxmask[] = {
-	{
-		.group = 2,
-		.mask = BIT(14),
-	},
-};
-
-static const struct sirfsoc_padmux pwm4_padmux = {
-	.muxmask_counts = ARRAY_SIZE(pwm4_muxmask),
-	.muxmask = pwm4_muxmask,
-};
-
-static const unsigned pwm4_pins[] = { 78 };
-
-static const struct sirfsoc_muxmask warm_rst_muxmask[] = {
-	{
-		.group = 0,
-		.mask = BIT(8),
-	},
-};
-
-static const struct sirfsoc_padmux warm_rst_padmux = {
-	.muxmask_counts = ARRAY_SIZE(warm_rst_muxmask),
-	.muxmask = warm_rst_muxmask,
-	.ctrlreg = SIRFSOC_RSC_PIN_MUX,
-	.funcmask = BIT(4),
-	.funcval = 0,
-};
-
-static const unsigned warm_rst_pins[] = { 8 };
-
-static const struct sirfsoc_muxmask usb0_upli_drvbus_muxmask[] = {
-	{
-		.group = 1,
-		.mask = BIT(4) | BIT(5) | BIT(6) | BIT(7) | BIT(8)
-			| BIT(9) | BIT(24) | BIT(25) | BIT(26) |
-			BIT(27) | BIT(28) | BIT(29),
-	},
-};
-static const struct sirfsoc_padmux usb0_upli_drvbus_padmux = {
-	.muxmask_counts = ARRAY_SIZE(usb0_upli_drvbus_muxmask),
-	.muxmask = usb0_upli_drvbus_muxmask,
-	.ctrlreg = SIRFSOC_RSC_PIN_MUX,
-	.funcmask = BIT(18),
-	.funcval = 0,
-};
-
-static const unsigned usb0_upli_drvbus_pins[] = { 36, 37, 38, 39, 40,
-	41, 56, 57, 58, 59, 60, 61 };
-
-static const struct sirfsoc_muxmask usb1_utmi_drvbus_muxmask[] = {
-	{
-		.group = 0,
-		.mask = BIT(28),
-	},
-};
-
-static const struct sirfsoc_padmux usb1_utmi_drvbus_padmux = {
-	.muxmask_counts = ARRAY_SIZE(usb1_utmi_drvbus_muxmask),
-	.muxmask = usb1_utmi_drvbus_muxmask,
-	.ctrlreg = SIRFSOC_RSC_PIN_MUX,
-	.funcmask = BIT(11),
-	.funcval = BIT(11), /* refer to PAD_UTMI_DRVVBUS1_ENABLE */
-};
-
-static const unsigned usb1_utmi_drvbus_pins[] = { 28 };
-
-static const struct sirfsoc_padmux usb1_dp_dn_padmux = {
-	.muxmask_counts = 0,
-	.ctrlreg = SIRFSOC_RSC_USB_UART_SHARE,
-	.funcmask = BIT(2),
-	.funcval = BIT(2),
-};
-
-static const unsigned usb1_dp_dn_pins[] = { 103, 104 };
-
-static const struct sirfsoc_padmux uart1_route_io_usb1_padmux = {
-	.muxmask_counts = 0,
-	.ctrlreg = SIRFSOC_RSC_USB_UART_SHARE,
-	.funcmask = BIT(2),
-	.funcval = 0,
-};
-
-static const unsigned uart1_route_io_usb1_pins[] = { 103, 104 };
-
-static const struct sirfsoc_muxmask pulse_count_muxmask[] = {
-	{
-		.group = 0,
-		.mask = BIT(9) | BIT(10) | BIT(11),
-	},
-};
-
-static const struct sirfsoc_padmux pulse_count_padmux = {
-	.muxmask_counts = ARRAY_SIZE(pulse_count_muxmask),
-	.muxmask = pulse_count_muxmask,
-};
-
-static const unsigned pulse_count_pins[] = { 9, 10, 11 };
-
-static const struct sirfsoc_pin_group sirfsoc_pin_groups[] = {
-	SIRFSOC_PIN_GROUP("lcd_16bitsgrp", lcd_16bits_pins),
-	SIRFSOC_PIN_GROUP("lcd_18bitsgrp", lcd_18bits_pins),
-	SIRFSOC_PIN_GROUP("lcd_24bitsgrp", lcd_24bits_pins),
-	SIRFSOC_PIN_GROUP("lcdrom_grp", lcdrom_pins),
-	SIRFSOC_PIN_GROUP("uart0grp", uart0_pins),
-	SIRFSOC_PIN_GROUP("uart0_nostreamctrlgrp", uart0_nostreamctrl_pins),
-	SIRFSOC_PIN_GROUP("uart1grp", uart1_pins),
-	SIRFSOC_PIN_GROUP("uart2grp", uart2_pins),
-	SIRFSOC_PIN_GROUP("uart2_nostreamctrlgrp", uart2_nostreamctrl_pins),
-	SIRFSOC_PIN_GROUP("usp0grp", usp0_pins),
-	SIRFSOC_PIN_GROUP("usp0_uart_nostreamctrl_grp",
-					usp0_uart_nostreamctrl_pins),
-	SIRFSOC_PIN_GROUP("usp0_only_utfs_grp", usp0_only_utfs_pins),
-	SIRFSOC_PIN_GROUP("usp0_only_urfs_grp", usp0_only_urfs_pins),
-	SIRFSOC_PIN_GROUP("usp1grp", usp1_pins),
-	SIRFSOC_PIN_GROUP("usp1_uart_nostreamctrl_grp",
-					usp1_uart_nostreamctrl_pins),
-	SIRFSOC_PIN_GROUP("i2c0grp", i2c0_pins),
-	SIRFSOC_PIN_GROUP("i2c1grp", i2c1_pins),
-	SIRFSOC_PIN_GROUP("pwm0grp", pwm0_pins),
-	SIRFSOC_PIN_GROUP("pwm1grp", pwm1_pins),
-	SIRFSOC_PIN_GROUP("pwm2grp", pwm2_pins),
-	SIRFSOC_PIN_GROUP("pwm3grp", pwm3_pins),
-	SIRFSOC_PIN_GROUP("pwm4grp", pwm4_pins),
-	SIRFSOC_PIN_GROUP("vipgrp", vip_pins),
-	SIRFSOC_PIN_GROUP("vip_noupligrp", vip_noupli_pins),
-	SIRFSOC_PIN_GROUP("warm_rstgrp", warm_rst_pins),
-	SIRFSOC_PIN_GROUP("cko0grp", cko0_pins),
-	SIRFSOC_PIN_GROUP("cko1grp", cko1_pins),
-	SIRFSOC_PIN_GROUP("sdmmc0grp", sdmmc0_pins),
-	SIRFSOC_PIN_GROUP("sdmmc1grp", sdmmc1_pins),
-	SIRFSOC_PIN_GROUP("sdmmc2grp", sdmmc2_pins),
-	SIRFSOC_PIN_GROUP("sdmmc2_nowpgrp", sdmmc2_nowp_pins),
-	SIRFSOC_PIN_GROUP("sdmmc3grp", sdmmc3_pins),
-	SIRFSOC_PIN_GROUP("sdmmc5grp", sdmmc5_pins),
-	SIRFSOC_PIN_GROUP("usb0_upli_drvbusgrp", usb0_upli_drvbus_pins),
-	SIRFSOC_PIN_GROUP("usb1_utmi_drvbusgrp", usb1_utmi_drvbus_pins),
-	SIRFSOC_PIN_GROUP("usb1_dp_dngrp", usb1_dp_dn_pins),
-	SIRFSOC_PIN_GROUP("uart1_route_io_usb1grp", uart1_route_io_usb1_pins),
-	SIRFSOC_PIN_GROUP("pulse_countgrp", pulse_count_pins),
-	SIRFSOC_PIN_GROUP("i2smclkgrp", i2s_mclk_pins),
-	SIRFSOC_PIN_GROUP("i2s_ext_clk_inputgrp", i2s_ext_clk_input_pins),
-	SIRFSOC_PIN_GROUP("i2sgrp", i2s_pins),
-	SIRFSOC_PIN_GROUP("i2s_no_dingrp", i2s_no_din_pins),
-	SIRFSOC_PIN_GROUP("i2s_6chngrp", i2s_6chn_pins),
-	SIRFSOC_PIN_GROUP("ac97grp", ac97_pins),
-	SIRFSOC_PIN_GROUP("nandgrp", nand_pins),
-	SIRFSOC_PIN_GROUP("spi0grp", spi0_pins),
-	SIRFSOC_PIN_GROUP("spi1grp", spi1_pins),
-	SIRFSOC_PIN_GROUP("gpsgrp", gps_pins),
-};
-
-static const char * const lcd_16bitsgrp[] = { "lcd_16bitsgrp" };
-static const char * const lcd_18bitsgrp[] = { "lcd_18bitsgrp" };
-static const char * const lcd_24bitsgrp[] = { "lcd_24bitsgrp" };
-static const char * const lcdromgrp[] = { "lcdromgrp" };
-static const char * const uart0grp[] = { "uart0grp" };
-static const char * const uart0_nostreamctrlgrp[] = { "uart0_nostreamctrlgrp" };
-static const char * const uart1grp[] = { "uart1grp" };
-static const char * const uart2grp[] = { "uart2grp" };
-static const char * const uart2_nostreamctrlgrp[] = { "uart2_nostreamctrlgrp" };
-static const char * const usp0_uart_nostreamctrl_grp[] = {
-					"usp0_uart_nostreamctrl_grp" };
-static const char * const usp0grp[] = { "usp0grp" };
-static const char * const usp0_only_utfs_grp[] = { "usp0_only_utfs_grp" };
-static const char * const usp0_only_urfs_grp[] = { "usp0_only_urfs_grp" };
-
-static const char * const usp1grp[] = { "usp1grp" };
-static const char * const usp1_uart_nostreamctrl_grp[] = {
-					"usp1_uart_nostreamctrl_grp" };
-static const char * const i2c0grp[] = { "i2c0grp" };
-static const char * const i2c1grp[] = { "i2c1grp" };
-static const char * const pwm0grp[] = { "pwm0grp" };
-static const char * const pwm1grp[] = { "pwm1grp" };
-static const char * const pwm2grp[] = { "pwm2grp" };
-static const char * const pwm3grp[] = { "pwm3grp" };
-static const char * const pwm4grp[] = { "pwm4grp" };
-static const char * const vipgrp[] = { "vipgrp" };
-static const char * const vip_noupligrp[] = { "vip_noupligrp" };
-static const char * const warm_rstgrp[] = { "warm_rstgrp" };
-static const char * const cko0grp[] = { "cko0grp" };
-static const char * const cko1grp[] = { "cko1grp" };
-static const char * const sdmmc0grp[] = { "sdmmc0grp" };
-static const char * const sdmmc1grp[] = { "sdmmc1grp" };
-static const char * const sdmmc2grp[] = { "sdmmc2grp" };
-static const char * const sdmmc3grp[] = { "sdmmc3grp" };
-static const char * const sdmmc5grp[] = { "sdmmc5grp" };
-static const char * const sdmmc2_nowpgrp[] = { "sdmmc2_nowpgrp" };
-static const char * const usb0_upli_drvbusgrp[] = { "usb0_upli_drvbusgrp" };
-static const char * const usb1_utmi_drvbusgrp[] = { "usb1_utmi_drvbusgrp" };
-static const char * const usb1_dp_dngrp[] = { "usb1_dp_dngrp" };
-static const char * const
-	uart1_route_io_usb1grp[] = { "uart1_route_io_usb1grp" };
-static const char * const pulse_countgrp[] = { "pulse_countgrp" };
-static const char * const i2smclkgrp[] = { "i2smclkgrp" };
-static const char * const i2s_ext_clk_inputgrp[] = { "i2s_ext_clk_inputgrp" };
-static const char * const i2sgrp[] = { "i2sgrp" };
-static const char * const i2s_no_dingrp[] = { "i2s_no_dingrp" };
-static const char * const i2s_6chngrp[] = { "i2s_6chngrp" };
-static const char * const ac97grp[] = { "ac97grp" };
-static const char * const nandgrp[] = { "nandgrp" };
-static const char * const spi0grp[] = { "spi0grp" };
-static const char * const spi1grp[] = { "spi1grp" };
-static const char * const gpsgrp[] = { "gpsgrp" };
-
-static const struct sirfsoc_pmx_func sirfsoc_pmx_functions[] = {
-	SIRFSOC_PMX_FUNCTION("lcd_16bits", lcd_16bitsgrp, lcd_16bits_padmux),
-	SIRFSOC_PMX_FUNCTION("lcd_18bits", lcd_18bitsgrp, lcd_18bits_padmux),
-	SIRFSOC_PMX_FUNCTION("lcd_24bits", lcd_24bitsgrp, lcd_24bits_padmux),
-	SIRFSOC_PMX_FUNCTION("lcdrom", lcdromgrp, lcdrom_padmux),
-	SIRFSOC_PMX_FUNCTION("uart0", uart0grp, uart0_padmux),
-	SIRFSOC_PMX_FUNCTION("uart0_nostreamctrl", uart0_nostreamctrlgrp,
-						uart0_nostreamctrl_padmux),
-	SIRFSOC_PMX_FUNCTION("uart1", uart1grp, uart1_padmux),
-	SIRFSOC_PMX_FUNCTION("uart2", uart2grp, uart2_padmux),
-	SIRFSOC_PMX_FUNCTION("uart2_nostreamctrl",
-		uart2_nostreamctrlgrp, uart2_nostreamctrl_padmux),
-	SIRFSOC_PMX_FUNCTION("usp0", usp0grp, usp0_padmux),
-	SIRFSOC_PMX_FUNCTION("usp0_uart_nostreamctrl",
-						usp0_uart_nostreamctrl_grp,
-						usp0_uart_nostreamctrl_padmux),
-	SIRFSOC_PMX_FUNCTION("usp0_only_utfs", usp0_only_utfs_grp,
-						usp0_only_utfs_padmux),
-	SIRFSOC_PMX_FUNCTION("usp0_only_urfs", usp0_only_urfs_grp,
-						usp0_only_urfs_padmux),
-	SIRFSOC_PMX_FUNCTION("usp1", usp1grp, usp1_padmux),
-	SIRFSOC_PMX_FUNCTION("usp1_uart_nostreamctrl",
-						usp1_uart_nostreamctrl_grp,
-						usp1_uart_nostreamctrl_padmux),
-	SIRFSOC_PMX_FUNCTION("i2c0", i2c0grp, i2c0_padmux),
-	SIRFSOC_PMX_FUNCTION("i2c1", i2c1grp, i2c1_padmux),
-	SIRFSOC_PMX_FUNCTION("pwm0", pwm0grp, pwm0_padmux),
-	SIRFSOC_PMX_FUNCTION("pwm1", pwm1grp, pwm1_padmux),
-	SIRFSOC_PMX_FUNCTION("pwm2", pwm2grp, pwm2_padmux),
-	SIRFSOC_PMX_FUNCTION("pwm3", pwm3grp, pwm3_padmux),
-	SIRFSOC_PMX_FUNCTION("pwm4", pwm4grp, pwm4_padmux),
-	SIRFSOC_PMX_FUNCTION("vip", vipgrp, vip_padmux),
-	SIRFSOC_PMX_FUNCTION("vip_noupli", vip_noupligrp, vip_noupli_padmux),
-	SIRFSOC_PMX_FUNCTION("warm_rst", warm_rstgrp, warm_rst_padmux),
-	SIRFSOC_PMX_FUNCTION("cko0", cko0grp, cko0_padmux),
-	SIRFSOC_PMX_FUNCTION("cko1", cko1grp, cko1_padmux),
-	SIRFSOC_PMX_FUNCTION("sdmmc0", sdmmc0grp, sdmmc0_padmux),
-	SIRFSOC_PMX_FUNCTION("sdmmc1", sdmmc1grp, sdmmc1_padmux),
-	SIRFSOC_PMX_FUNCTION("sdmmc2", sdmmc2grp, sdmmc2_padmux),
-	SIRFSOC_PMX_FUNCTION("sdmmc3", sdmmc3grp, sdmmc3_padmux),
-	SIRFSOC_PMX_FUNCTION("sdmmc5", sdmmc5grp, sdmmc5_padmux),
-	SIRFSOC_PMX_FUNCTION("sdmmc2_nowp",
-		sdmmc2_nowpgrp, sdmmc2_nowp_padmux),
-	SIRFSOC_PMX_FUNCTION("usb0_upli_drvbus",
-		usb0_upli_drvbusgrp, usb0_upli_drvbus_padmux),
-	SIRFSOC_PMX_FUNCTION("usb1_utmi_drvbus",
-		usb1_utmi_drvbusgrp, usb1_utmi_drvbus_padmux),
-	SIRFSOC_PMX_FUNCTION("usb1_dp_dn", usb1_dp_dngrp, usb1_dp_dn_padmux),
-	SIRFSOC_PMX_FUNCTION("uart1_route_io_usb1",
-		uart1_route_io_usb1grp, uart1_route_io_usb1_padmux),
-	SIRFSOC_PMX_FUNCTION("pulse_count", pulse_countgrp, pulse_count_padmux),
-	SIRFSOC_PMX_FUNCTION("i2s_mclk", i2smclkgrp, i2s_mclk_padmux),
-	SIRFSOC_PMX_FUNCTION("i2s_ext_clk_input", i2s_ext_clk_inputgrp,
-						i2s_ext_clk_input_padmux),
-	SIRFSOC_PMX_FUNCTION("i2s", i2sgrp, i2s_padmux),
-	SIRFSOC_PMX_FUNCTION("i2s_no_din", i2s_no_dingrp, i2s_no_din_padmux),
-	SIRFSOC_PMX_FUNCTION("i2s_6chn", i2s_6chngrp, i2s_6chn_padmux),
-	SIRFSOC_PMX_FUNCTION("ac97", ac97grp, ac97_padmux),
-	SIRFSOC_PMX_FUNCTION("nand", nandgrp, nand_padmux),
-	SIRFSOC_PMX_FUNCTION("spi0", spi0grp, spi0_padmux),
-	SIRFSOC_PMX_FUNCTION("spi1", spi1grp, spi1_padmux),
-	SIRFSOC_PMX_FUNCTION("gps", gpsgrp, gps_padmux),
-};
-
-struct sirfsoc_pinctrl_data atlas6_pinctrl_data = {
-	(struct pinctrl_pin_desc *)sirfsoc_pads,
-	ARRAY_SIZE(sirfsoc_pads),
-	(struct sirfsoc_pin_group *)sirfsoc_pin_groups,
-	ARRAY_SIZE(sirfsoc_pin_groups),
-	(struct sirfsoc_pmx_func *)sirfsoc_pmx_functions,
-	ARRAY_SIZE(sirfsoc_pmx_functions),
-};
-
diff --git a/drivers/pinctrl/sirf/pinctrl-atlas7.c b/drivers/pinctrl/sirf/pinctrl-atlas7.c
deleted file mode 100644
index e54a6e3cafd2..000000000000
--- a/drivers/pinctrl/sirf/pinctrl-atlas7.c
+++ /dev/null
@@ -1,6157 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-/*
- * pinctrl pads, groups, functions for CSR SiRFatlasVII
- *
- * Copyright (c) 2011 - 2014 Cambridge Silicon Radio Limited, a CSR plc group
- * company.
- */
-
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/io.h>
-#include <linux/bitops.h>
-#include <linux/irq.h>
-#include <linux/slab.h>
-#include <linux/clk.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-#include <linux/of_device.h>
-#include <linux/of_platform.h>
-#include <linux/of_irq.h>
-#include <linux/pinctrl/machine.h>
-#include <linux/pinctrl/pinconf.h>
-#include <linux/pinctrl/pinctrl.h>
-#include <linux/pinctrl/pinmux.h>
-#include <linux/pinctrl/consumer.h>
-#include <linux/pinctrl/pinconf-generic.h>
-#include <linux/gpio/driver.h>
-
-/* Definition of Pad&Mux Properties */
-#define N 0
-
-/* The Bank contains input-disable regisgers */
-#define BANK_DS	0
-
-/* Clear Register offset */
-#define CLR_REG(r)	((r) + 0x04)
-
-/* Definition of multiple function select register */
-#define FUNC_CLEAR_MASK		0x7
-#define FUNC_GPIO		0
-#define FUNC_ANALOGUE		0x8
-#define ANA_CLEAR_MASK		0x1
-
-/* The Atlas7's Pad Type List */
-enum altas7_pad_type {
-	PAD_T_4WE_PD = 0,	/* ZIO_PAD3V_4WE_PD */
-	PAD_T_4WE_PU,		/* ZIO_PAD3V_4WE_PD */
-	PAD_T_16ST,		/* ZIO_PAD3V_SDCLK_PD */
-	PAD_T_M31_0204_PD,	/* PRDW0204SDGZ_M311311_PD */
-	PAD_T_M31_0204_PU,	/* PRDW0204SDGZ_M311311_PU */
-	PAD_T_M31_0610_PD,	/* PRUW0610SDGZ_M311311_PD */
-	PAD_T_M31_0610_PU,	/* PRUW0610SDGZ_M311311_PU */
-	PAD_T_AD,		/* PRDWUWHW08SCDG_HZ */
-};
-
-/* Raw value of Driver-Strength Bits */
-#define DS3	BIT(3)
-#define DS2	BIT(2)
-#define DS1	BIT(1)
-#define DS0	BIT(0)
-#define DSZ	0
-
-/* Drive-Strength Intermediate Values */
-#define DS_NULL		-1
-#define DS_1BIT_IM_VAL  DS0
-#define DS_1BIT_MASK	0x1
-#define DS_2BIT_IM_VAL  (DS1 | DS0)
-#define DS_2BIT_MASK	0x3
-#define DS_4BIT_IM_VAL	(DS3 | DS2 | DS1 | DS0)
-#define DS_4BIT_MASK	0xf
-
-/* The Drive-Strength of 4WE Pad		 DS1  0  CO */
-#define DS_4WE_3   (DS1 | DS0)			/* 1  1  3  */
-#define DS_4WE_2   (DS1)			/* 1  0  2  */
-#define DS_4WE_1   (DS0)			/* 0  1  1  */
-#define DS_4WE_0   (DSZ)			/* 0  0  0  */
-
-/* The Drive-Strength of 16st Pad		 DS3  2  1  0  CO */
-#define DS_16ST_15  (DS3 | DS2 | DS1 | DS0)	/* 1  1  1  1  15 */
-#define DS_16ST_14  (DS3 | DS2 | DS0)		/* 1  1  0  1  13 */
-#define DS_16ST_13  (DS3 | DS2 | DS1)		/* 1  1  1  0  14 */
-#define DS_16ST_12  (DS2 | DS1 | DS0)		/* 0  1  1  1  7  */
-#define DS_16ST_11  (DS2 | DS0)			/* 0  1  0  1  5  */
-#define DS_16ST_10  (DS3 | DS1 | DS0)		/* 1  0  1  1  11 */
-#define DS_16ST_9   (DS3 | DS0)			/* 1  0  0  1  9  */
-#define DS_16ST_8   (DS1 | DS0)			/* 0  0  1  1  3  */
-#define DS_16ST_7   (DS2 | DS1)			/* 0  1  1  0  6  */
-#define DS_16ST_6   (DS3 | DS2)			/* 1  1  0  0  12 */
-#define DS_16ST_5   (DS2)			/* 0  1  0  0  4  */
-#define DS_16ST_4   (DS3 | DS1)			/* 1  0  1  0  10 */
-#define DS_16ST_3   (DS1)			/* 0  0  1  0  2  */
-#define DS_16ST_2   (DS0)			/* 0  0  0  1  1  */
-#define DS_16ST_1   (DSZ)			/* 0  0  0  0  0  */
-#define DS_16ST_0   (DS3)			/* 1  0  0  0  8  */
-
-/* The Drive-Strength of M31 Pad		 DS0  CO */
-#define DS_M31_0   (DSZ)			/* 0  0  */
-#define DS_M31_1   (DS0)			/* 1  1  */
-
-/* Raw values of Pull Option Bits */
-#define PUN	BIT(1)
-#define PD	BIT(0)
-#define PE	BIT(0)
-#define PZ	0
-
-/* Definition of Pull Types */
-#define PULL_UP		0
-#define HIGH_HYSTERESIS 1
-#define HIGH_Z		2
-#define PULL_DOWN	3
-#define PULL_DISABLE	4
-#define PULL_ENABLE	5
-#define PULL_UNKNOWN	-1
-
-/* Pull Options for 4WE Pad			  PUN  PD  CO */
-#define P4WE_PULL_MASK		0x3
-#define P4WE_PULL_DOWN		(PUN | PD)	/* 1   1   3  */
-#define P4WE_HIGH_Z		(PUN)		/* 1   0   2  */
-#define P4WE_HIGH_HYSTERESIS	(PD)		/* 0   1   1  */
-#define P4WE_PULL_UP		(PZ)		/* 0   0   0  */
-
-/* Pull Options for 16ST Pad			  PUN  PD  CO */
-#define P16ST_PULL_MASK		0x3
-#define P16ST_PULL_DOWN		(PUN | PD)	/* 1   1   3  */
-#define P16ST_HIGH_Z		(PUN)		/* 1   0   2  */
-#define P16ST_PULL_UP		(PZ)		/* 0   0   0  */
-
-/* Pull Options for M31 Pad			  PE */
-#define PM31_PULL_MASK		0x1
-#define PM31_PULL_ENABLED	(PE)		/* 1 */
-#define PM31_PULL_DISABLED	(PZ)		/* 0 */
-
-/* Pull Options for A/D Pad			  PUN  PD  CO */
-#define PANGD_PULL_MASK		0x3
-#define PANGD_PULL_DOWN		(PUN | PD)	/* 1   1   3  */
-#define PANGD_HIGH_Z		(PUN)		/* 1   0   2  */
-#define PANGD_PULL_UP		(PZ)		/* 0   0   0  */
-
-/* Definition of Input Disable */
-#define DI_MASK		0x1
-#define DI_DISABLE	0x1
-#define DI_ENABLE	0x0
-
-/* Definition of Input Disable Value */
-#define DIV_MASK	0x1
-#define DIV_DISABLE	0x1
-#define DIV_ENABLE	0x0
-
-/* Number of Function input disable registers */
-#define NUM_OF_IN_DISABLE_REG	0x2
-
-/* Offset of Function input disable registers */
-#define IN_DISABLE_0_REG_SET		0x0A00
-#define IN_DISABLE_0_REG_CLR		0x0A04
-#define IN_DISABLE_1_REG_SET		0x0A08
-#define IN_DISABLE_1_REG_CLR		0x0A0C
-#define IN_DISABLE_VAL_0_REG_SET	0x0A80
-#define IN_DISABLE_VAL_0_REG_CLR	0x0A84
-#define IN_DISABLE_VAL_1_REG_SET	0x0A88
-#define IN_DISABLE_VAL_1_REG_CLR	0x0A8C
-
-/* Offset of the SDIO9SEL*/
-#define SYS2PCI_SDIO9SEL 0x14
-
-struct dt_params {
-	const char *property;
-	int value;
-};
-
-/**
- * struct atlas7_pad_conf - Atlas7 Pad Configuration
- * @id:			The ID of this Pad.
- * @type:		The type of this Pad.
- * @mux_reg:		The mux register offset.
- *			This register contains the mux.
- * @pupd_reg:		The pull-up/down register offset.
- * @drvstr_reg:		The drive-strength register offset.
- * @ad_ctrl_reg:	The Analogue/Digital Control register.
- *
- * @mux_bit:		The start bit of mux register.
- * @pupd_bit:		The start bit of pull-up/down register.
- * @drvstr_bit:		The start bit of drive-strength register.
- * @ad_ctrl_bit:	The start bit of analogue/digital register.
- */
-struct atlas7_pad_config {
-	const u32 id;
-	u32 type;
-	u32 mux_reg;
-	u32 pupd_reg;
-	u32 drvstr_reg;
-	u32 ad_ctrl_reg;
-	/* bits in register */
-	u8 mux_bit;
-	u8 pupd_bit;
-	u8 drvstr_bit;
-	u8 ad_ctrl_bit;
-};
-
-#define PADCONF(pad, t, mr, pr, dsr, adr, mb, pb, dsb, adb)	\
-	{							\
-		.id = pad,					\
-		.type = t,					\
-		.mux_reg = mr,					\
-		.pupd_reg = pr,					\
-		.drvstr_reg = dsr,				\
-		.ad_ctrl_reg = adr,				\
-		.mux_bit = mb,					\
-		.pupd_bit = pb,					\
-		.drvstr_bit = dsb,				\
-		.ad_ctrl_bit = adb,				\
-	}
-
-/*
- * struct atlas7_pad_status - Atlas7 Pad status
- */
-struct atlas7_pad_status {
-	u8 func;
-	u8 pull;
-	u8 dstr;
-	u8 reserved;
-};
-
-/**
- * struct atlas7_pad_mux - Atlas7 mux
- * @bank:		The bank of this pad's registers on.
- * @pin	:		The ID of this Pad.
- * @func:		The mux func on this Pad.
- * @dinput_reg:		The Input-Disable register offset.
- * @dinput_bit:		The start bit of Input-Disable register.
- * @dinput_val_reg:	The Input-Disable-value register offset.
- *			This register is used to set the value of this pad
- *			if this pad was disabled.
- * @dinput_val_bit:	The start bit of Input-Disable Value register.
- */
-struct atlas7_pad_mux {
-	u32 bank;
-	u32 pin;
-	u32 func;
-	u32 dinput_reg;
-	u32 dinput_bit;
-	u32 dinput_val_reg;
-	u32 dinput_val_bit;
-};
-
-#define MUX(b, pad, f, dr, db, dvr, dvb)	\
-	{					\
-		.bank = b,			\
-		.pin = pad,			\
-		.func = f,			\
-		.dinput_reg = dr,		\
-		.dinput_bit = db,		\
-		.dinput_val_reg = dvr,		\
-		.dinput_val_bit = dvb,		\
-	}
-
-struct atlas7_grp_mux {
-	unsigned int group;
-	unsigned int pad_mux_count;
-	const struct atlas7_pad_mux *pad_mux_list;
-};
-
- /**
- * struct sirfsoc_pin_group - describes a SiRFprimaII pin group
- * @name: the name of this specific pin group
- * @pins: an array of discrete physical pins used in this group, taken
- *	from the driver-local pin enumeration space
- * @num_pins: the number of pins in this group array, i.e. the number of
- *	elements in .pins so we can iterate over that array
- */
-struct atlas7_pin_group {
-	const char *name;
-	const unsigned int *pins;
-	const unsigned num_pins;
-};
-
-#define GROUP(n, p)  \
-	{			\
-		.name = n,	\
-		.pins = p,	\
-		.num_pins = ARRAY_SIZE(p),	\
-	}
-
-struct atlas7_pmx_func {
-	const char *name;
-	const char * const *groups;
-	const unsigned num_groups;
-	const struct atlas7_grp_mux *grpmux;
-};
-
-#define FUNCTION(n, g, m)		\
-	{					\
-		.name = n,			\
-		.groups = g,			\
-		.num_groups = ARRAY_SIZE(g),	\
-		.grpmux = m,			\
-	}
-
-struct atlas7_pinctrl_data {
-	struct pinctrl_pin_desc *pads;
-	int pads_cnt;
-	struct atlas7_pin_group *grps;
-	int grps_cnt;
-	struct atlas7_pmx_func *funcs;
-	int funcs_cnt;
-	struct atlas7_pad_config *confs;
-	int confs_cnt;
-};
-
-/* Platform info of atlas7 pinctrl */
-#define ATLAS7_PINCTRL_REG_BANKS	2
-#define ATLAS7_PINCTRL_BANK_0_PINS	18
-#define ATLAS7_PINCTRL_BANK_1_PINS	141
-#define ATLAS7_PINCTRL_TOTAL_PINS	\
-	(ATLAS7_PINCTRL_BANK_0_PINS + ATLAS7_PINCTRL_BANK_1_PINS)
-
-/**
- * Atlas7 GPIO Chip
- */
-
-#define NGPIO_OF_BANK		32
-#define GPIO_TO_BANK(gpio)	((gpio) / NGPIO_OF_BANK)
-
-/* Registers of GPIO Controllers */
-#define ATLAS7_GPIO_BASE(g, b)		((g)->reg + 0x100 * (b))
-#define ATLAS7_GPIO_CTRL(b, i)		((b)->base + 4 * (i))
-#define ATLAS7_GPIO_INT_STATUS(b)	((b)->base + 0x8C)
-
-/* Definition bits of GPIO Control Registers */
-#define ATLAS7_GPIO_CTL_INTR_LOW_MASK		BIT(0)
-#define ATLAS7_GPIO_CTL_INTR_HIGH_MASK		BIT(1)
-#define ATLAS7_GPIO_CTL_INTR_TYPE_MASK		BIT(2)
-#define ATLAS7_GPIO_CTL_INTR_EN_MASK		BIT(3)
-#define ATLAS7_GPIO_CTL_INTR_STATUS_MASK	BIT(4)
-#define ATLAS7_GPIO_CTL_OUT_EN_MASK		BIT(5)
-#define ATLAS7_GPIO_CTL_DATAOUT_MASK		BIT(6)
-#define ATLAS7_GPIO_CTL_DATAIN_MASK		BIT(7)
-
-struct atlas7_gpio_bank {
-	int id;
-	int irq;
-	void __iomem *base;
-	unsigned int gpio_offset;
-	unsigned int ngpio;
-	const unsigned int *gpio_pins;
-	u32 sleep_data[NGPIO_OF_BANK];
-};
-
-struct atlas7_gpio_chip {
-	const char *name;
-	void __iomem *reg;
-	struct clk *clk;
-	int nbank;
-	raw_spinlock_t lock;
-	struct gpio_chip chip;
-	struct atlas7_gpio_bank banks[];
-};
-
-struct atlas7_pmx {
-	struct device *dev;
-	struct pinctrl_dev *pctl;
-	struct pinctrl_desc pctl_desc;
-	struct atlas7_pinctrl_data *pctl_data;
-	void __iomem *regs[ATLAS7_PINCTRL_REG_BANKS];
-	void __iomem *sys2pci_base;
-	u32 status_ds[NUM_OF_IN_DISABLE_REG];
-	u32 status_dsv[NUM_OF_IN_DISABLE_REG];
-	struct atlas7_pad_status sleep_data[ATLAS7_PINCTRL_TOTAL_PINS];
-};
-
-/*
- * Pad list for the pinmux subsystem
- * refer to A7DA IO Summary - CS-314158-DD-4E.xls
- */
-
-/* Pads in IOC RTC & TOP */
-static const struct pinctrl_pin_desc atlas7_ioc_pads[] = {
-	/* RTC PADs */
-	PINCTRL_PIN(0, "rtc_gpio_0"),
-	PINCTRL_PIN(1, "rtc_gpio_1"),
-	PINCTRL_PIN(2, "rtc_gpio_2"),
-	PINCTRL_PIN(3, "rtc_gpio_3"),
-	PINCTRL_PIN(4, "low_bat_ind_b"),
-	PINCTRL_PIN(5, "on_key_b"),
-	PINCTRL_PIN(6, "ext_on"),
-	PINCTRL_PIN(7, "mem_on"),
-	PINCTRL_PIN(8, "core_on"),
-	PINCTRL_PIN(9, "io_on"),
-	PINCTRL_PIN(10, "can0_tx"),
-	PINCTRL_PIN(11, "can0_rx"),
-	PINCTRL_PIN(12, "spi0_clk"),
-	PINCTRL_PIN(13, "spi0_cs_b"),
-	PINCTRL_PIN(14, "spi0_io_0"),
-	PINCTRL_PIN(15, "spi0_io_1"),
-	PINCTRL_PIN(16, "spi0_io_2"),
-	PINCTRL_PIN(17, "spi0_io_3"),
-
-	/* TOP PADs */
-	PINCTRL_PIN(18, "spi1_en"),
-	PINCTRL_PIN(19, "spi1_clk"),
-	PINCTRL_PIN(20, "spi1_din"),
-	PINCTRL_PIN(21, "spi1_dout"),
-	PINCTRL_PIN(22, "trg_spi_clk"),
-	PINCTRL_PIN(23, "trg_spi_di"),
-	PINCTRL_PIN(24, "trg_spi_do"),
-	PINCTRL_PIN(25, "trg_spi_cs_b"),
-	PINCTRL_PIN(26, "trg_acq_d1"),
-	PINCTRL_PIN(27, "trg_irq_b"),
-	PINCTRL_PIN(28, "trg_acq_d0"),
-	PINCTRL_PIN(29, "trg_acq_clk"),
-	PINCTRL_PIN(30, "trg_shutdown_b_out"),
-	PINCTRL_PIN(31, "sdio2_clk"),
-	PINCTRL_PIN(32, "sdio2_cmd"),
-	PINCTRL_PIN(33, "sdio2_dat_0"),
-	PINCTRL_PIN(34, "sdio2_dat_1"),
-	PINCTRL_PIN(35, "sdio2_dat_2"),
-	PINCTRL_PIN(36, "sdio2_dat_3"),
-	PINCTRL_PIN(37, "df_ad_7"),
-	PINCTRL_PIN(38, "df_ad_6"),
-	PINCTRL_PIN(39, "df_ad_5"),
-	PINCTRL_PIN(40, "df_ad_4"),
-	PINCTRL_PIN(41, "df_ad_3"),
-	PINCTRL_PIN(42, "df_ad_2"),
-	PINCTRL_PIN(43, "df_ad_1"),
-	PINCTRL_PIN(44, "df_ad_0"),
-	PINCTRL_PIN(45, "df_dqs"),
-	PINCTRL_PIN(46, "df_cle"),
-	PINCTRL_PIN(47, "df_ale"),
-	PINCTRL_PIN(48, "df_we_b"),
-	PINCTRL_PIN(49, "df_re_b"),
-	PINCTRL_PIN(50, "df_ry_by"),
-	PINCTRL_PIN(51, "df_cs_b_1"),
-	PINCTRL_PIN(52, "df_cs_b_0"),
-	PINCTRL_PIN(53, "l_pclk"),
-	PINCTRL_PIN(54, "l_lck"),
-	PINCTRL_PIN(55, "l_fck"),
-	PINCTRL_PIN(56, "l_de"),
-	PINCTRL_PIN(57, "ldd_0"),
-	PINCTRL_PIN(58, "ldd_1"),
-	PINCTRL_PIN(59, "ldd_2"),
-	PINCTRL_PIN(60, "ldd_3"),
-	PINCTRL_PIN(61, "ldd_4"),
-	PINCTRL_PIN(62, "ldd_5"),
-	PINCTRL_PIN(63, "ldd_6"),
-	PINCTRL_PIN(64, "ldd_7"),
-	PINCTRL_PIN(65, "ldd_8"),
-	PINCTRL_PIN(66, "ldd_9"),
-	PINCTRL_PIN(67, "ldd_10"),
-	PINCTRL_PIN(68, "ldd_11"),
-	PINCTRL_PIN(69, "ldd_12"),
-	PINCTRL_PIN(70, "ldd_13"),
-	PINCTRL_PIN(71, "ldd_14"),
-	PINCTRL_PIN(72, "ldd_15"),
-	PINCTRL_PIN(73, "lcd_gpio_20"),
-	PINCTRL_PIN(74, "vip_0"),
-	PINCTRL_PIN(75, "vip_1"),
-	PINCTRL_PIN(76, "vip_2"),
-	PINCTRL_PIN(77, "vip_3"),
-	PINCTRL_PIN(78, "vip_4"),
-	PINCTRL_PIN(79, "vip_5"),
-	PINCTRL_PIN(80, "vip_6"),
-	PINCTRL_PIN(81, "vip_7"),
-	PINCTRL_PIN(82, "vip_pxclk"),
-	PINCTRL_PIN(83, "vip_hsync"),
-	PINCTRL_PIN(84, "vip_vsync"),
-	PINCTRL_PIN(85, "sdio3_clk"),
-	PINCTRL_PIN(86, "sdio3_cmd"),
-	PINCTRL_PIN(87, "sdio3_dat_0"),
-	PINCTRL_PIN(88, "sdio3_dat_1"),
-	PINCTRL_PIN(89, "sdio3_dat_2"),
-	PINCTRL_PIN(90, "sdio3_dat_3"),
-	PINCTRL_PIN(91, "sdio5_clk"),
-	PINCTRL_PIN(92, "sdio5_cmd"),
-	PINCTRL_PIN(93, "sdio5_dat_0"),
-	PINCTRL_PIN(94, "sdio5_dat_1"),
-	PINCTRL_PIN(95, "sdio5_dat_2"),
-	PINCTRL_PIN(96, "sdio5_dat_3"),
-	PINCTRL_PIN(97, "rgmii_txd_0"),
-	PINCTRL_PIN(98, "rgmii_txd_1"),
-	PINCTRL_PIN(99, "rgmii_txd_2"),
-	PINCTRL_PIN(100, "rgmii_txd_3"),
-	PINCTRL_PIN(101, "rgmii_txclk"),
-	PINCTRL_PIN(102, "rgmii_tx_ctl"),
-	PINCTRL_PIN(103, "rgmii_rxd_0"),
-	PINCTRL_PIN(104, "rgmii_rxd_1"),
-	PINCTRL_PIN(105, "rgmii_rxd_2"),
-	PINCTRL_PIN(106, "rgmii_rxd_3"),
-	PINCTRL_PIN(107, "rgmii_rx_clk"),
-	PINCTRL_PIN(108, "rgmii_rxc_ctl"),
-	PINCTRL_PIN(109, "rgmii_mdio"),
-	PINCTRL_PIN(110, "rgmii_mdc"),
-	PINCTRL_PIN(111, "rgmii_intr_n"),
-	PINCTRL_PIN(112, "i2s_mclk"),
-	PINCTRL_PIN(113, "i2s_bclk"),
-	PINCTRL_PIN(114, "i2s_ws"),
-	PINCTRL_PIN(115, "i2s_dout0"),
-	PINCTRL_PIN(116, "i2s_dout1"),
-	PINCTRL_PIN(117, "i2s_dout2"),
-	PINCTRL_PIN(118, "i2s_din"),
-	PINCTRL_PIN(119, "gpio_0"),
-	PINCTRL_PIN(120, "gpio_1"),
-	PINCTRL_PIN(121, "gpio_2"),
-	PINCTRL_PIN(122, "gpio_3"),
-	PINCTRL_PIN(123, "gpio_4"),
-	PINCTRL_PIN(124, "gpio_5"),
-	PINCTRL_PIN(125, "gpio_6"),
-	PINCTRL_PIN(126, "gpio_7"),
-	PINCTRL_PIN(127, "sda_0"),
-	PINCTRL_PIN(128, "scl_0"),
-	PINCTRL_PIN(129, "coex_pio_0"),
-	PINCTRL_PIN(130, "coex_pio_1"),
-	PINCTRL_PIN(131, "coex_pio_2"),
-	PINCTRL_PIN(132, "coex_pio_3"),
-	PINCTRL_PIN(133, "uart0_tx"),
-	PINCTRL_PIN(134, "uart0_rx"),
-	PINCTRL_PIN(135, "uart1_tx"),
-	PINCTRL_PIN(136, "uart1_rx"),
-	PINCTRL_PIN(137, "uart3_tx"),
-	PINCTRL_PIN(138, "uart3_rx"),
-	PINCTRL_PIN(139, "uart4_tx"),
-	PINCTRL_PIN(140, "uart4_rx"),
-	PINCTRL_PIN(141, "usp0_clk"),
-	PINCTRL_PIN(142, "usp0_tx"),
-	PINCTRL_PIN(143, "usp0_rx"),
-	PINCTRL_PIN(144, "usp0_fs"),
-	PINCTRL_PIN(145, "usp1_clk"),
-	PINCTRL_PIN(146, "usp1_tx"),
-	PINCTRL_PIN(147, "usp1_rx"),
-	PINCTRL_PIN(148, "usp1_fs"),
-	PINCTRL_PIN(149, "lvds_tx0d4p"),
-	PINCTRL_PIN(150, "lvds_tx0d4n"),
-	PINCTRL_PIN(151, "lvds_tx0d3p"),
-	PINCTRL_PIN(152, "lvds_tx0d3n"),
-	PINCTRL_PIN(153, "lvds_tx0d2p"),
-	PINCTRL_PIN(154, "lvds_tx0d2n"),
-	PINCTRL_PIN(155, "lvds_tx0d1p"),
-	PINCTRL_PIN(156, "lvds_tx0d1n"),
-	PINCTRL_PIN(157, "lvds_tx0d0p"),
-	PINCTRL_PIN(158, "lvds_tx0d0n"),
-	PINCTRL_PIN(159, "jtag_tdo"),
-	PINCTRL_PIN(160, "jtag_tms"),
-	PINCTRL_PIN(161, "jtag_tck"),
-	PINCTRL_PIN(162, "jtag_tdi"),
-	PINCTRL_PIN(163, "jtag_trstn"),
-};
-
-static struct atlas7_pad_config atlas7_ioc_pad_confs[] = {
-	/* The Configuration of IOC_RTC Pads */
-	PADCONF(0, 3, 0x0, 0x100, 0x200, -1, 0, 0, 0, 0),
-	PADCONF(1, 3, 0x0, 0x100, 0x200, -1, 4, 2, 2, 0),
-	PADCONF(2, 3, 0x0, 0x100, 0x200, -1, 8, 4, 4, 0),
-	PADCONF(3, 5, 0x0, 0x100, 0x200, -1, 12, 6, 6, 0),
-	PADCONF(4, 4, 0x0, 0x100, 0x200, -1, 16, 8, 8, 0),
-	PADCONF(5, 4, 0x0, 0x100, 0x200, -1, 20, 10, 10, 0),
-	PADCONF(6, 3, 0x0, 0x100, 0x200, -1, 24, 12, 12, 0),
-	PADCONF(7, 3, 0x0, 0x100, 0x200, -1, 28, 14, 14, 0),
-	PADCONF(8, 3, 0x8, 0x100, 0x200, -1, 0, 16, 16, 0),
-	PADCONF(9, 3, 0x8, 0x100, 0x200, -1, 4, 18, 18, 0),
-	PADCONF(10, 4, 0x8, 0x100, 0x200, -1, 8, 20, 20, 0),
-	PADCONF(11, 4, 0x8, 0x100, 0x200, -1, 12, 22, 22, 0),
-	PADCONF(12, 5, 0x8, 0x100, 0x200, -1, 16, 24, 24, 0),
-	PADCONF(13, 6, 0x8, 0x100, 0x200, -1, 20, 26, 26, 0),
-	PADCONF(14, 5, 0x8, 0x100, 0x200, -1, 24, 28, 28, 0),
-	PADCONF(15, 5, 0x8, 0x100, 0x200, -1, 28, 30, 30, 0),
-	PADCONF(16, 5, 0x10, 0x108, 0x208, -1, 0, 0, 0, 0),
-	PADCONF(17, 5, 0x10, 0x108, 0x208, -1, 4, 2, 2, 0),
-	/* The Configuration of IOC_TOP Pads */
-	PADCONF(18, 5, 0x80, 0x180, 0x300, -1, 0, 0, 0, 0),
-	PADCONF(19, 5, 0x80, 0x180, 0x300, -1, 4, 2, 2, 0),
-	PADCONF(20, 5, 0x80, 0x180, 0x300, -1, 8, 4, 4, 0),
-	PADCONF(21, 5, 0x80, 0x180, 0x300, -1, 12, 6, 6, 0),
-	PADCONF(22, 5, 0x88, 0x188, 0x308, -1, 0, 0, 0, 0),
-	PADCONF(23, 5, 0x88, 0x188, 0x308, -1, 4, 2, 2, 0),
-	PADCONF(24, 5, 0x88, 0x188, 0x308, -1, 8, 4, 4, 0),
-	PADCONF(25, 6, 0x88, 0x188, 0x308, -1, 12, 6, 6, 0),
-	PADCONF(26, 5, 0x88, 0x188, 0x308, -1, 16, 8, 8, 0),
-	PADCONF(27, 6, 0x88, 0x188, 0x308, -1, 20, 10, 10, 0),
-	PADCONF(28, 5, 0x88, 0x188, 0x308, -1, 24, 12, 12, 0),
-	PADCONF(29, 5, 0x88, 0x188, 0x308, -1, 28, 14, 14, 0),
-	PADCONF(30, 5, 0x90, 0x188, 0x308, -1, 0, 16, 16, 0),
-	PADCONF(31, 2, 0x98, 0x190, 0x310, -1, 0, 0, 0, 0),
-	PADCONF(32, 1, 0x98, 0x190, 0x310, -1, 4, 2, 4, 0),
-	PADCONF(33, 1, 0x98, 0x190, 0x310, -1, 8, 4, 6, 0),
-	PADCONF(34, 1, 0x98, 0x190, 0x310, -1, 12, 6, 8, 0),
-	PADCONF(35, 1, 0x98, 0x190, 0x310, -1, 16, 8, 10, 0),
-	PADCONF(36, 1, 0x98, 0x190, 0x310, -1, 20, 10, 12, 0),
-	PADCONF(37, 1, 0xa0, 0x198, 0x318, -1, 0, 0, 0, 0),
-	PADCONF(38, 1, 0xa0, 0x198, 0x318, -1, 4, 2, 2, 0),
-	PADCONF(39, 1, 0xa0, 0x198, 0x318, -1, 8, 4, 4, 0),
-	PADCONF(40, 1, 0xa0, 0x198, 0x318, -1, 12, 6, 6, 0),
-	PADCONF(41, 1, 0xa0, 0x198, 0x318, -1, 16, 8, 8, 0),
-	PADCONF(42, 1, 0xa0, 0x198, 0x318, -1, 20, 10, 10, 0),
-	PADCONF(43, 1, 0xa0, 0x198, 0x318, -1, 24, 12, 12, 0),
-	PADCONF(44, 1, 0xa0, 0x198, 0x318, -1, 28, 14, 14, 0),
-	PADCONF(45, 0, 0xa8, 0x198, 0x318, -1, 0, 16, 16, 0),
-	PADCONF(46, 0, 0xa8, 0x198, 0x318, -1, 4, 18, 18, 0),
-	PADCONF(47, 1, 0xa8, 0x198, 0x318, -1, 8, 20, 20, 0),
-	PADCONF(48, 1, 0xa8, 0x198, 0x318, -1, 12, 22, 22, 0),
-	PADCONF(49, 1, 0xa8, 0x198, 0x318, -1, 16, 24, 24, 0),
-	PADCONF(50, 1, 0xa8, 0x198, 0x318, -1, 20, 26, 26, 0),
-	PADCONF(51, 1, 0xa8, 0x198, 0x318, -1, 24, 28, 28, 0),
-	PADCONF(52, 1, 0xa8, 0x198, 0x318, -1, 28, 30, 30, 0),
-	PADCONF(53, 0, 0xb0, 0x1a0, 0x320, -1, 0, 0, 0, 0),
-	PADCONF(54, 0, 0xb0, 0x1a0, 0x320, -1, 4, 2, 2, 0),
-	PADCONF(55, 0, 0xb0, 0x1a0, 0x320, -1, 8, 4, 4, 0),
-	PADCONF(56, 0, 0xb0, 0x1a0, 0x320, -1, 12, 6, 6, 0),
-	PADCONF(57, 0, 0xb0, 0x1a0, 0x320, -1, 16, 8, 8, 0),
-	PADCONF(58, 0, 0xb0, 0x1a0, 0x320, -1, 20, 10, 10, 0),
-	PADCONF(59, 0, 0xb0, 0x1a0, 0x320, -1, 24, 12, 12, 0),
-	PADCONF(60, 0, 0xb0, 0x1a0, 0x320, -1, 28, 14, 14, 0),
-	PADCONF(61, 0, 0xb8, 0x1a0, 0x320, -1, 0, 16, 16, 0),
-	PADCONF(62, 0, 0xb8, 0x1a0, 0x320, -1, 4, 18, 18, 0),
-	PADCONF(63, 0, 0xb8, 0x1a0, 0x320, -1, 8, 20, 20, 0),
-	PADCONF(64, 0, 0xb8, 0x1a0, 0x320, -1, 12, 22, 22, 0),
-	PADCONF(65, 0, 0xb8, 0x1a0, 0x320, -1, 16, 24, 24, 0),
-	PADCONF(66, 0, 0xb8, 0x1a0, 0x320, -1, 20, 26, 26, 0),
-	PADCONF(67, 0, 0xb8, 0x1a0, 0x320, -1, 24, 28, 28, 0),
-	PADCONF(68, 0, 0xb8, 0x1a0, 0x320, -1, 28, 30, 30, 0),
-	PADCONF(69, 0, 0xc0, 0x1a8, 0x328, -1, 0, 0, 0, 0),
-	PADCONF(70, 0, 0xc0, 0x1a8, 0x328, -1, 4, 2, 2, 0),
-	PADCONF(71, 0, 0xc0, 0x1a8, 0x328, -1, 8, 4, 4, 0),
-	PADCONF(72, 0, 0xc0, 0x1a8, 0x328, -1, 12, 6, 6, 0),
-	PADCONF(73, 0, 0xc0, 0x1a8, 0x328, -1, 16, 8, 8, 0),
-	PADCONF(74, 0, 0xc8, 0x1b0, 0x330, -1, 0, 0, 0, 0),
-	PADCONF(75, 0, 0xc8, 0x1b0, 0x330, -1, 4, 2, 2, 0),
-	PADCONF(76, 0, 0xc8, 0x1b0, 0x330, -1, 8, 4, 4, 0),
-	PADCONF(77, 0, 0xc8, 0x1b0, 0x330, -1, 12, 6, 6, 0),
-	PADCONF(78, 0, 0xc8, 0x1b0, 0x330, -1, 16, 8, 8, 0),
-	PADCONF(79, 0, 0xc8, 0x1b0, 0x330, -1, 20, 10, 10, 0),
-	PADCONF(80, 0, 0xc8, 0x1b0, 0x330, -1, 24, 12, 12, 0),
-	PADCONF(81, 0, 0xc8, 0x1b0, 0x330, -1, 28, 14, 14, 0),
-	PADCONF(82, 0, 0xd0, 0x1b0, 0x330, -1, 0, 16, 16, 0),
-	PADCONF(83, 0, 0xd0, 0x1b0, 0x330, -1, 4, 18, 18, 0),
-	PADCONF(84, 0, 0xd0, 0x1b0, 0x330, -1, 8, 20, 20, 0),
-	PADCONF(85, 2, 0xd8, 0x1b8, 0x338, -1, 0, 0, 0, 0),
-	PADCONF(86, 1, 0xd8, 0x1b8, 0x338, -1, 4, 4, 4, 0),
-	PADCONF(87, 1, 0xd8, 0x1b8, 0x338, -1, 8, 6, 6, 0),
-	PADCONF(88, 1, 0xd8, 0x1b8, 0x338, -1, 12, 8, 8, 0),
-	PADCONF(89, 1, 0xd8, 0x1b8, 0x338, -1, 16, 10, 10, 0),
-	PADCONF(90, 1, 0xd8, 0x1b8, 0x338, -1, 20, 12, 12, 0),
-	PADCONF(91, 2, 0xe0, 0x1c0, 0x340, -1, 0, 0, 0, 0),
-	PADCONF(92, 1, 0xe0, 0x1c0, 0x340, -1, 4, 4, 4, 0),
-	PADCONF(93, 1, 0xe0, 0x1c0, 0x340, -1, 8, 6, 6, 0),
-	PADCONF(94, 1, 0xe0, 0x1c0, 0x340, -1, 12, 8, 8, 0),
-	PADCONF(95, 1, 0xe0, 0x1c0, 0x340, -1, 16, 10, 10, 0),
-	PADCONF(96, 1, 0xe0, 0x1c0, 0x340, -1, 20, 12, 12, 0),
-	PADCONF(97, 0, 0xe8, 0x1c8, 0x348, -1, 0, 0, 0, 0),
-	PADCONF(98, 0, 0xe8, 0x1c8, 0x348, -1, 4, 2, 2, 0),
-	PADCONF(99, 0, 0xe8, 0x1c8, 0x348, -1, 8, 4, 4, 0),
-	PADCONF(100, 0, 0xe8, 0x1c8, 0x348, -1, 12, 6, 6, 0),
-	PADCONF(101, 2, 0xe8, 0x1c8, 0x348, -1, 16, 8, 8, 0),
-	PADCONF(102, 0, 0xe8, 0x1c8, 0x348, -1, 20, 12, 12, 0),
-	PADCONF(103, 0, 0xe8, 0x1c8, 0x348, -1, 24, 14, 14, 0),
-	PADCONF(104, 0, 0xe8, 0x1c8, 0x348, -1, 28, 16, 16, 0),
-	PADCONF(105, 0, 0xf0, 0x1c8, 0x348, -1, 0, 18, 18, 0),
-	PADCONF(106, 0, 0xf0, 0x1c8, 0x348, -1, 4, 20, 20, 0),
-	PADCONF(107, 0, 0xf0, 0x1c8, 0x348, -1, 8, 22, 22, 0),
-	PADCONF(108, 0, 0xf0, 0x1c8, 0x348, -1, 12, 24, 24, 0),
-	PADCONF(109, 1, 0xf0, 0x1c8, 0x348, -1, 16, 26, 26, 0),
-	PADCONF(110, 0, 0xf0, 0x1c8, 0x348, -1, 20, 28, 28, 0),
-	PADCONF(111, 1, 0xf0, 0x1c8, 0x348, -1, 24, 30, 30, 0),
-	PADCONF(112, 5, 0xf8, 0x200, 0x350, -1, 0, 0, 0, 0),
-	PADCONF(113, 5, 0xf8, 0x200, 0x350, -1, 4, 2, 2, 0),
-	PADCONF(114, 5, 0xf8, 0x200, 0x350, -1, 8, 4, 4, 0),
-	PADCONF(115, 5, 0xf8, 0x200, 0x350, -1, 12, 6, 6, 0),
-	PADCONF(116, 5, 0xf8, 0x200, 0x350, -1, 16, 8, 8, 0),
-	PADCONF(117, 5, 0xf8, 0x200, 0x350, -1, 20, 10, 10, 0),
-	PADCONF(118, 5, 0xf8, 0x200, 0x350, -1, 24, 12, 12, 0),
-	PADCONF(119, 5, 0x100, 0x250, 0x358, -1, 0, 0, 0, 0),
-	PADCONF(120, 5, 0x100, 0x250, 0x358, -1, 4, 2, 2, 0),
-	PADCONF(121, 5, 0x100, 0x250, 0x358, -1, 8, 4, 4, 0),
-	PADCONF(122, 5, 0x100, 0x250, 0x358, -1, 12, 6, 6, 0),
-	PADCONF(123, 6, 0x100, 0x250, 0x358, -1, 16, 8, 8, 0),
-	PADCONF(124, 6, 0x100, 0x250, 0x358, -1, 20, 10, 10, 0),
-	PADCONF(125, 6, 0x100, 0x250, 0x358, -1, 24, 12, 12, 0),
-	PADCONF(126, 6, 0x100, 0x250, 0x358, -1, 28, 14, 14, 0),
-	PADCONF(127, 6, 0x108, 0x250, 0x358, -1, 16, 24, 24, 0),
-	PADCONF(128, 6, 0x108, 0x250, 0x358, -1, 20, 26, 26, 0),
-	PADCONF(129, 0, 0x110, 0x258, 0x360, -1, 0, 0, 0, 0),
-	PADCONF(130, 0, 0x110, 0x258, 0x360, -1, 4, 2, 2, 0),
-	PADCONF(131, 0, 0x110, 0x258, 0x360, -1, 8, 4, 4, 0),
-	PADCONF(132, 0, 0x110, 0x258, 0x360, -1, 12, 6, 6, 0),
-	PADCONF(133, 6, 0x118, 0x260, 0x368, -1, 0, 0, 0, 0),
-	PADCONF(134, 6, 0x118, 0x260, 0x368, -1, 4, 2, 2, 0),
-	PADCONF(135, 6, 0x118, 0x260, 0x368, -1, 16, 8, 8, 0),
-	PADCONF(136, 6, 0x118, 0x260, 0x368, -1, 20, 10, 10, 0),
-	PADCONF(137, 6, 0x118, 0x260, 0x368, -1, 24, 12, 12, 0),
-	PADCONF(138, 6, 0x118, 0x260, 0x368, -1, 28, 14, 14, 0),
-	PADCONF(139, 6, 0x120, 0x260, 0x368, -1, 0, 16, 16, 0),
-	PADCONF(140, 6, 0x120, 0x260, 0x368, -1, 4, 18, 18, 0),
-	PADCONF(141, 5, 0x128, 0x268, 0x378, -1, 0, 0, 0, 0),
-	PADCONF(142, 5, 0x128, 0x268, 0x378, -1, 4, 2, 2, 0),
-	PADCONF(143, 5, 0x128, 0x268, 0x378, -1, 8, 4, 4, 0),
-	PADCONF(144, 5, 0x128, 0x268, 0x378, -1, 12, 6, 6, 0),
-	PADCONF(145, 5, 0x128, 0x268, 0x378, -1, 16, 8, 8, 0),
-	PADCONF(146, 5, 0x128, 0x268, 0x378, -1, 20, 10, 10, 0),
-	PADCONF(147, 5, 0x128, 0x268, 0x378, -1, 24, 12, 12, 0),
-	PADCONF(148, 5, 0x128, 0x268, 0x378, -1, 28, 14, 14, 0),
-	PADCONF(149, 7, 0x130, 0x270, -1, 0x480, 0, 0, 0, 0),
-	PADCONF(150, 7, 0x130, 0x270, -1, 0x480, 4, 2, 0, 1),
-	PADCONF(151, 7, 0x130, 0x270, -1, 0x480, 8, 4, 0, 2),
-	PADCONF(152, 7, 0x130, 0x270, -1, 0x480, 12, 6, 0, 3),
-	PADCONF(153, 7, 0x130, 0x270, -1, 0x480, 16, 8, 0, 4),
-	PADCONF(154, 7, 0x130, 0x270, -1, 0x480, 20, 10, 0, 5),
-	PADCONF(155, 7, 0x130, 0x270, -1, 0x480, 24, 12, 0, 6),
-	PADCONF(156, 7, 0x130, 0x270, -1, 0x480, 28, 14, 0, 7),
-	PADCONF(157, 7, 0x138, 0x278, -1, 0x480, 0, 0, 0, 8),
-	PADCONF(158, 7, 0x138, 0x278, -1, 0x480, 4, 2, 0, 9),
-	PADCONF(159, 5, 0x140, 0x280, 0x380, -1, 0, 0, 0, 0),
-	PADCONF(160, 6, 0x140, 0x280, 0x380, -1, 4, 2, 2, 0),
-	PADCONF(161, 5, 0x140, 0x280, 0x380, -1, 8, 4, 4, 0),
-	PADCONF(162, 6, 0x140, 0x280, 0x380, -1, 12, 6, 6, 0),
-	PADCONF(163, 6, 0x140, 0x280, 0x380, -1, 16, 8, 8, 0),
-};
-
-/* pin list of each pin group */
-static const unsigned int gnss_gpio_pins[] = { 119, 120, 121, 122, 123, 124,
-		125, 126, 127, 128, 22, 23, 24, 25, 26, 27, 28, 29, 30, };
-static const unsigned int lcd_vip_gpio_pins[] = { 74, 75, 76, 77, 78, 79, 80,
-		81, 82, 83, 84, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63,
-		64, 65, 66, 67, 68, 69, 70, 71, 72, 73, };
-static const unsigned int sdio_i2s_gpio_pins[] = { 31, 32, 33, 34, 35, 36,
-		85, 86, 87, 88, 89, 90, 129, 130, 131, 132, 91, 92, 93, 94,
-		95, 96, 112, 113, 114, 115, 116, 117, 118, };
-static const unsigned int sp_rgmii_gpio_pins[] = { 97, 98, 99, 100, 101, 102,
-		103, 104, 105, 106, 107, 108, 109, 110, 111, 18, 19, 20, 21,
-		141, 142, 143, 144, 145, 146, 147, 148, };
-static const unsigned int lvds_gpio_pins[] = { 157, 158, 155, 156, 153, 154,
-		151, 152, 149, 150, };
-static const unsigned int jtag_uart_nand_gpio_pins[] = { 44, 43, 42, 41, 40,
-		39, 38, 37, 46, 47, 48, 49, 50, 52, 51, 45, 133, 134, 135,
-		136, 137, 138, 139, 140, 159, 160, 161, 162, 163, };
-static const unsigned int rtc_gpio_pins[] = { 0, 1, 2, 3, 4, 10, 11, 12, 13,
-		14, 15, 16, 17, 9, };
-static const unsigned int audio_ac97_pins[] = { 113, 118, 115, 114, };
-static const unsigned int audio_digmic_pins0[] = { 51, };
-static const unsigned int audio_digmic_pins1[] = { 122, };
-static const unsigned int audio_digmic_pins2[] = { 161, };
-static const unsigned int audio_func_dbg_pins[] = { 141, 144, 44, 43, 42, 41,
-		40, 39, 38, 37, 74, 75, 76, 77, 78, 79, 81, 113, 114, 118,
-		115, 49, 50, 142, 143, 80, };
-static const unsigned int audio_i2s_pins[] = { 118, 115, 116, 117, 112, 113,
-		114, };
-static const unsigned int audio_i2s_2ch_pins[] = { 118, 115, 112, 113, 114, };
-static const unsigned int audio_i2s_extclk_pins[] = { 112, };
-static const unsigned int audio_spdif_out_pins0[] = { 112, };
-static const unsigned int audio_spdif_out_pins1[] = { 116, };
-static const unsigned int audio_spdif_out_pins2[] = { 142, };
-static const unsigned int audio_uart0_basic_pins[] = { 143, 142, 141, 144, };
-static const unsigned int audio_uart0_urfs_pins0[] = { 117, };
-static const unsigned int audio_uart0_urfs_pins1[] = { 139, };
-static const unsigned int audio_uart0_urfs_pins2[] = { 163, };
-static const unsigned int audio_uart0_urfs_pins3[] = { 162, };
-static const unsigned int audio_uart1_basic_pins[] = { 147, 146, 145, 148, };
-static const unsigned int audio_uart1_urfs_pins0[] = { 117, };
-static const unsigned int audio_uart1_urfs_pins1[] = { 140, };
-static const unsigned int audio_uart1_urfs_pins2[] = { 163, };
-static const unsigned int audio_uart2_urfs_pins0[] = { 139, };
-static const unsigned int audio_uart2_urfs_pins1[] = { 163, };
-static const unsigned int audio_uart2_urfs_pins2[] = { 96, };
-static const unsigned int audio_uart2_urxd_pins0[] = { 20, };
-static const unsigned int audio_uart2_urxd_pins1[] = { 109, };
-static const unsigned int audio_uart2_urxd_pins2[] = { 93, };
-static const unsigned int audio_uart2_usclk_pins0[] = { 19, };
-static const unsigned int audio_uart2_usclk_pins1[] = { 101, };
-static const unsigned int audio_uart2_usclk_pins2[] = { 91, };
-static const unsigned int audio_uart2_utfs_pins0[] = { 18, };
-static const unsigned int audio_uart2_utfs_pins1[] = { 111, };
-static const unsigned int audio_uart2_utfs_pins2[] = { 94, };
-static const unsigned int audio_uart2_utxd_pins0[] = { 21, };
-static const unsigned int audio_uart2_utxd_pins1[] = { 110, };
-static const unsigned int audio_uart2_utxd_pins2[] = { 92, };
-static const unsigned int c_can_trnsvr_en_pins0[] = { 2, };
-static const unsigned int c_can_trnsvr_en_pins1[] = { 0, };
-static const unsigned int c_can_trnsvr_intr_pins[] = { 1, };
-static const unsigned int c_can_trnsvr_stb_n_pins[] = { 3, };
-static const unsigned int c0_can_rxd_trnsv0_pins[] = { 11, };
-static const unsigned int c0_can_rxd_trnsv1_pins[] = { 2, };
-static const unsigned int c0_can_txd_trnsv0_pins[] = { 10, };
-static const unsigned int c0_can_txd_trnsv1_pins[] = { 3, };
-static const unsigned int c1_can_rxd_pins0[] = { 138, };
-static const unsigned int c1_can_rxd_pins1[] = { 147, };
-static const unsigned int c1_can_rxd_pins2[] = { 2, };
-static const unsigned int c1_can_rxd_pins3[] = { 162, };
-static const unsigned int c1_can_txd_pins0[] = { 137, };
-static const unsigned int c1_can_txd_pins1[] = { 146, };
-static const unsigned int c1_can_txd_pins2[] = { 3, };
-static const unsigned int c1_can_txd_pins3[] = { 161, };
-static const unsigned int ca_audio_lpc_pins[] = { 62, 63, 64, 65, 66, 67, 68,
-		69, 70, 71, };
-static const unsigned int ca_bt_lpc_pins[] = { 85, 86, 87, 88, 89, 90, };
-static const unsigned int ca_coex_pins[] = { 129, 130, 131, 132, };
-static const unsigned int ca_curator_lpc_pins[] = { 57, 58, 59, 60, };
-static const unsigned int ca_pcm_debug_pins[] = { 91, 93, 94, 92, };
-static const unsigned int ca_pio_pins[] = { 121, 122, 125, 126, 38, 37, 47,
-		49, 50, 54, 55, 56, };
-static const unsigned int ca_sdio_debug_pins[] = { 40, 39, 44, 43, 42, 41, };
-static const unsigned int ca_spi_pins[] = { 82, 79, 80, 81, };
-static const unsigned int ca_trb_pins[] = { 91, 93, 94, 95, 96, 78, 74, 75,
-		76, 77, };
-static const unsigned int ca_uart_debug_pins[] = { 136, 135, 134, 133, };
-static const unsigned int clkc_pins0[] = { 30, 47, };
-static const unsigned int clkc_pins1[] = { 78, 54, };
-static const unsigned int gn_gnss_i2c_pins[] = { 128, 127, };
-static const unsigned int gn_gnss_uart_nopause_pins[] = { 134, 133, };
-static const unsigned int gn_gnss_uart_pins[] = { 134, 133, 136, 135, };
-static const unsigned int gn_trg_spi_pins0[] = { 22, 25, 23, 24, };
-static const unsigned int gn_trg_spi_pins1[] = { 82, 79, 80, 81, };
-static const unsigned int cvbs_dbg_pins[] = { 54, 53, 82, 74, 75, 76, 77, 78,
-		79, 80, 81, 83, 84, 73, 55, 56, };
-static const unsigned int cvbs_dbg_test_pins0[] = { 57, };
-static const unsigned int cvbs_dbg_test_pins1[] = { 58, };
-static const unsigned int cvbs_dbg_test_pins2[] = { 59, };
-static const unsigned int cvbs_dbg_test_pins3[] = { 60, };
-static const unsigned int cvbs_dbg_test_pins4[] = { 61, };
-static const unsigned int cvbs_dbg_test_pins5[] = { 62, };
-static const unsigned int cvbs_dbg_test_pins6[] = { 63, };
-static const unsigned int cvbs_dbg_test_pins7[] = { 64, };
-static const unsigned int cvbs_dbg_test_pins8[] = { 65, };
-static const unsigned int cvbs_dbg_test_pins9[] = { 66, };
-static const unsigned int cvbs_dbg_test_pins10[] = { 67, };
-static const unsigned int cvbs_dbg_test_pins11[] = { 68, };
-static const unsigned int cvbs_dbg_test_pins12[] = { 69, };
-static const unsigned int cvbs_dbg_test_pins13[] = { 70, };
-static const unsigned int cvbs_dbg_test_pins14[] = { 71, };
-static const unsigned int cvbs_dbg_test_pins15[] = { 72, };
-static const unsigned int gn_gnss_power_pins[] = { 123, 124, 121, 122, 125,
-		120, };
-static const unsigned int gn_gnss_sw_status_pins[] = { 57, 58, 59, 60, 61,
-		62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 53, 55, 56, 54, };
-static const unsigned int gn_gnss_eclk_pins[] = { 113, };
-static const unsigned int gn_gnss_irq1_pins0[] = { 112, };
-static const unsigned int gn_gnss_irq2_pins0[] = { 118, };
-static const unsigned int gn_gnss_tm_pins[] = { 115, };
-static const unsigned int gn_gnss_tsync_pins[] = { 114, };
-static const unsigned int gn_io_gnsssys_sw_cfg_pins[] = { 44, 43, 42, 41, 40,
-		39, 38, 37, 49, 50, 91, 92, 93, 94, 95, 96, };
-static const unsigned int gn_trg_pins0[] = { 29, 28, 26, 27, };
-static const unsigned int gn_trg_pins1[] = { 77, 76, 74, 75, };
-static const unsigned int gn_trg_shutdown_pins0[] = { 30, };
-static const unsigned int gn_trg_shutdown_pins1[] = { 83, };
-static const unsigned int gn_trg_shutdown_pins2[] = { 117, };
-static const unsigned int gn_trg_shutdown_pins3[] = { 123, };
-static const unsigned int i2c0_pins[] = { 128, 127, };
-static const unsigned int i2c1_pins[] = { 126, 125, };
-static const unsigned int i2s0_pins[] = { 91, 93, 94, 92, };
-static const unsigned int i2s1_basic_pins[] = { 95, 96, };
-static const unsigned int i2s1_rxd0_pins0[] = { 61, };
-static const unsigned int i2s1_rxd0_pins1[] = { 131, };
-static const unsigned int i2s1_rxd0_pins2[] = { 129, };
-static const unsigned int i2s1_rxd0_pins3[] = { 117, };
-static const unsigned int i2s1_rxd0_pins4[] = { 83, };
-static const unsigned int i2s1_rxd1_pins0[] = { 72, };
-static const unsigned int i2s1_rxd1_pins1[] = { 132, };
-static const unsigned int i2s1_rxd1_pins2[] = { 130, };
-static const unsigned int i2s1_rxd1_pins3[] = { 118, };
-static const unsigned int i2s1_rxd1_pins4[] = { 84, };
-static const unsigned int jtag_jt_dbg_nsrst_pins[] = { 125, };
-static const unsigned int jtag_ntrst_pins0[] = { 4, };
-static const unsigned int jtag_ntrst_pins1[] = { 163, };
-static const unsigned int jtag_swdiotms_pins0[] = { 2, };
-static const unsigned int jtag_swdiotms_pins1[] = { 160, };
-static const unsigned int jtag_tck_pins0[] = { 0, };
-static const unsigned int jtag_tck_pins1[] = { 161, };
-static const unsigned int jtag_tdi_pins0[] = { 1, };
-static const unsigned int jtag_tdi_pins1[] = { 162, };
-static const unsigned int jtag_tdo_pins0[] = { 3, };
-static const unsigned int jtag_tdo_pins1[] = { 159, };
-static const unsigned int ks_kas_spi_pins0[] = { 141, 144, 143, 142, };
-static const unsigned int ld_ldd_pins[] = { 57, 58, 59, 60, 61, 62, 63, 64,
-		65, 66, 67, 68, 69, 70, 71, 72, 74, 75, 76, 77, 78, 79, 80,
-		81, 56, 53, };
-static const unsigned int ld_ldd_16bit_pins[] = { 57, 58, 59, 60, 61, 62, 63,
-		64, 65, 66, 67, 68, 69, 70, 71, 72, 56, 53, };
-static const unsigned int ld_ldd_fck_pins[] = { 55, };
-static const unsigned int ld_ldd_lck_pins[] = { 54, };
-static const unsigned int lr_lcdrom_pins[] = { 73, 54, 57, 58, 59, 60, 61,
-		62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 56, 53, 55, };
-static const unsigned int lvds_analog_pins[] = { 149, 150, 151, 152, 153, 154,
-		155, 156, 157, 158, };
-static const unsigned int nd_df_basic_pins[] = { 44, 43, 42, 41, 40, 39, 38,
-		37, 47, 46, 52, 45, 49, 50, 48, };
-static const unsigned int nd_df_wp_pins[] = { 124, };
-static const unsigned int nd_df_cs_pins[] = { 51, };
-static const unsigned int ps_pins[] = { 120, 119, 121, };
-static const unsigned int ps_no_dir_pins[] = { 119, };
-static const unsigned int pwc_core_on_pins[] = { 8, };
-static const unsigned int pwc_ext_on_pins[] = { 6, };
-static const unsigned int pwc_gpio3_clk_pins[] = { 3, };
-static const unsigned int pwc_io_on_pins[] = { 9, };
-static const unsigned int pwc_lowbatt_b_pins0[] = { 4, };
-static const unsigned int pwc_mem_on_pins[] = { 7, };
-static const unsigned int pwc_on_key_b_pins0[] = { 5, };
-static const unsigned int pwc_wakeup_src0_pins[] = { 0, };
-static const unsigned int pwc_wakeup_src1_pins[] = { 1, };
-static const unsigned int pwc_wakeup_src2_pins[] = { 2, };
-static const unsigned int pwc_wakeup_src3_pins[] = { 3, };
-static const unsigned int pw_cko0_pins0[] = { 123, };
-static const unsigned int pw_cko0_pins1[] = { 101, };
-static const unsigned int pw_cko0_pins2[] = { 82, };
-static const unsigned int pw_cko0_pins3[] = { 162, };
-static const unsigned int pw_cko1_pins0[] = { 124, };
-static const unsigned int pw_cko1_pins1[] = { 110, };
-static const unsigned int pw_cko1_pins2[] = { 163, };
-static const unsigned int pw_i2s01_clk_pins0[] = { 125, };
-static const unsigned int pw_i2s01_clk_pins1[] = { 117, };
-static const unsigned int pw_i2s01_clk_pins2[] = { 132, };
-static const unsigned int pw_pwm0_pins0[] = { 119, };
-static const unsigned int pw_pwm0_pins1[] = { 159, };
-static const unsigned int pw_pwm1_pins0[] = { 120, };
-static const unsigned int pw_pwm1_pins1[] = { 160, };
-static const unsigned int pw_pwm1_pins2[] = { 131, };
-static const unsigned int pw_pwm2_pins0[] = { 121, };
-static const unsigned int pw_pwm2_pins1[] = { 98, };
-static const unsigned int pw_pwm2_pins2[] = { 161, };
-static const unsigned int pw_pwm3_pins0[] = { 122, };
-static const unsigned int pw_pwm3_pins1[] = { 73, };
-static const unsigned int pw_pwm_cpu_vol_pins0[] = { 121, };
-static const unsigned int pw_pwm_cpu_vol_pins1[] = { 98, };
-static const unsigned int pw_pwm_cpu_vol_pins2[] = { 161, };
-static const unsigned int pw_backlight_pins0[] = { 122, };
-static const unsigned int pw_backlight_pins1[] = { 73, };
-static const unsigned int rg_eth_mac_pins[] = { 108, 103, 104, 105, 106, 107,
-		102, 97, 98, 99, 100, 101, };
-static const unsigned int rg_gmac_phy_intr_n_pins[] = { 111, };
-static const unsigned int rg_rgmii_mac_pins[] = { 109, 110, };
-static const unsigned int rg_rgmii_phy_ref_clk_pins0[] = { 111, };
-static const unsigned int rg_rgmii_phy_ref_clk_pins1[] = { 53, };
-static const unsigned int sd0_pins[] = { 46, 47, 44, 43, 42, 41, 40, 39, 38,
-		37, };
-static const unsigned int sd0_4bit_pins[] = { 46, 47, 44, 43, 42, 41, };
-static const unsigned int sd1_pins[] = { 48, 49, 44, 43, 42, 41, 40, 39, 38,
-		37, };
-static const unsigned int sd1_4bit_pins0[] = { 48, 49, 44, 43, 42, 41, };
-static const unsigned int sd1_4bit_pins1[] = { 48, 49, 40, 39, 38, 37, };
-static const unsigned int sd2_basic_pins[] = { 31, 32, 33, 34, 35, 36, };
-static const unsigned int sd2_cdb_pins0[] = { 124, };
-static const unsigned int sd2_cdb_pins1[] = { 161, };
-static const unsigned int sd2_wpb_pins0[] = { 123, };
-static const unsigned int sd2_wpb_pins1[] = { 163, };
-static const unsigned int sd3_9_pins[] = { 85, 86, 87, 88, 89, 90, };
-static const unsigned int sd5_pins[] = { 91, 92, 93, 94, 95, 96, };
-static const unsigned int sd6_pins0[] = { 79, 78, 74, 75, 76, 77, };
-static const unsigned int sd6_pins1[] = { 101, 99, 100, 110, 109, 111, };
-static const unsigned int sp0_ext_ldo_on_pins[] = { 4, };
-static const unsigned int sp0_qspi_pins[] = { 12, 13, 14, 15, 16, 17, };
-static const unsigned int sp1_spi_pins[] = { 19, 20, 21, 18, };
-static const unsigned int tpiu_trace_pins[] = { 53, 56, 57, 58, 59, 60, 61,
-		62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, };
-static const unsigned int uart0_pins[] = { 121, 120, 134, 133, };
-static const unsigned int uart0_nopause_pins[] = { 134, 133, };
-static const unsigned int uart1_pins[] = { 136, 135, };
-static const unsigned int uart2_cts_pins0[] = { 132, };
-static const unsigned int uart2_cts_pins1[] = { 162, };
-static const unsigned int uart2_rts_pins0[] = { 131, };
-static const unsigned int uart2_rts_pins1[] = { 161, };
-static const unsigned int uart2_rxd_pins0[] = { 11, };
-static const unsigned int uart2_rxd_pins1[] = { 160, };
-static const unsigned int uart2_rxd_pins2[] = { 130, };
-static const unsigned int uart2_txd_pins0[] = { 10, };
-static const unsigned int uart2_txd_pins1[] = { 159, };
-static const unsigned int uart2_txd_pins2[] = { 129, };
-static const unsigned int uart3_cts_pins0[] = { 125, };
-static const unsigned int uart3_cts_pins1[] = { 111, };
-static const unsigned int uart3_cts_pins2[] = { 140, };
-static const unsigned int uart3_rts_pins0[] = { 126, };
-static const unsigned int uart3_rts_pins1[] = { 109, };
-static const unsigned int uart3_rts_pins2[] = { 139, };
-static const unsigned int uart3_rxd_pins0[] = { 138, };
-static const unsigned int uart3_rxd_pins1[] = { 84, };
-static const unsigned int uart3_rxd_pins2[] = { 162, };
-static const unsigned int uart3_txd_pins0[] = { 137, };
-static const unsigned int uart3_txd_pins1[] = { 83, };
-static const unsigned int uart3_txd_pins2[] = { 161, };
-static const unsigned int uart4_basic_pins[] = { 140, 139, };
-static const unsigned int uart4_cts_pins0[] = { 122, };
-static const unsigned int uart4_cts_pins1[] = { 100, };
-static const unsigned int uart4_cts_pins2[] = { 117, };
-static const unsigned int uart4_rts_pins0[] = { 123, };
-static const unsigned int uart4_rts_pins1[] = { 99, };
-static const unsigned int uart4_rts_pins2[] = { 116, };
-static const unsigned int usb0_drvvbus_pins0[] = { 51, };
-static const unsigned int usb0_drvvbus_pins1[] = { 162, };
-static const unsigned int usb1_drvvbus_pins0[] = { 134, };
-static const unsigned int usb1_drvvbus_pins1[] = { 163, };
-static const unsigned int visbus_dout_pins[] = { 57, 58, 59, 60, 61, 62, 63,
-		64, 65, 66, 67, 68, 69, 70, 71, 72, 53, 54, 55, 56, 85, 86,
-		87, 88, 89, 90, 91, 92, 93, 94, 95, 96, };
-static const unsigned int vi_vip1_pins[] = { 74, 75, 76, 77, 78, 79, 80, 81,
-		82, 83, 84, 103, 104, 105, 106, 107, 102, 97, 98, };
-static const unsigned int vi_vip1_ext_pins[] = { 74, 75, 76, 77, 78, 79, 80,
-		81, 82, 83, 84, 108, 103, 104, 105, 106, 107, 102, 97, 98,
-		99, 100, };
-static const unsigned int vi_vip1_low8bit_pins[] = { 74, 75, 76, 77, 78, 79,
-		80, 81, 82, 83, 84, };
-static const unsigned int vi_vip1_high8bit_pins[] = { 82, 83, 84, 103, 104,
-		105, 106, 107, 102, 97, 98, };
-
-/* definition of pin group table */
-static struct atlas7_pin_group altas7_pin_groups[] = {
-	GROUP("gnss_gpio_grp", gnss_gpio_pins),
-	GROUP("lcd_vip_gpio_grp", lcd_vip_gpio_pins),
-	GROUP("sdio_i2s_gpio_grp", sdio_i2s_gpio_pins),
-	GROUP("sp_rgmii_gpio_grp", sp_rgmii_gpio_pins),
-	GROUP("lvds_gpio_grp", lvds_gpio_pins),
-	GROUP("jtag_uart_nand_gpio_grp", jtag_uart_nand_gpio_pins),
-	GROUP("rtc_gpio_grp", rtc_gpio_pins),
-	GROUP("audio_ac97_grp", audio_ac97_pins),
-	GROUP("audio_digmic_grp0", audio_digmic_pins0),
-	GROUP("audio_digmic_grp1", audio_digmic_pins1),
-	GROUP("audio_digmic_grp2", audio_digmic_pins2),
-	GROUP("audio_func_dbg_grp", audio_func_dbg_pins),
-	GROUP("audio_i2s_grp", audio_i2s_pins),
-	GROUP("audio_i2s_2ch_grp", audio_i2s_2ch_pins),
-	GROUP("audio_i2s_extclk_grp", audio_i2s_extclk_pins),
-	GROUP("audio_spdif_out_grp0", audio_spdif_out_pins0),
-	GROUP("audio_spdif_out_grp1", audio_spdif_out_pins1),
-	GROUP("audio_spdif_out_grp2", audio_spdif_out_pins2),
-	GROUP("audio_uart0_basic_grp", audio_uart0_basic_pins),
-	GROUP("audio_uart0_urfs_grp0", audio_uart0_urfs_pins0),
-	GROUP("audio_uart0_urfs_grp1", audio_uart0_urfs_pins1),
-	GROUP("audio_uart0_urfs_grp2", audio_uart0_urfs_pins2),
-	GROUP("audio_uart0_urfs_grp3", audio_uart0_urfs_pins3),
-	GROUP("audio_uart1_basic_grp", audio_uart1_basic_pins),
-	GROUP("audio_uart1_urfs_grp0", audio_uart1_urfs_pins0),
-	GROUP("audio_uart1_urfs_grp1", audio_uart1_urfs_pins1),
-	GROUP("audio_uart1_urfs_grp2", audio_uart1_urfs_pins2),
-	GROUP("audio_uart2_urfs_grp0", audio_uart2_urfs_pins0),
-	GROUP("audio_uart2_urfs_grp1", audio_uart2_urfs_pins1),
-	GROUP("audio_uart2_urfs_grp2", audio_uart2_urfs_pins2),
-	GROUP("audio_uart2_urxd_grp0", audio_uart2_urxd_pins0),
-	GROUP("audio_uart2_urxd_grp1", audio_uart2_urxd_pins1),
-	GROUP("audio_uart2_urxd_grp2", audio_uart2_urxd_pins2),
-	GROUP("audio_uart2_usclk_grp0", audio_uart2_usclk_pins0),
-	GROUP("audio_uart2_usclk_grp1", audio_uart2_usclk_pins1),
-	GROUP("audio_uart2_usclk_grp2", audio_uart2_usclk_pins2),
-	GROUP("audio_uart2_utfs_grp0", audio_uart2_utfs_pins0),
-	GROUP("audio_uart2_utfs_grp1", audio_uart2_utfs_pins1),
-	GROUP("audio_uart2_utfs_grp2", audio_uart2_utfs_pins2),
-	GROUP("audio_uart2_utxd_grp0", audio_uart2_utxd_pins0),
-	GROUP("audio_uart2_utxd_grp1", audio_uart2_utxd_pins1),
-	GROUP("audio_uart2_utxd_grp2", audio_uart2_utxd_pins2),
-	GROUP("c_can_trnsvr_en_grp0", c_can_trnsvr_en_pins0),
-	GROUP("c_can_trnsvr_en_grp1", c_can_trnsvr_en_pins1),
-	GROUP("c_can_trnsvr_intr_grp", c_can_trnsvr_intr_pins),
-	GROUP("c_can_trnsvr_stb_n_grp", c_can_trnsvr_stb_n_pins),
-	GROUP("c0_can_rxd_trnsv0_grp", c0_can_rxd_trnsv0_pins),
-	GROUP("c0_can_rxd_trnsv1_grp", c0_can_rxd_trnsv1_pins),
-	GROUP("c0_can_txd_trnsv0_grp", c0_can_txd_trnsv0_pins),
-	GROUP("c0_can_txd_trnsv1_grp", c0_can_txd_trnsv1_pins),
-	GROUP("c1_can_rxd_grp0", c1_can_rxd_pins0),
-	GROUP("c1_can_rxd_grp1", c1_can_rxd_pins1),
-	GROUP("c1_can_rxd_grp2", c1_can_rxd_pins2),
-	GROUP("c1_can_rxd_grp3", c1_can_rxd_pins3),
-	GROUP("c1_can_txd_grp0", c1_can_txd_pins0),
-	GROUP("c1_can_txd_grp1", c1_can_txd_pins1),
-	GROUP("c1_can_txd_grp2", c1_can_txd_pins2),
-	GROUP("c1_can_txd_grp3", c1_can_txd_pins3),
-	GROUP("ca_audio_lpc_grp", ca_audio_lpc_pins),
-	GROUP("ca_bt_lpc_grp", ca_bt_lpc_pins),
-	GROUP("ca_coex_grp", ca_coex_pins),
-	GROUP("ca_curator_lpc_grp", ca_curator_lpc_pins),
-	GROUP("ca_pcm_debug_grp", ca_pcm_debug_pins),
-	GROUP("ca_pio_grp", ca_pio_pins),
-	GROUP("ca_sdio_debug_grp", ca_sdio_debug_pins),
-	GROUP("ca_spi_grp", ca_spi_pins),
-	GROUP("ca_trb_grp", ca_trb_pins),
-	GROUP("ca_uart_debug_grp", ca_uart_debug_pins),
-	GROUP("clkc_grp0", clkc_pins0),
-	GROUP("clkc_grp1", clkc_pins1),
-	GROUP("gn_gnss_i2c_grp", gn_gnss_i2c_pins),
-	GROUP("gn_gnss_uart_nopause_grp", gn_gnss_uart_nopause_pins),
-	GROUP("gn_gnss_uart_grp", gn_gnss_uart_pins),
-	GROUP("gn_trg_spi_grp0", gn_trg_spi_pins0),
-	GROUP("gn_trg_spi_grp1", gn_trg_spi_pins1),
-	GROUP("cvbs_dbg_grp", cvbs_dbg_pins),
-	GROUP("cvbs_dbg_test_grp0", cvbs_dbg_test_pins0),
-	GROUP("cvbs_dbg_test_grp1", cvbs_dbg_test_pins1),
-	GROUP("cvbs_dbg_test_grp2", cvbs_dbg_test_pins2),
-	GROUP("cvbs_dbg_test_grp3", cvbs_dbg_test_pins3),
-	GROUP("cvbs_dbg_test_grp4", cvbs_dbg_test_pins4),
-	GROUP("cvbs_dbg_test_grp5", cvbs_dbg_test_pins5),
-	GROUP("cvbs_dbg_test_grp6", cvbs_dbg_test_pins6),
-	GROUP("cvbs_dbg_test_grp7", cvbs_dbg_test_pins7),
-	GROUP("cvbs_dbg_test_grp8", cvbs_dbg_test_pins8),
-	GROUP("cvbs_dbg_test_grp9", cvbs_dbg_test_pins9),
-	GROUP("cvbs_dbg_test_grp10", cvbs_dbg_test_pins10),
-	GROUP("cvbs_dbg_test_grp11", cvbs_dbg_test_pins11),
-	GROUP("cvbs_dbg_test_grp12", cvbs_dbg_test_pins12),
-	GROUP("cvbs_dbg_test_grp13", cvbs_dbg_test_pins13),
-	GROUP("cvbs_dbg_test_grp14", cvbs_dbg_test_pins14),
-	GROUP("cvbs_dbg_test_grp15", cvbs_dbg_test_pins15),
-	GROUP("gn_gnss_power_grp", gn_gnss_power_pins),
-	GROUP("gn_gnss_sw_status_grp", gn_gnss_sw_status_pins),
-	GROUP("gn_gnss_eclk_grp", gn_gnss_eclk_pins),
-	GROUP("gn_gnss_irq1_grp0", gn_gnss_irq1_pins0),
-	GROUP("gn_gnss_irq2_grp0", gn_gnss_irq2_pins0),
-	GROUP("gn_gnss_tm_grp", gn_gnss_tm_pins),
-	GROUP("gn_gnss_tsync_grp", gn_gnss_tsync_pins),
-	GROUP("gn_io_gnsssys_sw_cfg_grp", gn_io_gnsssys_sw_cfg_pins),
-	GROUP("gn_trg_grp0", gn_trg_pins0),
-	GROUP("gn_trg_grp1", gn_trg_pins1),
-	GROUP("gn_trg_shutdown_grp0", gn_trg_shutdown_pins0),
-	GROUP("gn_trg_shutdown_grp1", gn_trg_shutdown_pins1),
-	GROUP("gn_trg_shutdown_grp2", gn_trg_shutdown_pins2),
-	GROUP("gn_trg_shutdown_grp3", gn_trg_shutdown_pins3),
-	GROUP("i2c0_grp", i2c0_pins),
-	GROUP("i2c1_grp", i2c1_pins),
-	GROUP("i2s0_grp", i2s0_pins),
-	GROUP("i2s1_basic_grp", i2s1_basic_pins),
-	GROUP("i2s1_rxd0_grp0", i2s1_rxd0_pins0),
-	GROUP("i2s1_rxd0_grp1", i2s1_rxd0_pins1),
-	GROUP("i2s1_rxd0_grp2", i2s1_rxd0_pins2),
-	GROUP("i2s1_rxd0_grp3", i2s1_rxd0_pins3),
-	GROUP("i2s1_rxd0_grp4", i2s1_rxd0_pins4),
-	GROUP("i2s1_rxd1_grp0", i2s1_rxd1_pins0),
-	GROUP("i2s1_rxd1_grp1", i2s1_rxd1_pins1),
-	GROUP("i2s1_rxd1_grp2", i2s1_rxd1_pins2),
-	GROUP("i2s1_rxd1_grp3", i2s1_rxd1_pins3),
-	GROUP("i2s1_rxd1_grp4", i2s1_rxd1_pins4),
-	GROUP("jtag_jt_dbg_nsrst_grp", jtag_jt_dbg_nsrst_pins),
-	GROUP("jtag_ntrst_grp0", jtag_ntrst_pins0),
-	GROUP("jtag_ntrst_grp1", jtag_ntrst_pins1),
-	GROUP("jtag_swdiotms_grp0", jtag_swdiotms_pins0),
-	GROUP("jtag_swdiotms_grp1", jtag_swdiotms_pins1),
-	GROUP("jtag_tck_grp0", jtag_tck_pins0),
-	GROUP("jtag_tck_grp1", jtag_tck_pins1),
-	GROUP("jtag_tdi_grp0", jtag_tdi_pins0),
-	GROUP("jtag_tdi_grp1", jtag_tdi_pins1),
-	GROUP("jtag_tdo_grp0", jtag_tdo_pins0),
-	GROUP("jtag_tdo_grp1", jtag_tdo_pins1),
-	GROUP("ks_kas_spi_grp0", ks_kas_spi_pins0),
-	GROUP("ld_ldd_grp", ld_ldd_pins),
-	GROUP("ld_ldd_16bit_grp", ld_ldd_16bit_pins),
-	GROUP("ld_ldd_fck_grp", ld_ldd_fck_pins),
-	GROUP("ld_ldd_lck_grp", ld_ldd_lck_pins),
-	GROUP("lr_lcdrom_grp", lr_lcdrom_pins),
-	GROUP("lvds_analog_grp", lvds_analog_pins),
-	GROUP("nd_df_basic_grp", nd_df_basic_pins),
-	GROUP("nd_df_wp_grp", nd_df_wp_pins),
-	GROUP("nd_df_cs_grp", nd_df_cs_pins),
-	GROUP("ps_grp", ps_pins),
-	GROUP("ps_no_dir_grp", ps_no_dir_pins),
-	GROUP("pwc_core_on_grp", pwc_core_on_pins),
-	GROUP("pwc_ext_on_grp", pwc_ext_on_pins),
-	GROUP("pwc_gpio3_clk_grp", pwc_gpio3_clk_pins),
-	GROUP("pwc_io_on_grp", pwc_io_on_pins),
-	GROUP("pwc_lowbatt_b_grp0", pwc_lowbatt_b_pins0),
-	GROUP("pwc_mem_on_grp", pwc_mem_on_pins),
-	GROUP("pwc_on_key_b_grp0", pwc_on_key_b_pins0),
-	GROUP("pwc_wakeup_src0_grp", pwc_wakeup_src0_pins),
-	GROUP("pwc_wakeup_src1_grp", pwc_wakeup_src1_pins),
-	GROUP("pwc_wakeup_src2_grp", pwc_wakeup_src2_pins),
-	GROUP("pwc_wakeup_src3_grp", pwc_wakeup_src3_pins),
-	GROUP("pw_cko0_grp0", pw_cko0_pins0),
-	GROUP("pw_cko0_grp1", pw_cko0_pins1),
-	GROUP("pw_cko0_grp2", pw_cko0_pins2),
-	GROUP("pw_cko0_grp3", pw_cko0_pins3),
-	GROUP("pw_cko1_grp0", pw_cko1_pins0),
-	GROUP("pw_cko1_grp1", pw_cko1_pins1),
-	GROUP("pw_cko1_grp2", pw_cko1_pins2),
-	GROUP("pw_i2s01_clk_grp0", pw_i2s01_clk_pins0),
-	GROUP("pw_i2s01_clk_grp1", pw_i2s01_clk_pins1),
-	GROUP("pw_i2s01_clk_grp2", pw_i2s01_clk_pins2),
-	GROUP("pw_pwm0_grp0", pw_pwm0_pins0),
-	GROUP("pw_pwm0_grp1", pw_pwm0_pins1),
-	GROUP("pw_pwm1_grp0", pw_pwm1_pins0),
-	GROUP("pw_pwm1_grp1", pw_pwm1_pins1),
-	GROUP("pw_pwm1_grp2", pw_pwm1_pins2),
-	GROUP("pw_pwm2_grp0", pw_pwm2_pins0),
-	GROUP("pw_pwm2_grp1", pw_pwm2_pins1),
-	GROUP("pw_pwm2_grp2", pw_pwm2_pins2),
-	GROUP("pw_pwm3_grp0", pw_pwm3_pins0),
-	GROUP("pw_pwm3_grp1", pw_pwm3_pins1),
-	GROUP("pw_pwm_cpu_vol_grp0", pw_pwm_cpu_vol_pins0),
-	GROUP("pw_pwm_cpu_vol_grp1", pw_pwm_cpu_vol_pins1),
-	GROUP("pw_pwm_cpu_vol_grp2", pw_pwm_cpu_vol_pins2),
-	GROUP("pw_backlight_grp0", pw_backlight_pins0),
-	GROUP("pw_backlight_grp1", pw_backlight_pins1),
-	GROUP("rg_eth_mac_grp", rg_eth_mac_pins),
-	GROUP("rg_gmac_phy_intr_n_grp", rg_gmac_phy_intr_n_pins),
-	GROUP("rg_rgmii_mac_grp", rg_rgmii_mac_pins),
-	GROUP("rg_rgmii_phy_ref_clk_grp0", rg_rgmii_phy_ref_clk_pins0),
-	GROUP("rg_rgmii_phy_ref_clk_grp1", rg_rgmii_phy_ref_clk_pins1),
-	GROUP("sd0_grp", sd0_pins),
-	GROUP("sd0_4bit_grp", sd0_4bit_pins),
-	GROUP("sd1_grp", sd1_pins),
-	GROUP("sd1_4bit_grp0", sd1_4bit_pins0),
-	GROUP("sd1_4bit_grp1", sd1_4bit_pins1),
-	GROUP("sd2_basic_grp", sd2_basic_pins),
-	GROUP("sd2_cdb_grp0", sd2_cdb_pins0),
-	GROUP("sd2_cdb_grp1", sd2_cdb_pins1),
-	GROUP("sd2_wpb_grp0", sd2_wpb_pins0),
-	GROUP("sd2_wpb_grp1", sd2_wpb_pins1),
-	GROUP("sd3_9_grp", sd3_9_pins),
-	GROUP("sd5_grp", sd5_pins),
-	GROUP("sd6_grp0", sd6_pins0),
-	GROUP("sd6_grp1", sd6_pins1),
-	GROUP("sp0_ext_ldo_on_grp", sp0_ext_ldo_on_pins),
-	GROUP("sp0_qspi_grp", sp0_qspi_pins),
-	GROUP("sp1_spi_grp", sp1_spi_pins),
-	GROUP("tpiu_trace_grp", tpiu_trace_pins),
-	GROUP("uart0_grp", uart0_pins),
-	GROUP("uart0_nopause_grp", uart0_nopause_pins),
-	GROUP("uart1_grp", uart1_pins),
-	GROUP("uart2_cts_grp0", uart2_cts_pins0),
-	GROUP("uart2_cts_grp1", uart2_cts_pins1),
-	GROUP("uart2_rts_grp0", uart2_rts_pins0),
-	GROUP("uart2_rts_grp1", uart2_rts_pins1),
-	GROUP("uart2_rxd_grp0", uart2_rxd_pins0),
-	GROUP("uart2_rxd_grp1", uart2_rxd_pins1),
-	GROUP("uart2_rxd_grp2", uart2_rxd_pins2),
-	GROUP("uart2_txd_grp0", uart2_txd_pins0),
-	GROUP("uart2_txd_grp1", uart2_txd_pins1),
-	GROUP("uart2_txd_grp2", uart2_txd_pins2),
-	GROUP("uart3_cts_grp0", uart3_cts_pins0),
-	GROUP("uart3_cts_grp1", uart3_cts_pins1),
-	GROUP("uart3_cts_grp2", uart3_cts_pins2),
-	GROUP("uart3_rts_grp0", uart3_rts_pins0),
-	GROUP("uart3_rts_grp1", uart3_rts_pins1),
-	GROUP("uart3_rts_grp2", uart3_rts_pins2),
-	GROUP("uart3_rxd_grp0", uart3_rxd_pins0),
-	GROUP("uart3_rxd_grp1", uart3_rxd_pins1),
-	GROUP("uart3_rxd_grp2", uart3_rxd_pins2),
-	GROUP("uart3_txd_grp0", uart3_txd_pins0),
-	GROUP("uart3_txd_grp1", uart3_txd_pins1),
-	GROUP("uart3_txd_grp2", uart3_txd_pins2),
-	GROUP("uart4_basic_grp", uart4_basic_pins),
-	GROUP("uart4_cts_grp0", uart4_cts_pins0),
-	GROUP("uart4_cts_grp1", uart4_cts_pins1),
-	GROUP("uart4_cts_grp2", uart4_cts_pins2),
-	GROUP("uart4_rts_grp0", uart4_rts_pins0),
-	GROUP("uart4_rts_grp1", uart4_rts_pins1),
-	GROUP("uart4_rts_grp2", uart4_rts_pins2),
-	GROUP("usb0_drvvbus_grp0", usb0_drvvbus_pins0),
-	GROUP("usb0_drvvbus_grp1", usb0_drvvbus_pins1),
-	GROUP("usb1_drvvbus_grp0", usb1_drvvbus_pins0),
-	GROUP("usb1_drvvbus_grp1", usb1_drvvbus_pins1),
-	GROUP("visbus_dout_grp", visbus_dout_pins),
-	GROUP("vi_vip1_grp", vi_vip1_pins),
-	GROUP("vi_vip1_ext_grp", vi_vip1_ext_pins),
-	GROUP("vi_vip1_low8bit_grp", vi_vip1_low8bit_pins),
-	GROUP("vi_vip1_high8bit_grp", vi_vip1_high8bit_pins),
-};
-
-/* How many groups that a function can use */
-static const char * const gnss_gpio_grp[] = { "gnss_gpio_grp", };
-static const char * const lcd_vip_gpio_grp[] = { "lcd_vip_gpio_grp", };
-static const char * const sdio_i2s_gpio_grp[] = { "sdio_i2s_gpio_grp", };
-static const char * const sp_rgmii_gpio_grp[] = { "sp_rgmii_gpio_grp", };
-static const char * const lvds_gpio_grp[] = { "lvds_gpio_grp", };
-static const char * const jtag_uart_nand_gpio_grp[] = {
-				"jtag_uart_nand_gpio_grp", };
-static const char * const rtc_gpio_grp[] = { "rtc_gpio_grp", };
-static const char * const audio_ac97_grp[] = { "audio_ac97_grp", };
-static const char * const audio_digmic_grp0[] = { "audio_digmic_grp0", };
-static const char * const audio_digmic_grp1[] = { "audio_digmic_grp1", };
-static const char * const audio_digmic_grp2[] = { "audio_digmic_grp2", };
-static const char * const audio_func_dbg_grp[] = { "audio_func_dbg_grp", };
-static const char * const audio_i2s_grp[] = { "audio_i2s_grp", };
-static const char * const audio_i2s_2ch_grp[] = { "audio_i2s_2ch_grp", };
-static const char * const audio_i2s_extclk_grp[] = { "audio_i2s_extclk_grp", };
-static const char * const audio_spdif_out_grp0[] = { "audio_spdif_out_grp0", };
-static const char * const audio_spdif_out_grp1[] = { "audio_spdif_out_grp1", };
-static const char * const audio_spdif_out_grp2[] = { "audio_spdif_out_grp2", };
-static const char * const audio_uart0_basic_grp[] = {
-				"audio_uart0_basic_grp", };
-static const char * const audio_uart0_urfs_grp0[] = {
-				"audio_uart0_urfs_grp0", };
-static const char * const audio_uart0_urfs_grp1[] = {
-				"audio_uart0_urfs_grp1", };
-static const char * const audio_uart0_urfs_grp2[] = {
-				"audio_uart0_urfs_grp2", };
-static const char * const audio_uart0_urfs_grp3[] = {
-				"audio_uart0_urfs_grp3", };
-static const char * const audio_uart1_basic_grp[] = {
-				"audio_uart1_basic_grp", };
-static const char * const audio_uart1_urfs_grp0[] = {
-				"audio_uart1_urfs_grp0", };
-static const char * const audio_uart1_urfs_grp1[] = {
-				"audio_uart1_urfs_grp1", };
-static const char * const audio_uart1_urfs_grp2[] = {
-				"audio_uart1_urfs_grp2", };
-static const char * const audio_uart2_urfs_grp0[] = {
-				"audio_uart2_urfs_grp0", };
-static const char * const audio_uart2_urfs_grp1[] = {
-				"audio_uart2_urfs_grp1", };
-static const char * const audio_uart2_urfs_grp2[] = {
-				"audio_uart2_urfs_grp2", };
-static const char * const audio_uart2_urxd_grp0[] = {
-				"audio_uart2_urxd_grp0", };
-static const char * const audio_uart2_urxd_grp1[] = {
-				"audio_uart2_urxd_grp1", };
-static const char * const audio_uart2_urxd_grp2[] = {
-				"audio_uart2_urxd_grp2", };
-static const char * const audio_uart2_usclk_grp0[] = {
-				"audio_uart2_usclk_grp0", };
-static const char * const audio_uart2_usclk_grp1[] = {
-				"audio_uart2_usclk_grp1", };
-static const char * const audio_uart2_usclk_grp2[] = {
-				"audio_uart2_usclk_grp2", };
-static const char * const audio_uart2_utfs_grp0[] = {
-				"audio_uart2_utfs_grp0", };
-static const char * const audio_uart2_utfs_grp1[] = {
-				"audio_uart2_utfs_grp1", };
-static const char * const audio_uart2_utfs_grp2[] = {
-				"audio_uart2_utfs_grp2", };
-static const char * const audio_uart2_utxd_grp0[] = {
-				"audio_uart2_utxd_grp0", };
-static const char * const audio_uart2_utxd_grp1[] = {
-				"audio_uart2_utxd_grp1", };
-static const char * const audio_uart2_utxd_grp2[] = {
-				"audio_uart2_utxd_grp2", };
-static const char * const c_can_trnsvr_en_grp0[] = { "c_can_trnsvr_en_grp0", };
-static const char * const c_can_trnsvr_en_grp1[] = { "c_can_trnsvr_en_grp1", };
-static const char * const c_can_trnsvr_intr_grp[] = {
-				"c_can_trnsvr_intr_grp", };
-static const char * const c_can_trnsvr_stb_n_grp[] = {
-				"c_can_trnsvr_stb_n_grp", };
-static const char * const c0_can_rxd_trnsv0_grp[] = {
-				"c0_can_rxd_trnsv0_grp", };
-static const char * const c0_can_rxd_trnsv1_grp[] = {
-				"c0_can_rxd_trnsv1_grp", };
-static const char * const c0_can_txd_trnsv0_grp[] = {
-				"c0_can_txd_trnsv0_grp", };
-static const char * const c0_can_txd_trnsv1_grp[] = {
-				"c0_can_txd_trnsv1_grp", };
-static const char * const c1_can_rxd_grp0[] = { "c1_can_rxd_grp0", };
-static const char * const c1_can_rxd_grp1[] = { "c1_can_rxd_grp1", };
-static const char * const c1_can_rxd_grp2[] = { "c1_can_rxd_grp2", };
-static const char * const c1_can_rxd_grp3[] = { "c1_can_rxd_grp3", };
-static const char * const c1_can_txd_grp0[] = { "c1_can_txd_grp0", };
-static const char * const c1_can_txd_grp1[] = { "c1_can_txd_grp1", };
-static const char * const c1_can_txd_grp2[] = { "c1_can_txd_grp2", };
-static const char * const c1_can_txd_grp3[] = { "c1_can_txd_grp3", };
-static const char * const ca_audio_lpc_grp[] = { "ca_audio_lpc_grp", };
-static const char * const ca_bt_lpc_grp[] = { "ca_bt_lpc_grp", };
-static const char * const ca_coex_grp[] = { "ca_coex_grp", };
-static const char * const ca_curator_lpc_grp[] = { "ca_curator_lpc_grp", };
-static const char * const ca_pcm_debug_grp[] = { "ca_pcm_debug_grp", };
-static const char * const ca_pio_grp[] = { "ca_pio_grp", };
-static const char * const ca_sdio_debug_grp[] = { "ca_sdio_debug_grp", };
-static const char * const ca_spi_grp[] = { "ca_spi_grp", };
-static const char * const ca_trb_grp[] = { "ca_trb_grp", };
-static const char * const ca_uart_debug_grp[] = { "ca_uart_debug_grp", };
-static const char * const clkc_grp0[] = { "clkc_grp0", };
-static const char * const clkc_grp1[] = { "clkc_grp1", };
-static const char * const gn_gnss_i2c_grp[] = { "gn_gnss_i2c_grp", };
-static const char * const gn_gnss_uart_nopause_grp[] = {
-				"gn_gnss_uart_nopause_grp", };
-static const char * const gn_gnss_uart_grp[] = { "gn_gnss_uart_grp", };
-static const char * const gn_trg_spi_grp0[] = { "gn_trg_spi_grp0", };
-static const char * const gn_trg_spi_grp1[] = { "gn_trg_spi_grp1", };
-static const char * const cvbs_dbg_grp[] = { "cvbs_dbg_grp", };
-static const char * const cvbs_dbg_test_grp0[] = { "cvbs_dbg_test_grp0", };
-static const char * const cvbs_dbg_test_grp1[] = { "cvbs_dbg_test_grp1", };
-static const char * const cvbs_dbg_test_grp2[] = { "cvbs_dbg_test_grp2", };
-static const char * const cvbs_dbg_test_grp3[] = { "cvbs_dbg_test_grp3", };
-static const char * const cvbs_dbg_test_grp4[] = { "cvbs_dbg_test_grp4", };
-static const char * const cvbs_dbg_test_grp5[] = { "cvbs_dbg_test_grp5", };
-static const char * const cvbs_dbg_test_grp6[] = { "cvbs_dbg_test_grp6", };
-static const char * const cvbs_dbg_test_grp7[] = { "cvbs_dbg_test_grp7", };
-static const char * const cvbs_dbg_test_grp8[] = { "cvbs_dbg_test_grp8", };
-static const char * const cvbs_dbg_test_grp9[] = { "cvbs_dbg_test_grp9", };
-static const char * const cvbs_dbg_test_grp10[] = { "cvbs_dbg_test_grp10", };
-static const char * const cvbs_dbg_test_grp11[] = { "cvbs_dbg_test_grp11", };
-static const char * const cvbs_dbg_test_grp12[] = { "cvbs_dbg_test_grp12", };
-static const char * const cvbs_dbg_test_grp13[] = { "cvbs_dbg_test_grp13", };
-static const char * const cvbs_dbg_test_grp14[] = { "cvbs_dbg_test_grp14", };
-static const char * const cvbs_dbg_test_grp15[] = { "cvbs_dbg_test_grp15", };
-static const char * const gn_gnss_power_grp[] = { "gn_gnss_power_grp", };
-static const char * const gn_gnss_sw_status_grp[] = {
-				"gn_gnss_sw_status_grp", };
-static const char * const gn_gnss_eclk_grp[] = { "gn_gnss_eclk_grp", };
-static const char * const gn_gnss_irq1_grp0[] = { "gn_gnss_irq1_grp0", };
-static const char * const gn_gnss_irq2_grp0[] = { "gn_gnss_irq2_grp0", };
-static const char * const gn_gnss_tm_grp[] = { "gn_gnss_tm_grp", };
-static const char * const gn_gnss_tsync_grp[] = { "gn_gnss_tsync_grp", };
-static const char * const gn_io_gnsssys_sw_cfg_grp[] = {
-				"gn_io_gnsssys_sw_cfg_grp", };
-static const char * const gn_trg_grp0[] = { "gn_trg_grp0", };
-static const char * const gn_trg_grp1[] = { "gn_trg_grp1", };
-static const char * const gn_trg_shutdown_grp0[] = { "gn_trg_shutdown_grp0", };
-static const char * const gn_trg_shutdown_grp1[] = { "gn_trg_shutdown_grp1", };
-static const char * const gn_trg_shutdown_grp2[] = { "gn_trg_shutdown_grp2", };
-static const char * const gn_trg_shutdown_grp3[] = { "gn_trg_shutdown_grp3", };
-static const char * const i2c0_grp[] = { "i2c0_grp", };
-static const char * const i2c1_grp[] = { "i2c1_grp", };
-static const char * const i2s0_grp[] = { "i2s0_grp", };
-static const char * const i2s1_basic_grp[] = { "i2s1_basic_grp", };
-static const char * const i2s1_rxd0_grp0[] = { "i2s1_rxd0_grp0", };
-static const char * const i2s1_rxd0_grp1[] = { "i2s1_rxd0_grp1", };
-static const char * const i2s1_rxd0_grp2[] = { "i2s1_rxd0_grp2", };
-static const char * const i2s1_rxd0_grp3[] = { "i2s1_rxd0_grp3", };
-static const char * const i2s1_rxd0_grp4[] = { "i2s1_rxd0_grp4", };
-static const char * const i2s1_rxd1_grp0[] = { "i2s1_rxd1_grp0", };
-static const char * const i2s1_rxd1_grp1[] = { "i2s1_rxd1_grp1", };
-static const char * const i2s1_rxd1_grp2[] = { "i2s1_rxd1_grp2", };
-static const char * const i2s1_rxd1_grp3[] = { "i2s1_rxd1_grp3", };
-static const char * const i2s1_rxd1_grp4[] = { "i2s1_rxd1_grp4", };
-static const char * const jtag_jt_dbg_nsrst_grp[] = {
-				"jtag_jt_dbg_nsrst_grp", };
-static const char * const jtag_ntrst_grp0[] = { "jtag_ntrst_grp0", };
-static const char * const jtag_ntrst_grp1[] = { "jtag_ntrst_grp1", };
-static const char * const jtag_swdiotms_grp0[] = { "jtag_swdiotms_grp0", };
-static const char * const jtag_swdiotms_grp1[] = { "jtag_swdiotms_grp1", };
-static const char * const jtag_tck_grp0[] = { "jtag_tck_grp0", };
-static const char * const jtag_tck_grp1[] = { "jtag_tck_grp1", };
-static const char * const jtag_tdi_grp0[] = { "jtag_tdi_grp0", };
-static const char * const jtag_tdi_grp1[] = { "jtag_tdi_grp1", };
-static const char * const jtag_tdo_grp0[] = { "jtag_tdo_grp0", };
-static const char * const jtag_tdo_grp1[] = { "jtag_tdo_grp1", };
-static const char * const ks_kas_spi_grp0[] = { "ks_kas_spi_grp0", };
-static const char * const ld_ldd_grp[] = { "ld_ldd_grp", };
-static const char * const ld_ldd_16bit_grp[] = { "ld_ldd_16bit_grp", };
-static const char * const ld_ldd_fck_grp[] = { "ld_ldd_fck_grp", };
-static const char * const ld_ldd_lck_grp[] = { "ld_ldd_lck_grp", };
-static const char * const lr_lcdrom_grp[] = { "lr_lcdrom_grp", };
-static const char * const lvds_analog_grp[] = { "lvds_analog_grp", };
-static const char * const nd_df_basic_grp[] = { "nd_df_basic_grp", };
-static const char * const nd_df_wp_grp[] = { "nd_df_wp_grp", };
-static const char * const nd_df_cs_grp[] = { "nd_df_cs_grp", };
-static const char * const ps_grp[] = { "ps_grp", };
-static const char * const ps_no_dir_grp[] = { "ps_no_dir_grp", };
-static const char * const pwc_core_on_grp[] = { "pwc_core_on_grp", };
-static const char * const pwc_ext_on_grp[] = { "pwc_ext_on_grp", };
-static const char * const pwc_gpio3_clk_grp[] = { "pwc_gpio3_clk_grp", };
-static const char * const pwc_io_on_grp[] = { "pwc_io_on_grp", };
-static const char * const pwc_lowbatt_b_grp0[] = { "pwc_lowbatt_b_grp0", };
-static const char * const pwc_mem_on_grp[] = { "pwc_mem_on_grp", };
-static const char * const pwc_on_key_b_grp0[] = { "pwc_on_key_b_grp0", };
-static const char * const pwc_wakeup_src0_grp[] = { "pwc_wakeup_src0_grp", };
-static const char * const pwc_wakeup_src1_grp[] = { "pwc_wakeup_src1_grp", };
-static const char * const pwc_wakeup_src2_grp[] = { "pwc_wakeup_src2_grp", };
-static const char * const pwc_wakeup_src3_grp[] = { "pwc_wakeup_src3_grp", };
-static const char * const pw_cko0_grp0[] = { "pw_cko0_grp0", };
-static const char * const pw_cko0_grp1[] = { "pw_cko0_grp1", };
-static const char * const pw_cko0_grp2[] = { "pw_cko0_grp2", };
-static const char * const pw_cko0_grp3[] = { "pw_cko0_grp3", };
-static const char * const pw_cko1_grp0[] = { "pw_cko1_grp0", };
-static const char * const pw_cko1_grp1[] = { "pw_cko1_grp1", };
-static const char * const pw_cko1_grp2[] = { "pw_cko1_grp2", };
-static const char * const pw_i2s01_clk_grp0[] = { "pw_i2s01_clk_grp0", };
-static const char * const pw_i2s01_clk_grp1[] = { "pw_i2s01_clk_grp1", };
-static const char * const pw_i2s01_clk_grp2[] = { "pw_i2s01_clk_grp2", };
-static const char * const pw_pwm0_grp0[] = { "pw_pwm0_grp0", };
-static const char * const pw_pwm0_grp1[] = { "pw_pwm0_grp1", };
-static const char * const pw_pwm1_grp0[] = { "pw_pwm1_grp0", };
-static const char * const pw_pwm1_grp1[] = { "pw_pwm1_grp1", };
-static const char * const pw_pwm1_grp2[] = { "pw_pwm1_grp2", };
-static const char * const pw_pwm2_grp0[] = { "pw_pwm2_grp0", };
-static const char * const pw_pwm2_grp1[] = { "pw_pwm2_grp1", };
-static const char * const pw_pwm2_grp2[] = { "pw_pwm2_grp2", };
-static const char * const pw_pwm3_grp0[] = { "pw_pwm3_grp0", };
-static const char * const pw_pwm3_grp1[] = { "pw_pwm3_grp1", };
-static const char * const pw_pwm_cpu_vol_grp0[] = { "pw_pwm_cpu_vol_grp0", };
-static const char * const pw_pwm_cpu_vol_grp1[] = { "pw_pwm_cpu_vol_grp1", };
-static const char * const pw_pwm_cpu_vol_grp2[] = { "pw_pwm_cpu_vol_grp2", };
-static const char * const pw_backlight_grp0[] = { "pw_backlight_grp0", };
-static const char * const pw_backlight_grp1[] = { "pw_backlight_grp1", };
-static const char * const rg_eth_mac_grp[] = { "rg_eth_mac_grp", };
-static const char * const rg_gmac_phy_intr_n_grp[] = {
-				"rg_gmac_phy_intr_n_grp", };
-static const char * const rg_rgmii_mac_grp[] = { "rg_rgmii_mac_grp", };
-static const char * const rg_rgmii_phy_ref_clk_grp0[] = {
-				"rg_rgmii_phy_ref_clk_grp0", };
-static const char * const rg_rgmii_phy_ref_clk_grp1[] = {
-				"rg_rgmii_phy_ref_clk_grp1", };
-static const char * const sd0_grp[] = { "sd0_grp", };
-static const char * const sd0_4bit_grp[] = { "sd0_4bit_grp", };
-static const char * const sd1_grp[] = { "sd1_grp", };
-static const char * const sd1_4bit_grp0[] = { "sd1_4bit_grp0", };
-static const char * const sd1_4bit_grp1[] = { "sd1_4bit_grp1", };
-static const char * const sd2_basic_grp[] = { "sd2_basic_grp", };
-static const char * const sd2_cdb_grp0[] = { "sd2_cdb_grp0", };
-static const char * const sd2_cdb_grp1[] = { "sd2_cdb_grp1", };
-static const char * const sd2_wpb_grp0[] = { "sd2_wpb_grp0", };
-static const char * const sd2_wpb_grp1[] = { "sd2_wpb_grp1", };
-static const char * const sd3_9_grp[] = { "sd3_9_grp", };
-static const char * const sd5_grp[] = { "sd5_grp", };
-static const char * const sd6_grp0[] = { "sd6_grp0", };
-static const char * const sd6_grp1[] = { "sd6_grp1", };
-static const char * const sp0_ext_ldo_on_grp[] = { "sp0_ext_ldo_on_grp", };
-static const char * const sp0_qspi_grp[] = { "sp0_qspi_grp", };
-static const char * const sp1_spi_grp[] = { "sp1_spi_grp", };
-static const char * const tpiu_trace_grp[] = { "tpiu_trace_grp", };
-static const char * const uart0_grp[] = { "uart0_grp", };
-static const char * const uart0_nopause_grp[] = { "uart0_nopause_grp", };
-static const char * const uart1_grp[] = { "uart1_grp", };
-static const char * const uart2_cts_grp0[] = { "uart2_cts_grp0", };
-static const char * const uart2_cts_grp1[] = { "uart2_cts_grp1", };
-static const char * const uart2_rts_grp0[] = { "uart2_rts_grp0", };
-static const char * const uart2_rts_grp1[] = { "uart2_rts_grp1", };
-static const char * const uart2_rxd_grp0[] = { "uart2_rxd_grp0", };
-static const char * const uart2_rxd_grp1[] = { "uart2_rxd_grp1", };
-static const char * const uart2_rxd_grp2[] = { "uart2_rxd_grp2", };
-static const char * const uart2_txd_grp0[] = { "uart2_txd_grp0", };
-static const char * const uart2_txd_grp1[] = { "uart2_txd_grp1", };
-static const char * const uart2_txd_grp2[] = { "uart2_txd_grp2", };
-static const char * const uart3_cts_grp0[] = { "uart3_cts_grp0", };
-static const char * const uart3_cts_grp1[] = { "uart3_cts_grp1", };
-static const char * const uart3_cts_grp2[] = { "uart3_cts_grp2", };
-static const char * const uart3_rts_grp0[] = { "uart3_rts_grp0", };
-static const char * const uart3_rts_grp1[] = { "uart3_rts_grp1", };
-static const char * const uart3_rts_grp2[] = { "uart3_rts_grp2", };
-static const char * const uart3_rxd_grp0[] = { "uart3_rxd_grp0", };
-static const char * const uart3_rxd_grp1[] = { "uart3_rxd_grp1", };
-static const char * const uart3_rxd_grp2[] = { "uart3_rxd_grp2", };
-static const char * const uart3_txd_grp0[] = { "uart3_txd_grp0", };
-static const char * const uart3_txd_grp1[] = { "uart3_txd_grp1", };
-static const char * const uart3_txd_grp2[] = { "uart3_txd_grp2", };
-static const char * const uart4_basic_grp[] = { "uart4_basic_grp", };
-static const char * const uart4_cts_grp0[] = { "uart4_cts_grp0", };
-static const char * const uart4_cts_grp1[] = { "uart4_cts_grp1", };
-static const char * const uart4_cts_grp2[] = { "uart4_cts_grp2", };
-static const char * const uart4_rts_grp0[] = { "uart4_rts_grp0", };
-static const char * const uart4_rts_grp1[] = { "uart4_rts_grp1", };
-static const char * const uart4_rts_grp2[] = { "uart4_rts_grp2", };
-static const char * const usb0_drvvbus_grp0[] = { "usb0_drvvbus_grp0", };
-static const char * const usb0_drvvbus_grp1[] = { "usb0_drvvbus_grp1", };
-static const char * const usb1_drvvbus_grp0[] = { "usb1_drvvbus_grp0", };
-static const char * const usb1_drvvbus_grp1[] = { "usb1_drvvbus_grp1", };
-static const char * const visbus_dout_grp[] = { "visbus_dout_grp", };
-static const char * const vi_vip1_grp[] = { "vi_vip1_grp", };
-static const char * const vi_vip1_ext_grp[] = { "vi_vip1_ext_grp", };
-static const char * const vi_vip1_low8bit_grp[] = { "vi_vip1_low8bit_grp", };
-static const char * const vi_vip1_high8bit_grp[] = { "vi_vip1_high8bit_grp", };
-
-static struct atlas7_pad_mux gnss_gpio_grp_pad_mux[] = {
-	MUX(1, 119, 0, N, N, N, N),
-	MUX(1, 120, 0, N, N, N, N),
-	MUX(1, 121, 0, N, N, N, N),
-	MUX(1, 122, 0, N, N, N, N),
-	MUX(1, 123, 0, N, N, N, N),
-	MUX(1, 124, 0, N, N, N, N),
-	MUX(1, 125, 0, N, N, N, N),
-	MUX(1, 126, 0, N, N, N, N),
-	MUX(1, 127, 0, N, N, N, N),
-	MUX(1, 128, 0, N, N, N, N),
-	MUX(1, 22, 0, N, N, N, N),
-	MUX(1, 23, 0, N, N, N, N),
-	MUX(1, 24, 0, N, N, N, N),
-	MUX(1, 25, 0, N, N, N, N),
-	MUX(1, 26, 0, N, N, N, N),
-	MUX(1, 27, 0, N, N, N, N),
-	MUX(1, 28, 0, N, N, N, N),
-	MUX(1, 29, 0, N, N, N, N),
-	MUX(1, 30, 0, N, N, N, N),
-};
-
-static struct atlas7_grp_mux gnss_gpio_grp_mux = {
-	.pad_mux_count = ARRAY_SIZE(gnss_gpio_grp_pad_mux),
-	.pad_mux_list = gnss_gpio_grp_pad_mux,
-};
-
-static struct atlas7_pad_mux lcd_vip_gpio_grp_pad_mux[] = {
-	MUX(1, 74, 0, N, N, N, N),
-	MUX(1, 75, 0, N, N, N, N),
-	MUX(1, 76, 0, N, N, N, N),
-	MUX(1, 77, 0, N, N, N, N),
-	MUX(1, 78, 0, N, N, N, N),
-	MUX(1, 79, 0, N, N, N, N),
-	MUX(1, 80, 0, N, N, N, N),
-	MUX(1, 81, 0, N, N, N, N),
-	MUX(1, 82, 0, N, N, N, N),
-	MUX(1, 83, 0, N, N, N, N),
-	MUX(1, 84, 0, N, N, N, N),
-	MUX(1, 53, 0, N, N, N, N),
-	MUX(1, 54, 0, N, N, N, N),
-	MUX(1, 55, 0, N, N, N, N),
-	MUX(1, 56, 0, N, N, N, N),
-	MUX(1, 57, 0, N, N, N, N),
-	MUX(1, 58, 0, N, N, N, N),
-	MUX(1, 59, 0, N, N, N, N),
-	MUX(1, 60, 0, N, N, N, N),
-	MUX(1, 61, 0, N, N, N, N),
-	MUX(1, 62, 0, N, N, N, N),
-	MUX(1, 63, 0, N, N, N, N),
-	MUX(1, 64, 0, N, N, N, N),
-	MUX(1, 65, 0, N, N, N, N),
-	MUX(1, 66, 0, N, N, N, N),
-	MUX(1, 67, 0, N, N, N, N),
-	MUX(1, 68, 0, N, N, N, N),
-	MUX(1, 69, 0, N, N, N, N),
-	MUX(1, 70, 0, N, N, N, N),
-	MUX(1, 71, 0, N, N, N, N),
-	MUX(1, 72, 0, N, N, N, N),
-	MUX(1, 73, 0, N, N, N, N),
-};
-
-static struct atlas7_grp_mux lcd_vip_gpio_grp_mux = {
-	.pad_mux_count = ARRAY_SIZE(lcd_vip_gpio_grp_pad_mux),
-	.pad_mux_list = lcd_vip_gpio_grp_pad_mux,
-};
-
-static struct atlas7_pad_mux sdio_i2s_gpio_grp_pad_mux[] = {
-	MUX(1, 31, 0, N, N, N, N),
-	MUX(1, 32, 0, N, N, N, N),
-	MUX(1, 33, 0, N, N, N, N),
-	MUX(1, 34, 0, N, N, N, N),
-	MUX(1, 35, 0, N, N, N, N),
-	MUX(1, 36, 0, N, N, N, N),
-	MUX(1, 85, 0, N, N, N, N),
-	MUX(1, 86, 0, N, N, N, N),
-	MUX(1, 87, 0, N, N, N, N),
-	MUX(1, 88, 0, N, N, N, N),
-	MUX(1, 89, 0, N, N, N, N),
-	MUX(1, 90, 0, N, N, N, N),
-	MUX(1, 129, 0, N, N, N, N),
-	MUX(1, 130, 0, N, N, N, N),
-	MUX(1, 131, 0, N, N, N, N),
-	MUX(1, 132, 0, N, N, N, N),
-	MUX(1, 91, 0, N, N, N, N),
-	MUX(1, 92, 0, N, N, N, N),
-	MUX(1, 93, 0, N, N, N, N),
-	MUX(1, 94, 0, N, N, N, N),
-	MUX(1, 95, 0, N, N, N, N),
-	MUX(1, 96, 0, N, N, N, N),
-	MUX(1, 112, 0, N, N, N, N),
-	MUX(1, 113, 0, N, N, N, N),
-	MUX(1, 114, 0, N, N, N, N),
-	MUX(1, 115, 0, N, N, N, N),
-	MUX(1, 116, 0, N, N, N, N),
-	MUX(1, 117, 0, N, N, N, N),
-	MUX(1, 118, 0, N, N, N, N),
-};
-
-static struct atlas7_grp_mux sdio_i2s_gpio_grp_mux = {
-	.pad_mux_count = ARRAY_SIZE(sdio_i2s_gpio_grp_pad_mux),
-	.pad_mux_list = sdio_i2s_gpio_grp_pad_mux,
-};
-
-static struct atlas7_pad_mux sp_rgmii_gpio_grp_pad_mux[] = {
-	MUX(1, 97, 0, N, N, N, N),
-	MUX(1, 98, 0, N, N, N, N),
-	MUX(1, 99, 0, N, N, N, N),
-	MUX(1, 100, 0, N, N, N, N),
-	MUX(1, 101, 0, N, N, N, N),
-	MUX(1, 102, 0, N, N, N, N),
-	MUX(1, 103, 0, N, N, N, N),
-	MUX(1, 104, 0, N, N, N, N),
-	MUX(1, 105, 0, N, N, N, N),
-	MUX(1, 106, 0, N, N, N, N),
-	MUX(1, 107, 0, N, N, N, N),
-	MUX(1, 108, 0, N, N, N, N),
-	MUX(1, 109, 0, N, N, N, N),
-	MUX(1, 110, 0, N, N, N, N),
-	MUX(1, 111, 0, N, N, N, N),
-	MUX(1, 18, 0, N, N, N, N),
-	MUX(1, 19, 0, N, N, N, N),
-	MUX(1, 20, 0, N, N, N, N),
-	MUX(1, 21, 0, N, N, N, N),
-	MUX(1, 141, 0, N, N, N, N),
-	MUX(1, 142, 0, N, N, N, N),
-	MUX(1, 143, 0, N, N, N, N),
-	MUX(1, 144, 0, N, N, N, N),
-	MUX(1, 145, 0, N, N, N, N),
-	MUX(1, 146, 0, N, N, N, N),
-	MUX(1, 147, 0, N, N, N, N),
-	MUX(1, 148, 0, N, N, N, N),
-};
-
-static struct atlas7_grp_mux sp_rgmii_gpio_grp_mux = {
-	.pad_mux_count = ARRAY_SIZE(sp_rgmii_gpio_grp_pad_mux),
-	.pad_mux_list = sp_rgmii_gpio_grp_pad_mux,
-};
-
-static struct atlas7_pad_mux lvds_gpio_grp_pad_mux[] = {
-	MUX(1, 157, 0, N, N, N, N),
-	MUX(1, 158, 0, N, N, N, N),
-	MUX(1, 155, 0, N, N, N, N),
-	MUX(1, 156, 0, N, N, N, N),
-	MUX(1, 153, 0, N, N, N, N),
-	MUX(1, 154, 0, N, N, N, N),
-	MUX(1, 151, 0, N, N, N, N),
-	MUX(1, 152, 0, N, N, N, N),
-	MUX(1, 149, 0, N, N, N, N),
-	MUX(1, 150, 0, N, N, N, N),
-};
-
-static struct atlas7_grp_mux lvds_gpio_grp_mux = {
-	.pad_mux_count = ARRAY_SIZE(lvds_gpio_grp_pad_mux),
-	.pad_mux_list = lvds_gpio_grp_pad_mux,
-};
-
-static struct atlas7_pad_mux jtag_uart_nand_gpio_grp_pad_mux[] = {
-	MUX(1, 44, 0, N, N, N, N),
-	MUX(1, 43, 0, N, N, N, N),
-	MUX(1, 42, 0, N, N, N, N),
-	MUX(1, 41, 0, N, N, N, N),
-	MUX(1, 40, 0, N, N, N, N),
-	MUX(1, 39, 0, N, N, N, N),
-	MUX(1, 38, 0, N, N, N, N),
-	MUX(1, 37, 0, N, N, N, N),
-	MUX(1, 46, 0, N, N, N, N),
-	MUX(1, 47, 0, N, N, N, N),
-	MUX(1, 48, 0, N, N, N, N),
-	MUX(1, 49, 0, N, N, N, N),
-	MUX(1, 50, 0, N, N, N, N),
-	MUX(1, 52, 0, N, N, N, N),
-	MUX(1, 51, 0, N, N, N, N),
-	MUX(1, 45, 0, N, N, N, N),
-	MUX(1, 133, 0, N, N, N, N),
-	MUX(1, 134, 0, N, N, N, N),
-	MUX(1, 135, 0, N, N, N, N),
-	MUX(1, 136, 0, N, N, N, N),
-	MUX(1, 137, 0, N, N, N, N),
-	MUX(1, 138, 0, N, N, N, N),
-	MUX(1, 139, 0, N, N, N, N),
-	MUX(1, 140, 0, N, N, N, N),
-	MUX(1, 159, 0, N, N, N, N),
-	MUX(1, 160, 0, N, N, N, N),
-	MUX(1, 161, 0, N, N, N, N),
-	MUX(1, 162, 0, N, N, N, N),
-	MUX(1, 163, 0, N, N, N, N),
-};
-
-static struct atlas7_grp_mux jtag_uart_nand_gpio_grp_mux = {
-	.pad_mux_count = ARRAY_SIZE(jtag_uart_nand_gpio_grp_pad_mux),
-	.pad_mux_list = jtag_uart_nand_gpio_grp_pad_mux,
-};
-
-static struct atlas7_pad_mux rtc_gpio_grp_pad_mux[] = {
-	MUX(0, 0, 0, N, N, N, N),
-	MUX(0, 1, 0, N, N, N, N),
-	MUX(0, 2, 0, N, N, N, N),
-	MUX(0, 3, 0, N, N, N, N),
-	MUX(0, 4, 0, N, N, N, N),
-	MUX(0, 10, 0, N, N, N, N),
-	MUX(0, 11, 0, N, N, N, N),
-	MUX(0, 12, 0, N, N, N, N),
-	MUX(0, 13, 0, N, N, N, N),
-	MUX(0, 14, 0, N, N, N, N),
-	MUX(0, 15, 0, N, N, N, N),
-	MUX(0, 16, 0, N, N, N, N),
-	MUX(0, 17, 0, N, N, N, N),
-	MUX(0, 9, 0, N, N, N, N),
-};
-
-static struct atlas7_grp_mux rtc_gpio_grp_mux = {
-	.pad_mux_count = ARRAY_SIZE(rtc_gpio_grp_pad_mux),
-	.pad_mux_list = rtc_gpio_grp_pad_mux,
-};
-
-static struct atlas7_pad_mux audio_ac97_grp_pad_mux[] = {
-	MUX(1, 113, 2, N, N, N, N),
-	MUX(1, 118, 2, N, N, N, N),
-	MUX(1, 115, 2, N, N, N, N),
-	MUX(1, 114, 2, N, N, N, N),
-};
-
-static struct atlas7_grp_mux audio_ac97_grp_mux = {
-	.pad_mux_count = ARRAY_SIZE(audio_ac97_grp_pad_mux),
-	.pad_mux_list = audio_ac97_grp_pad_mux,
-};
-
-static struct atlas7_pad_mux audio_digmic_grp0_pad_mux[] = {
-	MUX(1, 51, 3, 0xa10, 20, 0xa90, 20),
-};
-
-static struct atlas7_grp_mux audio_digmic_grp0_mux = {
-	.pad_mux_count = ARRAY_SIZE(audio_digmic_grp0_pad_mux),
-	.pad_mux_list = audio_digmic_grp0_pad_mux,
-};
-
-static struct atlas7_pad_mux audio_digmic_grp1_pad_mux[] = {
-	MUX(1, 122, 5, 0xa10, 20, 0xa90, 20),
-};
-
-static struct atlas7_grp_mux audio_digmic_grp1_mux = {
-	.pad_mux_count = ARRAY_SIZE(audio_digmic_grp1_pad_mux),
-	.pad_mux_list = audio_digmic_grp1_pad_mux,
-};
-
-static struct atlas7_pad_mux audio_digmic_grp2_pad_mux[] = {
-	MUX(1, 161, 7, 0xa10, 20, 0xa90, 20),
-};
-
-static struct atlas7_grp_mux audio_digmic_grp2_mux = {
-	.pad_mux_count = ARRAY_SIZE(audio_digmic_grp2_pad_mux),
-	.pad_mux_list = audio_digmic_grp2_pad_mux,
-};
-
-static struct atlas7_pad_mux audio_func_dbg_grp_pad_mux[] = {
-	MUX(1, 141, 4, N, N, N, N),
-	MUX(1, 144, 4, N, N, N, N),
-	MUX(1, 44, 6, N, N, N, N),
-	MUX(1, 43, 6, N, N, N, N),
-	MUX(1, 42, 6, N, N, N, N),
-	MUX(1, 41, 6, N, N, N, N),
-	MUX(1, 40, 6, N, N, N, N),
-	MUX(1, 39, 6, N, N, N, N),
-	MUX(1, 38, 6, N, N, N, N),
-	MUX(1, 37, 6, N, N, N, N),
-	MUX(1, 74, 6, N, N, N, N),
-	MUX(1, 75, 6, N, N, N, N),
-	MUX(1, 76, 6, N, N, N, N),
-	MUX(1, 77, 6, N, N, N, N),
-	MUX(1, 78, 6, N, N, N, N),
-	MUX(1, 79, 6, N, N, N, N),
-	MUX(1, 81, 6, N, N, N, N),
-	MUX(1, 113, 6, N, N, N, N),
-	MUX(1, 114, 6, N, N, N, N),
-	MUX(1, 118, 6, N, N, N, N),
-	MUX(1, 115, 6, N, N, N, N),
-	MUX(1, 49, 6, N, N, N, N),
-	MUX(1, 50, 6, N, N, N, N),
-	MUX(1, 142, 4, N, N, N, N),
-	MUX(1, 143, 4, N, N, N, N),
-	MUX(1, 80, 6, N, N, N, N),
-};
-
-static struct atlas7_grp_mux audio_func_dbg_grp_mux = {
-	.pad_mux_count = ARRAY_SIZE(audio_func_dbg_grp_pad_mux),
-	.pad_mux_list = audio_func_dbg_grp_pad_mux,
-};
-
-static struct atlas7_pad_mux audio_i2s_grp_pad_mux[] = {
-	MUX(1, 118, 1, N, N, N, N),
-	MUX(1, 115, 1, N, N, N, N),
-	MUX(1, 116, 1, N, N, N, N),
-	MUX(1, 117, 1, N, N, N, N),
-	MUX(1, 112, 1, N, N, N, N),
-	MUX(1, 113, 1, N, N, N, N),
-	MUX(1, 114, 1, N, N, N, N),
-};
-
-static struct atlas7_grp_mux audio_i2s_grp_mux = {
-	.pad_mux_count = ARRAY_SIZE(audio_i2s_grp_pad_mux),
-	.pad_mux_list = audio_i2s_grp_pad_mux,
-};
-
-static struct atlas7_pad_mux audio_i2s_2ch_grp_pad_mux[] = {
-	MUX(1, 118, 1, N, N, N, N),
-	MUX(1, 115, 1, N, N, N, N),
-	MUX(1, 112, 1, N, N, N, N),
-	MUX(1, 113, 1, N, N, N, N),
-	MUX(1, 114, 1, N, N, N, N),
-};
-
-static struct atlas7_grp_mux audio_i2s_2ch_grp_mux = {
-	.pad_mux_count = ARRAY_SIZE(audio_i2s_2ch_grp_pad_mux),
-	.pad_mux_list = audio_i2s_2ch_grp_pad_mux,
-};
-
-static struct atlas7_pad_mux audio_i2s_extclk_grp_pad_mux[] = {
-	MUX(1, 112, 2, N, N, N, N),
-};
-
-static struct atlas7_grp_mux audio_i2s_extclk_grp_mux = {
-	.pad_mux_count = ARRAY_SIZE(audio_i2s_extclk_grp_pad_mux),
-	.pad_mux_list = audio_i2s_extclk_grp_pad_mux,
-};
-
-static struct atlas7_pad_mux audio_spdif_out_grp0_pad_mux[] = {
-	MUX(1, 112, 3, N, N, N, N),
-};
-
-static struct atlas7_grp_mux audio_spdif_out_grp0_mux = {
-	.pad_mux_count = ARRAY_SIZE(audio_spdif_out_grp0_pad_mux),
-	.pad_mux_list = audio_spdif_out_grp0_pad_mux,
-};
-
-static struct atlas7_pad_mux audio_spdif_out_grp1_pad_mux[] = {
-	MUX(1, 116, 3, N, N, N, N),
-};
-
-static struct atlas7_grp_mux audio_spdif_out_grp1_mux = {
-	.pad_mux_count = ARRAY_SIZE(audio_spdif_out_grp1_pad_mux),
-	.pad_mux_list = audio_spdif_out_grp1_pad_mux,
-};
-
-static struct atlas7_pad_mux audio_spdif_out_grp2_pad_mux[] = {
-	MUX(1, 142, 3, N, N, N, N),
-};
-
-static struct atlas7_grp_mux audio_spdif_out_grp2_mux = {
-	.pad_mux_count = ARRAY_SIZE(audio_spdif_out_grp2_pad_mux),
-	.pad_mux_list = audio_spdif_out_grp2_pad_mux,
-};
-
-static struct atlas7_pad_mux audio_uart0_basic_grp_pad_mux[] = {
-	MUX(1, 143, 1, N, N, N, N),
-	MUX(1, 142, 1, N, N, N, N),
-	MUX(1, 141, 1, N, N, N, N),
-	MUX(1, 144, 1, N, N, N, N),
-};
-
-static struct atlas7_grp_mux audio_uart0_basic_grp_mux = {
-	.pad_mux_count = ARRAY_SIZE(audio_uart0_basic_grp_pad_mux),
-	.pad_mux_list = audio_uart0_basic_grp_pad_mux,
-};
-
-static struct atlas7_pad_mux audio_uart0_urfs_grp0_pad_mux[] = {
-	MUX(1, 117, 5, 0xa10, 28, 0xa90, 28),
-};
-
-static struct atlas7_grp_mux audio_uart0_urfs_grp0_mux = {
-	.pad_mux_count = ARRAY_SIZE(audio_uart0_urfs_grp0_pad_mux),
-	.pad_mux_list = audio_uart0_urfs_grp0_pad_mux,
-};
-
-static struct atlas7_pad_mux audio_uart0_urfs_grp1_pad_mux[] = {
-	MUX(1, 139, 3, 0xa10, 28, 0xa90, 28),
-};
-
-static struct atlas7_grp_mux audio_uart0_urfs_grp1_mux = {
-	.pad_mux_count = ARRAY_SIZE(audio_uart0_urfs_grp1_pad_mux),
-	.pad_mux_list = audio_uart0_urfs_grp1_pad_mux,
-};
-
-static struct atlas7_pad_mux audio_uart0_urfs_grp2_pad_mux[] = {
-	MUX(1, 163, 3, 0xa10, 28, 0xa90, 28),
-};
-
-static struct atlas7_grp_mux audio_uart0_urfs_grp2_mux = {
-	.pad_mux_count = ARRAY_SIZE(audio_uart0_urfs_grp2_pad_mux),
-	.pad_mux_list = audio_uart0_urfs_grp2_pad_mux,
-};
-
-static struct atlas7_pad_mux audio_uart0_urfs_grp3_pad_mux[] = {
-	MUX(1, 162, 6, 0xa10, 28, 0xa90, 28),
-};
-
-static struct atlas7_grp_mux audio_uart0_urfs_grp3_mux = {
-	.pad_mux_count = ARRAY_SIZE(audio_uart0_urfs_grp3_pad_mux),
-	.pad_mux_list = audio_uart0_urfs_grp3_pad_mux,
-};
-
-static struct atlas7_pad_mux audio_uart1_basic_grp_pad_mux[] = {
-	MUX(1, 147, 1, 0xa10, 24, 0xa90, 24),
-	MUX(1, 146, 1, 0xa10, 25, 0xa90, 25),
-	MUX(1, 145, 1, 0xa10, 23, 0xa90, 23),
-	MUX(1, 148, 1, 0xa10, 22, 0xa90, 22),
-};
-
-static struct atlas7_grp_mux audio_uart1_basic_grp_mux = {
-	.pad_mux_count = ARRAY_SIZE(audio_uart1_basic_grp_pad_mux),
-	.pad_mux_list = audio_uart1_basic_grp_pad_mux,
-};
-
-static struct atlas7_pad_mux audio_uart1_urfs_grp0_pad_mux[] = {
-	MUX(1, 117, 6, 0xa10, 29, 0xa90, 29),
-};
-
-static struct atlas7_grp_mux audio_uart1_urfs_grp0_mux = {
-	.pad_mux_count = ARRAY_SIZE(audio_uart1_urfs_grp0_pad_mux),
-	.pad_mux_list = audio_uart1_urfs_grp0_pad_mux,
-};
-
-static struct atlas7_pad_mux audio_uart1_urfs_grp1_pad_mux[] = {
-	MUX(1, 140, 3, 0xa10, 29, 0xa90, 29),
-};
-
-static struct atlas7_grp_mux audio_uart1_urfs_grp1_mux = {
-	.pad_mux_count = ARRAY_SIZE(audio_uart1_urfs_grp1_pad_mux),
-	.pad_mux_list = audio_uart1_urfs_grp1_pad_mux,
-};
-
-static struct atlas7_pad_mux audio_uart1_urfs_grp2_pad_mux[] = {
-	MUX(1, 163, 4, 0xa10, 29, 0xa90, 29),
-};
-
-static struct atlas7_grp_mux audio_uart1_urfs_grp2_mux = {
-	.pad_mux_count = ARRAY_SIZE(audio_uart1_urfs_grp2_pad_mux),
-	.pad_mux_list = audio_uart1_urfs_grp2_pad_mux,
-};
-
-static struct atlas7_pad_mux audio_uart2_urfs_grp0_pad_mux[] = {
-	MUX(1, 139, 4, 0xa10, 30, 0xa90, 30),
-};
-
-static struct atlas7_grp_mux audio_uart2_urfs_grp0_mux = {
-	.pad_mux_count = ARRAY_SIZE(audio_uart2_urfs_grp0_pad_mux),
-	.pad_mux_list = audio_uart2_urfs_grp0_pad_mux,
-};
-
-static struct atlas7_pad_mux audio_uart2_urfs_grp1_pad_mux[] = {
-	MUX(1, 163, 6, 0xa10, 30, 0xa90, 30),
-};
-
-static struct atlas7_grp_mux audio_uart2_urfs_grp1_mux = {
-	.pad_mux_count = ARRAY_SIZE(audio_uart2_urfs_grp1_pad_mux),
-	.pad_mux_list = audio_uart2_urfs_grp1_pad_mux,
-};
-
-static struct atlas7_pad_mux audio_uart2_urfs_grp2_pad_mux[] = {
-	MUX(1, 96, 3, 0xa10, 30, 0xa90, 30),
-};
-
-static struct atlas7_grp_mux audio_uart2_urfs_grp2_mux = {
-	.pad_mux_count = ARRAY_SIZE(audio_uart2_urfs_grp2_pad_mux),
-	.pad_mux_list = audio_uart2_urfs_grp2_pad_mux,
-};
-
-static struct atlas7_pad_mux audio_uart2_urxd_grp0_pad_mux[] = {
-	MUX(1, 20, 2, 0xa00, 24, 0xa80, 24),
-};
-
-static struct atlas7_grp_mux audio_uart2_urxd_grp0_mux = {
-	.pad_mux_count = ARRAY_SIZE(audio_uart2_urxd_grp0_pad_mux),
-	.pad_mux_list = audio_uart2_urxd_grp0_pad_mux,
-};
-
-static struct atlas7_pad_mux audio_uart2_urxd_grp1_pad_mux[] = {
-	MUX(1, 109, 2, 0xa00, 24, 0xa80, 24),
-};
-
-static struct atlas7_grp_mux audio_uart2_urxd_grp1_mux = {
-	.pad_mux_count = ARRAY_SIZE(audio_uart2_urxd_grp1_pad_mux),
-	.pad_mux_list = audio_uart2_urxd_grp1_pad_mux,
-};
-
-static struct atlas7_pad_mux audio_uart2_urxd_grp2_pad_mux[] = {
-	MUX(1, 93, 3, 0xa00, 24, 0xa80, 24),
-};
-
-static struct atlas7_grp_mux audio_uart2_urxd_grp2_mux = {
-	.pad_mux_count = ARRAY_SIZE(audio_uart2_urxd_grp2_pad_mux),
-	.pad_mux_list = audio_uart2_urxd_grp2_pad_mux,
-};
-
-static struct atlas7_pad_mux audio_uart2_usclk_grp0_pad_mux[] = {
-	MUX(1, 19, 2, 0xa00, 23, 0xa80, 23),
-};
-
-static struct atlas7_grp_mux audio_uart2_usclk_grp0_mux = {
-	.pad_mux_count = ARRAY_SIZE(audio_uart2_usclk_grp0_pad_mux),
-	.pad_mux_list = audio_uart2_usclk_grp0_pad_mux,
-};
-
-static struct atlas7_pad_mux audio_uart2_usclk_grp1_pad_mux[] = {
-	MUX(1, 101, 2, 0xa00, 23, 0xa80, 23),
-};
-
-static struct atlas7_grp_mux audio_uart2_usclk_grp1_mux = {
-	.pad_mux_count = ARRAY_SIZE(audio_uart2_usclk_grp1_pad_mux),
-	.pad_mux_list = audio_uart2_usclk_grp1_pad_mux,
-};
-
-static struct atlas7_pad_mux audio_uart2_usclk_grp2_pad_mux[] = {
-	MUX(1, 91, 3, 0xa00, 23, 0xa80, 23),
-};
-
-static struct atlas7_grp_mux audio_uart2_usclk_grp2_mux = {
-	.pad_mux_count = ARRAY_SIZE(audio_uart2_usclk_grp2_pad_mux),
-	.pad_mux_list = audio_uart2_usclk_grp2_pad_mux,
-};
-
-static struct atlas7_pad_mux audio_uart2_utfs_grp0_pad_mux[] = {
-	MUX(1, 18, 2, 0xa00, 22, 0xa80, 22),
-};
-
-static struct atlas7_grp_mux audio_uart2_utfs_grp0_mux = {
-	.pad_mux_count = ARRAY_SIZE(audio_uart2_utfs_grp0_pad_mux),
-	.pad_mux_list = audio_uart2_utfs_grp0_pad_mux,
-};
-
-static struct atlas7_pad_mux audio_uart2_utfs_grp1_pad_mux[] = {
-	MUX(1, 111, 2, 0xa00, 22, 0xa80, 22),
-};
-
-static struct atlas7_grp_mux audio_uart2_utfs_grp1_mux = {
-	.pad_mux_count = ARRAY_SIZE(audio_uart2_utfs_grp1_pad_mux),
-	.pad_mux_list = audio_uart2_utfs_grp1_pad_mux,
-};
-
-static struct atlas7_pad_mux audio_uart2_utfs_grp2_pad_mux[] = {
-	MUX(1, 94, 3, 0xa00, 22, 0xa80, 22),
-};
-
-static struct atlas7_grp_mux audio_uart2_utfs_grp2_mux = {
-	.pad_mux_count = ARRAY_SIZE(audio_uart2_utfs_grp2_pad_mux),
-	.pad_mux_list = audio_uart2_utfs_grp2_pad_mux,
-};
-
-static struct atlas7_pad_mux audio_uart2_utxd_grp0_pad_mux[] = {
-	MUX(1, 21, 2, 0xa00, 25, 0xa80, 25),
-};
-
-static struct atlas7_grp_mux audio_uart2_utxd_grp0_mux = {
-	.pad_mux_count = ARRAY_SIZE(audio_uart2_utxd_grp0_pad_mux),
-	.pad_mux_list = audio_uart2_utxd_grp0_pad_mux,
-};
-
-static struct atlas7_pad_mux audio_uart2_utxd_grp1_pad_mux[] = {
-	MUX(1, 110, 2, 0xa00, 25, 0xa80, 25),
-};
-
-static struct atlas7_grp_mux audio_uart2_utxd_grp1_mux = {
-	.pad_mux_count = ARRAY_SIZE(audio_uart2_utxd_grp1_pad_mux),
-	.pad_mux_list = audio_uart2_utxd_grp1_pad_mux,
-};
-
-static struct atlas7_pad_mux audio_uart2_utxd_grp2_pad_mux[] = {
-	MUX(1, 92, 3, 0xa00, 25, 0xa80, 25),
-};
-
-static struct atlas7_grp_mux audio_uart2_utxd_grp2_mux = {
-	.pad_mux_count = ARRAY_SIZE(audio_uart2_utxd_grp2_pad_mux),
-	.pad_mux_list = audio_uart2_utxd_grp2_pad_mux,
-};
-
-static struct atlas7_pad_mux c_can_trnsvr_en_grp0_pad_mux[] = {
-	MUX(0, 2, 6, N, N, N, N),
-};
-
-static struct atlas7_grp_mux c_can_trnsvr_en_grp0_mux = {
-	.pad_mux_count = ARRAY_SIZE(c_can_trnsvr_en_grp0_pad_mux),
-	.pad_mux_list = c_can_trnsvr_en_grp0_pad_mux,
-};
-
-static struct atlas7_pad_mux c_can_trnsvr_en_grp1_pad_mux[] = {
-	MUX(0, 0, 2, N, N, N, N),
-};
-
-static struct atlas7_grp_mux c_can_trnsvr_en_grp1_mux = {
-	.pad_mux_count = ARRAY_SIZE(c_can_trnsvr_en_grp1_pad_mux),
-	.pad_mux_list = c_can_trnsvr_en_grp1_pad_mux,
-};
-
-static struct atlas7_pad_mux c_can_trnsvr_intr_grp_pad_mux[] = {
-	MUX(0, 1, 2, N, N, N, N),
-};
-
-static struct atlas7_grp_mux c_can_trnsvr_intr_grp_mux = {
-	.pad_mux_count = ARRAY_SIZE(c_can_trnsvr_intr_grp_pad_mux),
-	.pad_mux_list = c_can_trnsvr_intr_grp_pad_mux,
-};
-
-static struct atlas7_pad_mux c_can_trnsvr_stb_n_grp_pad_mux[] = {
-	MUX(0, 3, 6, N, N, N, N),
-};
-
-static struct atlas7_grp_mux c_can_trnsvr_stb_n_grp_mux = {
-	.pad_mux_count = ARRAY_SIZE(c_can_trnsvr_stb_n_grp_pad_mux),
-	.pad_mux_list = c_can_trnsvr_stb_n_grp_pad_mux,
-};
-
-static struct atlas7_pad_mux c0_can_rxd_trnsv0_grp_pad_mux[] = {
-	MUX(0, 11, 1, 0xa08, 9, 0xa88, 9),
-};
-
-static struct atlas7_grp_mux c0_can_rxd_trnsv0_grp_mux = {
-	.pad_mux_count = ARRAY_SIZE(c0_can_rxd_trnsv0_grp_pad_mux),
-	.pad_mux_list = c0_can_rxd_trnsv0_grp_pad_mux,
-};
-
-static struct atlas7_pad_mux c0_can_rxd_trnsv1_grp_pad_mux[] = {
-	MUX(0, 2, 5, 0xa10, 9, 0xa90, 9),
-};
-
-static struct atlas7_grp_mux c0_can_rxd_trnsv1_grp_mux = {
-	.pad_mux_count = ARRAY_SIZE(c0_can_rxd_trnsv1_grp_pad_mux),
-	.pad_mux_list = c0_can_rxd_trnsv1_grp_pad_mux,
-};
-
-static struct atlas7_pad_mux c0_can_txd_trnsv0_grp_pad_mux[] = {
-	MUX(0, 10, 1, N, N, N, N),
-};
-
-static struct atlas7_grp_mux c0_can_txd_trnsv0_grp_mux = {
-	.pad_mux_count = ARRAY_SIZE(c0_can_txd_trnsv0_grp_pad_mux),
-	.pad_mux_list = c0_can_txd_trnsv0_grp_pad_mux,
-};
-
-static struct atlas7_pad_mux c0_can_txd_trnsv1_grp_pad_mux[] = {
-	MUX(0, 3, 5, N, N, N, N),
-};
-
-static struct atlas7_grp_mux c0_can_txd_trnsv1_grp_mux = {
-	.pad_mux_count = ARRAY_SIZE(c0_can_txd_trnsv1_grp_pad_mux),
-	.pad_mux_list = c0_can_txd_trnsv1_grp_pad_mux,
-};
-
-static struct atlas7_pad_mux c1_can_rxd_grp0_pad_mux[] = {
-	MUX(1, 138, 2, 0xa00, 4, 0xa80, 4),
-};
-
-static struct atlas7_grp_mux c1_can_rxd_grp0_mux = {
-	.pad_mux_count = ARRAY_SIZE(c1_can_rxd_grp0_pad_mux),
-	.pad_mux_list = c1_can_rxd_grp0_pad_mux,
-};
-
-static struct atlas7_pad_mux c1_can_rxd_grp1_pad_mux[] = {
-	MUX(1, 147, 2, 0xa00, 4, 0xa80, 4),
-};
-
-static struct atlas7_grp_mux c1_can_rxd_grp1_mux = {
-	.pad_mux_count = ARRAY_SIZE(c1_can_rxd_grp1_pad_mux),
-	.pad_mux_list = c1_can_rxd_grp1_pad_mux,
-};
-
-static struct atlas7_pad_mux c1_can_rxd_grp2_pad_mux[] = {
-	MUX(0, 2, 2, 0xa00, 4, 0xa80, 4),
-};
-
-static struct atlas7_grp_mux c1_can_rxd_grp2_mux = {
-	.pad_mux_count = ARRAY_SIZE(c1_can_rxd_grp2_pad_mux),
-	.pad_mux_list = c1_can_rxd_grp2_pad_mux,
-};
-
-static struct atlas7_pad_mux c1_can_rxd_grp3_pad_mux[] = {
-	MUX(1, 162, 4, 0xa00, 4, 0xa80, 4),
-};
-
-static struct atlas7_grp_mux c1_can_rxd_grp3_mux = {
-	.pad_mux_count = ARRAY_SIZE(c1_can_rxd_grp3_pad_mux),
-	.pad_mux_list = c1_can_rxd_grp3_pad_mux,
-};
-
-static struct atlas7_pad_mux c1_can_txd_grp0_pad_mux[] = {
-	MUX(1, 137, 2, N, N, N, N),
-};
-
-static struct atlas7_grp_mux c1_can_txd_grp0_mux = {
-	.pad_mux_count = ARRAY_SIZE(c1_can_txd_grp0_pad_mux),
-	.pad_mux_list = c1_can_txd_grp0_pad_mux,
-};
-
-static struct atlas7_pad_mux c1_can_txd_grp1_pad_mux[] = {
-	MUX(1, 146, 2, N, N, N, N),
-};
-
-static struct atlas7_grp_mux c1_can_txd_grp1_mux = {
-	.pad_mux_count = ARRAY_SIZE(c1_can_txd_grp1_pad_mux),
-	.pad_mux_list = c1_can_txd_grp1_pad_mux,
-};
-
-static struct atlas7_pad_mux c1_can_txd_grp2_pad_mux[] = {
-	MUX(0, 3, 2, N, N, N, N),
-};
-
-static struct atlas7_grp_mux c1_can_txd_grp2_mux = {
-	.pad_mux_count = ARRAY_SIZE(c1_can_txd_grp2_pad_mux),
-	.pad_mux_list = c1_can_txd_grp2_pad_mux,
-};
-
-static struct atlas7_pad_mux c1_can_txd_grp3_pad_mux[] = {
-	MUX(1, 161, 4, N, N, N, N),
-};
-
-static struct atlas7_grp_mux c1_can_txd_grp3_mux = {
-	.pad_mux_count = ARRAY_SIZE(c1_can_txd_grp3_pad_mux),
-	.pad_mux_list = c1_can_txd_grp3_pad_mux,
-};
-
-static struct atlas7_pad_mux ca_audio_lpc_grp_pad_mux[] = {
-	MUX(1, 62, 4, N, N, N, N),
-	MUX(1, 63, 4, N, N, N, N),
-	MUX(1, 64, 4, N, N, N, N),
-	MUX(1, 65, 4, N, N, N, N),
-	MUX(1, 66, 4, N, N, N, N),
-	MUX(1, 67, 4, N, N, N, N),
-	MUX(1, 68, 4, N, N, N, N),
-	MUX(1, 69, 4, N, N, N, N),
-	MUX(1, 70, 4, N, N, N, N),
-	MUX(1, 71, 4, N, N, N, N),
-};
-
-static struct atlas7_grp_mux ca_audio_lpc_grp_mux = {
-	.pad_mux_count = ARRAY_SIZE(ca_audio_lpc_grp_pad_mux),
-	.pad_mux_list = ca_audio_lpc_grp_pad_mux,
-};
-
-static struct atlas7_pad_mux ca_bt_lpc_grp_pad_mux[] = {
-	MUX(1, 85, 5, N, N, N, N),
-	MUX(1, 86, 5, N, N, N, N),
-	MUX(1, 87, 5, N, N, N, N),
-	MUX(1, 88, 5, N, N, N, N),
-	MUX(1, 89, 5, N, N, N, N),
-	MUX(1, 90, 5, N, N, N, N),
-};
-
-static struct atlas7_grp_mux ca_bt_lpc_grp_mux = {
-	.pad_mux_count = ARRAY_SIZE(ca_bt_lpc_grp_pad_mux),
-	.pad_mux_list = ca_bt_lpc_grp_pad_mux,
-};
-
-static struct atlas7_pad_mux ca_coex_grp_pad_mux[] = {
-	MUX(1, 129, 1, N, N, N, N),
-	MUX(1, 130, 1, N, N, N, N),
-	MUX(1, 131, 1, N, N, N, N),
-	MUX(1, 132, 1, N, N, N, N),
-};
-
-static struct atlas7_grp_mux ca_coex_grp_mux = {
-	.pad_mux_count = ARRAY_SIZE(ca_coex_grp_pad_mux),
-	.pad_mux_list = ca_coex_grp_pad_mux,
-};
-
-static struct atlas7_pad_mux ca_curator_lpc_grp_pad_mux[] = {
-	MUX(1, 57, 4, N, N, N, N),
-	MUX(1, 58, 4, N, N, N, N),
-	MUX(1, 59, 4, N, N, N, N),
-	MUX(1, 60, 4, N, N, N, N),
-};
-
-static struct atlas7_grp_mux ca_curator_lpc_grp_mux = {
-	.pad_mux_count = ARRAY_SIZE(ca_curator_lpc_grp_pad_mux),
-	.pad_mux_list = ca_curator_lpc_grp_pad_mux,
-};
-
-static struct atlas7_pad_mux ca_pcm_debug_grp_pad_mux[] = {
-	MUX(1, 91, 5, N, N, N, N),
-	MUX(1, 93, 5, N, N, N, N),
-	MUX(1, 94, 5, N, N, N, N),
-	MUX(1, 92, 5, N, N, N, N),
-};
-
-static struct atlas7_grp_mux ca_pcm_debug_grp_mux = {
-	.pad_mux_count = ARRAY_SIZE(ca_pcm_debug_grp_pad_mux),
-	.pad_mux_list = ca_pcm_debug_grp_pad_mux,
-};
-
-static struct atlas7_pad_mux ca_pio_grp_pad_mux[] = {
-	MUX(1, 121, 2, N, N, N, N),
-	MUX(1, 122, 2, N, N, N, N),
-	MUX(1, 125, 6, N, N, N, N),
-	MUX(1, 126, 6, N, N, N, N),
-	MUX(1, 38, 5, N, N, N, N),
-	MUX(1, 37, 5, N, N, N, N),
-	MUX(1, 47, 5, N, N, N, N),
-	MUX(1, 49, 5, N, N, N, N),
-	MUX(1, 50, 5, N, N, N, N),
-	MUX(1, 54, 4, N, N, N, N),
-	MUX(1, 55, 4, N, N, N, N),
-	MUX(1, 56, 4, N, N, N, N),
-};
-
-static struct atlas7_grp_mux ca_pio_grp_mux = {
-	.pad_mux_count = ARRAY_SIZE(ca_pio_grp_pad_mux),
-	.pad_mux_list = ca_pio_grp_pad_mux,
-};
-
-static struct atlas7_pad_mux ca_sdio_debug_grp_pad_mux[] = {
-	MUX(1, 40, 5, N, N, N, N),
-	MUX(1, 39, 5, N, N, N, N),
-	MUX(1, 44, 5, N, N, N, N),
-	MUX(1, 43, 5, N, N, N, N),
-	MUX(1, 42, 5, N, N, N, N),
-	MUX(1, 41, 5, N, N, N, N),
-};
-
-static struct atlas7_grp_mux ca_sdio_debug_grp_mux = {
-	.pad_mux_count = ARRAY_SIZE(ca_sdio_debug_grp_pad_mux),
-	.pad_mux_list = ca_sdio_debug_grp_pad_mux,
-};
-
-static struct atlas7_pad_mux ca_spi_grp_pad_mux[] = {
-	MUX(1, 82, 5, N, N, N, N),
-	MUX(1, 79, 5, 0xa08, 6, 0xa88, 6),
-	MUX(1, 80, 5, N, N, N, N),
-	MUX(1, 81, 5, N, N, N, N),
-};
-
-static struct atlas7_grp_mux ca_spi_grp_mux = {
-	.pad_mux_count = ARRAY_SIZE(ca_spi_grp_pad_mux),
-	.pad_mux_list = ca_spi_grp_pad_mux,
-};
-
-static struct atlas7_pad_mux ca_trb_grp_pad_mux[] = {
-	MUX(1, 91, 4, N, N, N, N),
-	MUX(1, 93, 4, N, N, N, N),
-	MUX(1, 94, 4, N, N, N, N),
-	MUX(1, 95, 4, N, N, N, N),
-	MUX(1, 96, 4, N, N, N, N),
-	MUX(1, 78, 5, N, N, N, N),
-	MUX(1, 74, 5, N, N, N, N),
-	MUX(1, 75, 5, N, N, N, N),
-	MUX(1, 76, 5, N, N, N, N),
-	MUX(1, 77, 5, N, N, N, N),
-};
-
-static struct atlas7_grp_mux ca_trb_grp_mux = {
-	.pad_mux_count = ARRAY_SIZE(ca_trb_grp_pad_mux),
-	.pad_mux_list = ca_trb_grp_pad_mux,
-};
-
-static struct atlas7_pad_mux ca_uart_debug_grp_pad_mux[] = {
-	MUX(1, 136, 3, N, N, N, N),
-	MUX(1, 135, 3, N, N, N, N),
-	MUX(1, 134, 3, N, N, N, N),
-	MUX(1, 133, 3, N, N, N, N),
-};
-
-static struct atlas7_grp_mux ca_uart_debug_grp_mux = {
-	.pad_mux_count = ARRAY_SIZE(ca_uart_debug_grp_pad_mux),
-	.pad_mux_list = ca_uart_debug_grp_pad_mux,
-};
-
-static struct atlas7_pad_mux clkc_grp0_pad_mux[] = {
-	MUX(1, 30, 2, 0xa08, 14, 0xa88, 14),
-	MUX(1, 47, 6, N, N, N, N),
-};
-
-static struct atlas7_grp_mux clkc_grp0_mux = {
-	.pad_mux_count = ARRAY_SIZE(clkc_grp0_pad_mux),
-	.pad_mux_list = clkc_grp0_pad_mux,
-};
-
-static struct atlas7_pad_mux clkc_grp1_pad_mux[] = {
-	MUX(1, 78, 3, 0xa08, 14, 0xa88, 14),
-	MUX(1, 54, 5, N, N, N, N),
-};
-
-static struct atlas7_grp_mux clkc_grp1_mux = {
-	.pad_mux_count = ARRAY_SIZE(clkc_grp1_pad_mux),
-	.pad_mux_list = clkc_grp1_pad_mux,
-};
-
-static struct atlas7_pad_mux gn_gnss_i2c_grp_pad_mux[] = {
-	MUX(1, 128, 2, N, N, N, N),
-	MUX(1, 127, 2, N, N, N, N),
-};
-
-static struct atlas7_grp_mux gn_gnss_i2c_grp_mux = {
-	.pad_mux_count = ARRAY_SIZE(gn_gnss_i2c_grp_pad_mux),
-	.pad_mux_list = gn_gnss_i2c_grp_pad_mux,
-};
-
-static struct atlas7_pad_mux gn_gnss_uart_nopause_grp_pad_mux[] = {
-	MUX(1, 134, 4, N, N, N, N),
-	MUX(1, 133, 4, N, N, N, N),
-};
-
-static struct atlas7_grp_mux gn_gnss_uart_nopause_grp_mux = {
-	.pad_mux_count = ARRAY_SIZE(gn_gnss_uart_nopause_grp_pad_mux),
-	.pad_mux_list = gn_gnss_uart_nopause_grp_pad_mux,
-};
-
-static struct atlas7_pad_mux gn_gnss_uart_grp_pad_mux[] = {
-	MUX(1, 134, 4, N, N, N, N),
-	MUX(1, 133, 4, N, N, N, N),
-	MUX(1, 136, 4, N, N, N, N),
-	MUX(1, 135, 4, N, N, N, N),
-};
-
-static struct atlas7_grp_mux gn_gnss_uart_grp_mux = {
-	.pad_mux_count = ARRAY_SIZE(gn_gnss_uart_grp_pad_mux),
-	.pad_mux_list = gn_gnss_uart_grp_pad_mux,
-};
-
-static struct atlas7_pad_mux gn_trg_spi_grp0_pad_mux[] = {
-	MUX(1, 22, 1, N, N, N, N),
-	MUX(1, 25, 1, N, N, N, N),
-	MUX(1, 23, 1, 0xa00, 10, 0xa80, 10),
-	MUX(1, 24, 1, N, N, N, N),
-};
-
-static struct atlas7_grp_mux gn_trg_spi_grp0_mux = {
-	.pad_mux_count = ARRAY_SIZE(gn_trg_spi_grp0_pad_mux),
-	.pad_mux_list = gn_trg_spi_grp0_pad_mux,
-};
-
-static struct atlas7_pad_mux gn_trg_spi_grp1_pad_mux[] = {
-	MUX(1, 82, 3, N, N, N, N),
-	MUX(1, 79, 3, N, N, N, N),
-	MUX(1, 80, 3, 0xa00, 10, 0xa80, 10),
-	MUX(1, 81, 3, N, N, N, N),
-};
-
-static struct atlas7_grp_mux gn_trg_spi_grp1_mux = {
-	.pad_mux_count = ARRAY_SIZE(gn_trg_spi_grp1_pad_mux),
-	.pad_mux_list = gn_trg_spi_grp1_pad_mux,
-};
-
-static struct atlas7_pad_mux cvbs_dbg_grp_pad_mux[] = {
-	MUX(1, 54, 3, N, N, N, N),
-	MUX(1, 53, 3, N, N, N, N),
-	MUX(1, 82, 7, N, N, N, N),
-	MUX(1, 74, 7, N, N, N, N),
-	MUX(1, 75, 7, N, N, N, N),
-	MUX(1, 76, 7, N, N, N, N),
-	MUX(1, 77, 7, N, N, N, N),
-	MUX(1, 78, 7, N, N, N, N),
-	MUX(1, 79, 7, N, N, N, N),
-	MUX(1, 80, 7, N, N, N, N),
-	MUX(1, 81, 7, N, N, N, N),
-	MUX(1, 83, 7, N, N, N, N),
-	MUX(1, 84, 7, N, N, N, N),
-	MUX(1, 73, 3, N, N, N, N),
-	MUX(1, 55, 3, N, N, N, N),
-	MUX(1, 56, 3, N, N, N, N),
-};
-
-static struct atlas7_grp_mux cvbs_dbg_grp_mux = {
-	.pad_mux_count = ARRAY_SIZE(cvbs_dbg_grp_pad_mux),
-	.pad_mux_list = cvbs_dbg_grp_pad_mux,
-};
-
-static struct atlas7_pad_mux cvbs_dbg_test_grp0_pad_mux[] = {
-	MUX(1, 57, 3, N, N, N, N),
-};
-
-static struct atlas7_grp_mux cvbs_dbg_test_grp0_mux = {
-	.pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp0_pad_mux),
-	.pad_mux_list = cvbs_dbg_test_grp0_pad_mux,
-};
-
-static struct atlas7_pad_mux cvbs_dbg_test_grp1_pad_mux[] = {
-	MUX(1, 58, 3, N, N, N, N),
-};
-
-static struct atlas7_grp_mux cvbs_dbg_test_grp1_mux = {
-	.pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp1_pad_mux),
-	.pad_mux_list = cvbs_dbg_test_grp1_pad_mux,
-};
-
-static struct atlas7_pad_mux cvbs_dbg_test_grp2_pad_mux[] = {
-	MUX(1, 59, 3, N, N, N, N),
-};
-
-static struct atlas7_grp_mux cvbs_dbg_test_grp2_mux = {
-	.pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp2_pad_mux),
-	.pad_mux_list = cvbs_dbg_test_grp2_pad_mux,
-};
-
-static struct atlas7_pad_mux cvbs_dbg_test_grp3_pad_mux[] = {
-	MUX(1, 60, 3, N, N, N, N),
-};
-
-static struct atlas7_grp_mux cvbs_dbg_test_grp3_mux = {
-	.pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp3_pad_mux),
-	.pad_mux_list = cvbs_dbg_test_grp3_pad_mux,
-};
-
-static struct atlas7_pad_mux cvbs_dbg_test_grp4_pad_mux[] = {
-	MUX(1, 61, 3, N, N, N, N),
-};
-
-static struct atlas7_grp_mux cvbs_dbg_test_grp4_mux = {
-	.pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp4_pad_mux),
-	.pad_mux_list = cvbs_dbg_test_grp4_pad_mux,
-};
-
-static struct atlas7_pad_mux cvbs_dbg_test_grp5_pad_mux[] = {
-	MUX(1, 62, 3, N, N, N, N),
-};
-
-static struct atlas7_grp_mux cvbs_dbg_test_grp5_mux = {
-	.pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp5_pad_mux),
-	.pad_mux_list = cvbs_dbg_test_grp5_pad_mux,
-};
-
-static struct atlas7_pad_mux cvbs_dbg_test_grp6_pad_mux[] = {
-	MUX(1, 63, 3, N, N, N, N),
-};
-
-static struct atlas7_grp_mux cvbs_dbg_test_grp6_mux = {
-	.pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp6_pad_mux),
-	.pad_mux_list = cvbs_dbg_test_grp6_pad_mux,
-};
-
-static struct atlas7_pad_mux cvbs_dbg_test_grp7_pad_mux[] = {
-	MUX(1, 64, 3, N, N, N, N),
-};
-
-static struct atlas7_grp_mux cvbs_dbg_test_grp7_mux = {
-	.pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp7_pad_mux),
-	.pad_mux_list = cvbs_dbg_test_grp7_pad_mux,
-};
-
-static struct atlas7_pad_mux cvbs_dbg_test_grp8_pad_mux[] = {
-	MUX(1, 65, 3, N, N, N, N),
-};
-
-static struct atlas7_grp_mux cvbs_dbg_test_grp8_mux = {
-	.pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp8_pad_mux),
-	.pad_mux_list = cvbs_dbg_test_grp8_pad_mux,
-};
-
-static struct atlas7_pad_mux cvbs_dbg_test_grp9_pad_mux[] = {
-	MUX(1, 66, 3, N, N, N, N),
-};
-
-static struct atlas7_grp_mux cvbs_dbg_test_grp9_mux = {
-	.pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp9_pad_mux),
-	.pad_mux_list = cvbs_dbg_test_grp9_pad_mux,
-};
-
-static struct atlas7_pad_mux cvbs_dbg_test_grp10_pad_mux[] = {
-	MUX(1, 67, 3, N, N, N, N),
-};
-
-static struct atlas7_grp_mux cvbs_dbg_test_grp10_mux = {
-	.pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp10_pad_mux),
-	.pad_mux_list = cvbs_dbg_test_grp10_pad_mux,
-};
-
-static struct atlas7_pad_mux cvbs_dbg_test_grp11_pad_mux[] = {
-	MUX(1, 68, 3, N, N, N, N),
-};
-
-static struct atlas7_grp_mux cvbs_dbg_test_grp11_mux = {
-	.pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp11_pad_mux),
-	.pad_mux_list = cvbs_dbg_test_grp11_pad_mux,
-};
-
-static struct atlas7_pad_mux cvbs_dbg_test_grp12_pad_mux[] = {
-	MUX(1, 69, 3, N, N, N, N),
-};
-
-static struct atlas7_grp_mux cvbs_dbg_test_grp12_mux = {
-	.pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp12_pad_mux),
-	.pad_mux_list = cvbs_dbg_test_grp12_pad_mux,
-};
-
-static struct atlas7_pad_mux cvbs_dbg_test_grp13_pad_mux[] = {
-	MUX(1, 70, 3, N, N, N, N),
-};
-
-static struct atlas7_grp_mux cvbs_dbg_test_grp13_mux = {
-	.pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp13_pad_mux),
-	.pad_mux_list = cvbs_dbg_test_grp13_pad_mux,
-};
-
-static struct atlas7_pad_mux cvbs_dbg_test_grp14_pad_mux[] = {
-	MUX(1, 71, 3, N, N, N, N),
-};
-
-static struct atlas7_grp_mux cvbs_dbg_test_grp14_mux = {
-	.pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp14_pad_mux),
-	.pad_mux_list = cvbs_dbg_test_grp14_pad_mux,
-};
-
-static struct atlas7_pad_mux cvbs_dbg_test_grp15_pad_mux[] = {
-	MUX(1, 72, 3, N, N, N, N),
-};
-
-static struct atlas7_grp_mux cvbs_dbg_test_grp15_mux = {
-	.pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp15_pad_mux),
-	.pad_mux_list = cvbs_dbg_test_grp15_pad_mux,
-};
-
-static struct atlas7_pad_mux gn_gnss_power_grp_pad_mux[] = {
-	MUX(1, 123, 7, N, N, N, N),
-	MUX(1, 124, 7, N, N, N, N),
-	MUX(1, 121, 7, N, N, N, N),
-	MUX(1, 122, 7, N, N, N, N),
-	MUX(1, 125, 7, N, N, N, N),
-	MUX(1, 120, 7, N, N, N, N),
-};
-
-static struct atlas7_grp_mux gn_gnss_power_grp_mux = {
-	.pad_mux_count = ARRAY_SIZE(gn_gnss_power_grp_pad_mux),
-	.pad_mux_list = gn_gnss_power_grp_pad_mux,
-};
-
-static struct atlas7_pad_mux gn_gnss_sw_status_grp_pad_mux[] = {
-	MUX(1, 57, 7, N, N, N, N),
-	MUX(1, 58, 7, N, N, N, N),
-	MUX(1, 59, 7, N, N, N, N),
-	MUX(1, 60, 7, N, N, N, N),
-	MUX(1, 61, 7, N, N, N, N),
-	MUX(1, 62, 7, N, N, N, N),
-	MUX(1, 63, 7, N, N, N, N),
-	MUX(1, 64, 7, N, N, N, N),
-	MUX(1, 65, 7, N, N, N, N),
-	MUX(1, 66, 7, N, N, N, N),
-	MUX(1, 67, 7, N, N, N, N),
-	MUX(1, 68, 7, N, N, N, N),
-	MUX(1, 69, 7, N, N, N, N),
-	MUX(1, 70, 7, N, N, N, N),
-	MUX(1, 71, 7, N, N, N, N),
-	MUX(1, 72, 7, N, N, N, N),
-	MUX(1, 53, 7, N, N, N, N),
-	MUX(1, 55, 7, N, N, N, N),
-	MUX(1, 56, 7, 0xa08, 12, 0xa88, 12),
-	MUX(1, 54, 7, N, N, N, N),
-};
-
-static struct atlas7_grp_mux gn_gnss_sw_status_grp_mux = {
-	.pad_mux_count = ARRAY_SIZE(gn_gnss_sw_status_grp_pad_mux),
-	.pad_mux_list = gn_gnss_sw_status_grp_pad_mux,
-};
-
-static struct atlas7_pad_mux gn_gnss_eclk_grp_pad_mux[] = {
-	MUX(1, 113, 4, N, N, N, N),
-};
-
-static struct atlas7_grp_mux gn_gnss_eclk_grp_mux = {
-	.pad_mux_count = ARRAY_SIZE(gn_gnss_eclk_grp_pad_mux),
-	.pad_mux_list = gn_gnss_eclk_grp_pad_mux,
-};
-
-static struct atlas7_pad_mux gn_gnss_irq1_grp0_pad_mux[] = {
-	MUX(1, 112, 4, 0xa08, 10, 0xa88, 10),
-};
-
-static struct atlas7_grp_mux gn_gnss_irq1_grp0_mux = {
-	.pad_mux_count = ARRAY_SIZE(gn_gnss_irq1_grp0_pad_mux),
-	.pad_mux_list = gn_gnss_irq1_grp0_pad_mux,
-};
-
-static struct atlas7_pad_mux gn_gnss_irq2_grp0_pad_mux[] = {
-	MUX(1, 118, 4, 0xa08, 11, 0xa88, 11),
-};
-
-static struct atlas7_grp_mux gn_gnss_irq2_grp0_mux = {
-	.pad_mux_count = ARRAY_SIZE(gn_gnss_irq2_grp0_pad_mux),
-	.pad_mux_list = gn_gnss_irq2_grp0_pad_mux,
-};
-
-static struct atlas7_pad_mux gn_gnss_tm_grp_pad_mux[] = {
-	MUX(1, 115, 4, N, N, N, N),
-};
-
-static struct atlas7_grp_mux gn_gnss_tm_grp_mux = {
-	.pad_mux_count = ARRAY_SIZE(gn_gnss_tm_grp_pad_mux),
-	.pad_mux_list = gn_gnss_tm_grp_pad_mux,
-};
-
-static struct atlas7_pad_mux gn_gnss_tsync_grp_pad_mux[] = {
-	MUX(1, 114, 4, N, N, N, N),
-};
-
-static struct atlas7_grp_mux gn_gnss_tsync_grp_mux = {
-	.pad_mux_count = ARRAY_SIZE(gn_gnss_tsync_grp_pad_mux),
-	.pad_mux_list = gn_gnss_tsync_grp_pad_mux,
-};
-
-static struct atlas7_pad_mux gn_io_gnsssys_sw_cfg_grp_pad_mux[] = {
-	MUX(1, 44, 7, N, N, N, N),
-	MUX(1, 43, 7, N, N, N, N),
-	MUX(1, 42, 7, N, N, N, N),
-	MUX(1, 41, 7, N, N, N, N),
-	MUX(1, 40, 7, N, N, N, N),
-	MUX(1, 39, 7, N, N, N, N),
-	MUX(1, 38, 7, N, N, N, N),
-	MUX(1, 37, 7, N, N, N, N),
-	MUX(1, 49, 7, N, N, N, N),
-	MUX(1, 50, 7, N, N, N, N),
-	MUX(1, 91, 7, N, N, N, N),
-	MUX(1, 92, 7, N, N, N, N),
-	MUX(1, 93, 7, N, N, N, N),
-	MUX(1, 94, 7, N, N, N, N),
-	MUX(1, 95, 7, N, N, N, N),
-	MUX(1, 96, 7, N, N, N, N),
-};
-
-static struct atlas7_grp_mux gn_io_gnsssys_sw_cfg_grp_mux = {
-	.pad_mux_count = ARRAY_SIZE(gn_io_gnsssys_sw_cfg_grp_pad_mux),
-	.pad_mux_list = gn_io_gnsssys_sw_cfg_grp_pad_mux,
-};
-
-static struct atlas7_pad_mux gn_trg_grp0_pad_mux[] = {
-	MUX(1, 29, 1, 0xa00, 6, 0xa80, 6),
-	MUX(1, 28, 1, 0xa00, 7, 0xa80, 7),
-	MUX(1, 26, 1, 0xa00, 8, 0xa80, 8),
-	MUX(1, 27, 1, 0xa00, 9, 0xa80, 9),
-};
-
-static struct atlas7_grp_mux gn_trg_grp0_mux = {
-	.pad_mux_count = ARRAY_SIZE(gn_trg_grp0_pad_mux),
-	.pad_mux_list = gn_trg_grp0_pad_mux,
-};
-
-static struct atlas7_pad_mux gn_trg_grp1_pad_mux[] = {
-	MUX(1, 77, 3, 0xa00, 6, 0xa80, 6),
-	MUX(1, 76, 3, 0xa00, 7, 0xa80, 7),
-	MUX(1, 74, 3, 0xa00, 8, 0xa80, 8),
-	MUX(1, 75, 3, 0xa00, 9, 0xa80, 9),
-};
-
-static struct atlas7_grp_mux gn_trg_grp1_mux = {
-	.pad_mux_count = ARRAY_SIZE(gn_trg_grp1_pad_mux),
-	.pad_mux_list = gn_trg_grp1_pad_mux,
-};
-
-static struct atlas7_pad_mux gn_trg_shutdown_grp0_pad_mux[] = {
-	MUX(1, 30, 1, N, N, N, N),
-};
-
-static struct atlas7_grp_mux gn_trg_shutdown_grp0_mux = {
-	.pad_mux_count = ARRAY_SIZE(gn_trg_shutdown_grp0_pad_mux),
-	.pad_mux_list = gn_trg_shutdown_grp0_pad_mux,
-};
-
-static struct atlas7_pad_mux gn_trg_shutdown_grp1_pad_mux[] = {
-	MUX(1, 83, 3, N, N, N, N),
-};
-
-static struct atlas7_grp_mux gn_trg_shutdown_grp1_mux = {
-	.pad_mux_count = ARRAY_SIZE(gn_trg_shutdown_grp1_pad_mux),
-	.pad_mux_list = gn_trg_shutdown_grp1_pad_mux,
-};
-
-static struct atlas7_pad_mux gn_trg_shutdown_grp2_pad_mux[] = {
-	MUX(1, 117, 4, N, N, N, N),
-};
-
-static struct atlas7_grp_mux gn_trg_shutdown_grp2_mux = {
-	.pad_mux_count = ARRAY_SIZE(gn_trg_shutdown_grp2_pad_mux),
-	.pad_mux_list = gn_trg_shutdown_grp2_pad_mux,
-};
-
-static struct atlas7_pad_mux gn_trg_shutdown_grp3_pad_mux[] = {
-	MUX(1, 123, 5, N, N, N, N),
-};
-
-static struct atlas7_grp_mux gn_trg_shutdown_grp3_mux = {
-	.pad_mux_count = ARRAY_SIZE(gn_trg_shutdown_grp3_pad_mux),
-	.pad_mux_list = gn_trg_shutdown_grp3_pad_mux,
-};
-
-static struct atlas7_pad_mux i2c0_grp_pad_mux[] = {
-	MUX(1, 128, 1, N, N, N, N),
-	MUX(1, 127, 1, N, N, N, N),
-};
-
-static struct atlas7_grp_mux i2c0_grp_mux = {
-	.pad_mux_count = ARRAY_SIZE(i2c0_grp_pad_mux),
-	.pad_mux_list = i2c0_grp_pad_mux,
-};
-
-static struct atlas7_pad_mux i2c1_grp_pad_mux[] = {
-	MUX(1, 126, 4, N, N, N, N),
-	MUX(1, 125, 4, N, N, N, N),
-};
-
-static struct atlas7_grp_mux i2c1_grp_mux = {
-	.pad_mux_count = ARRAY_SIZE(i2c1_grp_pad_mux),
-	.pad_mux_list = i2c1_grp_pad_mux,
-};
-
-static struct atlas7_pad_mux i2s0_grp_pad_mux[] = {
-	MUX(1, 91, 2, 0xa10, 12, 0xa90, 12),
-	MUX(1, 93, 2, 0xa10, 13, 0xa90, 13),
-	MUX(1, 94, 2, 0xa10, 14, 0xa90, 14),
-	MUX(1, 92, 2, 0xa10, 15, 0xa90, 15),
-};
-
-static struct atlas7_grp_mux i2s0_grp_mux = {
-	.pad_mux_count = ARRAY_SIZE(i2s0_grp_pad_mux),
-	.pad_mux_list = i2s0_grp_pad_mux,
-};
-
-static struct atlas7_pad_mux i2s1_basic_grp_pad_mux[] = {
-	MUX(1, 95, 2, 0xa10, 16, 0xa90, 16),
-	MUX(1, 96, 2, 0xa10, 19, 0xa90, 19),
-};
-
-static struct atlas7_grp_mux i2s1_basic_grp_mux = {
-	.pad_mux_count = ARRAY_SIZE(i2s1_basic_grp_pad_mux),
-	.pad_mux_list = i2s1_basic_grp_pad_mux,
-};
-
-static struct atlas7_pad_mux i2s1_rxd0_grp0_pad_mux[] = {
-	MUX(1, 61, 4, 0xa10, 17, 0xa90, 17),
-};
-
-static struct atlas7_grp_mux i2s1_rxd0_grp0_mux = {
-	.pad_mux_count = ARRAY_SIZE(i2s1_rxd0_grp0_pad_mux),
-	.pad_mux_list = i2s1_rxd0_grp0_pad_mux,
-};
-
-static struct atlas7_pad_mux i2s1_rxd0_grp1_pad_mux[] = {
-	MUX(1, 131, 4, 0xa10, 17, 0xa90, 17),
-};
-
-static struct atlas7_grp_mux i2s1_rxd0_grp1_mux = {
-	.pad_mux_count = ARRAY_SIZE(i2s1_rxd0_grp1_pad_mux),
-	.pad_mux_list = i2s1_rxd0_grp1_pad_mux,
-};
-
-static struct atlas7_pad_mux i2s1_rxd0_grp2_pad_mux[] = {
-	MUX(1, 129, 2, 0xa10, 17, 0xa90, 17),
-};
-
-static struct atlas7_grp_mux i2s1_rxd0_grp2_mux = {
-	.pad_mux_count = ARRAY_SIZE(i2s1_rxd0_grp2_pad_mux),
-	.pad_mux_list = i2s1_rxd0_grp2_pad_mux,
-};
-
-static struct atlas7_pad_mux i2s1_rxd0_grp3_pad_mux[] = {
-	MUX(1, 117, 7, 0xa10, 17, 0xa90, 17),
-};
-
-static struct atlas7_grp_mux i2s1_rxd0_grp3_mux = {
-	.pad_mux_count = ARRAY_SIZE(i2s1_rxd0_grp3_pad_mux),
-	.pad_mux_list = i2s1_rxd0_grp3_pad_mux,
-};
-
-static struct atlas7_pad_mux i2s1_rxd0_grp4_pad_mux[] = {
-	MUX(1, 83, 4, 0xa10, 17, 0xa90, 17),
-};
-
-static struct atlas7_grp_mux i2s1_rxd0_grp4_mux = {
-	.pad_mux_count = ARRAY_SIZE(i2s1_rxd0_grp4_pad_mux),
-	.pad_mux_list = i2s1_rxd0_grp4_pad_mux,
-};
-
-static struct atlas7_pad_mux i2s1_rxd1_grp0_pad_mux[] = {
-	MUX(1, 72, 4, 0xa10, 18, 0xa90, 18),
-};
-
-static struct atlas7_grp_mux i2s1_rxd1_grp0_mux = {
-	.pad_mux_count = ARRAY_SIZE(i2s1_rxd1_grp0_pad_mux),
-	.pad_mux_list = i2s1_rxd1_grp0_pad_mux,
-};
-
-static struct atlas7_pad_mux i2s1_rxd1_grp1_pad_mux[] = {
-	MUX(1, 132, 4, 0xa10, 18, 0xa90, 18),
-};
-
-static struct atlas7_grp_mux i2s1_rxd1_grp1_mux = {
-	.pad_mux_count = ARRAY_SIZE(i2s1_rxd1_grp1_pad_mux),
-	.pad_mux_list = i2s1_rxd1_grp1_pad_mux,
-};
-
-static struct atlas7_pad_mux i2s1_rxd1_grp2_pad_mux[] = {
-	MUX(1, 130, 2, 0xa10, 18, 0xa90, 18),
-};
-
-static struct atlas7_grp_mux i2s1_rxd1_grp2_mux = {
-	.pad_mux_count = ARRAY_SIZE(i2s1_rxd1_grp2_pad_mux),
-	.pad_mux_list = i2s1_rxd1_grp2_pad_mux,
-};
-
-static struct atlas7_pad_mux i2s1_rxd1_grp3_pad_mux[] = {
-	MUX(1, 118, 7, 0xa10, 18, 0xa90, 18),
-};
-
-static struct atlas7_grp_mux i2s1_rxd1_grp3_mux = {
-	.pad_mux_count = ARRAY_SIZE(i2s1_rxd1_grp3_pad_mux),
-	.pad_mux_list = i2s1_rxd1_grp3_pad_mux,
-};
-
-static struct atlas7_pad_mux i2s1_rxd1_grp4_pad_mux[] = {
-	MUX(1, 84, 4, 0xa10, 18, 0xa90, 18),
-};
-
-static struct atlas7_grp_mux i2s1_rxd1_grp4_mux = {
-	.pad_mux_count = ARRAY_SIZE(i2s1_rxd1_grp4_pad_mux),
-	.pad_mux_list = i2s1_rxd1_grp4_pad_mux,
-};
-
-static struct atlas7_pad_mux jtag_jt_dbg_nsrst_grp_pad_mux[] = {
-	MUX(1, 125, 5, 0xa08, 2, 0xa88, 2),
-};
-
-static struct atlas7_grp_mux jtag_jt_dbg_nsrst_grp_mux = {
-	.pad_mux_count = ARRAY_SIZE(jtag_jt_dbg_nsrst_grp_pad_mux),
-	.pad_mux_list = jtag_jt_dbg_nsrst_grp_pad_mux,
-};
-
-static struct atlas7_pad_mux jtag_ntrst_grp0_pad_mux[] = {
-	MUX(0, 4, 3, 0xa08, 3, 0xa88, 3),
-};
-
-static struct atlas7_grp_mux jtag_ntrst_grp0_mux = {
-	.pad_mux_count = ARRAY_SIZE(jtag_ntrst_grp0_pad_mux),
-	.pad_mux_list = jtag_ntrst_grp0_pad_mux,
-};
-
-static struct atlas7_pad_mux jtag_ntrst_grp1_pad_mux[] = {
-	MUX(1, 163, 1, 0xa08, 3, 0xa88, 3),
-};
-
-static struct atlas7_grp_mux jtag_ntrst_grp1_mux = {
-	.pad_mux_count = ARRAY_SIZE(jtag_ntrst_grp1_pad_mux),
-	.pad_mux_list = jtag_ntrst_grp1_pad_mux,
-};
-
-static struct atlas7_pad_mux jtag_swdiotms_grp0_pad_mux[] = {
-	MUX(0, 2, 3, 0xa10, 10, 0xa90, 10),
-};
-
-static struct atlas7_grp_mux jtag_swdiotms_grp0_mux = {
-	.pad_mux_count = ARRAY_SIZE(jtag_swdiotms_grp0_pad_mux),
-	.pad_mux_list = jtag_swdiotms_grp0_pad_mux,
-};
-
-static struct atlas7_pad_mux jtag_swdiotms_grp1_pad_mux[] = {
-	MUX(1, 160, 1, 0xa10, 10, 0xa90, 10),
-};
-
-static struct atlas7_grp_mux jtag_swdiotms_grp1_mux = {
-	.pad_mux_count = ARRAY_SIZE(jtag_swdiotms_grp1_pad_mux),
-	.pad_mux_list = jtag_swdiotms_grp1_pad_mux,
-};
-
-static struct atlas7_pad_mux jtag_tck_grp0_pad_mux[] = {
-	MUX(0, 0, 3, 0xa10, 11, 0xa90, 11),
-};
-
-static struct atlas7_grp_mux jtag_tck_grp0_mux = {
-	.pad_mux_count = ARRAY_SIZE(jtag_tck_grp0_pad_mux),
-	.pad_mux_list = jtag_tck_grp0_pad_mux,
-};
-
-static struct atlas7_pad_mux jtag_tck_grp1_pad_mux[] = {
-	MUX(1, 161, 1, 0xa10, 11, 0xa90, 11),
-};
-
-static struct atlas7_grp_mux jtag_tck_grp1_mux = {
-	.pad_mux_count = ARRAY_SIZE(jtag_tck_grp1_pad_mux),
-	.pad_mux_list = jtag_tck_grp1_pad_mux,
-};
-
-static struct atlas7_pad_mux jtag_tdi_grp0_pad_mux[] = {
-	MUX(0, 1, 3, 0xa10, 31, 0xa90, 31),
-};
-
-static struct atlas7_grp_mux jtag_tdi_grp0_mux = {
-	.pad_mux_count = ARRAY_SIZE(jtag_tdi_grp0_pad_mux),
-	.pad_mux_list = jtag_tdi_grp0_pad_mux,
-};
-
-static struct atlas7_pad_mux jtag_tdi_grp1_pad_mux[] = {
-	MUX(1, 162, 1, 0xa10, 31, 0xa90, 31),
-};
-
-static struct atlas7_grp_mux jtag_tdi_grp1_mux = {
-	.pad_mux_count = ARRAY_SIZE(jtag_tdi_grp1_pad_mux),
-	.pad_mux_list = jtag_tdi_grp1_pad_mux,
-};
-
-static struct atlas7_pad_mux jtag_tdo_grp0_pad_mux[] = {
-	MUX(0, 3, 3, N, N, N, N),
-};
-
-static struct atlas7_grp_mux jtag_tdo_grp0_mux = {
-	.pad_mux_count = ARRAY_SIZE(jtag_tdo_grp0_pad_mux),
-	.pad_mux_list = jtag_tdo_grp0_pad_mux,
-};
-
-static struct atlas7_pad_mux jtag_tdo_grp1_pad_mux[] = {
-	MUX(1, 159, 1, N, N, N, N),
-};
-
-static struct atlas7_grp_mux jtag_tdo_grp1_mux = {
-	.pad_mux_count = ARRAY_SIZE(jtag_tdo_grp1_pad_mux),
-	.pad_mux_list = jtag_tdo_grp1_pad_mux,
-};
-
-static struct atlas7_pad_mux ks_kas_spi_grp0_pad_mux[] = {
-	MUX(1, 141, 2, N, N, N, N),
-	MUX(1, 144, 2, 0xa08, 8, 0xa88, 8),
-	MUX(1, 143, 2, N, N, N, N),
-	MUX(1, 142, 2, N, N, N, N),
-};
-
-static struct atlas7_grp_mux ks_kas_spi_grp0_mux = {
-	.pad_mux_count = ARRAY_SIZE(ks_kas_spi_grp0_pad_mux),
-	.pad_mux_list = ks_kas_spi_grp0_pad_mux,
-};
-
-static struct atlas7_pad_mux ld_ldd_grp_pad_mux[] = {
-	MUX(1, 57, 1, N, N, N, N),
-	MUX(1, 58, 1, N, N, N, N),
-	MUX(1, 59, 1, N, N, N, N),
-	MUX(1, 60, 1, N, N, N, N),
-	MUX(1, 61, 1, N, N, N, N),
-	MUX(1, 62, 1, N, N, N, N),
-	MUX(1, 63, 1, N, N, N, N),
-	MUX(1, 64, 1, N, N, N, N),
-	MUX(1, 65, 1, N, N, N, N),
-	MUX(1, 66, 1, N, N, N, N),
-	MUX(1, 67, 1, N, N, N, N),
-	MUX(1, 68, 1, N, N, N, N),
-	MUX(1, 69, 1, N, N, N, N),
-	MUX(1, 70, 1, N, N, N, N),
-	MUX(1, 71, 1, N, N, N, N),
-	MUX(1, 72, 1, N, N, N, N),
-	MUX(1, 74, 2, N, N, N, N),
-	MUX(1, 75, 2, N, N, N, N),
-	MUX(1, 76, 2, N, N, N, N),
-	MUX(1, 77, 2, N, N, N, N),
-	MUX(1, 78, 2, N, N, N, N),
-	MUX(1, 79, 2, N, N, N, N),
-	MUX(1, 80, 2, N, N, N, N),
-	MUX(1, 81, 2, N, N, N, N),
-	MUX(1, 56, 1, N, N, N, N),
-	MUX(1, 53, 1, N, N, N, N),
-};
-
-static struct atlas7_grp_mux ld_ldd_grp_mux = {
-	.pad_mux_count = ARRAY_SIZE(ld_ldd_grp_pad_mux),
-	.pad_mux_list = ld_ldd_grp_pad_mux,
-};
-
-static struct atlas7_pad_mux ld_ldd_16bit_grp_pad_mux[] = {
-	MUX(1, 57, 1, N, N, N, N),
-	MUX(1, 58, 1, N, N, N, N),
-	MUX(1, 59, 1, N, N, N, N),
-	MUX(1, 60, 1, N, N, N, N),
-	MUX(1, 61, 1, N, N, N, N),
-	MUX(1, 62, 1, N, N, N, N),
-	MUX(1, 63, 1, N, N, N, N),
-	MUX(1, 64, 1, N, N, N, N),
-	MUX(1, 65, 1, N, N, N, N),
-	MUX(1, 66, 1, N, N, N, N),
-	MUX(1, 67, 1, N, N, N, N),
-	MUX(1, 68, 1, N, N, N, N),
-	MUX(1, 69, 1, N, N, N, N),
-	MUX(1, 70, 1, N, N, N, N),
-	MUX(1, 71, 1, N, N, N, N),
-	MUX(1, 72, 1, N, N, N, N),
-	MUX(1, 56, 1, N, N, N, N),
-	MUX(1, 53, 1, N, N, N, N),
-};
-
-static struct atlas7_grp_mux ld_ldd_16bit_grp_mux = {
-	.pad_mux_count = ARRAY_SIZE(ld_ldd_16bit_grp_pad_mux),
-	.pad_mux_list = ld_ldd_16bit_grp_pad_mux,
-};
-
-static struct atlas7_pad_mux ld_ldd_fck_grp_pad_mux[] = {
-	MUX(1, 55, 1, N, N, N, N),
-};
-
-static struct atlas7_grp_mux ld_ldd_fck_grp_mux = {
-	.pad_mux_count = ARRAY_SIZE(ld_ldd_fck_grp_pad_mux),
-	.pad_mux_list = ld_ldd_fck_grp_pad_mux,
-};
-
-static struct atlas7_pad_mux ld_ldd_lck_grp_pad_mux[] = {
-	MUX(1, 54, 1, N, N, N, N),
-};
-
-static struct atlas7_grp_mux ld_ldd_lck_grp_mux = {
-	.pad_mux_count = ARRAY_SIZE(ld_ldd_lck_grp_pad_mux),
-	.pad_mux_list = ld_ldd_lck_grp_pad_mux,
-};
-
-static struct atlas7_pad_mux lr_lcdrom_grp_pad_mux[] = {
-	MUX(1, 73, 2, N, N, N, N),
-	MUX(1, 54, 2, N, N, N, N),
-	MUX(1, 57, 2, N, N, N, N),
-	MUX(1, 58, 2, N, N, N, N),
-	MUX(1, 59, 2, N, N, N, N),
-	MUX(1, 60, 2, N, N, N, N),
-	MUX(1, 61, 2, N, N, N, N),
-	MUX(1, 62, 2, N, N, N, N),
-	MUX(1, 63, 2, N, N, N, N),
-	MUX(1, 64, 2, N, N, N, N),
-	MUX(1, 65, 2, N, N, N, N),
-	MUX(1, 66, 2, N, N, N, N),
-	MUX(1, 67, 2, N, N, N, N),
-	MUX(1, 68, 2, N, N, N, N),
-	MUX(1, 69, 2, N, N, N, N),
-	MUX(1, 70, 2, N, N, N, N),
-	MUX(1, 71, 2, N, N, N, N),
-	MUX(1, 72, 2, N, N, N, N),
-	MUX(1, 56, 2, N, N, N, N),
-	MUX(1, 53, 2, N, N, N, N),
-	MUX(1, 55, 2, N, N, N, N),
-};
-
-static struct atlas7_grp_mux lr_lcdrom_grp_mux = {
-	.pad_mux_count = ARRAY_SIZE(lr_lcdrom_grp_pad_mux),
-	.pad_mux_list = lr_lcdrom_grp_pad_mux,
-};
-
-static struct atlas7_pad_mux lvds_analog_grp_pad_mux[] = {
-	MUX(1, 149, 8, N, N, N, N),
-	MUX(1, 150, 8, N, N, N, N),
-	MUX(1, 151, 8, N, N, N, N),
-	MUX(1, 152, 8, N, N, N, N),
-	MUX(1, 153, 8, N, N, N, N),
-	MUX(1, 154, 8, N, N, N, N),
-	MUX(1, 155, 8, N, N, N, N),
-	MUX(1, 156, 8, N, N, N, N),
-	MUX(1, 157, 8, N, N, N, N),
-	MUX(1, 158, 8, N, N, N, N),
-};
-
-static struct atlas7_grp_mux lvds_analog_grp_mux = {
-	.pad_mux_count = ARRAY_SIZE(lvds_analog_grp_pad_mux),
-	.pad_mux_list = lvds_analog_grp_pad_mux,
-};
-
-static struct atlas7_pad_mux nd_df_basic_grp_pad_mux[] = {
-	MUX(1, 44, 1, N, N, N, N),
-	MUX(1, 43, 1, N, N, N, N),
-	MUX(1, 42, 1, N, N, N, N),
-	MUX(1, 41, 1, N, N, N, N),
-	MUX(1, 40, 1, N, N, N, N),
-	MUX(1, 39, 1, N, N, N, N),
-	MUX(1, 38, 1, N, N, N, N),
-	MUX(1, 37, 1, N, N, N, N),
-	MUX(1, 47, 1, N, N, N, N),
-	MUX(1, 46, 1, N, N, N, N),
-	MUX(1, 52, 1, N, N, N, N),
-	MUX(1, 45, 1, N, N, N, N),
-	MUX(1, 49, 1, N, N, N, N),
-	MUX(1, 50, 1, N, N, N, N),
-	MUX(1, 48, 1, N, N, N, N),
-};
-
-static struct atlas7_grp_mux nd_df_basic_grp_mux = {
-	.pad_mux_count = ARRAY_SIZE(nd_df_basic_grp_pad_mux),
-	.pad_mux_list = nd_df_basic_grp_pad_mux,
-};
-
-static struct atlas7_pad_mux nd_df_wp_grp_pad_mux[] = {
-	MUX(1, 124, 4, N, N, N, N),
-};
-
-static struct atlas7_grp_mux nd_df_wp_grp_mux = {
-	.pad_mux_count = ARRAY_SIZE(nd_df_wp_grp_pad_mux),
-	.pad_mux_list = nd_df_wp_grp_pad_mux,
-};
-
-static struct atlas7_pad_mux nd_df_cs_grp_pad_mux[] = {
-	MUX(1, 51, 1, N, N, N, N),
-};
-
-static struct atlas7_grp_mux nd_df_cs_grp_mux = {
-	.pad_mux_count = ARRAY_SIZE(nd_df_cs_grp_pad_mux),
-	.pad_mux_list = nd_df_cs_grp_pad_mux,
-};
-
-static struct atlas7_pad_mux ps_grp_pad_mux[] = {
-	MUX(1, 120, 2, N, N, N, N),
-	MUX(1, 119, 2, N, N, N, N),
-	MUX(1, 121, 5, N, N, N, N),
-};
-
-static struct atlas7_grp_mux ps_grp_mux = {
-	.pad_mux_count = ARRAY_SIZE(ps_grp_pad_mux),
-	.pad_mux_list = ps_grp_pad_mux,
-};
-
-static struct atlas7_pad_mux ps_no_dir_grp_pad_mux[] = {
-	MUX(1, 119, 2, N, N, N, N),
-};
-
-static struct atlas7_grp_mux ps_no_dir_grp_mux = {
-	.pad_mux_count = ARRAY_SIZE(ps_no_dir_grp_pad_mux),
-	.pad_mux_list = ps_no_dir_grp_pad_mux,
-};
-
-static struct atlas7_pad_mux pwc_core_on_grp_pad_mux[] = {
-	MUX(0, 8, 1, N, N, N, N),
-};
-
-static struct atlas7_grp_mux pwc_core_on_grp_mux = {
-	.pad_mux_count = ARRAY_SIZE(pwc_core_on_grp_pad_mux),
-	.pad_mux_list = pwc_core_on_grp_pad_mux,
-};
-
-static struct atlas7_pad_mux pwc_ext_on_grp_pad_mux[] = {
-	MUX(0, 6, 1, N, N, N, N),
-};
-
-static struct atlas7_grp_mux pwc_ext_on_grp_mux = {
-	.pad_mux_count = ARRAY_SIZE(pwc_ext_on_grp_pad_mux),
-	.pad_mux_list = pwc_ext_on_grp_pad_mux,
-};
-
-static struct atlas7_pad_mux pwc_gpio3_clk_grp_pad_mux[] = {
-	MUX(0, 3, 4, N, N, N, N),
-};
-
-static struct atlas7_grp_mux pwc_gpio3_clk_grp_mux = {
-	.pad_mux_count = ARRAY_SIZE(pwc_gpio3_clk_grp_pad_mux),
-	.pad_mux_list = pwc_gpio3_clk_grp_pad_mux,
-};
-
-static struct atlas7_pad_mux pwc_io_on_grp_pad_mux[] = {
-	MUX(0, 9, 1, N, N, N, N),
-};
-
-static struct atlas7_grp_mux pwc_io_on_grp_mux = {
-	.pad_mux_count = ARRAY_SIZE(pwc_io_on_grp_pad_mux),
-	.pad_mux_list = pwc_io_on_grp_pad_mux,
-};
-
-static struct atlas7_pad_mux pwc_lowbatt_b_grp0_pad_mux[] = {
-	MUX(0, 4, 1, 0xa08, 4, 0xa88, 4),
-};
-
-static struct atlas7_grp_mux pwc_lowbatt_b_grp0_mux = {
-	.pad_mux_count = ARRAY_SIZE(pwc_lowbatt_b_grp0_pad_mux),
-	.pad_mux_list = pwc_lowbatt_b_grp0_pad_mux,
-};
-
-static struct atlas7_pad_mux pwc_mem_on_grp_pad_mux[] = {
-	MUX(0, 7, 1, N, N, N, N),
-};
-
-static struct atlas7_grp_mux pwc_mem_on_grp_mux = {
-	.pad_mux_count = ARRAY_SIZE(pwc_mem_on_grp_pad_mux),
-	.pad_mux_list = pwc_mem_on_grp_pad_mux,
-};
-
-static struct atlas7_pad_mux pwc_on_key_b_grp0_pad_mux[] = {
-	MUX(0, 5, 1, 0xa08, 5, 0xa88, 5),
-};
-
-static struct atlas7_grp_mux pwc_on_key_b_grp0_mux = {
-	.pad_mux_count = ARRAY_SIZE(pwc_on_key_b_grp0_pad_mux),
-	.pad_mux_list = pwc_on_key_b_grp0_pad_mux,
-};
-
-static struct atlas7_pad_mux pwc_wakeup_src0_grp_pad_mux[] = {
-	MUX(0, 0, 1, N, N, N, N),
-};
-
-static struct atlas7_grp_mux pwc_wakeup_src0_grp_mux = {
-	.pad_mux_count = ARRAY_SIZE(pwc_wakeup_src0_grp_pad_mux),
-	.pad_mux_list = pwc_wakeup_src0_grp_pad_mux,
-};
-
-static struct atlas7_pad_mux pwc_wakeup_src1_grp_pad_mux[] = {
-	MUX(0, 1, 1, N, N, N, N),
-};
-
-static struct atlas7_grp_mux pwc_wakeup_src1_grp_mux = {
-	.pad_mux_count = ARRAY_SIZE(pwc_wakeup_src1_grp_pad_mux),
-	.pad_mux_list = pwc_wakeup_src1_grp_pad_mux,
-};
-
-static struct atlas7_pad_mux pwc_wakeup_src2_grp_pad_mux[] = {
-	MUX(0, 2, 1, N, N, N, N),
-};
-
-static struct atlas7_grp_mux pwc_wakeup_src2_grp_mux = {
-	.pad_mux_count = ARRAY_SIZE(pwc_wakeup_src2_grp_pad_mux),
-	.pad_mux_list = pwc_wakeup_src2_grp_pad_mux,
-};
-
-static struct atlas7_pad_mux pwc_wakeup_src3_grp_pad_mux[] = {
-	MUX(0, 3, 1, N, N, N, N),
-};
-
-static struct atlas7_grp_mux pwc_wakeup_src3_grp_mux = {
-	.pad_mux_count = ARRAY_SIZE(pwc_wakeup_src3_grp_pad_mux),
-	.pad_mux_list = pwc_wakeup_src3_grp_pad_mux,
-};
-
-static struct atlas7_pad_mux pw_cko0_grp0_pad_mux[] = {
-	MUX(1, 123, 3, N, N, N, N),
-};
-
-static struct atlas7_grp_mux pw_cko0_grp0_mux = {
-	.pad_mux_count = ARRAY_SIZE(pw_cko0_grp0_pad_mux),
-	.pad_mux_list = pw_cko0_grp0_pad_mux,
-};
-
-static struct atlas7_pad_mux pw_cko0_grp1_pad_mux[] = {
-	MUX(1, 101, 4, N, N, N, N),
-};
-
-static struct atlas7_grp_mux pw_cko0_grp1_mux = {
-	.pad_mux_count = ARRAY_SIZE(pw_cko0_grp1_pad_mux),
-	.pad_mux_list = pw_cko0_grp1_pad_mux,
-};
-
-static struct atlas7_pad_mux pw_cko0_grp2_pad_mux[] = {
-	MUX(1, 82, 2, N, N, N, N),
-};
-
-static struct atlas7_grp_mux pw_cko0_grp2_mux = {
-	.pad_mux_count = ARRAY_SIZE(pw_cko0_grp2_pad_mux),
-	.pad_mux_list = pw_cko0_grp2_pad_mux,
-};
-
-static struct atlas7_pad_mux pw_cko0_grp3_pad_mux[] = {
-	MUX(1, 162, 5, N, N, N, N),
-};
-
-static struct atlas7_grp_mux pw_cko0_grp3_mux = {
-	.pad_mux_count = ARRAY_SIZE(pw_cko0_grp3_pad_mux),
-	.pad_mux_list = pw_cko0_grp3_pad_mux,
-};
-
-static struct atlas7_pad_mux pw_cko1_grp0_pad_mux[] = {
-	MUX(1, 124, 3, N, N, N, N),
-};
-
-static struct atlas7_grp_mux pw_cko1_grp0_mux = {
-	.pad_mux_count = ARRAY_SIZE(pw_cko1_grp0_pad_mux),
-	.pad_mux_list = pw_cko1_grp0_pad_mux,
-};
-
-static struct atlas7_pad_mux pw_cko1_grp1_pad_mux[] = {
-	MUX(1, 110, 4, N, N, N, N),
-};
-
-static struct atlas7_grp_mux pw_cko1_grp1_mux = {
-	.pad_mux_count = ARRAY_SIZE(pw_cko1_grp1_pad_mux),
-	.pad_mux_list = pw_cko1_grp1_pad_mux,
-};
-
-static struct atlas7_pad_mux pw_cko1_grp2_pad_mux[] = {
-	MUX(1, 163, 5, N, N, N, N),
-};
-
-static struct atlas7_grp_mux pw_cko1_grp2_mux = {
-	.pad_mux_count = ARRAY_SIZE(pw_cko1_grp2_pad_mux),
-	.pad_mux_list = pw_cko1_grp2_pad_mux,
-};
-
-static struct atlas7_pad_mux pw_i2s01_clk_grp0_pad_mux[] = {
-	MUX(1, 125, 3, N, N, N, N),
-};
-
-static struct atlas7_grp_mux pw_i2s01_clk_grp0_mux = {
-	.pad_mux_count = ARRAY_SIZE(pw_i2s01_clk_grp0_pad_mux),
-	.pad_mux_list = pw_i2s01_clk_grp0_pad_mux,
-};
-
-static struct atlas7_pad_mux pw_i2s01_clk_grp1_pad_mux[] = {
-	MUX(1, 117, 3, N, N, N, N),
-};
-
-static struct atlas7_grp_mux pw_i2s01_clk_grp1_mux = {
-	.pad_mux_count = ARRAY_SIZE(pw_i2s01_clk_grp1_pad_mux),
-	.pad_mux_list = pw_i2s01_clk_grp1_pad_mux,
-};
-
-static struct atlas7_pad_mux pw_i2s01_clk_grp2_pad_mux[] = {
-	MUX(1, 132, 2, N, N, N, N),
-};
-
-static struct atlas7_grp_mux pw_i2s01_clk_grp2_mux = {
-	.pad_mux_count = ARRAY_SIZE(pw_i2s01_clk_grp2_pad_mux),
-	.pad_mux_list = pw_i2s01_clk_grp2_pad_mux,
-};
-
-static struct atlas7_pad_mux pw_pwm0_grp0_pad_mux[] = {
-	MUX(1, 119, 3, N, N, N, N),
-};
-
-static struct atlas7_grp_mux pw_pwm0_grp0_mux = {
-	.pad_mux_count = ARRAY_SIZE(pw_pwm0_grp0_pad_mux),
-	.pad_mux_list = pw_pwm0_grp0_pad_mux,
-};
-
-static struct atlas7_pad_mux pw_pwm0_grp1_pad_mux[] = {
-	MUX(1, 159, 5, N, N, N, N),
-};
-
-static struct atlas7_grp_mux pw_pwm0_grp1_mux = {
-	.pad_mux_count = ARRAY_SIZE(pw_pwm0_grp1_pad_mux),
-	.pad_mux_list = pw_pwm0_grp1_pad_mux,
-};
-
-static struct atlas7_pad_mux pw_pwm1_grp0_pad_mux[] = {
-	MUX(1, 120, 3, N, N, N, N),
-};
-
-static struct atlas7_grp_mux pw_pwm1_grp0_mux = {
-	.pad_mux_count = ARRAY_SIZE(pw_pwm1_grp0_pad_mux),
-	.pad_mux_list = pw_pwm1_grp0_pad_mux,
-};
-
-static struct atlas7_pad_mux pw_pwm1_grp1_pad_mux[] = {
-	MUX(1, 160, 5, N, N, N, N),
-};
-
-static struct atlas7_grp_mux pw_pwm1_grp1_mux = {
-	.pad_mux_count = ARRAY_SIZE(pw_pwm1_grp1_pad_mux),
-	.pad_mux_list = pw_pwm1_grp1_pad_mux,
-};
-
-static struct atlas7_pad_mux pw_pwm1_grp2_pad_mux[] = {
-	MUX(1, 131, 2, N, N, N, N),
-};
-
-static struct atlas7_grp_mux pw_pwm1_grp2_mux = {
-	.pad_mux_count = ARRAY_SIZE(pw_pwm1_grp2_pad_mux),
-	.pad_mux_list = pw_pwm1_grp2_pad_mux,
-};
-
-static struct atlas7_pad_mux pw_pwm2_grp0_pad_mux[] = {
-	MUX(1, 121, 3, N, N, N, N),
-};
-
-static struct atlas7_grp_mux pw_pwm2_grp0_mux = {
-	.pad_mux_count = ARRAY_SIZE(pw_pwm2_grp0_pad_mux),
-	.pad_mux_list = pw_pwm2_grp0_pad_mux,
-};
-
-static struct atlas7_pad_mux pw_pwm2_grp1_pad_mux[] = {
-	MUX(1, 98, 3, N, N, N, N),
-};
-
-static struct atlas7_grp_mux pw_pwm2_grp1_mux = {
-	.pad_mux_count = ARRAY_SIZE(pw_pwm2_grp1_pad_mux),
-	.pad_mux_list = pw_pwm2_grp1_pad_mux,
-};
-
-static struct atlas7_pad_mux pw_pwm2_grp2_pad_mux[] = {
-	MUX(1, 161, 5, N, N, N, N),
-};
-
-static struct atlas7_grp_mux pw_pwm2_grp2_mux = {
-	.pad_mux_count = ARRAY_SIZE(pw_pwm2_grp2_pad_mux),
-	.pad_mux_list = pw_pwm2_grp2_pad_mux,
-};
-
-static struct atlas7_pad_mux pw_pwm3_grp0_pad_mux[] = {
-	MUX(1, 122, 3, N, N, N, N),
-};
-
-static struct atlas7_grp_mux pw_pwm3_grp0_mux = {
-	.pad_mux_count = ARRAY_SIZE(pw_pwm3_grp0_pad_mux),
-	.pad_mux_list = pw_pwm3_grp0_pad_mux,
-};
-
-static struct atlas7_pad_mux pw_pwm3_grp1_pad_mux[] = {
-	MUX(1, 73, 4, N, N, N, N),
-};
-
-static struct atlas7_grp_mux pw_pwm3_grp1_mux = {
-	.pad_mux_count = ARRAY_SIZE(pw_pwm3_grp1_pad_mux),
-	.pad_mux_list = pw_pwm3_grp1_pad_mux,
-};
-
-static struct atlas7_pad_mux pw_pwm_cpu_vol_grp0_pad_mux[] = {
-	MUX(1, 121, 3, N, N, N, N),
-};
-
-static struct atlas7_grp_mux pw_pwm_cpu_vol_grp0_mux = {
-	.pad_mux_count = ARRAY_SIZE(pw_pwm_cpu_vol_grp0_pad_mux),
-	.pad_mux_list = pw_pwm_cpu_vol_grp0_pad_mux,
-};
-
-static struct atlas7_pad_mux pw_pwm_cpu_vol_grp1_pad_mux[] = {
-	MUX(1, 98, 3, N, N, N, N),
-};
-
-static struct atlas7_grp_mux pw_pwm_cpu_vol_grp1_mux = {
-	.pad_mux_count = ARRAY_SIZE(pw_pwm_cpu_vol_grp1_pad_mux),
-	.pad_mux_list = pw_pwm_cpu_vol_grp1_pad_mux,
-};
-
-static struct atlas7_pad_mux pw_pwm_cpu_vol_grp2_pad_mux[] = {
-	MUX(1, 161, 5, N, N, N, N),
-};
-
-static struct atlas7_grp_mux pw_pwm_cpu_vol_grp2_mux = {
-	.pad_mux_count = ARRAY_SIZE(pw_pwm_cpu_vol_grp2_pad_mux),
-	.pad_mux_list = pw_pwm_cpu_vol_grp2_pad_mux,
-};
-
-static struct atlas7_pad_mux pw_backlight_grp0_pad_mux[] = {
-	MUX(1, 122, 3, N, N, N, N),
-};
-
-static struct atlas7_grp_mux pw_backlight_grp0_mux = {
-	.pad_mux_count = ARRAY_SIZE(pw_backlight_grp0_pad_mux),
-	.pad_mux_list = pw_backlight_grp0_pad_mux,
-};
-
-static struct atlas7_pad_mux pw_backlight_grp1_pad_mux[] = {
-	MUX(1, 73, 4, N, N, N, N),
-};
-
-static struct atlas7_grp_mux pw_backlight_grp1_mux = {
-	.pad_mux_count = ARRAY_SIZE(pw_backlight_grp1_pad_mux),
-	.pad_mux_list = pw_backlight_grp1_pad_mux,
-};
-
-static struct atlas7_pad_mux rg_eth_mac_grp_pad_mux[] = {
-	MUX(1, 108, 1, N, N, N, N),
-	MUX(1, 103, 1, N, N, N, N),
-	MUX(1, 104, 1, N, N, N, N),
-	MUX(1, 105, 1, N, N, N, N),
-	MUX(1, 106, 1, N, N, N, N),
-	MUX(1, 107, 1, N, N, N, N),
-	MUX(1, 102, 1, N, N, N, N),
-	MUX(1, 97, 1, N, N, N, N),
-	MUX(1, 98, 1, N, N, N, N),
-	MUX(1, 99, 1, N, N, N, N),
-	MUX(1, 100, 1, N, N, N, N),
-	MUX(1, 101, 1, N, N, N, N),
-};
-
-static struct atlas7_grp_mux rg_eth_mac_grp_mux = {
-	.pad_mux_count = ARRAY_SIZE(rg_eth_mac_grp_pad_mux),
-	.pad_mux_list = rg_eth_mac_grp_pad_mux,
-};
-
-static struct atlas7_pad_mux rg_gmac_phy_intr_n_grp_pad_mux[] = {
-	MUX(1, 111, 1, 0xa08, 13, 0xa88, 13),
-};
-
-static struct atlas7_grp_mux rg_gmac_phy_intr_n_grp_mux = {
-	.pad_mux_count = ARRAY_SIZE(rg_gmac_phy_intr_n_grp_pad_mux),
-	.pad_mux_list = rg_gmac_phy_intr_n_grp_pad_mux,
-};
-
-static struct atlas7_pad_mux rg_rgmii_mac_grp_pad_mux[] = {
-	MUX(1, 109, 1, N, N, N, N),
-	MUX(1, 110, 1, N, N, N, N),
-};
-
-static struct atlas7_grp_mux rg_rgmii_mac_grp_mux = {
-	.pad_mux_count = ARRAY_SIZE(rg_rgmii_mac_grp_pad_mux),
-	.pad_mux_list = rg_rgmii_mac_grp_pad_mux,
-};
-
-static struct atlas7_pad_mux rg_rgmii_phy_ref_clk_grp0_pad_mux[] = {
-	MUX(1, 111, 5, N, N, N, N),
-};
-
-static struct atlas7_grp_mux rg_rgmii_phy_ref_clk_grp0_mux = {
-	.pad_mux_count = ARRAY_SIZE(rg_rgmii_phy_ref_clk_grp0_pad_mux),
-	.pad_mux_list = rg_rgmii_phy_ref_clk_grp0_pad_mux,
-};
-
-static struct atlas7_pad_mux rg_rgmii_phy_ref_clk_grp1_pad_mux[] = {
-	MUX(1, 53, 4, N, N, N, N),
-};
-
-static struct atlas7_grp_mux rg_rgmii_phy_ref_clk_grp1_mux = {
-	.pad_mux_count = ARRAY_SIZE(rg_rgmii_phy_ref_clk_grp1_pad_mux),
-	.pad_mux_list = rg_rgmii_phy_ref_clk_grp1_pad_mux,
-};
-
-static struct atlas7_pad_mux sd0_grp_pad_mux[] = {
-	MUX(1, 46, 2, N, N, N, N),
-	MUX(1, 47, 2, N, N, N, N),
-	MUX(1, 44, 2, N, N, N, N),
-	MUX(1, 43, 2, N, N, N, N),
-	MUX(1, 42, 2, N, N, N, N),
-	MUX(1, 41, 2, N, N, N, N),
-	MUX(1, 40, 2, N, N, N, N),
-	MUX(1, 39, 2, N, N, N, N),
-	MUX(1, 38, 2, N, N, N, N),
-	MUX(1, 37, 2, N, N, N, N),
-};
-
-static struct atlas7_grp_mux sd0_grp_mux = {
-	.pad_mux_count = ARRAY_SIZE(sd0_grp_pad_mux),
-	.pad_mux_list = sd0_grp_pad_mux,
-};
-
-static struct atlas7_pad_mux sd0_4bit_grp_pad_mux[] = {
-	MUX(1, 46, 2, N, N, N, N),
-	MUX(1, 47, 2, N, N, N, N),
-	MUX(1, 44, 2, N, N, N, N),
-	MUX(1, 43, 2, N, N, N, N),
-	MUX(1, 42, 2, N, N, N, N),
-	MUX(1, 41, 2, N, N, N, N),
-};
-
-static struct atlas7_grp_mux sd0_4bit_grp_mux = {
-	.pad_mux_count = ARRAY_SIZE(sd0_4bit_grp_pad_mux),
-	.pad_mux_list = sd0_4bit_grp_pad_mux,
-};
-
-static struct atlas7_pad_mux sd1_grp_pad_mux[] = {
-	MUX(1, 48, 3, N, N, N, N),
-	MUX(1, 49, 3, N, N, N, N),
-	MUX(1, 44, 3, 0xa00, 0, 0xa80, 0),
-	MUX(1, 43, 3, 0xa00, 1, 0xa80, 1),
-	MUX(1, 42, 3, 0xa00, 2, 0xa80, 2),
-	MUX(1, 41, 3, 0xa00, 3, 0xa80, 3),
-	MUX(1, 40, 3, N, N, N, N),
-	MUX(1, 39, 3, N, N, N, N),
-	MUX(1, 38, 3, N, N, N, N),
-	MUX(1, 37, 3, N, N, N, N),
-};
-
-static struct atlas7_grp_mux sd1_grp_mux = {
-	.pad_mux_count = ARRAY_SIZE(sd1_grp_pad_mux),
-	.pad_mux_list = sd1_grp_pad_mux,
-};
-
-static struct atlas7_pad_mux sd1_4bit_grp0_pad_mux[] = {
-	MUX(1, 48, 3, N, N, N, N),
-	MUX(1, 49, 3, N, N, N, N),
-	MUX(1, 44, 3, 0xa00, 0, 0xa80, 0),
-	MUX(1, 43, 3, 0xa00, 1, 0xa80, 1),
-	MUX(1, 42, 3, 0xa00, 2, 0xa80, 2),
-	MUX(1, 41, 3, 0xa00, 3, 0xa80, 3),
-};
-
-static struct atlas7_grp_mux sd1_4bit_grp0_mux = {
-	.pad_mux_count = ARRAY_SIZE(sd1_4bit_grp0_pad_mux),
-	.pad_mux_list = sd1_4bit_grp0_pad_mux,
-};
-
-static struct atlas7_pad_mux sd1_4bit_grp1_pad_mux[] = {
-	MUX(1, 48, 3, N, N, N, N),
-	MUX(1, 49, 3, N, N, N, N),
-	MUX(1, 40, 4, 0xa00, 0, 0xa80, 0),
-	MUX(1, 39, 4, 0xa00, 1, 0xa80, 1),
-	MUX(1, 38, 4, 0xa00, 2, 0xa80, 2),
-	MUX(1, 37, 4, 0xa00, 3, 0xa80, 3),
-};
-
-static struct atlas7_grp_mux sd1_4bit_grp1_mux = {
-	.pad_mux_count = ARRAY_SIZE(sd1_4bit_grp1_pad_mux),
-	.pad_mux_list = sd1_4bit_grp1_pad_mux,
-};
-
-static struct atlas7_pad_mux sd2_basic_grp_pad_mux[] = {
-	MUX(1, 31, 1, N, N, N, N),
-	MUX(1, 32, 1, N, N, N, N),
-	MUX(1, 33, 1, N, N, N, N),
-	MUX(1, 34, 1, N, N, N, N),
-	MUX(1, 35, 1, N, N, N, N),
-	MUX(1, 36, 1, N, N, N, N),
-};
-
-static struct atlas7_grp_mux sd2_basic_grp_mux = {
-	.pad_mux_count = ARRAY_SIZE(sd2_basic_grp_pad_mux),
-	.pad_mux_list = sd2_basic_grp_pad_mux,
-};
-
-static struct atlas7_pad_mux sd2_cdb_grp0_pad_mux[] = {
-	MUX(1, 124, 2, 0xa08, 7, 0xa88, 7),
-};
-
-static struct atlas7_grp_mux sd2_cdb_grp0_mux = {
-	.pad_mux_count = ARRAY_SIZE(sd2_cdb_grp0_pad_mux),
-	.pad_mux_list = sd2_cdb_grp0_pad_mux,
-};
-
-static struct atlas7_pad_mux sd2_cdb_grp1_pad_mux[] = {
-	MUX(1, 161, 6, 0xa08, 7, 0xa88, 7),
-};
-
-static struct atlas7_grp_mux sd2_cdb_grp1_mux = {
-	.pad_mux_count = ARRAY_SIZE(sd2_cdb_grp1_pad_mux),
-	.pad_mux_list = sd2_cdb_grp1_pad_mux,
-};
-
-static struct atlas7_pad_mux sd2_wpb_grp0_pad_mux[] = {
-	MUX(1, 123, 2, 0xa10, 6, 0xa90, 6),
-};
-
-static struct atlas7_grp_mux sd2_wpb_grp0_mux = {
-	.pad_mux_count = ARRAY_SIZE(sd2_wpb_grp0_pad_mux),
-	.pad_mux_list = sd2_wpb_grp0_pad_mux,
-};
-
-static struct atlas7_pad_mux sd2_wpb_grp1_pad_mux[] = {
-	MUX(1, 163, 7, 0xa10, 6, 0xa90, 6),
-};
-
-static struct atlas7_grp_mux sd2_wpb_grp1_mux = {
-	.pad_mux_count = ARRAY_SIZE(sd2_wpb_grp1_pad_mux),
-	.pad_mux_list = sd2_wpb_grp1_pad_mux,
-};
-
-static struct atlas7_pad_mux sd3_9_grp_pad_mux[] = {
-	MUX(1, 85, 1, N, N, N, N),
-	MUX(1, 86, 1, N, N, N, N),
-	MUX(1, 87, 1, N, N, N, N),
-	MUX(1, 88, 1, N, N, N, N),
-	MUX(1, 89, 1, N, N, N, N),
-	MUX(1, 90, 1, N, N, N, N),
-};
-
-static struct atlas7_grp_mux sd3_9_grp_mux = {
-	.pad_mux_count = ARRAY_SIZE(sd3_9_grp_pad_mux),
-	.pad_mux_list = sd3_9_grp_pad_mux,
-};
-
-static struct atlas7_pad_mux sd5_grp_pad_mux[] = {
-	MUX(1, 91, 1, N, N, N, N),
-	MUX(1, 92, 1, N, N, N, N),
-	MUX(1, 93, 1, N, N, N, N),
-	MUX(1, 94, 1, N, N, N, N),
-	MUX(1, 95, 1, N, N, N, N),
-	MUX(1, 96, 1, N, N, N, N),
-};
-
-static struct atlas7_grp_mux sd5_grp_mux = {
-	.pad_mux_count = ARRAY_SIZE(sd5_grp_pad_mux),
-	.pad_mux_list = sd5_grp_pad_mux,
-};
-
-static struct atlas7_pad_mux sd6_grp0_pad_mux[] = {
-	MUX(1, 79, 4, 0xa00, 27, 0xa80, 27),
-	MUX(1, 78, 4, 0xa00, 26, 0xa80, 26),
-	MUX(1, 74, 4, 0xa00, 28, 0xa80, 28),
-	MUX(1, 75, 4, 0xa00, 29, 0xa80, 29),
-	MUX(1, 76, 4, 0xa00, 30, 0xa80, 30),
-	MUX(1, 77, 4, 0xa00, 31, 0xa80, 31),
-};
-
-static struct atlas7_grp_mux sd6_grp0_mux = {
-	.pad_mux_count = ARRAY_SIZE(sd6_grp0_pad_mux),
-	.pad_mux_list = sd6_grp0_pad_mux,
-};
-
-static struct atlas7_pad_mux sd6_grp1_pad_mux[] = {
-	MUX(1, 101, 3, 0xa00, 27, 0xa80, 27),
-	MUX(1, 99, 3, 0xa00, 26, 0xa80, 26),
-	MUX(1, 100, 3, 0xa00, 28, 0xa80, 28),
-	MUX(1, 110, 3, 0xa00, 29, 0xa80, 29),
-	MUX(1, 109, 3, 0xa00, 30, 0xa80, 30),
-	MUX(1, 111, 3, 0xa00, 31, 0xa80, 31),
-};
-
-static struct atlas7_grp_mux sd6_grp1_mux = {
-	.pad_mux_count = ARRAY_SIZE(sd6_grp1_pad_mux),
-	.pad_mux_list = sd6_grp1_pad_mux,
-};
-
-static struct atlas7_pad_mux sp0_ext_ldo_on_grp_pad_mux[] = {
-	MUX(0, 4, 2, N, N, N, N),
-};
-
-static struct atlas7_grp_mux sp0_ext_ldo_on_grp_mux = {
-	.pad_mux_count = ARRAY_SIZE(sp0_ext_ldo_on_grp_pad_mux),
-	.pad_mux_list = sp0_ext_ldo_on_grp_pad_mux,
-};
-
-static struct atlas7_pad_mux sp0_qspi_grp_pad_mux[] = {
-	MUX(0, 12, 1, N, N, N, N),
-	MUX(0, 13, 1, N, N, N, N),
-	MUX(0, 14, 1, N, N, N, N),
-	MUX(0, 15, 1, N, N, N, N),
-	MUX(0, 16, 1, N, N, N, N),
-	MUX(0, 17, 1, N, N, N, N),
-};
-
-static struct atlas7_grp_mux sp0_qspi_grp_mux = {
-	.pad_mux_count = ARRAY_SIZE(sp0_qspi_grp_pad_mux),
-	.pad_mux_list = sp0_qspi_grp_pad_mux,
-};
-
-static struct atlas7_pad_mux sp1_spi_grp_pad_mux[] = {
-	MUX(1, 19, 1, N, N, N, N),
-	MUX(1, 20, 1, N, N, N, N),
-	MUX(1, 21, 1, N, N, N, N),
-	MUX(1, 18, 1, N, N, N, N),
-};
-
-static struct atlas7_grp_mux sp1_spi_grp_mux = {
-	.pad_mux_count = ARRAY_SIZE(sp1_spi_grp_pad_mux),
-	.pad_mux_list = sp1_spi_grp_pad_mux,
-};
-
-static struct atlas7_pad_mux tpiu_trace_grp_pad_mux[] = {
-	MUX(1, 53, 5, N, N, N, N),
-	MUX(1, 56, 5, N, N, N, N),
-	MUX(1, 57, 5, N, N, N, N),
-	MUX(1, 58, 5, N, N, N, N),
-	MUX(1, 59, 5, N, N, N, N),
-	MUX(1, 60, 5, N, N, N, N),
-	MUX(1, 61, 5, N, N, N, N),
-	MUX(1, 62, 5, N, N, N, N),
-	MUX(1, 63, 5, N, N, N, N),
-	MUX(1, 64, 5, N, N, N, N),
-	MUX(1, 65, 5, N, N, N, N),
-	MUX(1, 66, 5, N, N, N, N),
-	MUX(1, 67, 5, N, N, N, N),
-	MUX(1, 68, 5, N, N, N, N),
-	MUX(1, 69, 5, N, N, N, N),
-	MUX(1, 70, 5, N, N, N, N),
-	MUX(1, 71, 5, N, N, N, N),
-	MUX(1, 72, 5, N, N, N, N),
-};
-
-static struct atlas7_grp_mux tpiu_trace_grp_mux = {
-	.pad_mux_count = ARRAY_SIZE(tpiu_trace_grp_pad_mux),
-	.pad_mux_list = tpiu_trace_grp_pad_mux,
-};
-
-static struct atlas7_pad_mux uart0_grp_pad_mux[] = {
-	MUX(1, 121, 4, N, N, N, N),
-	MUX(1, 120, 4, N, N, N, N),
-	MUX(1, 134, 1, N, N, N, N),
-	MUX(1, 133, 1, N, N, N, N),
-};
-
-static struct atlas7_grp_mux uart0_grp_mux = {
-	.pad_mux_count = ARRAY_SIZE(uart0_grp_pad_mux),
-	.pad_mux_list = uart0_grp_pad_mux,
-};
-
-static struct atlas7_pad_mux uart0_nopause_grp_pad_mux[] = {
-	MUX(1, 134, 1, N, N, N, N),
-	MUX(1, 133, 1, N, N, N, N),
-};
-
-static struct atlas7_grp_mux uart0_nopause_grp_mux = {
-	.pad_mux_count = ARRAY_SIZE(uart0_nopause_grp_pad_mux),
-	.pad_mux_list = uart0_nopause_grp_pad_mux,
-};
-
-static struct atlas7_pad_mux uart1_grp_pad_mux[] = {
-	MUX(1, 136, 1, N, N, N, N),
-	MUX(1, 135, 1, N, N, N, N),
-};
-
-static struct atlas7_grp_mux uart1_grp_mux = {
-	.pad_mux_count = ARRAY_SIZE(uart1_grp_pad_mux),
-	.pad_mux_list = uart1_grp_pad_mux,
-};
-
-static struct atlas7_pad_mux uart2_cts_grp0_pad_mux[] = {
-	MUX(1, 132, 3, 0xa10, 2, 0xa90, 2),
-};
-
-static struct atlas7_grp_mux uart2_cts_grp0_mux = {
-	.pad_mux_count = ARRAY_SIZE(uart2_cts_grp0_pad_mux),
-	.pad_mux_list = uart2_cts_grp0_pad_mux,
-};
-
-static struct atlas7_pad_mux uart2_cts_grp1_pad_mux[] = {
-	MUX(1, 162, 2, 0xa10, 2, 0xa90, 2),
-};
-
-static struct atlas7_grp_mux uart2_cts_grp1_mux = {
-	.pad_mux_count = ARRAY_SIZE(uart2_cts_grp1_pad_mux),
-	.pad_mux_list = uart2_cts_grp1_pad_mux,
-};
-
-static struct atlas7_pad_mux uart2_rts_grp0_pad_mux[] = {
-	MUX(1, 131, 3, N, N, N, N),
-};
-
-static struct atlas7_grp_mux uart2_rts_grp0_mux = {
-	.pad_mux_count = ARRAY_SIZE(uart2_rts_grp0_pad_mux),
-	.pad_mux_list = uart2_rts_grp0_pad_mux,
-};
-
-static struct atlas7_pad_mux uart2_rts_grp1_pad_mux[] = {
-	MUX(1, 161, 2, N, N, N, N),
-};
-
-static struct atlas7_grp_mux uart2_rts_grp1_mux = {
-	.pad_mux_count = ARRAY_SIZE(uart2_rts_grp1_pad_mux),
-	.pad_mux_list = uart2_rts_grp1_pad_mux,
-};
-
-static struct atlas7_pad_mux uart2_rxd_grp0_pad_mux[] = {
-	MUX(0, 11, 2, 0xa10, 5, 0xa90, 5),
-};
-
-static struct atlas7_grp_mux uart2_rxd_grp0_mux = {
-	.pad_mux_count = ARRAY_SIZE(uart2_rxd_grp0_pad_mux),
-	.pad_mux_list = uart2_rxd_grp0_pad_mux,
-};
-
-static struct atlas7_pad_mux uart2_rxd_grp1_pad_mux[] = {
-	MUX(1, 160, 2, 0xa10, 5, 0xa90, 5),
-};
-
-static struct atlas7_grp_mux uart2_rxd_grp1_mux = {
-	.pad_mux_count = ARRAY_SIZE(uart2_rxd_grp1_pad_mux),
-	.pad_mux_list = uart2_rxd_grp1_pad_mux,
-};
-
-static struct atlas7_pad_mux uart2_rxd_grp2_pad_mux[] = {
-	MUX(1, 130, 3, 0xa10, 5, 0xa90, 5),
-};
-
-static struct atlas7_grp_mux uart2_rxd_grp2_mux = {
-	.pad_mux_count = ARRAY_SIZE(uart2_rxd_grp2_pad_mux),
-	.pad_mux_list = uart2_rxd_grp2_pad_mux,
-};
-
-static struct atlas7_pad_mux uart2_txd_grp0_pad_mux[] = {
-	MUX(0, 10, 2, N, N, N, N),
-};
-
-static struct atlas7_grp_mux uart2_txd_grp0_mux = {
-	.pad_mux_count = ARRAY_SIZE(uart2_txd_grp0_pad_mux),
-	.pad_mux_list = uart2_txd_grp0_pad_mux,
-};
-
-static struct atlas7_pad_mux uart2_txd_grp1_pad_mux[] = {
-	MUX(1, 159, 2, N, N, N, N),
-};
-
-static struct atlas7_grp_mux uart2_txd_grp1_mux = {
-	.pad_mux_count = ARRAY_SIZE(uart2_txd_grp1_pad_mux),
-	.pad_mux_list = uart2_txd_grp1_pad_mux,
-};
-
-static struct atlas7_pad_mux uart2_txd_grp2_pad_mux[] = {
-	MUX(1, 129, 3, N, N, N, N),
-};
-
-static struct atlas7_grp_mux uart2_txd_grp2_mux = {
-	.pad_mux_count = ARRAY_SIZE(uart2_txd_grp2_pad_mux),
-	.pad_mux_list = uart2_txd_grp2_pad_mux,
-};
-
-static struct atlas7_pad_mux uart3_cts_grp0_pad_mux[] = {
-	MUX(1, 125, 2, 0xa08, 0, 0xa88, 0),
-};
-
-static struct atlas7_grp_mux uart3_cts_grp0_mux = {
-	.pad_mux_count = ARRAY_SIZE(uart3_cts_grp0_pad_mux),
-	.pad_mux_list = uart3_cts_grp0_pad_mux,
-};
-
-static struct atlas7_pad_mux uart3_cts_grp1_pad_mux[] = {
-	MUX(1, 111, 4, 0xa08, 0, 0xa88, 0),
-};
-
-static struct atlas7_grp_mux uart3_cts_grp1_mux = {
-	.pad_mux_count = ARRAY_SIZE(uart3_cts_grp1_pad_mux),
-	.pad_mux_list = uart3_cts_grp1_pad_mux,
-};
-
-static struct atlas7_pad_mux uart3_cts_grp2_pad_mux[] = {
-	MUX(1, 140, 2, 0xa08, 0, 0xa88, 0),
-};
-
-static struct atlas7_grp_mux uart3_cts_grp2_mux = {
-	.pad_mux_count = ARRAY_SIZE(uart3_cts_grp2_pad_mux),
-	.pad_mux_list = uart3_cts_grp2_pad_mux,
-};
-
-static struct atlas7_pad_mux uart3_rts_grp0_pad_mux[] = {
-	MUX(1, 126, 2, N, N, N, N),
-};
-
-static struct atlas7_grp_mux uart3_rts_grp0_mux = {
-	.pad_mux_count = ARRAY_SIZE(uart3_rts_grp0_pad_mux),
-	.pad_mux_list = uart3_rts_grp0_pad_mux,
-};
-
-static struct atlas7_pad_mux uart3_rts_grp1_pad_mux[] = {
-	MUX(1, 109, 4, N, N, N, N),
-};
-
-static struct atlas7_grp_mux uart3_rts_grp1_mux = {
-	.pad_mux_count = ARRAY_SIZE(uart3_rts_grp1_pad_mux),
-	.pad_mux_list = uart3_rts_grp1_pad_mux,
-};
-
-static struct atlas7_pad_mux uart3_rts_grp2_pad_mux[] = {
-	MUX(1, 139, 2, N, N, N, N),
-};
-
-static struct atlas7_grp_mux uart3_rts_grp2_mux = {
-	.pad_mux_count = ARRAY_SIZE(uart3_rts_grp2_pad_mux),
-	.pad_mux_list = uart3_rts_grp2_pad_mux,
-};
-
-static struct atlas7_pad_mux uart3_rxd_grp0_pad_mux[] = {
-	MUX(1, 138, 1, 0xa00, 5, 0xa80, 5),
-};
-
-static struct atlas7_grp_mux uart3_rxd_grp0_mux = {
-	.pad_mux_count = ARRAY_SIZE(uart3_rxd_grp0_pad_mux),
-	.pad_mux_list = uart3_rxd_grp0_pad_mux,
-};
-
-static struct atlas7_pad_mux uart3_rxd_grp1_pad_mux[] = {
-	MUX(1, 84, 2, 0xa00, 5, 0xa80, 5),
-};
-
-static struct atlas7_grp_mux uart3_rxd_grp1_mux = {
-	.pad_mux_count = ARRAY_SIZE(uart3_rxd_grp1_pad_mux),
-	.pad_mux_list = uart3_rxd_grp1_pad_mux,
-};
-
-static struct atlas7_pad_mux uart3_rxd_grp2_pad_mux[] = {
-	MUX(1, 162, 3, 0xa00, 5, 0xa80, 5),
-};
-
-static struct atlas7_grp_mux uart3_rxd_grp2_mux = {
-	.pad_mux_count = ARRAY_SIZE(uart3_rxd_grp2_pad_mux),
-	.pad_mux_list = uart3_rxd_grp2_pad_mux,
-};
-
-static struct atlas7_pad_mux uart3_txd_grp0_pad_mux[] = {
-	MUX(1, 137, 1, N, N, N, N),
-};
-
-static struct atlas7_grp_mux uart3_txd_grp0_mux = {
-	.pad_mux_count = ARRAY_SIZE(uart3_txd_grp0_pad_mux),
-	.pad_mux_list = uart3_txd_grp0_pad_mux,
-};
-
-static struct atlas7_pad_mux uart3_txd_grp1_pad_mux[] = {
-	MUX(1, 83, 2, N, N, N, N),
-};
-
-static struct atlas7_grp_mux uart3_txd_grp1_mux = {
-	.pad_mux_count = ARRAY_SIZE(uart3_txd_grp1_pad_mux),
-	.pad_mux_list = uart3_txd_grp1_pad_mux,
-};
-
-static struct atlas7_pad_mux uart3_txd_grp2_pad_mux[] = {
-	MUX(1, 161, 3, N, N, N, N),
-};
-
-static struct atlas7_grp_mux uart3_txd_grp2_mux = {
-	.pad_mux_count = ARRAY_SIZE(uart3_txd_grp2_pad_mux),
-	.pad_mux_list = uart3_txd_grp2_pad_mux,
-};
-
-static struct atlas7_pad_mux uart4_basic_grp_pad_mux[] = {
-	MUX(1, 140, 1, N, N, N, N),
-	MUX(1, 139, 1, N, N, N, N),
-};
-
-static struct atlas7_grp_mux uart4_basic_grp_mux = {
-	.pad_mux_count = ARRAY_SIZE(uart4_basic_grp_pad_mux),
-	.pad_mux_list = uart4_basic_grp_pad_mux,
-};
-
-static struct atlas7_pad_mux uart4_cts_grp0_pad_mux[] = {
-	MUX(1, 122, 4, 0xa08, 1, 0xa88, 1),
-};
-
-static struct atlas7_grp_mux uart4_cts_grp0_mux = {
-	.pad_mux_count = ARRAY_SIZE(uart4_cts_grp0_pad_mux),
-	.pad_mux_list = uart4_cts_grp0_pad_mux,
-};
-
-static struct atlas7_pad_mux uart4_cts_grp1_pad_mux[] = {
-	MUX(1, 100, 4, 0xa08, 1, 0xa88, 1),
-};
-
-static struct atlas7_grp_mux uart4_cts_grp1_mux = {
-	.pad_mux_count = ARRAY_SIZE(uart4_cts_grp1_pad_mux),
-	.pad_mux_list = uart4_cts_grp1_pad_mux,
-};
-
-static struct atlas7_pad_mux uart4_cts_grp2_pad_mux[] = {
-	MUX(1, 117, 2, 0xa08, 1, 0xa88, 1),
-};
-
-static struct atlas7_grp_mux uart4_cts_grp2_mux = {
-	.pad_mux_count = ARRAY_SIZE(uart4_cts_grp2_pad_mux),
-	.pad_mux_list = uart4_cts_grp2_pad_mux,
-};
-
-static struct atlas7_pad_mux uart4_rts_grp0_pad_mux[] = {
-	MUX(1, 123, 4, N, N, N, N),
-};
-
-static struct atlas7_grp_mux uart4_rts_grp0_mux = {
-	.pad_mux_count = ARRAY_SIZE(uart4_rts_grp0_pad_mux),
-	.pad_mux_list = uart4_rts_grp0_pad_mux,
-};
-
-static struct atlas7_pad_mux uart4_rts_grp1_pad_mux[] = {
-	MUX(1, 99, 4, N, N, N, N),
-};
-
-static struct atlas7_grp_mux uart4_rts_grp1_mux = {
-	.pad_mux_count = ARRAY_SIZE(uart4_rts_grp1_pad_mux),
-	.pad_mux_list = uart4_rts_grp1_pad_mux,
-};
-
-static struct atlas7_pad_mux uart4_rts_grp2_pad_mux[] = {
-	MUX(1, 116, 2, N, N, N, N),
-};
-
-static struct atlas7_grp_mux uart4_rts_grp2_mux = {
-	.pad_mux_count = ARRAY_SIZE(uart4_rts_grp2_pad_mux),
-	.pad_mux_list = uart4_rts_grp2_pad_mux,
-};
-
-static struct atlas7_pad_mux usb0_drvvbus_grp0_pad_mux[] = {
-	MUX(1, 51, 2, N, N, N, N),
-};
-
-static struct atlas7_grp_mux usb0_drvvbus_grp0_mux = {
-	.pad_mux_count = ARRAY_SIZE(usb0_drvvbus_grp0_pad_mux),
-	.pad_mux_list = usb0_drvvbus_grp0_pad_mux,
-};
-
-static struct atlas7_pad_mux usb0_drvvbus_grp1_pad_mux[] = {
-	MUX(1, 162, 7, N, N, N, N),
-};
-
-static struct atlas7_grp_mux usb0_drvvbus_grp1_mux = {
-	.pad_mux_count = ARRAY_SIZE(usb0_drvvbus_grp1_pad_mux),
-	.pad_mux_list = usb0_drvvbus_grp1_pad_mux,
-};
-
-static struct atlas7_pad_mux usb1_drvvbus_grp0_pad_mux[] = {
-	MUX(1, 134, 2, N, N, N, N),
-};
-
-static struct atlas7_grp_mux usb1_drvvbus_grp0_mux = {
-	.pad_mux_count = ARRAY_SIZE(usb1_drvvbus_grp0_pad_mux),
-	.pad_mux_list = usb1_drvvbus_grp0_pad_mux,
-};
-
-static struct atlas7_pad_mux usb1_drvvbus_grp1_pad_mux[] = {
-	MUX(1, 163, 2, N, N, N, N),
-};
-
-static struct atlas7_grp_mux usb1_drvvbus_grp1_mux = {
-	.pad_mux_count = ARRAY_SIZE(usb1_drvvbus_grp1_pad_mux),
-	.pad_mux_list = usb1_drvvbus_grp1_pad_mux,
-};
-
-static struct atlas7_pad_mux visbus_dout_grp_pad_mux[] = {
-	MUX(1, 57, 6, N, N, N, N),
-	MUX(1, 58, 6, N, N, N, N),
-	MUX(1, 59, 6, N, N, N, N),
-	MUX(1, 60, 6, N, N, N, N),
-	MUX(1, 61, 6, N, N, N, N),
-	MUX(1, 62, 6, N, N, N, N),
-	MUX(1, 63, 6, N, N, N, N),
-	MUX(1, 64, 6, N, N, N, N),
-	MUX(1, 65, 6, N, N, N, N),
-	MUX(1, 66, 6, N, N, N, N),
-	MUX(1, 67, 6, N, N, N, N),
-	MUX(1, 68, 6, N, N, N, N),
-	MUX(1, 69, 6, N, N, N, N),
-	MUX(1, 70, 6, N, N, N, N),
-	MUX(1, 71, 6, N, N, N, N),
-	MUX(1, 72, 6, N, N, N, N),
-	MUX(1, 53, 6, N, N, N, N),
-	MUX(1, 54, 6, N, N, N, N),
-	MUX(1, 55, 6, N, N, N, N),
-	MUX(1, 56, 6, N, N, N, N),
-	MUX(1, 85, 6, N, N, N, N),
-	MUX(1, 86, 6, N, N, N, N),
-	MUX(1, 87, 6, N, N, N, N),
-	MUX(1, 88, 6, N, N, N, N),
-	MUX(1, 89, 6, N, N, N, N),
-	MUX(1, 90, 6, N, N, N, N),
-	MUX(1, 91, 6, N, N, N, N),
-	MUX(1, 92, 6, N, N, N, N),
-	MUX(1, 93, 6, N, N, N, N),
-	MUX(1, 94, 6, N, N, N, N),
-	MUX(1, 95, 6, N, N, N, N),
-	MUX(1, 96, 6, N, N, N, N),
-};
-
-static struct atlas7_grp_mux visbus_dout_grp_mux = {
-	.pad_mux_count = ARRAY_SIZE(visbus_dout_grp_pad_mux),
-	.pad_mux_list = visbus_dout_grp_pad_mux,
-};
-
-static struct atlas7_pad_mux vi_vip1_grp_pad_mux[] = {
-	MUX(1, 74, 1, N, N, N, N),
-	MUX(1, 75, 1, N, N, N, N),
-	MUX(1, 76, 1, N, N, N, N),
-	MUX(1, 77, 1, N, N, N, N),
-	MUX(1, 78, 1, N, N, N, N),
-	MUX(1, 79, 1, N, N, N, N),
-	MUX(1, 80, 1, N, N, N, N),
-	MUX(1, 81, 1, N, N, N, N),
-	MUX(1, 82, 1, N, N, N, N),
-	MUX(1, 83, 1, N, N, N, N),
-	MUX(1, 84, 1, N, N, N, N),
-	MUX(1, 103, 2, N, N, N, N),
-	MUX(1, 104, 2, N, N, N, N),
-	MUX(1, 105, 2, N, N, N, N),
-	MUX(1, 106, 2, N, N, N, N),
-	MUX(1, 107, 2, N, N, N, N),
-	MUX(1, 102, 2, N, N, N, N),
-	MUX(1, 97, 2, N, N, N, N),
-	MUX(1, 98, 2, N, N, N, N),
-};
-
-static struct atlas7_grp_mux vi_vip1_grp_mux = {
-	.pad_mux_count = ARRAY_SIZE(vi_vip1_grp_pad_mux),
-	.pad_mux_list = vi_vip1_grp_pad_mux,
-};
-
-static struct atlas7_pad_mux vi_vip1_ext_grp_pad_mux[] = {
-	MUX(1, 74, 1, N, N, N, N),
-	MUX(1, 75, 1, N, N, N, N),
-	MUX(1, 76, 1, N, N, N, N),
-	MUX(1, 77, 1, N, N, N, N),
-	MUX(1, 78, 1, N, N, N, N),
-	MUX(1, 79, 1, N, N, N, N),
-	MUX(1, 80, 1, N, N, N, N),
-	MUX(1, 81, 1, N, N, N, N),
-	MUX(1, 82, 1, N, N, N, N),
-	MUX(1, 83, 1, N, N, N, N),
-	MUX(1, 84, 1, N, N, N, N),
-	MUX(1, 108, 2, N, N, N, N),
-	MUX(1, 103, 2, N, N, N, N),
-	MUX(1, 104, 2, N, N, N, N),
-	MUX(1, 105, 2, N, N, N, N),
-	MUX(1, 106, 2, N, N, N, N),
-	MUX(1, 107, 2, N, N, N, N),
-	MUX(1, 102, 2, N, N, N, N),
-	MUX(1, 97, 2, N, N, N, N),
-	MUX(1, 98, 2, N, N, N, N),
-	MUX(1, 99, 2, N, N, N, N),
-	MUX(1, 100, 2, N, N, N, N),
-};
-
-static struct atlas7_grp_mux vi_vip1_ext_grp_mux = {
-	.pad_mux_count = ARRAY_SIZE(vi_vip1_ext_grp_pad_mux),
-	.pad_mux_list = vi_vip1_ext_grp_pad_mux,
-};
-
-static struct atlas7_pad_mux vi_vip1_low8bit_grp_pad_mux[] = {
-	MUX(1, 74, 1, N, N, N, N),
-	MUX(1, 75, 1, N, N, N, N),
-	MUX(1, 76, 1, N, N, N, N),
-	MUX(1, 77, 1, N, N, N, N),
-	MUX(1, 78, 1, N, N, N, N),
-	MUX(1, 79, 1, N, N, N, N),
-	MUX(1, 80, 1, N, N, N, N),
-	MUX(1, 81, 1, N, N, N, N),
-	MUX(1, 82, 1, N, N, N, N),
-	MUX(1, 83, 1, N, N, N, N),
-	MUX(1, 84, 1, N, N, N, N),
-};
-
-static struct atlas7_grp_mux vi_vip1_low8bit_grp_mux = {
-	.pad_mux_count = ARRAY_SIZE(vi_vip1_low8bit_grp_pad_mux),
-	.pad_mux_list = vi_vip1_low8bit_grp_pad_mux,
-};
-
-static struct atlas7_pad_mux vi_vip1_high8bit_grp_pad_mux[] = {
-	MUX(1, 82, 1, N, N, N, N),
-	MUX(1, 83, 1, N, N, N, N),
-	MUX(1, 84, 1, N, N, N, N),
-	MUX(1, 103, 2, N, N, N, N),
-	MUX(1, 104, 2, N, N, N, N),
-	MUX(1, 105, 2, N, N, N, N),
-	MUX(1, 106, 2, N, N, N, N),
-	MUX(1, 107, 2, N, N, N, N),
-	MUX(1, 102, 2, N, N, N, N),
-	MUX(1, 97, 2, N, N, N, N),
-	MUX(1, 98, 2, N, N, N, N),
-};
-
-static struct atlas7_grp_mux vi_vip1_high8bit_grp_mux = {
-	.pad_mux_count = ARRAY_SIZE(vi_vip1_high8bit_grp_pad_mux),
-	.pad_mux_list = vi_vip1_high8bit_grp_pad_mux,
-};
-
-static struct atlas7_pmx_func atlas7_pmx_functions[] = {
-	FUNCTION("gnss_gpio", gnss_gpio_grp, &gnss_gpio_grp_mux),
-	FUNCTION("lcd_vip_gpio", lcd_vip_gpio_grp, &lcd_vip_gpio_grp_mux),
-	FUNCTION("sdio_i2s_gpio", sdio_i2s_gpio_grp, &sdio_i2s_gpio_grp_mux),
-	FUNCTION("sp_rgmii_gpio", sp_rgmii_gpio_grp, &sp_rgmii_gpio_grp_mux),
-	FUNCTION("lvds_gpio", lvds_gpio_grp, &lvds_gpio_grp_mux),
-	FUNCTION("jtag_uart_nand_gpio",
-			jtag_uart_nand_gpio_grp,
-			&jtag_uart_nand_gpio_grp_mux),
-	FUNCTION("rtc_gpio", rtc_gpio_grp, &rtc_gpio_grp_mux),
-	FUNCTION("audio_ac97", audio_ac97_grp, &audio_ac97_grp_mux),
-	FUNCTION("audio_digmic_m0",
-			audio_digmic_grp0,
-			&audio_digmic_grp0_mux),
-	FUNCTION("audio_digmic_m1",
-			audio_digmic_grp1,
-			&audio_digmic_grp1_mux),
-	FUNCTION("audio_digmic_m2",
-			audio_digmic_grp2,
-			&audio_digmic_grp2_mux),
-	FUNCTION("audio_func_dbg",
-			audio_func_dbg_grp,
-			&audio_func_dbg_grp_mux),
-	FUNCTION("audio_i2s", audio_i2s_grp, &audio_i2s_grp_mux),
-	FUNCTION("audio_i2s_2ch", audio_i2s_2ch_grp, &audio_i2s_2ch_grp_mux),
-	FUNCTION("audio_i2s_extclk",
-			audio_i2s_extclk_grp,
-			&audio_i2s_extclk_grp_mux),
-	FUNCTION("audio_spdif_out_m0",
-			audio_spdif_out_grp0,
-			&audio_spdif_out_grp0_mux),
-	FUNCTION("audio_spdif_out_m1",
-			audio_spdif_out_grp1,
-			&audio_spdif_out_grp1_mux),
-	FUNCTION("audio_spdif_out_m2",
-			audio_spdif_out_grp2,
-			&audio_spdif_out_grp2_mux),
-	FUNCTION("audio_uart0_basic",
-			audio_uart0_basic_grp,
-			&audio_uart0_basic_grp_mux),
-	FUNCTION("audio_uart0_urfs_m0",
-			audio_uart0_urfs_grp0,
-			&audio_uart0_urfs_grp0_mux),
-	FUNCTION("audio_uart0_urfs_m1",
-			audio_uart0_urfs_grp1,
-			&audio_uart0_urfs_grp1_mux),
-	FUNCTION("audio_uart0_urfs_m2",
-			audio_uart0_urfs_grp2,
-			&audio_uart0_urfs_grp2_mux),
-	FUNCTION("audio_uart0_urfs_m3",
-			audio_uart0_urfs_grp3,
-			&audio_uart0_urfs_grp3_mux),
-	FUNCTION("audio_uart1_basic",
-			audio_uart1_basic_grp,
-			&audio_uart1_basic_grp_mux),
-	FUNCTION("audio_uart1_urfs_m0",
-			audio_uart1_urfs_grp0,
-			&audio_uart1_urfs_grp0_mux),
-	FUNCTION("audio_uart1_urfs_m1",
-			audio_uart1_urfs_grp1,
-			&audio_uart1_urfs_grp1_mux),
-	FUNCTION("audio_uart1_urfs_m2",
-			audio_uart1_urfs_grp2,
-			&audio_uart1_urfs_grp2_mux),
-	FUNCTION("audio_uart2_urfs_m0",
-			audio_uart2_urfs_grp0,
-			&audio_uart2_urfs_grp0_mux),
-	FUNCTION("audio_uart2_urfs_m1",
-			audio_uart2_urfs_grp1,
-			&audio_uart2_urfs_grp1_mux),
-	FUNCTION("audio_uart2_urfs_m2",
-			audio_uart2_urfs_grp2,
-			&audio_uart2_urfs_grp2_mux),
-	FUNCTION("audio_uart2_urxd_m0",
-			audio_uart2_urxd_grp0,
-			&audio_uart2_urxd_grp0_mux),
-	FUNCTION("audio_uart2_urxd_m1",
-			audio_uart2_urxd_grp1,
-			&audio_uart2_urxd_grp1_mux),
-	FUNCTION("audio_uart2_urxd_m2",
-			audio_uart2_urxd_grp2,
-			&audio_uart2_urxd_grp2_mux),
-	FUNCTION("audio_uart2_usclk_m0",
-			audio_uart2_usclk_grp0,
-			&audio_uart2_usclk_grp0_mux),
-	FUNCTION("audio_uart2_usclk_m1",
-			audio_uart2_usclk_grp1,
-			&audio_uart2_usclk_grp1_mux),
-	FUNCTION("audio_uart2_usclk_m2",
-			audio_uart2_usclk_grp2,
-			&audio_uart2_usclk_grp2_mux),
-	FUNCTION("audio_uart2_utfs_m0",
-			audio_uart2_utfs_grp0,
-			&audio_uart2_utfs_grp0_mux),
-	FUNCTION("audio_uart2_utfs_m1",
-			audio_uart2_utfs_grp1,
-			&audio_uart2_utfs_grp1_mux),
-	FUNCTION("audio_uart2_utfs_m2",
-			audio_uart2_utfs_grp2,
-			&audio_uart2_utfs_grp2_mux),
-	FUNCTION("audio_uart2_utxd_m0",
-			audio_uart2_utxd_grp0,
-			&audio_uart2_utxd_grp0_mux),
-	FUNCTION("audio_uart2_utxd_m1",
-			audio_uart2_utxd_grp1,
-			&audio_uart2_utxd_grp1_mux),
-	FUNCTION("audio_uart2_utxd_m2",
-			audio_uart2_utxd_grp2,
-			&audio_uart2_utxd_grp2_mux),
-	FUNCTION("c_can_trnsvr_en_m0",
-			c_can_trnsvr_en_grp0,
-			&c_can_trnsvr_en_grp0_mux),
-	FUNCTION("c_can_trnsvr_en_m1",
-			c_can_trnsvr_en_grp1,
-			&c_can_trnsvr_en_grp1_mux),
-	FUNCTION("c_can_trnsvr_intr",
-			c_can_trnsvr_intr_grp,
-			&c_can_trnsvr_intr_grp_mux),
-	FUNCTION("c_can_trnsvr_stb_n",
-			c_can_trnsvr_stb_n_grp,
-			&c_can_trnsvr_stb_n_grp_mux),
-	FUNCTION("c0_can_rxd_trnsv0",
-			c0_can_rxd_trnsv0_grp,
-			&c0_can_rxd_trnsv0_grp_mux),
-	FUNCTION("c0_can_rxd_trnsv1",
-			c0_can_rxd_trnsv1_grp,
-			&c0_can_rxd_trnsv1_grp_mux),
-	FUNCTION("c0_can_txd_trnsv0",
-			c0_can_txd_trnsv0_grp,
-			&c0_can_txd_trnsv0_grp_mux),
-	FUNCTION("c0_can_txd_trnsv1",
-			c0_can_txd_trnsv1_grp,
-			&c0_can_txd_trnsv1_grp_mux),
-	FUNCTION("c1_can_rxd_m0", c1_can_rxd_grp0, &c1_can_rxd_grp0_mux),
-	FUNCTION("c1_can_rxd_m1", c1_can_rxd_grp1, &c1_can_rxd_grp1_mux),
-	FUNCTION("c1_can_rxd_m2", c1_can_rxd_grp2, &c1_can_rxd_grp2_mux),
-	FUNCTION("c1_can_rxd_m3", c1_can_rxd_grp3, &c1_can_rxd_grp3_mux),
-	FUNCTION("c1_can_txd_m0", c1_can_txd_grp0, &c1_can_txd_grp0_mux),
-	FUNCTION("c1_can_txd_m1", c1_can_txd_grp1, &c1_can_txd_grp1_mux),
-	FUNCTION("c1_can_txd_m2", c1_can_txd_grp2, &c1_can_txd_grp2_mux),
-	FUNCTION("c1_can_txd_m3", c1_can_txd_grp3, &c1_can_txd_grp3_mux),
-	FUNCTION("ca_audio_lpc", ca_audio_lpc_grp, &ca_audio_lpc_grp_mux),
-	FUNCTION("ca_bt_lpc", ca_bt_lpc_grp, &ca_bt_lpc_grp_mux),
-	FUNCTION("ca_coex", ca_coex_grp, &ca_coex_grp_mux),
-	FUNCTION("ca_curator_lpc",
-			ca_curator_lpc_grp,
-			&ca_curator_lpc_grp_mux),
-	FUNCTION("ca_pcm_debug", ca_pcm_debug_grp, &ca_pcm_debug_grp_mux),
-	FUNCTION("ca_pio", ca_pio_grp, &ca_pio_grp_mux),
-	FUNCTION("ca_sdio_debug", ca_sdio_debug_grp, &ca_sdio_debug_grp_mux),
-	FUNCTION("ca_spi", ca_spi_grp, &ca_spi_grp_mux),
-	FUNCTION("ca_trb", ca_trb_grp, &ca_trb_grp_mux),
-	FUNCTION("ca_uart_debug", ca_uart_debug_grp, &ca_uart_debug_grp_mux),
-	FUNCTION("clkc_m0", clkc_grp0, &clkc_grp0_mux),
-	FUNCTION("clkc_m1", clkc_grp1, &clkc_grp1_mux),
-	FUNCTION("gn_gnss_i2c", gn_gnss_i2c_grp, &gn_gnss_i2c_grp_mux),
-	FUNCTION("gn_gnss_uart_nopause",
-			gn_gnss_uart_nopause_grp,
-			&gn_gnss_uart_nopause_grp_mux),
-	FUNCTION("gn_gnss_uart", gn_gnss_uart_grp, &gn_gnss_uart_grp_mux),
-	FUNCTION("gn_trg_spi_m0", gn_trg_spi_grp0, &gn_trg_spi_grp0_mux),
-	FUNCTION("gn_trg_spi_m1", gn_trg_spi_grp1, &gn_trg_spi_grp1_mux),
-	FUNCTION("cvbs_dbg", cvbs_dbg_grp, &cvbs_dbg_grp_mux),
-	FUNCTION("cvbs_dbg_test_m0",
-			cvbs_dbg_test_grp0,
-			&cvbs_dbg_test_grp0_mux),
-	FUNCTION("cvbs_dbg_test_m1",
-			cvbs_dbg_test_grp1,
-			&cvbs_dbg_test_grp1_mux),
-	FUNCTION("cvbs_dbg_test_m2",
-			cvbs_dbg_test_grp2,
-			&cvbs_dbg_test_grp2_mux),
-	FUNCTION("cvbs_dbg_test_m3",
-			cvbs_dbg_test_grp3,
-			&cvbs_dbg_test_grp3_mux),
-	FUNCTION("cvbs_dbg_test_m4",
-			cvbs_dbg_test_grp4,
-			&cvbs_dbg_test_grp4_mux),
-	FUNCTION("cvbs_dbg_test_m5",
-			cvbs_dbg_test_grp5,
-			&cvbs_dbg_test_grp5_mux),
-	FUNCTION("cvbs_dbg_test_m6",
-			cvbs_dbg_test_grp6,
-			&cvbs_dbg_test_grp6_mux),
-	FUNCTION("cvbs_dbg_test_m7",
-			cvbs_dbg_test_grp7,
-			&cvbs_dbg_test_grp7_mux),
-	FUNCTION("cvbs_dbg_test_m8",
-			cvbs_dbg_test_grp8,
-			&cvbs_dbg_test_grp8_mux),
-	FUNCTION("cvbs_dbg_test_m9",
-			cvbs_dbg_test_grp9,
-			&cvbs_dbg_test_grp9_mux),
-	FUNCTION("cvbs_dbg_test_m10",
-			cvbs_dbg_test_grp10,
-			&cvbs_dbg_test_grp10_mux),
-	FUNCTION("cvbs_dbg_test_m11",
-			cvbs_dbg_test_grp11,
-			&cvbs_dbg_test_grp11_mux),
-	FUNCTION("cvbs_dbg_test_m12",
-			cvbs_dbg_test_grp12,
-			&cvbs_dbg_test_grp12_mux),
-	FUNCTION("cvbs_dbg_test_m13",
-			cvbs_dbg_test_grp13,
-			&cvbs_dbg_test_grp13_mux),
-	FUNCTION("cvbs_dbg_test_m14",
-			cvbs_dbg_test_grp14,
-			&cvbs_dbg_test_grp14_mux),
-	FUNCTION("cvbs_dbg_test_m15",
-			cvbs_dbg_test_grp15,
-			&cvbs_dbg_test_grp15_mux),
-	FUNCTION("gn_gnss_power", gn_gnss_power_grp, &gn_gnss_power_grp_mux),
-	FUNCTION("gn_gnss_sw_status",
-			gn_gnss_sw_status_grp,
-			&gn_gnss_sw_status_grp_mux),
-	FUNCTION("gn_gnss_eclk", gn_gnss_eclk_grp, &gn_gnss_eclk_grp_mux),
-	FUNCTION("gn_gnss_irq1_m0",
-			gn_gnss_irq1_grp0,
-			&gn_gnss_irq1_grp0_mux),
-	FUNCTION("gn_gnss_irq2_m0",
-			gn_gnss_irq2_grp0,
-			&gn_gnss_irq2_grp0_mux),
-	FUNCTION("gn_gnss_tm", gn_gnss_tm_grp, &gn_gnss_tm_grp_mux),
-	FUNCTION("gn_gnss_tsync", gn_gnss_tsync_grp, &gn_gnss_tsync_grp_mux),
-	FUNCTION("gn_io_gnsssys_sw_cfg",
-			gn_io_gnsssys_sw_cfg_grp,
-			&gn_io_gnsssys_sw_cfg_grp_mux),
-	FUNCTION("gn_trg_m0", gn_trg_grp0, &gn_trg_grp0_mux),
-	FUNCTION("gn_trg_m1", gn_trg_grp1, &gn_trg_grp1_mux),
-	FUNCTION("gn_trg_shutdown_m0",
-			gn_trg_shutdown_grp0,
-			&gn_trg_shutdown_grp0_mux),
-	FUNCTION("gn_trg_shutdown_m1",
-			gn_trg_shutdown_grp1,
-			&gn_trg_shutdown_grp1_mux),
-	FUNCTION("gn_trg_shutdown_m2",
-			gn_trg_shutdown_grp2,
-			&gn_trg_shutdown_grp2_mux),
-	FUNCTION("gn_trg_shutdown_m3",
-			gn_trg_shutdown_grp3,
-			&gn_trg_shutdown_grp3_mux),
-	FUNCTION("i2c0", i2c0_grp, &i2c0_grp_mux),
-	FUNCTION("i2c1", i2c1_grp, &i2c1_grp_mux),
-	FUNCTION("i2s0", i2s0_grp, &i2s0_grp_mux),
-	FUNCTION("i2s1_basic", i2s1_basic_grp, &i2s1_basic_grp_mux),
-	FUNCTION("i2s1_rxd0_m0", i2s1_rxd0_grp0, &i2s1_rxd0_grp0_mux),
-	FUNCTION("i2s1_rxd0_m1", i2s1_rxd0_grp1, &i2s1_rxd0_grp1_mux),
-	FUNCTION("i2s1_rxd0_m2", i2s1_rxd0_grp2, &i2s1_rxd0_grp2_mux),
-	FUNCTION("i2s1_rxd0_m3", i2s1_rxd0_grp3, &i2s1_rxd0_grp3_mux),
-	FUNCTION("i2s1_rxd0_m4", i2s1_rxd0_grp4, &i2s1_rxd0_grp4_mux),
-	FUNCTION("i2s1_rxd1_m0", i2s1_rxd1_grp0, &i2s1_rxd1_grp0_mux),
-	FUNCTION("i2s1_rxd1_m1", i2s1_rxd1_grp1, &i2s1_rxd1_grp1_mux),
-	FUNCTION("i2s1_rxd1_m2", i2s1_rxd1_grp2, &i2s1_rxd1_grp2_mux),
-	FUNCTION("i2s1_rxd1_m3", i2s1_rxd1_grp3, &i2s1_rxd1_grp3_mux),
-	FUNCTION("i2s1_rxd1_m4", i2s1_rxd1_grp4, &i2s1_rxd1_grp4_mux),
-	FUNCTION("jtag_jt_dbg_nsrst",
-			jtag_jt_dbg_nsrst_grp,
-			&jtag_jt_dbg_nsrst_grp_mux),
-	FUNCTION("jtag_ntrst_m0", jtag_ntrst_grp0, &jtag_ntrst_grp0_mux),
-	FUNCTION("jtag_ntrst_m1", jtag_ntrst_grp1, &jtag_ntrst_grp1_mux),
-	FUNCTION("jtag_swdiotms_m0",
-			jtag_swdiotms_grp0,
-			&jtag_swdiotms_grp0_mux),
-	FUNCTION("jtag_swdiotms_m1",
-			jtag_swdiotms_grp1,
-			&jtag_swdiotms_grp1_mux),
-	FUNCTION("jtag_tck_m0", jtag_tck_grp0, &jtag_tck_grp0_mux),
-	FUNCTION("jtag_tck_m1", jtag_tck_grp1, &jtag_tck_grp1_mux),
-	FUNCTION("jtag_tdi_m0", jtag_tdi_grp0, &jtag_tdi_grp0_mux),
-	FUNCTION("jtag_tdi_m1", jtag_tdi_grp1, &jtag_tdi_grp1_mux),
-	FUNCTION("jtag_tdo_m0", jtag_tdo_grp0, &jtag_tdo_grp0_mux),
-	FUNCTION("jtag_tdo_m1", jtag_tdo_grp1, &jtag_tdo_grp1_mux),
-	FUNCTION("ks_kas_spi_m0", ks_kas_spi_grp0, &ks_kas_spi_grp0_mux),
-	FUNCTION("ld_ldd", ld_ldd_grp, &ld_ldd_grp_mux),
-	FUNCTION("ld_ldd_16bit", ld_ldd_16bit_grp, &ld_ldd_16bit_grp_mux),
-	FUNCTION("ld_ldd_fck", ld_ldd_fck_grp, &ld_ldd_fck_grp_mux),
-	FUNCTION("ld_ldd_lck", ld_ldd_lck_grp, &ld_ldd_lck_grp_mux),
-	FUNCTION("lr_lcdrom", lr_lcdrom_grp, &lr_lcdrom_grp_mux),
-	FUNCTION("lvds_analog", lvds_analog_grp, &lvds_analog_grp_mux),
-	FUNCTION("nd_df_basic", nd_df_basic_grp, &nd_df_basic_grp_mux),
-	FUNCTION("nd_df_wp", nd_df_wp_grp, &nd_df_wp_grp_mux),
-	FUNCTION("nd_df_cs", nd_df_cs_grp, &nd_df_cs_grp_mux),
-	FUNCTION("ps", ps_grp, &ps_grp_mux),
-	FUNCTION("ps_no_dir", ps_no_dir_grp, &ps_no_dir_grp_mux),
-	FUNCTION("pwc_core_on", pwc_core_on_grp, &pwc_core_on_grp_mux),
-	FUNCTION("pwc_ext_on", pwc_ext_on_grp, &pwc_ext_on_grp_mux),
-	FUNCTION("pwc_gpio3_clk", pwc_gpio3_clk_grp, &pwc_gpio3_clk_grp_mux),
-	FUNCTION("pwc_io_on", pwc_io_on_grp, &pwc_io_on_grp_mux),
-	FUNCTION("pwc_lowbatt_b_m0",
-			pwc_lowbatt_b_grp0,
-			&pwc_lowbatt_b_grp0_mux),
-	FUNCTION("pwc_mem_on", pwc_mem_on_grp, &pwc_mem_on_grp_mux),
-	FUNCTION("pwc_on_key_b_m0",
-			pwc_on_key_b_grp0,
-			&pwc_on_key_b_grp0_mux),
-	FUNCTION("pwc_wakeup_src0",
-			pwc_wakeup_src0_grp,
-			&pwc_wakeup_src0_grp_mux),
-	FUNCTION("pwc_wakeup_src1",
-			pwc_wakeup_src1_grp,
-			&pwc_wakeup_src1_grp_mux),
-	FUNCTION("pwc_wakeup_src2",
-			pwc_wakeup_src2_grp,
-			&pwc_wakeup_src2_grp_mux),
-	FUNCTION("pwc_wakeup_src3",
-			pwc_wakeup_src3_grp,
-			&pwc_wakeup_src3_grp_mux),
-	FUNCTION("pw_cko0_m0", pw_cko0_grp0, &pw_cko0_grp0_mux),
-	FUNCTION("pw_cko0_m1", pw_cko0_grp1, &pw_cko0_grp1_mux),
-	FUNCTION("pw_cko0_m2", pw_cko0_grp2, &pw_cko0_grp2_mux),
-	FUNCTION("pw_cko0_m3", pw_cko0_grp3, &pw_cko0_grp3_mux),
-	FUNCTION("pw_cko1_m0", pw_cko1_grp0, &pw_cko1_grp0_mux),
-	FUNCTION("pw_cko1_m1", pw_cko1_grp1, &pw_cko1_grp1_mux),
-	FUNCTION("pw_cko1_m2", pw_cko1_grp2, &pw_cko1_grp2_mux),
-	FUNCTION("pw_i2s01_clk_m0",
-			pw_i2s01_clk_grp0,
-			&pw_i2s01_clk_grp0_mux),
-	FUNCTION("pw_i2s01_clk_m1",
-			pw_i2s01_clk_grp1,
-			&pw_i2s01_clk_grp1_mux),
-	FUNCTION("pw_i2s01_clk_m2",
-			pw_i2s01_clk_grp2,
-			&pw_i2s01_clk_grp2_mux),
-	FUNCTION("pw_pwm0_m0", pw_pwm0_grp0, &pw_pwm0_grp0_mux),
-	FUNCTION("pw_pwm0_m1", pw_pwm0_grp1, &pw_pwm0_grp1_mux),
-	FUNCTION("pw_pwm1_m0", pw_pwm1_grp0, &pw_pwm1_grp0_mux),
-	FUNCTION("pw_pwm1_m1", pw_pwm1_grp1, &pw_pwm1_grp1_mux),
-	FUNCTION("pw_pwm1_m2", pw_pwm1_grp2, &pw_pwm1_grp2_mux),
-	FUNCTION("pw_pwm2_m0", pw_pwm2_grp0, &pw_pwm2_grp0_mux),
-	FUNCTION("pw_pwm2_m1", pw_pwm2_grp1, &pw_pwm2_grp1_mux),
-	FUNCTION("pw_pwm2_m2", pw_pwm2_grp2, &pw_pwm2_grp2_mux),
-	FUNCTION("pw_pwm3_m0", pw_pwm3_grp0, &pw_pwm3_grp0_mux),
-	FUNCTION("pw_pwm3_m1", pw_pwm3_grp1, &pw_pwm3_grp1_mux),
-	FUNCTION("pw_pwm_cpu_vol_m0",
-			pw_pwm_cpu_vol_grp0,
-			&pw_pwm_cpu_vol_grp0_mux),
-	FUNCTION("pw_pwm_cpu_vol_m1",
-			pw_pwm_cpu_vol_grp1,
-			&pw_pwm_cpu_vol_grp1_mux),
-	FUNCTION("pw_pwm_cpu_vol_m2",
-			pw_pwm_cpu_vol_grp2,
-			&pw_pwm_cpu_vol_grp2_mux),
-	FUNCTION("pw_backlight_m0",
-			pw_backlight_grp0,
-			&pw_backlight_grp0_mux),
-	FUNCTION("pw_backlight_m1",
-			pw_backlight_grp1,
-			&pw_backlight_grp1_mux),
-	FUNCTION("rg_eth_mac", rg_eth_mac_grp, &rg_eth_mac_grp_mux),
-	FUNCTION("rg_gmac_phy_intr_n",
-			rg_gmac_phy_intr_n_grp,
-			&rg_gmac_phy_intr_n_grp_mux),
-	FUNCTION("rg_rgmii_mac", rg_rgmii_mac_grp, &rg_rgmii_mac_grp_mux),
-	FUNCTION("rg_rgmii_phy_ref_clk_m0",
-			rg_rgmii_phy_ref_clk_grp0,
-			&rg_rgmii_phy_ref_clk_grp0_mux),
-	FUNCTION("rg_rgmii_phy_ref_clk_m1",
-			rg_rgmii_phy_ref_clk_grp1,
-			&rg_rgmii_phy_ref_clk_grp1_mux),
-	FUNCTION("sd0", sd0_grp, &sd0_grp_mux),
-	FUNCTION("sd0_4bit", sd0_4bit_grp, &sd0_4bit_grp_mux),
-	FUNCTION("sd1", sd1_grp, &sd1_grp_mux),
-	FUNCTION("sd1_4bit_m0", sd1_4bit_grp0, &sd1_4bit_grp0_mux),
-	FUNCTION("sd1_4bit_m1", sd1_4bit_grp1, &sd1_4bit_grp1_mux),
-	FUNCTION("sd2_basic", sd2_basic_grp, &sd2_basic_grp_mux),
-	FUNCTION("sd2_cdb_m0", sd2_cdb_grp0, &sd2_cdb_grp0_mux),
-	FUNCTION("sd2_cdb_m1", sd2_cdb_grp1, &sd2_cdb_grp1_mux),
-	FUNCTION("sd2_wpb_m0", sd2_wpb_grp0, &sd2_wpb_grp0_mux),
-	FUNCTION("sd2_wpb_m1", sd2_wpb_grp1, &sd2_wpb_grp1_mux),
-	FUNCTION("sd3", sd3_9_grp, &sd3_9_grp_mux),
-	FUNCTION("sd5", sd5_grp, &sd5_grp_mux),
-	FUNCTION("sd6_m0", sd6_grp0, &sd6_grp0_mux),
-	FUNCTION("sd6_m1", sd6_grp1, &sd6_grp1_mux),
-	FUNCTION("sd9", sd3_9_grp, &sd3_9_grp_mux),
-	FUNCTION("sp0_ext_ldo_on",
-			sp0_ext_ldo_on_grp,
-			&sp0_ext_ldo_on_grp_mux),
-	FUNCTION("sp0_qspi", sp0_qspi_grp, &sp0_qspi_grp_mux),
-	FUNCTION("sp1_spi", sp1_spi_grp, &sp1_spi_grp_mux),
-	FUNCTION("tpiu_trace", tpiu_trace_grp, &tpiu_trace_grp_mux),
-	FUNCTION("uart0", uart0_grp, &uart0_grp_mux),
-	FUNCTION("uart0_nopause", uart0_nopause_grp, &uart0_nopause_grp_mux),
-	FUNCTION("uart1", uart1_grp, &uart1_grp_mux),
-	FUNCTION("uart2_cts_m0", uart2_cts_grp0, &uart2_cts_grp0_mux),
-	FUNCTION("uart2_cts_m1", uart2_cts_grp1, &uart2_cts_grp1_mux),
-	FUNCTION("uart2_rts_m0", uart2_rts_grp0, &uart2_rts_grp0_mux),
-	FUNCTION("uart2_rts_m1", uart2_rts_grp1, &uart2_rts_grp1_mux),
-	FUNCTION("uart2_rxd_m0", uart2_rxd_grp0, &uart2_rxd_grp0_mux),
-	FUNCTION("uart2_rxd_m1", uart2_rxd_grp1, &uart2_rxd_grp1_mux),
-	FUNCTION("uart2_rxd_m2", uart2_rxd_grp2, &uart2_rxd_grp2_mux),
-	FUNCTION("uart2_txd_m0", uart2_txd_grp0, &uart2_txd_grp0_mux),
-	FUNCTION("uart2_txd_m1", uart2_txd_grp1, &uart2_txd_grp1_mux),
-	FUNCTION("uart2_txd_m2", uart2_txd_grp2, &uart2_txd_grp2_mux),
-	FUNCTION("uart3_cts_m0", uart3_cts_grp0, &uart3_cts_grp0_mux),
-	FUNCTION("uart3_cts_m1", uart3_cts_grp1, &uart3_cts_grp1_mux),
-	FUNCTION("uart3_cts_m2", uart3_cts_grp2, &uart3_cts_grp2_mux),
-	FUNCTION("uart3_rts_m0", uart3_rts_grp0, &uart3_rts_grp0_mux),
-	FUNCTION("uart3_rts_m1", uart3_rts_grp1, &uart3_rts_grp1_mux),
-	FUNCTION("uart3_rts_m2", uart3_rts_grp2, &uart3_rts_grp2_mux),
-	FUNCTION("uart3_rxd_m0", uart3_rxd_grp0, &uart3_rxd_grp0_mux),
-	FUNCTION("uart3_rxd_m1", uart3_rxd_grp1, &uart3_rxd_grp1_mux),
-	FUNCTION("uart3_rxd_m2", uart3_rxd_grp2, &uart3_rxd_grp2_mux),
-	FUNCTION("uart3_txd_m0", uart3_txd_grp0, &uart3_txd_grp0_mux),
-	FUNCTION("uart3_txd_m1", uart3_txd_grp1, &uart3_txd_grp1_mux),
-	FUNCTION("uart3_txd_m2", uart3_txd_grp2, &uart3_txd_grp2_mux),
-	FUNCTION("uart4_basic", uart4_basic_grp, &uart4_basic_grp_mux),
-	FUNCTION("uart4_cts_m0", uart4_cts_grp0, &uart4_cts_grp0_mux),
-	FUNCTION("uart4_cts_m1", uart4_cts_grp1, &uart4_cts_grp1_mux),
-	FUNCTION("uart4_cts_m2", uart4_cts_grp2, &uart4_cts_grp2_mux),
-	FUNCTION("uart4_rts_m0", uart4_rts_grp0, &uart4_rts_grp0_mux),
-	FUNCTION("uart4_rts_m1", uart4_rts_grp1, &uart4_rts_grp1_mux),
-	FUNCTION("uart4_rts_m2", uart4_rts_grp2, &uart4_rts_grp2_mux),
-	FUNCTION("usb0_drvvbus_m0",
-			usb0_drvvbus_grp0,
-			&usb0_drvvbus_grp0_mux),
-	FUNCTION("usb0_drvvbus_m1",
-			usb0_drvvbus_grp1,
-			&usb0_drvvbus_grp1_mux),
-	FUNCTION("usb1_drvvbus_m0",
-			usb1_drvvbus_grp0,
-			&usb1_drvvbus_grp0_mux),
-	FUNCTION("usb1_drvvbus_m1",
-			usb1_drvvbus_grp1,
-			&usb1_drvvbus_grp1_mux),
-	FUNCTION("visbus_dout", visbus_dout_grp, &visbus_dout_grp_mux),
-	FUNCTION("vi_vip1", vi_vip1_grp, &vi_vip1_grp_mux),
-	FUNCTION("vi_vip1_ext", vi_vip1_ext_grp, &vi_vip1_ext_grp_mux),
-	FUNCTION("vi_vip1_low8bit",
-			vi_vip1_low8bit_grp,
-			&vi_vip1_low8bit_grp_mux),
-	FUNCTION("vi_vip1_high8bit",
-			vi_vip1_high8bit_grp,
-			&vi_vip1_high8bit_grp_mux),
-};
-
-static struct atlas7_pinctrl_data atlas7_ioc_data = {
-	.pads = (struct pinctrl_pin_desc *)atlas7_ioc_pads,
-	.pads_cnt = ARRAY_SIZE(atlas7_ioc_pads),
-	.grps = (struct atlas7_pin_group *)altas7_pin_groups,
-	.grps_cnt = ARRAY_SIZE(altas7_pin_groups),
-	.funcs = (struct atlas7_pmx_func *)atlas7_pmx_functions,
-	.funcs_cnt = ARRAY_SIZE(atlas7_pmx_functions),
-	.confs = (struct atlas7_pad_config *)atlas7_ioc_pad_confs,
-	.confs_cnt = ARRAY_SIZE(atlas7_ioc_pad_confs),
-};
-
-/* Simple map data structure */
-struct map_data {
-	u8 idx;
-	u8 data;
-};
-
-/**
- * struct atlas7_pull_info - Atlas7 Pad pull info
- * @pad_type:	The type of this Pad.
- * @mask:	The mas value of this pin's pull bits.
- * @v2s:	The map of pull register value to pull status.
- * @s2v:	The map of pull status to pull register value.
- */
-struct atlas7_pull_info {
-	u8 pad_type;
-	u8 mask;
-	const struct map_data *v2s;
-	const struct map_data *s2v;
-};
-
-/* Pull Register value map to status */
-static const struct map_data p4we_pull_v2s[] = {
-	{ P4WE_PULL_UP, PULL_UP },
-	{ P4WE_HIGH_HYSTERESIS, HIGH_HYSTERESIS },
-	{ P4WE_HIGH_Z, HIGH_Z },
-	{ P4WE_PULL_DOWN, PULL_DOWN },
-};
-
-static const struct map_data p16st_pull_v2s[] = {
-	{ P16ST_PULL_UP, PULL_UP },
-	{ PD, PULL_UNKNOWN },
-	{ P16ST_HIGH_Z, HIGH_Z },
-	{ P16ST_PULL_DOWN, PULL_DOWN },
-};
-
-static const struct map_data pm31_pull_v2s[] = {
-	{ PM31_PULL_DISABLED, PULL_DOWN },
-	{ PM31_PULL_ENABLED, PULL_UP },
-};
-
-static const struct map_data pangd_pull_v2s[] = {
-	{ PANGD_PULL_UP, PULL_UP },
-	{ PD, PULL_UNKNOWN },
-	{ PANGD_HIGH_Z, HIGH_Z },
-	{ PANGD_PULL_DOWN, PULL_DOWN },
-};
-
-/* Pull status map to register value */
-static const struct map_data p4we_pull_s2v[] = {
-	{ PULL_UP, P4WE_PULL_UP },
-	{ HIGH_HYSTERESIS, P4WE_HIGH_HYSTERESIS },
-	{ HIGH_Z, P4WE_HIGH_Z },
-	{ PULL_DOWN, P4WE_PULL_DOWN },
-	{ PULL_DISABLE, -1 },
-	{ PULL_ENABLE, -1 },
-};
-
-static const struct map_data p16st_pull_s2v[] = {
-	{ PULL_UP, P16ST_PULL_UP },
-	{ HIGH_HYSTERESIS, -1 },
-	{ HIGH_Z, P16ST_HIGH_Z },
-	{ PULL_DOWN, P16ST_PULL_DOWN },
-	{ PULL_DISABLE, -1 },
-	{ PULL_ENABLE, -1 },
-};
-
-static const struct map_data pm31_pull_s2v[] = {
-	{ PULL_UP, PM31_PULL_ENABLED },
-	{ HIGH_HYSTERESIS, -1 },
-	{ HIGH_Z, -1 },
-	{ PULL_DOWN, PM31_PULL_DISABLED },
-	{ PULL_DISABLE, -1 },
-	{ PULL_ENABLE, -1 },
-};
-
-static const struct map_data pangd_pull_s2v[] = {
-	{ PULL_UP, PANGD_PULL_UP },
-	{ HIGH_HYSTERESIS, -1 },
-	{ HIGH_Z, PANGD_HIGH_Z },
-	{ PULL_DOWN, PANGD_PULL_DOWN },
-	{ PULL_DISABLE, -1 },
-	{ PULL_ENABLE, -1 },
-};
-
-static const struct atlas7_pull_info atlas7_pull_map[] = {
-	{ PAD_T_4WE_PD, P4WE_PULL_MASK, p4we_pull_v2s, p4we_pull_s2v },
-	{ PAD_T_4WE_PU, P4WE_PULL_MASK, p4we_pull_v2s, p4we_pull_s2v },
-	{ PAD_T_16ST, P16ST_PULL_MASK, p16st_pull_v2s, p16st_pull_s2v },
-	{ PAD_T_M31_0204_PD, PM31_PULL_MASK, pm31_pull_v2s, pm31_pull_s2v },
-	{ PAD_T_M31_0204_PU, PM31_PULL_MASK, pm31_pull_v2s, pm31_pull_s2v },
-	{ PAD_T_M31_0610_PD, PM31_PULL_MASK, pm31_pull_v2s, pm31_pull_s2v },
-	{ PAD_T_M31_0610_PU, PM31_PULL_MASK, pm31_pull_v2s, pm31_pull_s2v },
-	{ PAD_T_AD, PANGD_PULL_MASK, pangd_pull_v2s, pangd_pull_s2v },
-};
-
-/**
- * struct atlas7_ds_ma_info - Atlas7 Pad DriveStrength & currents info
- * @ma:		The Drive Strength in current value .
- * @ds_16st:	The correspond raw value of 16st pad.
- * @ds_4we:	The correspond raw value of 4we pad.
- * @ds_0204m31:	The correspond raw value of 0204m31 pad.
- * @ds_0610m31:	The correspond raw value of 0610m31 pad.
- */
-struct atlas7_ds_ma_info {
-	u32 ma;
-	u32 ds_16st;
-	u32 ds_4we;
-	u32 ds_0204m31;
-	u32 ds_0610m31;
-};
-
-static const struct atlas7_ds_ma_info atlas7_ma2ds_map[] = {
-	{ 2, DS_16ST_0, DS_4WE_0, DS_M31_0, DS_NULL },
-	{ 4, DS_16ST_1, DS_NULL, DS_M31_1, DS_NULL },
-	{ 6, DS_16ST_2, DS_NULL, DS_NULL, DS_M31_0 },
-	{ 8, DS_16ST_3, DS_4WE_1, DS_NULL, DS_NULL },
-	{ 10, DS_16ST_4, DS_NULL, DS_NULL, DS_M31_1 },
-	{ 12, DS_16ST_5, DS_NULL, DS_NULL, DS_NULL },
-	{ 14, DS_16ST_6, DS_NULL, DS_NULL, DS_NULL },
-	{ 16, DS_16ST_7, DS_4WE_2, DS_NULL, DS_NULL },
-	{ 18, DS_16ST_8, DS_NULL, DS_NULL, DS_NULL },
-	{ 20, DS_16ST_9, DS_NULL, DS_NULL, DS_NULL },
-	{ 22, DS_16ST_10, DS_NULL, DS_NULL, DS_NULL },
-	{ 24, DS_16ST_11, DS_NULL, DS_NULL, DS_NULL },
-	{ 26, DS_16ST_12, DS_NULL, DS_NULL, DS_NULL },
-	{ 28, DS_16ST_13, DS_4WE_3, DS_NULL, DS_NULL },
-	{ 30, DS_16ST_14, DS_NULL, DS_NULL, DS_NULL },
-	{ 32, DS_16ST_15, DS_NULL, DS_NULL, DS_NULL },
-};
-
-/**
- * struct atlas7_ds_info - Atlas7 Pad DriveStrength info
- * @type:		The type of this Pad.
- * @mask:		The mask value of this pin's pull bits.
- * @imval:		The immediate value of drives trength register.
- * @reserved:		Reserved space
- */
-struct atlas7_ds_info {
-	u8 type;
-	u8 mask;
-	u8 imval;
-	u8 reserved;
-};
-
-static const struct atlas7_ds_info atlas7_ds_map[] = {
-	{ PAD_T_4WE_PD, DS_2BIT_MASK, DS_2BIT_IM_VAL },
-	{ PAD_T_4WE_PU, DS_2BIT_MASK, DS_2BIT_IM_VAL },
-	{ PAD_T_16ST, DS_4BIT_MASK, DS_4BIT_IM_VAL },
-	{ PAD_T_M31_0204_PD, DS_1BIT_MASK, DS_1BIT_IM_VAL },
-	{ PAD_T_M31_0204_PU, DS_1BIT_MASK, DS_1BIT_IM_VAL },
-	{ PAD_T_M31_0610_PD, DS_1BIT_MASK, DS_1BIT_IM_VAL },
-	{ PAD_T_M31_0610_PU, DS_1BIT_MASK, DS_1BIT_IM_VAL },
-	{ PAD_T_AD, DS_NULL, DS_NULL },
-};
-
-static inline u32 atlas7_pin_to_bank(u32 pin)
-{
-	return (pin >= ATLAS7_PINCTRL_BANK_0_PINS) ? 1 : 0;
-}
-
-static int atlas7_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
-{
-	struct atlas7_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
-
-	return pmx->pctl_data->funcs_cnt;
-}
-
-static const char *atlas7_pmx_get_func_name(struct pinctrl_dev *pctldev,
-					u32 selector)
-{
-	struct atlas7_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
-
-	return pmx->pctl_data->funcs[selector].name;
-}
-
-static int atlas7_pmx_get_func_groups(struct pinctrl_dev *pctldev,
-		u32 selector, const char * const **groups,
-		u32 * const num_groups)
-{
-	struct atlas7_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
-
-	*groups = pmx->pctl_data->funcs[selector].groups;
-	*num_groups = pmx->pctl_data->funcs[selector].num_groups;
-
-	return 0;
-}
-
-static void __atlas7_pmx_pin_input_disable_set(struct atlas7_pmx *pmx,
-				const struct atlas7_pad_mux *mux)
-{
-	/* Set Input Disable to avoid input glitches
-	 *
-	 * All Input-Disable Control registers are located on IOCRTC.
-	 * So the regs bank is always 0.
-	 *
-	 */
-	if (mux->dinput_reg && mux->dinput_val_reg) {
-		writel(DI_MASK << mux->dinput_bit,
-			pmx->regs[BANK_DS] + CLR_REG(mux->dinput_reg));
-		writel(DI_DISABLE << mux->dinput_bit,
-			pmx->regs[BANK_DS] + mux->dinput_reg);
-
-
-		writel(DIV_MASK << mux->dinput_val_bit,
-			pmx->regs[BANK_DS] + CLR_REG(mux->dinput_val_reg));
-		writel(DIV_DISABLE << mux->dinput_val_bit,
-			pmx->regs[BANK_DS] + mux->dinput_val_reg);
-	}
-}
-
-static void __atlas7_pmx_pin_input_disable_clr(struct atlas7_pmx *pmx,
-				const struct atlas7_pad_mux *mux)
-{
-	/* Clear Input Disable to avoid input glitches */
-	if (mux->dinput_reg && mux->dinput_val_reg) {
-		writel(DI_MASK << mux->dinput_bit,
-			pmx->regs[BANK_DS] + CLR_REG(mux->dinput_reg));
-		writel(DI_ENABLE << mux->dinput_bit,
-			pmx->regs[BANK_DS] + mux->dinput_reg);
-
-		writel(DIV_MASK << mux->dinput_val_bit,
-			pmx->regs[BANK_DS] + CLR_REG(mux->dinput_val_reg));
-		writel(DIV_ENABLE << mux->dinput_val_bit,
-			pmx->regs[BANK_DS] + mux->dinput_val_reg);
-	}
-}
-
-static int __atlas7_pmx_pin_ad_sel(struct atlas7_pmx *pmx,
-			struct atlas7_pad_config *conf,
-			u32 bank, u32 ad_sel)
-{
-	unsigned long regv;
-
-	/* Write to clear register to clear A/D selector */
-	writel(ANA_CLEAR_MASK << conf->ad_ctrl_bit,
-		pmx->regs[bank] + CLR_REG(conf->ad_ctrl_reg));
-
-	/* Set target pad A/D selector */
-	regv = readl(pmx->regs[bank] + conf->ad_ctrl_reg);
-	regv &= ~(ANA_CLEAR_MASK << conf->ad_ctrl_bit);
-	writel(regv | (ad_sel << conf->ad_ctrl_bit),
-			pmx->regs[bank] + conf->ad_ctrl_reg);
-
-	regv = readl(pmx->regs[bank] + conf->ad_ctrl_reg);
-	pr_debug("bank:%d reg:0x%04x val:0x%08lx\n",
-			bank, conf->ad_ctrl_reg, regv);
-	return 0;
-}
-
-static int  __atlas7_pmx_pin_analog_enable(struct atlas7_pmx *pmx,
-			struct atlas7_pad_config *conf, u32 bank)
-{
-	/* Only PAD_T_AD pins can change between Analogue&Digital */
-	if (conf->type != PAD_T_AD)
-		return -EINVAL;
-
-	return __atlas7_pmx_pin_ad_sel(pmx, conf, bank, 0);
-}
-
-static int __atlas7_pmx_pin_digital_enable(struct atlas7_pmx *pmx,
-			struct atlas7_pad_config *conf, u32 bank)
-{
-	/* Other type pads are always digital */
-	if (conf->type != PAD_T_AD)
-		return 0;
-
-	return __atlas7_pmx_pin_ad_sel(pmx, conf, bank, 1);
-}
-
-static int __atlas7_pmx_pin_enable(struct atlas7_pmx *pmx,
-				u32 pin, u32 func)
-{
-	struct atlas7_pad_config *conf;
-	u32 bank;
-	int ret;
-	unsigned long regv;
-
-	pr_debug("PMX DUMP ### pin#%d func:%d #### START >>>\n",
-			pin, func);
-
-	/* Get this Pad's descriptor from PINCTRL */
-	conf = &pmx->pctl_data->confs[pin];
-	bank = atlas7_pin_to_bank(pin);
-
-	/* Just enable the analog function of this pad */
-	if (FUNC_ANALOGUE == func) {
-		ret = __atlas7_pmx_pin_analog_enable(pmx, conf, bank);
-		if (ret)
-			dev_err(pmx->dev,
-				"Convert pad#%d to analog failed, ret=%d\n",
-				pin, ret);
-		return ret;
-	}
-
-	/* Set Pads from analog to digital */
-	ret = __atlas7_pmx_pin_digital_enable(pmx, conf, bank);
-	if (ret) {
-		dev_err(pmx->dev,
-			"Convert pad#%d to digital failed, ret=%d\n",
-			pin, ret);
-		return ret;
-	}
-
-	/* Write to clear register to clear current function */
-	writel(FUNC_CLEAR_MASK << conf->mux_bit,
-		pmx->regs[bank] + CLR_REG(conf->mux_reg));
-
-	/* Set target pad mux function */
-	regv = readl(pmx->regs[bank] + conf->mux_reg);
-	regv &= ~(FUNC_CLEAR_MASK << conf->mux_bit);
-	writel(regv | (func << conf->mux_bit),
-			pmx->regs[bank] + conf->mux_reg);
-
-	regv = readl(pmx->regs[bank] + conf->mux_reg);
-	pr_debug("bank:%d reg:0x%04x val:0x%08lx\n",
-		bank, conf->mux_reg, regv);
-
-	return 0;
-}
-
-static int atlas7_pmx_set_mux(struct pinctrl_dev *pctldev,
-			u32 func_selector, u32 group_selector)
-{
-	int idx, ret;
-	struct atlas7_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
-	struct atlas7_pmx_func *pmx_func;
-	struct atlas7_pin_group *pin_grp;
-	const struct atlas7_grp_mux *grp_mux;
-	const struct atlas7_pad_mux *mux;
-
-	pmx_func = &pmx->pctl_data->funcs[func_selector];
-	pin_grp = &pmx->pctl_data->grps[group_selector];
-
-	pr_debug("PMX DUMP ### Function:[%s] Group:[%s] #### START >>>\n",
-			pmx_func->name, pin_grp->name);
-
-	/* the sd3 and sd9 pin select by SYS2PCI_SDIO9SEL register */
-	if (pin_grp->pins == (unsigned int *)&sd3_9_pins) {
-		if (!strcmp(pmx_func->name, "sd9"))
-			writel(1, pmx->sys2pci_base + SYS2PCI_SDIO9SEL);
-		else
-			writel(0, pmx->sys2pci_base + SYS2PCI_SDIO9SEL);
-	}
-
-	grp_mux = pmx_func->grpmux;
-
-	for (idx = 0; idx < grp_mux->pad_mux_count; idx++) {
-		mux = &grp_mux->pad_mux_list[idx];
-		__atlas7_pmx_pin_input_disable_set(pmx, mux);
-		ret = __atlas7_pmx_pin_enable(pmx, mux->pin, mux->func);
-		if (ret) {
-			dev_err(pmx->dev,
-				"FUNC:%s GRP:%s PIN#%d.%d failed, ret=%d\n",
-				pmx_func->name, pin_grp->name,
-				mux->pin, mux->func, ret);
-			BUG_ON(1);
-		}
-		__atlas7_pmx_pin_input_disable_clr(pmx, mux);
-	}
-	pr_debug("PMX DUMP ### Function:[%s] Group:[%s] #### END <<<\n",
-			pmx_func->name, pin_grp->name);
-
-	return 0;
-}
-
-static u32 convert_current_to_drive_strength(u32 type, u32 ma)
-{
-	int idx;
-
-	for (idx = 0; idx < ARRAY_SIZE(atlas7_ma2ds_map); idx++) {
-		if (atlas7_ma2ds_map[idx].ma != ma)
-			continue;
-
-		if (type == PAD_T_4WE_PD || type == PAD_T_4WE_PU)
-			return atlas7_ma2ds_map[idx].ds_4we;
-		else if (type == PAD_T_16ST)
-			return atlas7_ma2ds_map[idx].ds_16st;
-		else if (type == PAD_T_M31_0204_PD || type == PAD_T_M31_0204_PU)
-			return atlas7_ma2ds_map[idx].ds_0204m31;
-		else if (type == PAD_T_M31_0610_PD || type == PAD_T_M31_0610_PU)
-			return atlas7_ma2ds_map[idx].ds_0610m31;
-	}
-
-	return DS_NULL;
-}
-
-static int altas7_pinctrl_set_pull_sel(struct pinctrl_dev *pctldev,
-					u32 pin, u32 sel)
-{
-	struct atlas7_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
-	struct atlas7_pad_config *conf = &pmx->pctl_data->confs[pin];
-	const struct atlas7_pull_info *pull_info;
-	u32 bank;
-	unsigned long regv;
-	void __iomem *pull_sel_reg;
-
-	bank = atlas7_pin_to_bank(pin);
-	pull_info = &atlas7_pull_map[conf->type];
-	pull_sel_reg = pmx->regs[bank] + conf->pupd_reg;
-
-	/* Retrieve correspond register value from table by sel */
-	regv = pull_info->s2v[sel].data & pull_info->mask;
-
-	/* Clear & Set new value to pull register */
-	writel(pull_info->mask << conf->pupd_bit, CLR_REG(pull_sel_reg));
-	writel(regv << conf->pupd_bit, pull_sel_reg);
-
-	pr_debug("PIN_CFG ### SET PIN#%d PULL SELECTOR:%d == OK ####\n",
-		pin, sel);
-	return 0;
-}
-
-static int __altas7_pinctrl_set_drive_strength_sel(struct pinctrl_dev *pctldev,
-						u32 pin, u32 sel)
-{
-	struct atlas7_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
-	struct atlas7_pad_config *conf = &pmx->pctl_data->confs[pin];
-	const struct atlas7_ds_info *ds_info;
-	u32 bank;
-	void __iomem *ds_sel_reg;
-
-	ds_info = &atlas7_ds_map[conf->type];
-	if (sel & (~(ds_info->mask)))
-		goto unsupport;
-
-	bank = atlas7_pin_to_bank(pin);
-	ds_sel_reg = pmx->regs[bank] + conf->drvstr_reg;
-
-	writel(ds_info->imval << conf->drvstr_bit, CLR_REG(ds_sel_reg));
-	writel(sel << conf->drvstr_bit, ds_sel_reg);
-
-	return 0;
-
-unsupport:
-	pr_err("Pad#%d type[%d] doesn't support ds code[%d]!\n",
-		pin, conf->type, sel);
-	return -ENOTSUPP;
-}
-
-static int altas7_pinctrl_set_drive_strength_sel(struct pinctrl_dev *pctldev,
-						u32 pin, u32 ma)
-{
-	struct atlas7_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
-	struct atlas7_pad_config *conf = &pmx->pctl_data->confs[pin];
-	u32 type = conf->type;
-	u32 sel;
-	int ret;
-
-	sel = convert_current_to_drive_strength(conf->type, ma);
-	if (DS_NULL == sel) {
-		pr_err("Pad#%d type[%d] doesn't support ds current[%d]!\n",
-		pin, type, ma);
-		return -ENOTSUPP;
-	}
-
-	ret =  __altas7_pinctrl_set_drive_strength_sel(pctldev,
-						pin, sel);
-	pr_debug("PIN_CFG ### SET PIN#%d DS:%d MA:%d == %s ####\n",
-		pin, sel, ma, ret?"FAILED":"OK");
-	return ret;
-}
-
-static int atlas7_pmx_gpio_request_enable(struct pinctrl_dev *pctldev,
-		struct pinctrl_gpio_range *range, u32 pin)
-{
-	struct atlas7_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
-	u32 idx;
-
-	dev_dbg(pmx->dev,
-		"atlas7_pmx_gpio_request_enable: pin=%d\n", pin);
-	for (idx = 0; idx < range->npins; idx++) {
-		if (pin == range->pins[idx])
-			break;
-	}
-
-	if (idx >= range->npins) {
-		dev_err(pmx->dev,
-			"The pin#%d could not be requested as GPIO!!\n",
-			pin);
-		return -EPERM;
-	}
-
-	__atlas7_pmx_pin_enable(pmx, pin, FUNC_GPIO);
-
-	return 0;
-}
-
-static const struct pinmux_ops atlas7_pinmux_ops = {
-	.get_functions_count = atlas7_pmx_get_funcs_count,
-	.get_function_name = atlas7_pmx_get_func_name,
-	.get_function_groups = atlas7_pmx_get_func_groups,
-	.set_mux = atlas7_pmx_set_mux,
-	.gpio_request_enable = atlas7_pmx_gpio_request_enable,
-};
-
-static int atlas7_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
-{
-	struct atlas7_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
-
-	return pmx->pctl_data->grps_cnt;
-}
-
-static const char *atlas7_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
-						u32 group)
-{
-	struct atlas7_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
-
-	return pmx->pctl_data->grps[group].name;
-}
-
-static int atlas7_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
-		u32 group, const u32 **pins, u32 *num_pins)
-{
-	struct atlas7_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
-
-	*num_pins = pmx->pctl_data->grps[group].num_pins;
-	*pins = pmx->pctl_data->grps[group].pins;
-
-	return 0;
-}
-
-static int atlas7_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
-					struct device_node *np_config,
-					struct pinctrl_map **map,
-					u32 *num_maps)
-{
-	return pinconf_generic_dt_node_to_map(pctldev, np_config, map,
-				num_maps, PIN_MAP_TYPE_INVALID);
-}
-
-static void atlas7_pinctrl_dt_free_map(struct pinctrl_dev *pctldev,
-		struct pinctrl_map *map, u32 num_maps)
-{
-	kfree(map);
-}
-
-static const struct pinctrl_ops atlas7_pinctrl_ops = {
-	.get_groups_count = atlas7_pinctrl_get_groups_count,
-	.get_group_name = atlas7_pinctrl_get_group_name,
-	.get_group_pins = atlas7_pinctrl_get_group_pins,
-	.dt_node_to_map = atlas7_pinctrl_dt_node_to_map,
-	.dt_free_map = atlas7_pinctrl_dt_free_map,
-};
-
-static int atlas7_pin_config_set(struct pinctrl_dev *pctldev,
-				unsigned pin, unsigned long *configs,
-				unsigned num_configs)
-{
-	u16 param;
-	u32 arg;
-	int idx, err;
-
-	for (idx = 0; idx < num_configs; idx++) {
-		param = pinconf_to_config_param(configs[idx]);
-		arg = pinconf_to_config_argument(configs[idx]);
-
-		pr_debug("PMX CFG###### ATLAS7 PIN#%d [%s] CONFIG PARAM:%d ARG:%d >>>>>\n",
-			pin, atlas7_ioc_pads[pin].name, param, arg);
-		switch (param) {
-		case PIN_CONFIG_BIAS_PULL_UP:
-			err = altas7_pinctrl_set_pull_sel(pctldev,
-							pin, PULL_UP);
-			if (err)
-				return err;
-			break;
-
-		case PIN_CONFIG_BIAS_PULL_DOWN:
-			err = altas7_pinctrl_set_pull_sel(pctldev,
-							pin, PULL_DOWN);
-			if (err)
-				return err;
-			break;
-
-		case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
-			err = altas7_pinctrl_set_pull_sel(pctldev,
-							pin, HIGH_HYSTERESIS);
-			if (err)
-				return err;
-			break;
-		case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
-			err = altas7_pinctrl_set_pull_sel(pctldev,
-							pin, HIGH_Z);
-			if (err)
-				return err;
-			break;
-
-		case PIN_CONFIG_DRIVE_STRENGTH:
-			err = altas7_pinctrl_set_drive_strength_sel(pctldev,
-							pin, arg);
-			if (err)
-				return err;
-			break;
-		default:
-			return -ENOTSUPP;
-		}
-		pr_debug("PMX CFG###### ATLAS7 PIN#%d [%s] CONFIG PARAM:%d ARG:%d <<<<\n",
-			pin, atlas7_ioc_pads[pin].name, param, arg);
-	}
-
-	return 0;
-}
-
-static int atlas7_pin_config_group_set(struct pinctrl_dev *pctldev,
-				unsigned group, unsigned long *configs,
-				unsigned num_configs)
-{
-	const unsigned *pins;
-	unsigned npins;
-	int i, ret;
-
-	ret = atlas7_pinctrl_get_group_pins(pctldev, group, &pins, &npins);
-	if (ret)
-		return ret;
-	for (i = 0; i < npins; i++) {
-		if (atlas7_pin_config_set(pctldev, pins[i],
-					  configs, num_configs))
-			return -ENOTSUPP;
-	}
-	return 0;
-}
-
-static const struct pinconf_ops atlas7_pinconf_ops = {
-	.pin_config_set = atlas7_pin_config_set,
-	.pin_config_group_set = atlas7_pin_config_group_set,
-	.is_generic = true,
-};
-
-static int atlas7_pinmux_probe(struct platform_device *pdev)
-{
-	int ret, idx;
-	struct atlas7_pmx *pmx;
-	struct device_node *np = pdev->dev.of_node;
-	u32 banks = ATLAS7_PINCTRL_REG_BANKS;
-	struct device_node *sys2pci_np;
-	struct resource res;
-
-	/* Create state holders etc for this driver */
-	pmx = devm_kzalloc(&pdev->dev, sizeof(*pmx), GFP_KERNEL);
-	if (!pmx)
-		return -ENOMEM;
-
-	/* The sd3 and sd9 shared all pins, and the function select by
-	 * SYS2PCI_SDIO9SEL register
-	 */
-	sys2pci_np = of_find_node_by_name(NULL, "sys2pci");
-	if (!sys2pci_np)
-		return -EINVAL;
-
-	ret = of_address_to_resource(sys2pci_np, 0, &res);
-	of_node_put(sys2pci_np);
-	if (ret)
-		return ret;
-
-	pmx->sys2pci_base = devm_ioremap_resource(&pdev->dev, &res);
-	if (IS_ERR(pmx->sys2pci_base))
-		return -ENOMEM;
-
-	pmx->dev = &pdev->dev;
-
-	pmx->pctl_data = &atlas7_ioc_data;
-	pmx->pctl_desc.name = "pinctrl-atlas7";
-	pmx->pctl_desc.pins = pmx->pctl_data->pads;
-	pmx->pctl_desc.npins = pmx->pctl_data->pads_cnt;
-	pmx->pctl_desc.pctlops = &atlas7_pinctrl_ops;
-	pmx->pctl_desc.pmxops = &atlas7_pinmux_ops;
-	pmx->pctl_desc.confops = &atlas7_pinconf_ops;
-
-	for (idx = 0; idx < banks; idx++) {
-		pmx->regs[idx] = of_iomap(np, idx);
-		if (!pmx->regs[idx]) {
-			dev_err(&pdev->dev,
-				"can't map ioc bank#%d registers\n", idx);
-			ret = -ENOMEM;
-			goto unmap_io;
-		}
-	}
-
-	/* Now register the pin controller and all pins it handles */
-	pmx->pctl = pinctrl_register(&pmx->pctl_desc, &pdev->dev, pmx);
-	if (IS_ERR(pmx->pctl)) {
-		dev_err(&pdev->dev, "could not register atlas7 pinmux driver\n");
-		ret = PTR_ERR(pmx->pctl);
-		goto unmap_io;
-	}
-
-	platform_set_drvdata(pdev, pmx);
-
-	dev_info(&pdev->dev, "initialized atlas7 pinmux driver\n");
-
-	return 0;
-
-unmap_io:
-	for (idx = 0; idx < banks; idx++) {
-		if (!pmx->regs[idx])
-			break;
-		iounmap(pmx->regs[idx]);
-	}
-
-	return ret;
-}
-
-#ifdef CONFIG_PM_SLEEP
-static int atlas7_pinmux_suspend_noirq(struct device *dev)
-{
-	struct atlas7_pmx *pmx = dev_get_drvdata(dev);
-	struct atlas7_pad_status *status;
-	struct atlas7_pad_config *conf;
-	const struct atlas7_ds_info *ds_info;
-	const struct atlas7_pull_info *pull_info;
-	int idx;
-	u32 bank;
-	unsigned long regv;
-
-	for (idx = 0; idx < pmx->pctl_desc.npins; idx++) {
-		/* Get this Pad's descriptor from PINCTRL */
-		conf = &pmx->pctl_data->confs[idx];
-		bank = atlas7_pin_to_bank(idx);
-		status = &pmx->sleep_data[idx];
-
-		/* Save Function selector */
-		regv = readl(pmx->regs[bank] + conf->mux_reg);
-		status->func = (regv >> conf->mux_bit) & FUNC_CLEAR_MASK;
-
-		/* Check if Pad is in Analogue selector */
-		if (conf->ad_ctrl_reg == -1)
-			goto save_ds_sel;
-
-		regv = readl(pmx->regs[bank] + conf->ad_ctrl_reg);
-		if (!(regv & (conf->ad_ctrl_bit << ANA_CLEAR_MASK)))
-			status->func = FUNC_ANALOGUE;
-
-save_ds_sel:
-		if (conf->drvstr_reg == -1)
-			goto save_pull_sel;
-
-		/* Save Drive Strength selector */
-		ds_info = &atlas7_ds_map[conf->type];
-		regv = readl(pmx->regs[bank] + conf->drvstr_reg);
-		status->dstr = (regv >> conf->drvstr_bit) & ds_info->mask;
-
-save_pull_sel:
-		/* Save Pull selector */
-		pull_info = &atlas7_pull_map[conf->type];
-		regv = readl(pmx->regs[bank] + conf->pupd_reg);
-		regv = (regv >> conf->pupd_bit) & pull_info->mask;
-		status->pull = pull_info->v2s[regv].data;
-	}
-
-	/*
-	 * Save disable input selector, this selector is not for Pin,
-	 * but for Mux function.
-	 */
-	for (idx = 0; idx < NUM_OF_IN_DISABLE_REG; idx++) {
-		pmx->status_ds[idx] = readl(pmx->regs[BANK_DS] +
-					IN_DISABLE_0_REG_SET + 0x8 * idx);
-		pmx->status_dsv[idx] = readl(pmx->regs[BANK_DS] +
-					IN_DISABLE_VAL_0_REG_SET + 0x8 * idx);
-	}
-
-	return 0;
-}
-
-static int atlas7_pinmux_resume_noirq(struct device *dev)
-{
-	struct atlas7_pmx *pmx = dev_get_drvdata(dev);
-	struct atlas7_pad_status *status;
-	int idx;
-
-	for (idx = 0; idx < pmx->pctl_desc.npins; idx++) {
-		/* Get this Pad's descriptor from PINCTRL */
-		status = &pmx->sleep_data[idx];
-
-		/* Restore Function selector */
-		__atlas7_pmx_pin_enable(pmx, idx, (u32)status->func & 0xff);
-
-		if (FUNC_ANALOGUE == status->func)
-			goto restore_pull_sel;
-
-		/* Restore Drive Strength selector */
-		__altas7_pinctrl_set_drive_strength_sel(pmx->pctl, idx,
-						(u32)status->dstr & 0xff);
-
-restore_pull_sel:
-		/* Restore Pull selector */
-		altas7_pinctrl_set_pull_sel(pmx->pctl, idx,
-						(u32)status->pull & 0xff);
-	}
-
-	/*
-	 * Restore disable input selector, this selector is not for Pin,
-	 * but for Mux function
-	 */
-	for (idx = 0; idx < NUM_OF_IN_DISABLE_REG; idx++) {
-		writel(~0, pmx->regs[BANK_DS] +
-					IN_DISABLE_0_REG_CLR + 0x8 * idx);
-		writel(pmx->status_ds[idx], pmx->regs[BANK_DS] +
-					IN_DISABLE_0_REG_SET + 0x8 * idx);
-		writel(~0, pmx->regs[BANK_DS] +
-					IN_DISABLE_VAL_0_REG_CLR + 0x8 * idx);
-		writel(pmx->status_dsv[idx], pmx->regs[BANK_DS] +
-					IN_DISABLE_VAL_0_REG_SET + 0x8 * idx);
-	}
-
-	return 0;
-}
-
-static const struct dev_pm_ops atlas7_pinmux_pm_ops = {
-	.suspend_noirq = atlas7_pinmux_suspend_noirq,
-	.resume_noirq = atlas7_pinmux_resume_noirq,
-	.freeze_noirq = atlas7_pinmux_suspend_noirq,
-	.restore_noirq = atlas7_pinmux_resume_noirq,
-};
-#endif
-
-static const struct of_device_id atlas7_pinmux_ids[] = {
-	{ .compatible = "sirf,atlas7-ioc",},
-	{},
-};
-
-static struct platform_driver atlas7_pinmux_driver = {
-	.driver = {
-		.name = "atlas7-ioc",
-		.of_match_table = atlas7_pinmux_ids,
-#ifdef CONFIG_PM_SLEEP
-		.pm = &atlas7_pinmux_pm_ops,
-#endif
-	},
-	.probe = atlas7_pinmux_probe,
-};
-
-static int __init atlas7_pinmux_init(void)
-{
-	return platform_driver_register(&atlas7_pinmux_driver);
-}
-arch_initcall(atlas7_pinmux_init);
-
-
-/*
- * The Following is GPIO Code
- */
-static inline struct
-atlas7_gpio_bank *atlas7_gpio_to_bank(struct atlas7_gpio_chip *a7gc, u32 gpio)
-{
-	return &a7gc->banks[GPIO_TO_BANK(gpio)];
-}
-
-static int __atlas7_gpio_to_pin(struct atlas7_gpio_chip *a7gc, u32 gpio)
-{
-	struct atlas7_gpio_bank *bank;
-	u32 ofs;
-
-	bank = atlas7_gpio_to_bank(a7gc, gpio);
-	ofs = gpio - bank->gpio_offset;
-	if (ofs >= bank->ngpio)
-		return -ENODEV;
-
-	return bank->gpio_pins[ofs];
-}
-
-static void atlas7_gpio_irq_ack(struct irq_data *d)
-{
-	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
-	struct atlas7_gpio_chip *a7gc = gpiochip_get_data(gc);
-	struct atlas7_gpio_bank *bank;
-	void __iomem *ctrl_reg;
-	u32 val, pin_in_bank;
-	unsigned long flags;
-
-	bank = atlas7_gpio_to_bank(a7gc, d->hwirq);
-	pin_in_bank = d->hwirq - bank->gpio_offset;
-	ctrl_reg = ATLAS7_GPIO_CTRL(bank, pin_in_bank);
-
-	raw_spin_lock_irqsave(&a7gc->lock, flags);
-
-	val = readl(ctrl_reg);
-	/* clear interrupt status */
-	writel(val, ctrl_reg);
-
-	raw_spin_unlock_irqrestore(&a7gc->lock, flags);
-}
-
-static void __atlas7_gpio_irq_mask(struct atlas7_gpio_chip *a7gc, int idx)
-{
-	struct atlas7_gpio_bank *bank;
-	void __iomem *ctrl_reg;
-	u32 val, pin_in_bank;
-
-	bank = atlas7_gpio_to_bank(a7gc, idx);
-	pin_in_bank = idx - bank->gpio_offset;
-	ctrl_reg = ATLAS7_GPIO_CTRL(bank, pin_in_bank);
-
-	val = readl(ctrl_reg);
-	val &= ~(ATLAS7_GPIO_CTL_INTR_EN_MASK |
-		ATLAS7_GPIO_CTL_INTR_STATUS_MASK);
-	writel(val, ctrl_reg);
-}
-
-static void atlas7_gpio_irq_mask(struct irq_data *d)
-{
-	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
-	struct atlas7_gpio_chip *a7gc = gpiochip_get_data(gc);
-	unsigned long flags;
-
-	raw_spin_lock_irqsave(&a7gc->lock, flags);
-
-	__atlas7_gpio_irq_mask(a7gc, d->hwirq);
-
-	raw_spin_unlock_irqrestore(&a7gc->lock, flags);
-}
-
-static void atlas7_gpio_irq_unmask(struct irq_data *d)
-{
-	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
-	struct atlas7_gpio_chip *a7gc = gpiochip_get_data(gc);
-	struct atlas7_gpio_bank *bank;
-	void __iomem *ctrl_reg;
-	u32 val, pin_in_bank;
-	unsigned long flags;
-
-	bank = atlas7_gpio_to_bank(a7gc, d->hwirq);
-	pin_in_bank = d->hwirq - bank->gpio_offset;
-	ctrl_reg = ATLAS7_GPIO_CTRL(bank, pin_in_bank);
-
-	raw_spin_lock_irqsave(&a7gc->lock, flags);
-
-	val = readl(ctrl_reg);
-	val &= ~ATLAS7_GPIO_CTL_INTR_STATUS_MASK;
-	val |= ATLAS7_GPIO_CTL_INTR_EN_MASK;
-	writel(val, ctrl_reg);
-
-	raw_spin_unlock_irqrestore(&a7gc->lock, flags);
-}
-
-static int atlas7_gpio_irq_type(struct irq_data *d,
-				unsigned int type)
-{
-	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
-	struct atlas7_gpio_chip *a7gc = gpiochip_get_data(gc);
-	struct atlas7_gpio_bank *bank;
-	void __iomem *ctrl_reg;
-	u32 val, pin_in_bank;
-	unsigned long flags;
-
-	bank = atlas7_gpio_to_bank(a7gc, d->hwirq);
-	pin_in_bank = d->hwirq - bank->gpio_offset;
-	ctrl_reg = ATLAS7_GPIO_CTRL(bank, pin_in_bank);
-
-	raw_spin_lock_irqsave(&a7gc->lock, flags);
-
-	val = readl(ctrl_reg);
-	val &= ~(ATLAS7_GPIO_CTL_INTR_STATUS_MASK |
-		ATLAS7_GPIO_CTL_INTR_EN_MASK);
-
-	switch (type) {
-	case IRQ_TYPE_NONE:
-		break;
-
-	case IRQ_TYPE_EDGE_RISING:
-		val |= ATLAS7_GPIO_CTL_INTR_HIGH_MASK |
-			ATLAS7_GPIO_CTL_INTR_TYPE_MASK;
-		val &= ~ATLAS7_GPIO_CTL_INTR_LOW_MASK;
-		break;
-
-	case IRQ_TYPE_EDGE_FALLING:
-		val &= ~ATLAS7_GPIO_CTL_INTR_HIGH_MASK;
-		val |= ATLAS7_GPIO_CTL_INTR_LOW_MASK |
-			ATLAS7_GPIO_CTL_INTR_TYPE_MASK;
-		break;
-
-	case IRQ_TYPE_EDGE_BOTH:
-		val |= ATLAS7_GPIO_CTL_INTR_HIGH_MASK |
-			ATLAS7_GPIO_CTL_INTR_LOW_MASK |
-			ATLAS7_GPIO_CTL_INTR_TYPE_MASK;
-		break;
-
-	case IRQ_TYPE_LEVEL_LOW:
-		val &= ~(ATLAS7_GPIO_CTL_INTR_HIGH_MASK |
-			ATLAS7_GPIO_CTL_INTR_TYPE_MASK);
-		val |= ATLAS7_GPIO_CTL_INTR_LOW_MASK;
-		break;
-
-	case IRQ_TYPE_LEVEL_HIGH:
-		val |= ATLAS7_GPIO_CTL_INTR_HIGH_MASK;
-		val &= ~(ATLAS7_GPIO_CTL_INTR_LOW_MASK |
-			ATLAS7_GPIO_CTL_INTR_TYPE_MASK);
-		break;
-	}
-
-	writel(val, ctrl_reg);
-
-	raw_spin_unlock_irqrestore(&a7gc->lock, flags);
-
-	return 0;
-}
-
-static struct irq_chip atlas7_gpio_irq_chip = {
-	.name = "atlas7-gpio-irq",
-	.irq_ack = atlas7_gpio_irq_ack,
-	.irq_mask = atlas7_gpio_irq_mask,
-	.irq_unmask = atlas7_gpio_irq_unmask,
-	.irq_set_type = atlas7_gpio_irq_type,
-};
-
-static void atlas7_gpio_handle_irq(struct irq_desc *desc)
-{
-	struct gpio_chip *gc = irq_desc_get_handler_data(desc);
-	struct atlas7_gpio_chip *a7gc = gpiochip_get_data(gc);
-	struct atlas7_gpio_bank *bank = NULL;
-	u32 status, ctrl;
-	int pin_in_bank = 0, idx;
-	struct irq_chip *chip = irq_desc_get_chip(desc);
-	unsigned int irq = irq_desc_get_irq(desc);
-
-	for (idx = 0; idx < a7gc->nbank; idx++) {
-		bank = &a7gc->banks[idx];
-		if (bank->irq == irq)
-			break;
-	}
-	BUG_ON(idx == a7gc->nbank);
-
-	chained_irq_enter(chip, desc);
-
-	status = readl(ATLAS7_GPIO_INT_STATUS(bank));
-	if (!status) {
-		pr_warn("%s: gpio [%s] status %#x no interrupt is flagged\n",
-			__func__, gc->label, status);
-		handle_bad_irq(desc);
-		return;
-	}
-
-	while (status) {
-		ctrl = readl(ATLAS7_GPIO_CTRL(bank, pin_in_bank));
-
-		/*
-		 * Here we must check whether the corresponding GPIO's
-		 * interrupt has been enabled, otherwise just skip it
-		 */
-		if ((status & 0x1) && (ctrl & ATLAS7_GPIO_CTL_INTR_EN_MASK)) {
-			pr_debug("%s: chip[%s] gpio:%d happens\n",
-				__func__, gc->label,
-				bank->gpio_offset + pin_in_bank);
-			generic_handle_irq(
-				irq_find_mapping(gc->irq.domain,
-					bank->gpio_offset + pin_in_bank));
-		}
-
-		if (++pin_in_bank >= bank->ngpio)
-			break;
-
-		status = status >> 1;
-	}
-
-	chained_irq_exit(chip, desc);
-}
-
-static void __atlas7_gpio_set_input(struct atlas7_gpio_chip *a7gc,
-				unsigned int gpio)
-{
-	struct atlas7_gpio_bank *bank;
-	void __iomem *ctrl_reg;
-	u32 val, pin_in_bank;
-
-	bank = atlas7_gpio_to_bank(a7gc, gpio);
-	pin_in_bank = gpio - bank->gpio_offset;
-	ctrl_reg = ATLAS7_GPIO_CTRL(bank, pin_in_bank);
-
-	val = readl(ctrl_reg);
-	val &= ~ATLAS7_GPIO_CTL_OUT_EN_MASK;
-	writel(val, ctrl_reg);
-}
-
-static int atlas7_gpio_request(struct gpio_chip *chip,
-				unsigned int gpio)
-{
-	struct atlas7_gpio_chip *a7gc = gpiochip_get_data(chip);
-	int ret;
-	unsigned long flags;
-
-	ret = __atlas7_gpio_to_pin(a7gc, gpio);
-	if (ret < 0)
-		return ret;
-
-	if (pinctrl_gpio_request(chip->base + gpio))
-		return -ENODEV;
-
-	raw_spin_lock_irqsave(&a7gc->lock, flags);
-
-	/*
-	 * default status:
-	 * set direction as input and mask irq
-	 */
-	__atlas7_gpio_set_input(a7gc, gpio);
-	__atlas7_gpio_irq_mask(a7gc, gpio);
-
-	raw_spin_unlock_irqrestore(&a7gc->lock, flags);
-
-	return 0;
-}
-
-static void atlas7_gpio_free(struct gpio_chip *chip,
-				unsigned int gpio)
-{
-	struct atlas7_gpio_chip *a7gc = gpiochip_get_data(chip);
-	unsigned long flags;
-
-	raw_spin_lock_irqsave(&a7gc->lock, flags);
-
-	__atlas7_gpio_irq_mask(a7gc, gpio);
-	__atlas7_gpio_set_input(a7gc, gpio);
-
-	raw_spin_unlock_irqrestore(&a7gc->lock, flags);
-
-	pinctrl_gpio_free(chip->base + gpio);
-}
-
-static int atlas7_gpio_direction_input(struct gpio_chip *chip,
-					unsigned int gpio)
-{
-	struct atlas7_gpio_chip *a7gc = gpiochip_get_data(chip);
-	unsigned long flags;
-
-	raw_spin_lock_irqsave(&a7gc->lock, flags);
-
-	__atlas7_gpio_set_input(a7gc, gpio);
-
-	raw_spin_unlock_irqrestore(&a7gc->lock, flags);
-
-	return 0;
-}
-
-static void __atlas7_gpio_set_output(struct atlas7_gpio_chip *a7gc,
-			   unsigned int gpio, int value)
-{
-	struct atlas7_gpio_bank *bank;
-	void __iomem *ctrl_reg;
-	u32 out_ctrl, pin_in_bank;
-
-	bank = atlas7_gpio_to_bank(a7gc, gpio);
-	pin_in_bank = gpio - bank->gpio_offset;
-	ctrl_reg = ATLAS7_GPIO_CTRL(bank, pin_in_bank);
-
-	out_ctrl = readl(ctrl_reg);
-	if (value)
-		out_ctrl |= ATLAS7_GPIO_CTL_DATAOUT_MASK;
-	else
-		out_ctrl &= ~ATLAS7_GPIO_CTL_DATAOUT_MASK;
-
-	out_ctrl &= ~ATLAS7_GPIO_CTL_INTR_EN_MASK;
-	out_ctrl |= ATLAS7_GPIO_CTL_OUT_EN_MASK;
-	writel(out_ctrl, ctrl_reg);
-}
-
-static int atlas7_gpio_direction_output(struct gpio_chip *chip,
-				unsigned int gpio, int value)
-{
-	struct atlas7_gpio_chip *a7gc = gpiochip_get_data(chip);
-	unsigned long flags;
-
-	raw_spin_lock_irqsave(&a7gc->lock, flags);
-
-	__atlas7_gpio_set_output(a7gc, gpio, value);
-
-	raw_spin_unlock_irqrestore(&a7gc->lock, flags);
-
-	return 0;
-}
-
-static int atlas7_gpio_get_value(struct gpio_chip *chip,
-					unsigned int gpio)
-{
-	struct atlas7_gpio_chip *a7gc = gpiochip_get_data(chip);
-	struct atlas7_gpio_bank *bank;
-	u32 val, pin_in_bank;
-	unsigned long flags;
-
-	bank = atlas7_gpio_to_bank(a7gc, gpio);
-	pin_in_bank = gpio - bank->gpio_offset;
-
-	raw_spin_lock_irqsave(&a7gc->lock, flags);
-
-	val = readl(ATLAS7_GPIO_CTRL(bank, pin_in_bank));
-
-	raw_spin_unlock_irqrestore(&a7gc->lock, flags);
-
-	return !!(val & ATLAS7_GPIO_CTL_DATAIN_MASK);
-}
-
-static void atlas7_gpio_set_value(struct gpio_chip *chip,
-				unsigned int gpio, int value)
-{
-	struct atlas7_gpio_chip *a7gc = gpiochip_get_data(chip);
-	struct atlas7_gpio_bank *bank;
-	void __iomem *ctrl_reg;
-	u32 ctrl, pin_in_bank;
-	unsigned long flags;
-
-	bank = atlas7_gpio_to_bank(a7gc, gpio);
-	pin_in_bank = gpio - bank->gpio_offset;
-	ctrl_reg = ATLAS7_GPIO_CTRL(bank, pin_in_bank);
-
-	raw_spin_lock_irqsave(&a7gc->lock, flags);
-
-	ctrl = readl(ctrl_reg);
-	if (value)
-		ctrl |= ATLAS7_GPIO_CTL_DATAOUT_MASK;
-	else
-		ctrl &= ~ATLAS7_GPIO_CTL_DATAOUT_MASK;
-	writel(ctrl, ctrl_reg);
-
-	raw_spin_unlock_irqrestore(&a7gc->lock, flags);
-}
-
-static const struct of_device_id atlas7_gpio_ids[] = {
-	{ .compatible = "sirf,atlas7-gpio", },
-	{},
-};
-
-static int atlas7_gpio_probe(struct platform_device *pdev)
-{
-	struct device_node *np = pdev->dev.of_node;
-	struct atlas7_gpio_chip *a7gc;
-	struct gpio_chip *chip;
-	u32 nbank;
-	int ret, idx;
-	struct gpio_irq_chip *girq;
-
-	ret = of_property_read_u32(np, "gpio-banks", &nbank);
-	if (ret) {
-		dev_err(&pdev->dev,
-			"Could not find GPIO bank info,ret=%d!\n",
-			ret);
-		return ret;
-	}
-
-	/* retrieve gpio descriptor data */
-	a7gc = devm_kzalloc(&pdev->dev, struct_size(a7gc, banks, nbank),
-			    GFP_KERNEL);
-	if (!a7gc)
-		return -ENOMEM;
-
-	/* Get Gpio clk */
-	a7gc->clk = of_clk_get(np, 0);
-	if (!IS_ERR(a7gc->clk)) {
-		ret = clk_prepare_enable(a7gc->clk);
-		if (ret) {
-			dev_err(&pdev->dev,
-				"Could not enable clock!\n");
-			return ret;
-		}
-	}
-
-	/* Get Gpio Registers */
-	a7gc->reg = of_iomap(np, 0);
-	if (!a7gc->reg) {
-		dev_err(&pdev->dev, "Could not map GPIO Registers!\n");
-		return -ENOMEM;
-	}
-
-	a7gc->nbank = nbank;
-	raw_spin_lock_init(&a7gc->lock);
-
-	/* Setup GPIO Chip */
-	chip = &a7gc->chip;
-	chip->request = atlas7_gpio_request;
-	chip->free = atlas7_gpio_free;
-	chip->direction_input = atlas7_gpio_direction_input;
-	chip->get = atlas7_gpio_get_value;
-	chip->direction_output = atlas7_gpio_direction_output;
-	chip->set = atlas7_gpio_set_value;
-	chip->base = -1;
-	/* Each chip can support 32 pins at one bank */
-	chip->ngpio = NGPIO_OF_BANK * nbank;
-	chip->label = kstrdup(np->name, GFP_KERNEL);
-	chip->of_node = np;
-	chip->of_gpio_n_cells = 2;
-	chip->parent = &pdev->dev;
-
-	girq = &chip->irq;
-	girq->chip = &atlas7_gpio_irq_chip;
-	girq->parent_handler = atlas7_gpio_handle_irq;
-	girq->num_parents = nbank;
-	girq->parents = devm_kcalloc(&pdev->dev, nbank,
-				     sizeof(*girq->parents),
-				     GFP_KERNEL);
-	if (!girq->parents)
-		return -ENOMEM;
-	for (idx = 0; idx < nbank; idx++) {
-		struct atlas7_gpio_bank *bank;
-
-		bank = &a7gc->banks[idx];
-		/* Set ctrl registers' base of this bank */
-		bank->base = ATLAS7_GPIO_BASE(a7gc, idx);
-		bank->gpio_offset = idx * NGPIO_OF_BANK;
-
-		/* Get interrupt number from DTS */
-		ret = of_irq_get(np, idx);
-		if (ret <= 0) {
-			dev_err(&pdev->dev,
-				"Unable to find IRQ number. ret=%d\n", ret);
-			if (!ret)
-				ret = -ENXIO;
-			goto failed;
-		}
-		bank->irq = ret;
-		girq->parents[idx] = ret;
-	}
-	girq->default_type = IRQ_TYPE_NONE;
-	girq->handler = handle_level_irq;
-
-	/* Add gpio chip to system */
-	ret = gpiochip_add_data(chip, a7gc);
-	if (ret) {
-		dev_err(&pdev->dev,
-			"%pOF: error in probe function with status %d\n",
-			np, ret);
-		goto failed;
-	}
-
-	platform_set_drvdata(pdev, a7gc);
-	dev_info(&pdev->dev, "add to system.\n");
-	return 0;
-failed:
-	return ret;
-}
-
-#ifdef CONFIG_PM_SLEEP
-static int atlas7_gpio_suspend_noirq(struct device *dev)
-{
-	struct atlas7_gpio_chip *a7gc = dev_get_drvdata(dev);
-	struct atlas7_gpio_bank *bank;
-	void __iomem *ctrl_reg;
-	u32 idx, pin;
-
-	for (idx = 0; idx < a7gc->nbank; idx++) {
-		bank = &a7gc->banks[idx];
-		for (pin = 0; pin < bank->ngpio; pin++) {
-			ctrl_reg = ATLAS7_GPIO_CTRL(bank, pin);
-			bank->sleep_data[pin] = readl(ctrl_reg);
-		}
-	}
-
-	return 0;
-}
-
-static int atlas7_gpio_resume_noirq(struct device *dev)
-{
-	struct atlas7_gpio_chip *a7gc = dev_get_drvdata(dev);
-	struct atlas7_gpio_bank *bank;
-	void __iomem *ctrl_reg;
-	u32 idx, pin;
-
-	for (idx = 0; idx < a7gc->nbank; idx++) {
-		bank = &a7gc->banks[idx];
-		for (pin = 0; pin < bank->ngpio; pin++) {
-			ctrl_reg = ATLAS7_GPIO_CTRL(bank, pin);
-			writel(bank->sleep_data[pin], ctrl_reg);
-		}
-	}
-
-	return 0;
-}
-
-static const struct dev_pm_ops atlas7_gpio_pm_ops = {
-	.suspend_noirq = atlas7_gpio_suspend_noirq,
-	.resume_noirq = atlas7_gpio_resume_noirq,
-	.freeze_noirq = atlas7_gpio_suspend_noirq,
-	.restore_noirq = atlas7_gpio_resume_noirq,
-};
-#endif
-
-static struct platform_driver atlas7_gpio_driver = {
-	.driver = {
-		.name = "atlas7-gpio",
-		.of_match_table = atlas7_gpio_ids,
-#ifdef CONFIG_PM_SLEEP
-		.pm = &atlas7_gpio_pm_ops,
-#endif
-	},
-	.probe = atlas7_gpio_probe,
-};
-
-static int __init atlas7_gpio_init(void)
-{
-	return platform_driver_register(&atlas7_gpio_driver);
-}
-subsys_initcall(atlas7_gpio_init);
diff --git a/drivers/pinctrl/sirf/pinctrl-prima2.c b/drivers/pinctrl/sirf/pinctrl-prima2.c
deleted file mode 100644
index 49da2a7eba1f..000000000000
--- a/drivers/pinctrl/sirf/pinctrl-prima2.c
+++ /dev/null
@@ -1,1131 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-/*
- * pinctrl pads, groups, functions for CSR SiRFprimaII
- *
- * Copyright (c) 2011 - 2014 Cambridge Silicon Radio Limited, a CSR plc group
- * company.
- */
-
-#include <linux/pinctrl/pinctrl.h>
-#include <linux/bitops.h>
-
-#include "pinctrl-sirf.h"
-
-/*
- * pad list for the pinmux subsystem
- * refer to CS-131858-DC-6A.xls
- */
-static const struct pinctrl_pin_desc sirfsoc_pads[] = {
-	PINCTRL_PIN(0, "gpio0-0"),
-	PINCTRL_PIN(1, "gpio0-1"),
-	PINCTRL_PIN(2, "gpio0-2"),
-	PINCTRL_PIN(3, "gpio0-3"),
-	PINCTRL_PIN(4, "pwm0"),
-	PINCTRL_PIN(5, "pwm1"),
-	PINCTRL_PIN(6, "pwm2"),
-	PINCTRL_PIN(7, "pwm3"),
-	PINCTRL_PIN(8, "warm_rst_b"),
-	PINCTRL_PIN(9, "odo_0"),
-	PINCTRL_PIN(10, "odo_1"),
-	PINCTRL_PIN(11, "dr_dir"),
-	PINCTRL_PIN(12, "viprom_fa"),
-	PINCTRL_PIN(13, "scl_1"),
-	PINCTRL_PIN(14, "ntrst"),
-	PINCTRL_PIN(15, "sda_1"),
-	PINCTRL_PIN(16, "x_ldd[16]"),
-	PINCTRL_PIN(17, "x_ldd[17]"),
-	PINCTRL_PIN(18, "x_ldd[18]"),
-	PINCTRL_PIN(19, "x_ldd[19]"),
-	PINCTRL_PIN(20, "x_ldd[20]"),
-	PINCTRL_PIN(21, "x_ldd[21]"),
-	PINCTRL_PIN(22, "x_ldd[22]"),
-	PINCTRL_PIN(23, "x_ldd[23], lcdrom_frdy"),
-	PINCTRL_PIN(24, "gps_sgn"),
-	PINCTRL_PIN(25, "gps_mag"),
-	PINCTRL_PIN(26, "gps_clk"),
-	PINCTRL_PIN(27,	"sd_cd_b_1"),
-	PINCTRL_PIN(28, "sd_vcc_on_1"),
-	PINCTRL_PIN(29, "sd_wp_b_1"),
-	PINCTRL_PIN(30, "sd_clk_3"),
-	PINCTRL_PIN(31, "sd_cmd_3"),
-
-	PINCTRL_PIN(32, "x_sd_dat_3[0]"),
-	PINCTRL_PIN(33, "x_sd_dat_3[1]"),
-	PINCTRL_PIN(34, "x_sd_dat_3[2]"),
-	PINCTRL_PIN(35, "x_sd_dat_3[3]"),
-	PINCTRL_PIN(36, "x_sd_clk_4"),
-	PINCTRL_PIN(37, "x_sd_cmd_4"),
-	PINCTRL_PIN(38, "x_sd_dat_4[0]"),
-	PINCTRL_PIN(39, "x_sd_dat_4[1]"),
-	PINCTRL_PIN(40, "x_sd_dat_4[2]"),
-	PINCTRL_PIN(41, "x_sd_dat_4[3]"),
-	PINCTRL_PIN(42, "x_cko_1"),
-	PINCTRL_PIN(43, "x_ac97_bit_clk"),
-	PINCTRL_PIN(44, "x_ac97_dout"),
-	PINCTRL_PIN(45, "x_ac97_din"),
-	PINCTRL_PIN(46, "x_ac97_sync"),
-	PINCTRL_PIN(47, "x_txd_1"),
-	PINCTRL_PIN(48, "x_txd_2"),
-	PINCTRL_PIN(49, "x_rxd_1"),
-	PINCTRL_PIN(50, "x_rxd_2"),
-	PINCTRL_PIN(51, "x_usclk_0"),
-	PINCTRL_PIN(52, "x_utxd_0"),
-	PINCTRL_PIN(53, "x_urxd_0"),
-	PINCTRL_PIN(54, "x_utfs_0"),
-	PINCTRL_PIN(55, "x_urfs_0"),
-	PINCTRL_PIN(56, "x_usclk_1"),
-	PINCTRL_PIN(57, "x_utxd_1"),
-	PINCTRL_PIN(58, "x_urxd_1"),
-	PINCTRL_PIN(59, "x_utfs_1"),
-	PINCTRL_PIN(60, "x_urfs_1"),
-	PINCTRL_PIN(61, "x_usclk_2"),
-	PINCTRL_PIN(62, "x_utxd_2"),
-	PINCTRL_PIN(63, "x_urxd_2"),
-
-	PINCTRL_PIN(64, "x_utfs_2"),
-	PINCTRL_PIN(65, "x_urfs_2"),
-	PINCTRL_PIN(66, "x_df_we_b"),
-	PINCTRL_PIN(67, "x_df_re_b"),
-	PINCTRL_PIN(68, "x_txd_0"),
-	PINCTRL_PIN(69, "x_rxd_0"),
-	PINCTRL_PIN(78, "x_cko_0"),
-	PINCTRL_PIN(79, "x_vip_pxd[7]"),
-	PINCTRL_PIN(80, "x_vip_pxd[6]"),
-	PINCTRL_PIN(81, "x_vip_pxd[5]"),
-	PINCTRL_PIN(82, "x_vip_pxd[4]"),
-	PINCTRL_PIN(83, "x_vip_pxd[3]"),
-	PINCTRL_PIN(84, "x_vip_pxd[2]"),
-	PINCTRL_PIN(85, "x_vip_pxd[1]"),
-	PINCTRL_PIN(86, "x_vip_pxd[0]"),
-	PINCTRL_PIN(87, "x_vip_vsync"),
-	PINCTRL_PIN(88, "x_vip_hsync"),
-	PINCTRL_PIN(89, "x_vip_pxclk"),
-	PINCTRL_PIN(90, "x_sda_0"),
-	PINCTRL_PIN(91, "x_scl_0"),
-	PINCTRL_PIN(92, "x_df_ry_by"),
-	PINCTRL_PIN(93, "x_df_cs_b[1]"),
-	PINCTRL_PIN(94, "x_df_cs_b[0]"),
-	PINCTRL_PIN(95, "x_l_pclk"),
-
-	PINCTRL_PIN(96, "x_l_lck"),
-	PINCTRL_PIN(97, "x_l_fck"),
-	PINCTRL_PIN(98, "x_l_de"),
-	PINCTRL_PIN(99, "x_ldd[0]"),
-	PINCTRL_PIN(100, "x_ldd[1]"),
-	PINCTRL_PIN(101, "x_ldd[2]"),
-	PINCTRL_PIN(102, "x_ldd[3]"),
-	PINCTRL_PIN(103, "x_ldd[4]"),
-	PINCTRL_PIN(104, "x_ldd[5]"),
-	PINCTRL_PIN(105, "x_ldd[6]"),
-	PINCTRL_PIN(106, "x_ldd[7]"),
-	PINCTRL_PIN(107, "x_ldd[8]"),
-	PINCTRL_PIN(108, "x_ldd[9]"),
-	PINCTRL_PIN(109, "x_ldd[10]"),
-	PINCTRL_PIN(110, "x_ldd[11]"),
-	PINCTRL_PIN(111, "x_ldd[12]"),
-	PINCTRL_PIN(112, "x_ldd[13]"),
-	PINCTRL_PIN(113, "x_ldd[14]"),
-	PINCTRL_PIN(114, "x_ldd[15]"),
-
-	PINCTRL_PIN(115, "x_usb1_dp"),
-	PINCTRL_PIN(116, "x_usb1_dn"),
-};
-
-static const struct sirfsoc_muxmask lcd_16bits_sirfsoc_muxmask[] = {
-	{
-		.group = 3,
-		.mask = BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) |
-			BIT(6) | BIT(7) | BIT(8) | BIT(9) | BIT(10) | BIT(11) |
-			BIT(12) | BIT(13) | BIT(14) | BIT(15) | BIT(16) |
-			BIT(17) | BIT(18),
-	}, {
-		.group = 2,
-		.mask = BIT(31),
-	},
-};
-
-static const struct sirfsoc_padmux lcd_16bits_padmux = {
-	.muxmask_counts = ARRAY_SIZE(lcd_16bits_sirfsoc_muxmask),
-	.muxmask = lcd_16bits_sirfsoc_muxmask,
-	.ctrlreg = SIRFSOC_RSC_PIN_MUX,
-	.funcmask = BIT(4),
-	.funcval = 0,
-};
-
-static const unsigned lcd_16bits_pins[] = { 95, 96, 97, 98, 99, 100, 101, 102,
-	103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113, 114 };
-
-static const struct sirfsoc_muxmask lcd_18bits_muxmask[] = {
-	{
-		.group = 3,
-		.mask = BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) |
-			BIT(6) | BIT(7) | BIT(8) | BIT(9) | BIT(10) | BIT(11) |
-			BIT(12) | BIT(13) | BIT(14) | BIT(15) | BIT(16) |
-			BIT(17) | BIT(18),
-	}, {
-		.group = 2,
-		.mask = BIT(31),
-	}, {
-		.group = 0,
-		.mask = BIT(16) | BIT(17),
-	},
-};
-
-static const struct sirfsoc_padmux lcd_18bits_padmux = {
-	.muxmask_counts = ARRAY_SIZE(lcd_18bits_muxmask),
-	.muxmask = lcd_18bits_muxmask,
-	.ctrlreg = SIRFSOC_RSC_PIN_MUX,
-	.funcmask = BIT(4),
-	.funcval = 0,
-};
-
-static const unsigned lcd_18bits_pins[] = { 16, 17, 95, 96, 97, 98, 99, 100,
-	101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113, 114};
-
-static const struct sirfsoc_muxmask lcd_24bits_muxmask[] = {
-	{
-		.group = 3,
-		.mask = BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) |
-			BIT(6) | BIT(7) | BIT(8) | BIT(9) | BIT(10) | BIT(11) |
-			BIT(12) | BIT(13) | BIT(14) | BIT(15) | BIT(16) |
-			BIT(17) | BIT(18),
-	}, {
-		.group = 2,
-		.mask = BIT(31),
-	}, {
-		.group = 0,
-		.mask = BIT(16) | BIT(17) | BIT(18) | BIT(19) | BIT(20) |
-			BIT(21) | BIT(22) | BIT(23),
-	},
-};
-
-static const struct sirfsoc_padmux lcd_24bits_padmux = {
-	.muxmask_counts = ARRAY_SIZE(lcd_24bits_muxmask),
-	.muxmask = lcd_24bits_muxmask,
-	.ctrlreg = SIRFSOC_RSC_PIN_MUX,
-	.funcmask = BIT(4),
-	.funcval = 0,
-};
-
-static const unsigned lcd_24bits_pins[] = { 16, 17, 18, 19, 20, 21, 22, 23,
-	95, 96,	97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 108, 109,
-	110, 111, 112, 113, 114 };
-
-static const struct sirfsoc_muxmask lcdrom_muxmask[] = {
-	{
-		.group = 3,
-		.mask = BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) |
-			BIT(6) | BIT(7) | BIT(8) | BIT(9) | BIT(10) | BIT(11) |
-			BIT(12) | BIT(13) | BIT(14) | BIT(15) | BIT(16) |
-			BIT(17) | BIT(18),
-	}, {
-		.group = 2,
-		.mask = BIT(31),
-	}, {
-		.group = 0,
-		.mask = BIT(23),
-	},
-};
-
-static const struct sirfsoc_padmux lcdrom_padmux = {
-	.muxmask_counts = ARRAY_SIZE(lcdrom_muxmask),
-	.muxmask = lcdrom_muxmask,
-	.ctrlreg = SIRFSOC_RSC_PIN_MUX,
-	.funcmask = BIT(4),
-	.funcval = BIT(4),
-};
-
-static const unsigned lcdrom_pins[] = { 23, 95, 96, 97, 98, 99, 100, 101, 102,
-	103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113, 114 };
-
-static const struct sirfsoc_muxmask uart0_muxmask[] = {
-	{
-		.group = 2,
-		.mask = BIT(4) | BIT(5),
-	}, {
-		.group = 1,
-		.mask = BIT(23) | BIT(28),
-	},
-};
-
-static const struct sirfsoc_padmux uart0_padmux = {
-	.muxmask_counts = ARRAY_SIZE(uart0_muxmask),
-	.muxmask = uart0_muxmask,
-	.ctrlreg = SIRFSOC_RSC_PIN_MUX,
-	.funcmask = BIT(9),
-	.funcval = BIT(9),
-};
-
-static const unsigned uart0_pins[] = { 55, 60, 68, 69 };
-
-static const struct sirfsoc_muxmask uart0_nostreamctrl_muxmask[] = {
-	{
-		.group = 2,
-		.mask = BIT(4) | BIT(5),
-	},
-};
-
-static const struct sirfsoc_padmux uart0_nostreamctrl_padmux = {
-	.muxmask_counts = ARRAY_SIZE(uart0_nostreamctrl_muxmask),
-	.muxmask = uart0_nostreamctrl_muxmask,
-};
-
-static const unsigned uart0_nostreamctrl_pins[] = { 68, 69 };
-
-static const struct sirfsoc_muxmask uart1_muxmask[] = {
-	{
-		.group = 1,
-		.mask = BIT(15) | BIT(17),
-	},
-};
-
-static const struct sirfsoc_padmux uart1_padmux = {
-	.muxmask_counts = ARRAY_SIZE(uart1_muxmask),
-	.muxmask = uart1_muxmask,
-};
-
-static const unsigned uart1_pins[] = { 47, 49 };
-
-static const struct sirfsoc_muxmask uart2_muxmask[] = {
-	{
-		.group = 1,
-		.mask = BIT(16) | BIT(18) | BIT(24) | BIT(27),
-	},
-};
-
-static const struct sirfsoc_padmux uart2_padmux = {
-	.muxmask_counts = ARRAY_SIZE(uart2_muxmask),
-	.muxmask = uart2_muxmask,
-	.ctrlreg = SIRFSOC_RSC_PIN_MUX,
-	.funcmask = BIT(10),
-	.funcval = BIT(10),
-};
-
-static const unsigned uart2_pins[] = { 48, 50, 56, 59 };
-
-static const struct sirfsoc_muxmask uart2_nostreamctrl_muxmask[] = {
-	{
-		.group = 1,
-		.mask = BIT(16) | BIT(18),
-	},
-};
-
-static const struct sirfsoc_padmux uart2_nostreamctrl_padmux = {
-	.muxmask_counts = ARRAY_SIZE(uart2_nostreamctrl_muxmask),
-	.muxmask = uart2_nostreamctrl_muxmask,
-};
-
-static const unsigned uart2_nostreamctrl_pins[] = { 48, 50 };
-
-static const struct sirfsoc_muxmask sdmmc3_muxmask[] = {
-	{
-		.group = 0,
-		.mask = BIT(30) | BIT(31),
-	}, {
-		.group = 1,
-		.mask = BIT(0) | BIT(1) | BIT(2) | BIT(3),
-	},
-};
-
-static const struct sirfsoc_padmux sdmmc3_padmux = {
-	.muxmask_counts = ARRAY_SIZE(sdmmc3_muxmask),
-	.muxmask = sdmmc3_muxmask,
-	.ctrlreg = SIRFSOC_RSC_PIN_MUX,
-	.funcmask = BIT(7),
-	.funcval = 0,
-};
-
-static const unsigned sdmmc3_pins[] = { 30, 31, 32, 33, 34, 35 };
-
-static const struct sirfsoc_muxmask spi0_muxmask[] = {
-	{
-		.group = 1,
-		.mask = BIT(0) | BIT(1) | BIT(2) | BIT(3),
-	},
-};
-
-static const struct sirfsoc_padmux spi0_padmux = {
-	.muxmask_counts = ARRAY_SIZE(spi0_muxmask),
-	.muxmask = spi0_muxmask,
-	.ctrlreg = SIRFSOC_RSC_PIN_MUX,
-	.funcmask = BIT(7),
-	.funcval = BIT(7),
-};
-
-static const unsigned spi0_pins[] = { 32, 33, 34, 35 };
-
-static const struct sirfsoc_muxmask sdmmc4_muxmask[] = {
-	{
-		.group = 1,
-		.mask = BIT(4) | BIT(5) | BIT(6) | BIT(7) | BIT(8) | BIT(9),
-	},
-};
-
-static const struct sirfsoc_padmux sdmmc4_padmux = {
-	.muxmask_counts = ARRAY_SIZE(sdmmc4_muxmask),
-	.muxmask = sdmmc4_muxmask,
-};
-
-static const unsigned sdmmc4_pins[] = { 36, 37, 38, 39, 40, 41 };
-
-static const struct sirfsoc_muxmask cko1_muxmask[] = {
-	{
-		.group = 1,
-		.mask = BIT(10),
-	},
-};
-
-static const struct sirfsoc_padmux cko1_padmux = {
-	.muxmask_counts = ARRAY_SIZE(cko1_muxmask),
-	.muxmask = cko1_muxmask,
-	.ctrlreg = SIRFSOC_RSC_PIN_MUX,
-	.funcmask = BIT(3),
-	.funcval = 0,
-};
-
-static const unsigned cko1_pins[] = { 42 };
-
-static const struct sirfsoc_muxmask i2s_mclk_muxmask[] = {
-	{
-		.group = 1,
-		.mask = BIT(10),
-	},
-};
-
-static const struct sirfsoc_padmux i2s_mclk_padmux = {
-	.muxmask_counts = ARRAY_SIZE(i2s_mclk_muxmask),
-	.muxmask = i2s_mclk_muxmask,
-	.ctrlreg = SIRFSOC_RSC_PIN_MUX,
-	.funcmask = BIT(3),
-	.funcval = BIT(3),
-};
-
-static const unsigned i2s_mclk_pins[] = { 42 };
-
-static const struct sirfsoc_muxmask i2s_ext_clk_input_muxmask[] = {
-	{
-		.group = 1,
-		.mask = BIT(19),
-	},
-};
-
-static const struct sirfsoc_padmux i2s_ext_clk_input_padmux = {
-	.muxmask_counts = ARRAY_SIZE(i2s_ext_clk_input_muxmask),
-	.muxmask = i2s_ext_clk_input_muxmask,
-	.ctrlreg = SIRFSOC_RSC_PIN_MUX,
-	.funcmask = BIT(2),
-	.funcval = BIT(2),
-};
-
-static const unsigned i2s_ext_clk_input_pins[] = { 51 };
-
-static const struct sirfsoc_muxmask i2s_muxmask[] = {
-	{
-		.group = 1,
-		.mask = BIT(11) | BIT(12) | BIT(13) | BIT(14),
-	},
-};
-
-static const struct sirfsoc_padmux i2s_padmux = {
-	.muxmask_counts = ARRAY_SIZE(i2s_muxmask),
-	.muxmask = i2s_muxmask,
-	.ctrlreg = SIRFSOC_RSC_PIN_MUX,
-};
-
-static const unsigned i2s_pins[] = { 43, 44, 45, 46 };
-
-static const struct sirfsoc_muxmask i2s_no_din_muxmask[] = {
-	{
-		.group = 1,
-		.mask = BIT(11) | BIT(12) | BIT(14),
-	},
-};
-
-static const struct sirfsoc_padmux i2s_no_din_padmux = {
-	.muxmask_counts = ARRAY_SIZE(i2s_no_din_muxmask),
-	.muxmask = i2s_no_din_muxmask,
-	.ctrlreg = SIRFSOC_RSC_PIN_MUX,
-};
-
-static const unsigned i2s_no_din_pins[] = { 43, 44, 46 };
-
-static const struct sirfsoc_muxmask i2s_6chn_muxmask[] = {
-	{
-		.group = 1,
-		.mask = BIT(11) | BIT(12) | BIT(13) | BIT(14)
-			| BIT(23) | BIT(28),
-	},
-};
-
-static const struct sirfsoc_padmux i2s_6chn_padmux = {
-	.muxmask_counts = ARRAY_SIZE(i2s_6chn_muxmask),
-	.muxmask = i2s_6chn_muxmask,
-	.ctrlreg = SIRFSOC_RSC_PIN_MUX,
-	.funcmask = BIT(1) | BIT(9),
-	.funcval = BIT(1) | BIT(9),
-};
-
-static const unsigned i2s_6chn_pins[] = { 43, 44, 45, 46, 55, 60  };
-
-static const struct sirfsoc_muxmask ac97_muxmask[] = {
-	{
-		.group = 1,
-		.mask = BIT(11) | BIT(12) | BIT(13) | BIT(14),
-	},
-};
-
-static const struct sirfsoc_padmux ac97_padmux = {
-	.muxmask_counts = ARRAY_SIZE(ac97_muxmask),
-	.muxmask = ac97_muxmask,
-	.ctrlreg = SIRFSOC_RSC_PIN_MUX,
-	.funcmask = BIT(8),
-	.funcval = 0,
-};
-
-static const unsigned ac97_pins[] = { 43, 44, 45, 46 };
-
-static const struct sirfsoc_muxmask spi1_muxmask[] = {
-	{
-		.group = 1,
-		.mask = BIT(11) | BIT(12) | BIT(13) | BIT(14),
-	},
-};
-
-static const struct sirfsoc_padmux spi1_padmux = {
-	.muxmask_counts = ARRAY_SIZE(spi1_muxmask),
-	.muxmask = spi1_muxmask,
-	.ctrlreg = SIRFSOC_RSC_PIN_MUX,
-	.funcmask = BIT(8),
-	.funcval = BIT(8),
-};
-
-static const unsigned spi1_pins[] = { 43, 44, 45, 46 };
-
-static const struct sirfsoc_muxmask sdmmc1_muxmask[] = {
-	{
-		.group = 0,
-		.mask = BIT(27) | BIT(28) | BIT(29),
-	},
-};
-
-static const struct sirfsoc_padmux sdmmc1_padmux = {
-	.muxmask_counts = ARRAY_SIZE(sdmmc1_muxmask),
-	.muxmask = sdmmc1_muxmask,
-};
-
-static const unsigned sdmmc1_pins[] = { 27, 28, 29 };
-
-static const struct sirfsoc_muxmask gps_muxmask[] = {
-	{
-		.group = 0,
-		.mask = BIT(24) | BIT(25) | BIT(26),
-	},
-};
-
-static const struct sirfsoc_padmux gps_padmux = {
-	.muxmask_counts = ARRAY_SIZE(gps_muxmask),
-	.muxmask = gps_muxmask,
-	.ctrlreg = SIRFSOC_RSC_PIN_MUX,
-	.funcmask = BIT(12) | BIT(13) | BIT(14),
-	.funcval = BIT(12),
-};
-
-static const unsigned gps_pins[] = { 24, 25, 26 };
-
-static const struct sirfsoc_muxmask sdmmc5_muxmask[] = {
-	{
-		.group = 0,
-		.mask = BIT(24) | BIT(25) | BIT(26),
-	},
-};
-
-static const struct sirfsoc_padmux sdmmc5_padmux = {
-	.muxmask_counts = ARRAY_SIZE(sdmmc5_muxmask),
-	.muxmask = sdmmc5_muxmask,
-	.ctrlreg = SIRFSOC_RSC_PIN_MUX,
-	.funcmask = BIT(13) | BIT(14),
-	.funcval = BIT(13) | BIT(14),
-};
-
-static const unsigned sdmmc5_pins[] = { 24, 25, 26 };
-
-static const struct sirfsoc_muxmask usp0_muxmask[] = {
-	{
-		.group = 1,
-		.mask = BIT(19) | BIT(20) | BIT(21) | BIT(22) | BIT(23),
-	},
-};
-
-static const struct sirfsoc_padmux usp0_padmux = {
-	.muxmask_counts = ARRAY_SIZE(usp0_muxmask),
-	.muxmask = usp0_muxmask,
-	.ctrlreg = SIRFSOC_RSC_PIN_MUX,
-	.funcmask = BIT(1) | BIT(2) | BIT(6) | BIT(9),
-	.funcval = 0,
-};
-
-static const unsigned usp0_pins[] = { 51, 52, 53, 54, 55 };
-
-static const struct sirfsoc_muxmask usp0_only_utfs_muxmask[] = {
-	{
-		.group = 1,
-		.mask = BIT(19) | BIT(20) | BIT(21) | BIT(22),
-	},
-};
-
-static const struct sirfsoc_padmux usp0_only_utfs_padmux = {
-	.muxmask_counts = ARRAY_SIZE(usp0_only_utfs_muxmask),
-	.muxmask = usp0_only_utfs_muxmask,
-	.ctrlreg = SIRFSOC_RSC_PIN_MUX,
-	.funcmask = BIT(1) | BIT(2) | BIT(6),
-	.funcval = 0,
-};
-
-static const unsigned usp0_only_utfs_pins[] = { 51, 52, 53, 54 };
-
-static const struct sirfsoc_muxmask usp0_only_urfs_muxmask[] = {
-	{
-		.group = 1,
-		.mask = BIT(19) | BIT(20) | BIT(21) | BIT(23),
-	},
-};
-
-static const struct sirfsoc_padmux usp0_only_urfs_padmux = {
-	.muxmask_counts = ARRAY_SIZE(usp0_only_urfs_muxmask),
-	.muxmask = usp0_only_urfs_muxmask,
-	.ctrlreg = SIRFSOC_RSC_PIN_MUX,
-	.funcmask = BIT(1) | BIT(2) | BIT(9),
-	.funcval = 0,
-};
-
-static const unsigned usp0_only_urfs_pins[] = { 51, 52, 53, 55 };
-
-static const struct sirfsoc_muxmask usp0_uart_nostreamctrl_muxmask[] = {
-	{
-		.group = 1,
-		.mask = BIT(20) | BIT(21),
-	},
-};
-
-static const struct sirfsoc_padmux usp0_uart_nostreamctrl_padmux = {
-	.muxmask_counts = ARRAY_SIZE(usp0_uart_nostreamctrl_muxmask),
-	.muxmask = usp0_uart_nostreamctrl_muxmask,
-};
-
-static const unsigned usp0_uart_nostreamctrl_pins[] = { 52, 53 };
-
-static const struct sirfsoc_muxmask usp1_muxmask[] = {
-	{
-		.group = 1,
-		.mask = BIT(24) | BIT(25) | BIT(26) | BIT(27) | BIT(28),
-	},
-};
-
-static const struct sirfsoc_padmux usp1_padmux = {
-	.muxmask_counts = ARRAY_SIZE(usp1_muxmask),
-	.muxmask = usp1_muxmask,
-	.ctrlreg = SIRFSOC_RSC_PIN_MUX,
-	.funcmask = BIT(1) | BIT(9) | BIT(10) | BIT(11),
-	.funcval = 0,
-};
-
-static const unsigned usp1_pins[] = { 56, 57, 58, 59, 60 };
-
-static const struct sirfsoc_muxmask usp1_uart_nostreamctrl_muxmask[] = {
-	{
-		.group = 1,
-		.mask = BIT(25) | BIT(26),
-	},
-};
-
-static const struct sirfsoc_padmux usp1_uart_nostreamctrl_padmux = {
-	.muxmask_counts = ARRAY_SIZE(usp1_uart_nostreamctrl_muxmask),
-	.muxmask = usp1_uart_nostreamctrl_muxmask,
-};
-
-static const unsigned usp1_uart_nostreamctrl_pins[] = { 57, 58 };
-
-static const struct sirfsoc_muxmask usp2_muxmask[] = {
-	{
-		.group = 1,
-		.mask = BIT(29) | BIT(30) | BIT(31),
-	}, {
-		.group = 2,
-		.mask = BIT(0) | BIT(1),
-	},
-};
-
-static const struct sirfsoc_padmux usp2_padmux = {
-	.muxmask_counts = ARRAY_SIZE(usp2_muxmask),
-	.muxmask = usp2_muxmask,
-	.ctrlreg = SIRFSOC_RSC_PIN_MUX,
-	.funcmask = BIT(13) | BIT(14),
-	.funcval = 0,
-};
-
-static const unsigned usp2_pins[] = { 61, 62, 63, 64, 65 };
-
-static const struct sirfsoc_muxmask usp2_uart_nostreamctrl_muxmask[] = {
-	{
-		.group = 1,
-		.mask = BIT(30) | BIT(31),
-	},
-};
-
-static const struct sirfsoc_padmux usp2_uart_nostreamctrl_padmux = {
-	.muxmask_counts = ARRAY_SIZE(usp2_uart_nostreamctrl_muxmask),
-	.muxmask = usp2_uart_nostreamctrl_muxmask,
-};
-
-static const unsigned usp2_uart_nostreamctrl_pins[] = { 62, 63 };
-
-static const struct sirfsoc_muxmask nand_muxmask[] = {
-	{
-		.group = 2,
-		.mask = BIT(2) | BIT(3) | BIT(28) | BIT(29) | BIT(30),
-	},
-};
-
-static const struct sirfsoc_padmux nand_padmux = {
-	.muxmask_counts = ARRAY_SIZE(nand_muxmask),
-	.muxmask = nand_muxmask,
-	.ctrlreg = SIRFSOC_RSC_PIN_MUX,
-	.funcmask = BIT(5),
-	.funcval = 0,
-};
-
-static const unsigned nand_pins[] = { 64, 65, 92, 93, 94 };
-
-static const struct sirfsoc_padmux sdmmc0_padmux = {
-	.muxmask_counts = 0,
-	.ctrlreg = SIRFSOC_RSC_PIN_MUX,
-	.funcmask = BIT(5),
-	.funcval = 0,
-};
-
-static const unsigned sdmmc0_pins[] = { };
-
-static const struct sirfsoc_muxmask sdmmc2_muxmask[] = {
-	{
-		.group = 2,
-		.mask = BIT(2) | BIT(3),
-	},
-};
-
-static const struct sirfsoc_padmux sdmmc2_padmux = {
-	.muxmask_counts = ARRAY_SIZE(sdmmc2_muxmask),
-	.muxmask = sdmmc2_muxmask,
-	.ctrlreg = SIRFSOC_RSC_PIN_MUX,
-	.funcmask = BIT(5),
-	.funcval = BIT(5),
-};
-
-static const unsigned sdmmc2_pins[] = { 66, 67 };
-
-static const struct sirfsoc_muxmask cko0_muxmask[] = {
-	{
-		.group = 2,
-		.mask = BIT(14),
-	},
-};
-
-static const struct sirfsoc_padmux cko0_padmux = {
-	.muxmask_counts = ARRAY_SIZE(cko0_muxmask),
-	.muxmask = cko0_muxmask,
-};
-
-static const unsigned cko0_pins[] = { 78 };
-
-static const struct sirfsoc_muxmask vip_muxmask[] = {
-	{
-		.group = 2,
-		.mask = BIT(15) | BIT(16) | BIT(17) | BIT(18) | BIT(19)
-			| BIT(20) | BIT(21) | BIT(22) | BIT(23) | BIT(24) |
-			BIT(25),
-	},
-};
-
-static const struct sirfsoc_padmux vip_padmux = {
-	.muxmask_counts = ARRAY_SIZE(vip_muxmask),
-	.muxmask = vip_muxmask,
-	.ctrlreg = SIRFSOC_RSC_PIN_MUX,
-	.funcmask = BIT(0),
-	.funcval = 0,
-};
-
-static const unsigned vip_pins[] = { 79, 80, 81, 82, 83, 84, 85, 86, 87,
-	88, 89 };
-
-static const struct sirfsoc_muxmask i2c0_muxmask[] = {
-	{
-		.group = 2,
-		.mask = BIT(26) | BIT(27),
-	},
-};
-
-static const struct sirfsoc_padmux i2c0_padmux = {
-	.muxmask_counts = ARRAY_SIZE(i2c0_muxmask),
-	.muxmask = i2c0_muxmask,
-};
-
-static const unsigned i2c0_pins[] = { 90, 91 };
-
-static const struct sirfsoc_muxmask i2c1_muxmask[] = {
-	{
-		.group = 0,
-		.mask = BIT(13) | BIT(15),
-	},
-};
-
-static const struct sirfsoc_padmux i2c1_padmux = {
-	.muxmask_counts = ARRAY_SIZE(i2c1_muxmask),
-	.muxmask = i2c1_muxmask,
-};
-
-static const unsigned i2c1_pins[] = { 13, 15 };
-
-static const struct sirfsoc_muxmask viprom_muxmask[] = {
-	{
-		.group = 2,
-		.mask = BIT(15) | BIT(16) | BIT(17) | BIT(18) | BIT(19)
-			| BIT(20) | BIT(21) | BIT(22) | BIT(23) | BIT(24) |
-			BIT(25),
-	}, {
-		.group = 0,
-		.mask = BIT(12),
-	},
-};
-
-static const struct sirfsoc_padmux viprom_padmux = {
-	.muxmask_counts = ARRAY_SIZE(viprom_muxmask),
-	.muxmask = viprom_muxmask,
-	.ctrlreg = SIRFSOC_RSC_PIN_MUX,
-	.funcmask = BIT(0),
-	.funcval = BIT(0),
-};
-
-static const unsigned viprom_pins[] = { 12, 79, 80, 81, 82, 83, 84, 85, 86,
-	87, 88, 89 };
-
-static const struct sirfsoc_muxmask pwm0_muxmask[] = {
-	{
-		.group = 0,
-		.mask = BIT(4),
-	},
-};
-
-static const struct sirfsoc_padmux pwm0_padmux = {
-	.muxmask_counts = ARRAY_SIZE(pwm0_muxmask),
-	.muxmask = pwm0_muxmask,
-	.ctrlreg = SIRFSOC_RSC_PIN_MUX,
-	.funcmask = BIT(12),
-	.funcval = 0,
-};
-
-static const unsigned pwm0_pins[] = { 4 };
-
-static const struct sirfsoc_muxmask pwm1_muxmask[] = {
-	{
-		.group = 0,
-		.mask = BIT(5),
-	},
-};
-
-static const struct sirfsoc_padmux pwm1_padmux = {
-	.muxmask_counts = ARRAY_SIZE(pwm1_muxmask),
-	.muxmask = pwm1_muxmask,
-};
-
-static const unsigned pwm1_pins[] = { 5 };
-
-static const struct sirfsoc_muxmask pwm2_muxmask[] = {
-	{
-		.group = 0,
-		.mask = BIT(6),
-	},
-};
-
-static const struct sirfsoc_padmux pwm2_padmux = {
-	.muxmask_counts = ARRAY_SIZE(pwm2_muxmask),
-	.muxmask = pwm2_muxmask,
-};
-
-static const unsigned pwm2_pins[] = { 6 };
-
-static const struct sirfsoc_muxmask pwm3_muxmask[] = {
-	{
-		.group = 0,
-		.mask = BIT(7),
-	},
-};
-
-static const struct sirfsoc_padmux pwm3_padmux = {
-	.muxmask_counts = ARRAY_SIZE(pwm3_muxmask),
-	.muxmask = pwm3_muxmask,
-};
-
-static const unsigned pwm3_pins[] = { 7 };
-
-static const struct sirfsoc_muxmask warm_rst_muxmask[] = {
-	{
-		.group = 0,
-		.mask = BIT(8),
-	},
-};
-
-static const struct sirfsoc_padmux warm_rst_padmux = {
-	.muxmask_counts = ARRAY_SIZE(warm_rst_muxmask),
-	.muxmask = warm_rst_muxmask,
-};
-
-static const unsigned warm_rst_pins[] = { 8 };
-
-static const struct sirfsoc_muxmask usb0_utmi_drvbus_muxmask[] = {
-	{
-		.group = 1,
-		.mask = BIT(22),
-	},
-};
-static const struct sirfsoc_padmux usb0_utmi_drvbus_padmux = {
-	.muxmask_counts = ARRAY_SIZE(usb0_utmi_drvbus_muxmask),
-	.muxmask = usb0_utmi_drvbus_muxmask,
-	.ctrlreg = SIRFSOC_RSC_PIN_MUX,
-	.funcmask = BIT(6),
-	.funcval = BIT(6), /* refer to PAD_UTMI_DRVVBUS0_ENABLE */
-};
-
-static const unsigned usb0_utmi_drvbus_pins[] = { 54 };
-
-static const struct sirfsoc_muxmask usb1_utmi_drvbus_muxmask[] = {
-	{
-		.group = 1,
-		.mask = BIT(27),
-	},
-};
-
-static const struct sirfsoc_padmux usb1_utmi_drvbus_padmux = {
-	.muxmask_counts = ARRAY_SIZE(usb1_utmi_drvbus_muxmask),
-	.muxmask = usb1_utmi_drvbus_muxmask,
-	.ctrlreg = SIRFSOC_RSC_PIN_MUX,
-	.funcmask = BIT(11),
-	.funcval = BIT(11), /* refer to PAD_UTMI_DRVVBUS1_ENABLE */
-};
-
-static const unsigned usb1_utmi_drvbus_pins[] = { 59 };
-
-static const struct sirfsoc_padmux usb1_dp_dn_padmux = {
-	.muxmask_counts = 0,
-	.ctrlreg = SIRFSOC_RSC_USB_UART_SHARE,
-	.funcmask = BIT(2),
-	.funcval = BIT(2),
-};
-
-static const unsigned usb1_dp_dn_pins[] = { 115, 116 };
-
-static const struct sirfsoc_padmux uart1_route_io_usb1_padmux = {
-	.muxmask_counts = 0,
-	.ctrlreg = SIRFSOC_RSC_USB_UART_SHARE,
-	.funcmask = BIT(2),
-	.funcval = 0,
-};
-
-static const unsigned uart1_route_io_usb1_pins[] = { 115, 116 };
-
-static const struct sirfsoc_muxmask pulse_count_muxmask[] = {
-	{
-		.group = 0,
-		.mask = BIT(9) | BIT(10) | BIT(11),
-	},
-};
-
-static const struct sirfsoc_padmux pulse_count_padmux = {
-	.muxmask_counts = ARRAY_SIZE(pulse_count_muxmask),
-	.muxmask = pulse_count_muxmask,
-};
-
-static const unsigned pulse_count_pins[] = { 9, 10, 11 };
-
-static const struct sirfsoc_pin_group sirfsoc_pin_groups[] = {
-	SIRFSOC_PIN_GROUP("lcd_16bitsgrp", lcd_16bits_pins),
-	SIRFSOC_PIN_GROUP("lcd_18bitsgrp", lcd_18bits_pins),
-	SIRFSOC_PIN_GROUP("lcd_24bitsgrp", lcd_24bits_pins),
-	SIRFSOC_PIN_GROUP("lcdrom_grp", lcdrom_pins),
-	SIRFSOC_PIN_GROUP("uart0grp", uart0_pins),
-	SIRFSOC_PIN_GROUP("uart0_nostreamctrlgrp", uart0_nostreamctrl_pins),
-	SIRFSOC_PIN_GROUP("uart1grp", uart1_pins),
-	SIRFSOC_PIN_GROUP("uart2grp", uart2_pins),
-	SIRFSOC_PIN_GROUP("uart2_nostreamctrlgrp", uart2_nostreamctrl_pins),
-	SIRFSOC_PIN_GROUP("usp0grp", usp0_pins),
-	SIRFSOC_PIN_GROUP("usp0_uart_nostreamctrl_grp",
-					usp0_uart_nostreamctrl_pins),
-	SIRFSOC_PIN_GROUP("usp0_only_utfs_grp", usp0_only_utfs_pins),
-	SIRFSOC_PIN_GROUP("usp0_only_urfs_grp", usp0_only_urfs_pins),
-	SIRFSOC_PIN_GROUP("usp1grp", usp1_pins),
-	SIRFSOC_PIN_GROUP("usp1_uart_nostreamctrl_grp",
-					usp1_uart_nostreamctrl_pins),
-	SIRFSOC_PIN_GROUP("usp2grp", usp2_pins),
-	SIRFSOC_PIN_GROUP("usp2_uart_nostreamctrl_grp",
-					usp2_uart_nostreamctrl_pins),
-	SIRFSOC_PIN_GROUP("i2c0grp", i2c0_pins),
-	SIRFSOC_PIN_GROUP("i2c1grp", i2c1_pins),
-	SIRFSOC_PIN_GROUP("pwm0grp", pwm0_pins),
-	SIRFSOC_PIN_GROUP("pwm1grp", pwm1_pins),
-	SIRFSOC_PIN_GROUP("pwm2grp", pwm2_pins),
-	SIRFSOC_PIN_GROUP("pwm3grp", pwm3_pins),
-	SIRFSOC_PIN_GROUP("vipgrp", vip_pins),
-	SIRFSOC_PIN_GROUP("vipromgrp", viprom_pins),
-	SIRFSOC_PIN_GROUP("warm_rstgrp", warm_rst_pins),
-	SIRFSOC_PIN_GROUP("cko0grp", cko0_pins),
-	SIRFSOC_PIN_GROUP("cko1grp", cko1_pins),
-	SIRFSOC_PIN_GROUP("sdmmc0grp", sdmmc0_pins),
-	SIRFSOC_PIN_GROUP("sdmmc1grp", sdmmc1_pins),
-	SIRFSOC_PIN_GROUP("sdmmc2grp", sdmmc2_pins),
-	SIRFSOC_PIN_GROUP("sdmmc3grp", sdmmc3_pins),
-	SIRFSOC_PIN_GROUP("sdmmc4grp", sdmmc4_pins),
-	SIRFSOC_PIN_GROUP("sdmmc5grp", sdmmc5_pins),
-	SIRFSOC_PIN_GROUP("usb0_utmi_drvbusgrp", usb0_utmi_drvbus_pins),
-	SIRFSOC_PIN_GROUP("usb1_utmi_drvbusgrp", usb1_utmi_drvbus_pins),
-	SIRFSOC_PIN_GROUP("usb1_dp_dngrp", usb1_dp_dn_pins),
-	SIRFSOC_PIN_GROUP("uart1_route_io_usb1grp", uart1_route_io_usb1_pins),
-	SIRFSOC_PIN_GROUP("pulse_countgrp", pulse_count_pins),
-	SIRFSOC_PIN_GROUP("i2smclkgrp", i2s_mclk_pins),
-	SIRFSOC_PIN_GROUP("i2s_ext_clk_inputgrp", i2s_ext_clk_input_pins),
-	SIRFSOC_PIN_GROUP("i2sgrp", i2s_pins),
-	SIRFSOC_PIN_GROUP("i2s_no_dingrp", i2s_no_din_pins),
-	SIRFSOC_PIN_GROUP("i2s_6chngrp", i2s_6chn_pins),
-	SIRFSOC_PIN_GROUP("ac97grp", ac97_pins),
-	SIRFSOC_PIN_GROUP("nandgrp", nand_pins),
-	SIRFSOC_PIN_GROUP("spi0grp", spi0_pins),
-	SIRFSOC_PIN_GROUP("spi1grp", spi1_pins),
-	SIRFSOC_PIN_GROUP("gpsgrp", gps_pins),
-};
-
-static const char * const lcd_16bitsgrp[] = { "lcd_16bitsgrp" };
-static const char * const lcd_18bitsgrp[] = { "lcd_18bitsgrp" };
-static const char * const lcd_24bitsgrp[] = { "lcd_24bitsgrp" };
-static const char * const lcdromgrp[] = { "lcdromgrp" };
-static const char * const uart0grp[] = { "uart0grp" };
-static const char * const uart0_nostreamctrlgrp[] = { "uart0_nostreamctrlgrp" };
-static const char * const uart1grp[] = { "uart1grp" };
-static const char * const uart2grp[] = { "uart2grp" };
-static const char * const uart2_nostreamctrlgrp[] = { "uart2_nostreamctrlgrp" };
-static const char * const usp0grp[] = { "usp0grp" };
-static const char * const usp0_uart_nostreamctrl_grp[] = {
-	"usp0_uart_nostreamctrl_grp"
-};
-static const char * const usp0_only_utfs_grp[] = { "usp0_only_utfs_grp" };
-static const char * const usp0_only_urfs_grp[] = { "usp0_only_urfs_grp" };
-static const char * const usp1grp[] = { "usp1grp" };
-static const char * const usp1_uart_nostreamctrl_grp[] = {
-	"usp1_uart_nostreamctrl_grp"
-};
-static const char * const usp2grp[] = { "usp2grp" };
-static const char * const usp2_uart_nostreamctrl_grp[] = {
-	"usp2_uart_nostreamctrl_grp"
-};
-static const char * const i2c0grp[] = { "i2c0grp" };
-static const char * const i2c1grp[] = { "i2c1grp" };
-static const char * const pwm0grp[] = { "pwm0grp" };
-static const char * const pwm1grp[] = { "pwm1grp" };
-static const char * const pwm2grp[] = { "pwm2grp" };
-static const char * const pwm3grp[] = { "pwm3grp" };
-static const char * const vipgrp[] = { "vipgrp" };
-static const char * const vipromgrp[] = { "vipromgrp" };
-static const char * const warm_rstgrp[] = { "warm_rstgrp" };
-static const char * const cko0grp[] = { "cko0grp" };
-static const char * const cko1grp[] = { "cko1grp" };
-static const char * const sdmmc0grp[] = { "sdmmc0grp" };
-static const char * const sdmmc1grp[] = { "sdmmc1grp" };
-static const char * const sdmmc2grp[] = { "sdmmc2grp" };
-static const char * const sdmmc3grp[] = { "sdmmc3grp" };
-static const char * const sdmmc4grp[] = { "sdmmc4grp" };
-static const char * const sdmmc5grp[] = { "sdmmc5grp" };
-static const char * const usb0_utmi_drvbusgrp[] = { "usb0_utmi_drvbusgrp" };
-static const char * const usb1_utmi_drvbusgrp[] = { "usb1_utmi_drvbusgrp" };
-static const char * const usb1_dp_dngrp[] = { "usb1_dp_dngrp" };
-static const char * const
-	uart1_route_io_usb1grp[] = { "uart1_route_io_usb1grp" };
-static const char * const pulse_countgrp[] = { "pulse_countgrp" };
-static const char * const i2smclkgrp[] = { "i2smclkgrp" };
-static const char * const i2s_ext_clk_inputgrp[] = { "i2s_ext_clk_inputgrp" };
-static const char * const i2sgrp[] = { "i2sgrp" };
-static const char * const i2s_no_dingrp[] = { "i2s_no_dingrp" };
-static const char * const i2s_6chngrp[] = { "i2s_6chngrp" };
-static const char * const ac97grp[] = { "ac97grp" };
-static const char * const nandgrp[] = { "nandgrp" };
-static const char * const spi0grp[] = { "spi0grp" };
-static const char * const spi1grp[] = { "spi1grp" };
-static const char * const gpsgrp[] = { "gpsgrp" };
-
-static const struct sirfsoc_pmx_func sirfsoc_pmx_functions[] = {
-	SIRFSOC_PMX_FUNCTION("lcd_16bits", lcd_16bitsgrp, lcd_16bits_padmux),
-	SIRFSOC_PMX_FUNCTION("lcd_18bits", lcd_18bitsgrp, lcd_18bits_padmux),
-	SIRFSOC_PMX_FUNCTION("lcd_24bits", lcd_24bitsgrp, lcd_24bits_padmux),
-	SIRFSOC_PMX_FUNCTION("lcdrom", lcdromgrp, lcdrom_padmux),
-	SIRFSOC_PMX_FUNCTION("uart0", uart0grp, uart0_padmux),
-	SIRFSOC_PMX_FUNCTION("uart0_nostreamctrl",
-		uart0_nostreamctrlgrp, uart0_nostreamctrl_padmux),
-	SIRFSOC_PMX_FUNCTION("uart1", uart1grp, uart1_padmux),
-	SIRFSOC_PMX_FUNCTION("uart2", uart2grp, uart2_padmux),
-	SIRFSOC_PMX_FUNCTION("uart2_nostreamctrl",
-		uart2_nostreamctrlgrp, uart2_nostreamctrl_padmux),
-	SIRFSOC_PMX_FUNCTION("usp0", usp0grp, usp0_padmux),
-	SIRFSOC_PMX_FUNCTION("usp0_uart_nostreamctrl",
-		usp0_uart_nostreamctrl_grp, usp0_uart_nostreamctrl_padmux),
-	SIRFSOC_PMX_FUNCTION("usp0_only_utfs",
-		usp0_only_utfs_grp, usp0_only_utfs_padmux),
-	SIRFSOC_PMX_FUNCTION("usp0_only_urfs",
-		usp0_only_urfs_grp, usp0_only_urfs_padmux),
-	SIRFSOC_PMX_FUNCTION("usp1", usp1grp, usp1_padmux),
-	SIRFSOC_PMX_FUNCTION("usp1_uart_nostreamctrl",
-		usp1_uart_nostreamctrl_grp, usp1_uart_nostreamctrl_padmux),
-	SIRFSOC_PMX_FUNCTION("usp2", usp2grp, usp2_padmux),
-	SIRFSOC_PMX_FUNCTION("usp2_uart_nostreamctrl",
-		usp2_uart_nostreamctrl_grp, usp2_uart_nostreamctrl_padmux),
-	SIRFSOC_PMX_FUNCTION("i2c0", i2c0grp, i2c0_padmux),
-	SIRFSOC_PMX_FUNCTION("i2c1", i2c1grp, i2c1_padmux),
-	SIRFSOC_PMX_FUNCTION("pwm0", pwm0grp, pwm0_padmux),
-	SIRFSOC_PMX_FUNCTION("pwm1", pwm1grp, pwm1_padmux),
-	SIRFSOC_PMX_FUNCTION("pwm2", pwm2grp, pwm2_padmux),
-	SIRFSOC_PMX_FUNCTION("pwm3", pwm3grp, pwm3_padmux),
-	SIRFSOC_PMX_FUNCTION("vip", vipgrp, vip_padmux),
-	SIRFSOC_PMX_FUNCTION("viprom", vipromgrp, viprom_padmux),
-	SIRFSOC_PMX_FUNCTION("warm_rst", warm_rstgrp, warm_rst_padmux),
-	SIRFSOC_PMX_FUNCTION("cko0", cko0grp, cko0_padmux),
-	SIRFSOC_PMX_FUNCTION("cko1", cko1grp, cko1_padmux),
-	SIRFSOC_PMX_FUNCTION("sdmmc0", sdmmc0grp, sdmmc0_padmux),
-	SIRFSOC_PMX_FUNCTION("sdmmc1", sdmmc1grp, sdmmc1_padmux),
-	SIRFSOC_PMX_FUNCTION("sdmmc2", sdmmc2grp, sdmmc2_padmux),
-	SIRFSOC_PMX_FUNCTION("sdmmc3", sdmmc3grp, sdmmc3_padmux),
-	SIRFSOC_PMX_FUNCTION("sdmmc4", sdmmc4grp, sdmmc4_padmux),
-	SIRFSOC_PMX_FUNCTION("sdmmc5", sdmmc5grp, sdmmc5_padmux),
-	SIRFSOC_PMX_FUNCTION("usb0_utmi_drvbus",
-		usb0_utmi_drvbusgrp, usb0_utmi_drvbus_padmux),
-	SIRFSOC_PMX_FUNCTION("usb1_utmi_drvbus",
-		usb1_utmi_drvbusgrp, usb1_utmi_drvbus_padmux),
-	SIRFSOC_PMX_FUNCTION("usb1_dp_dn", usb1_dp_dngrp, usb1_dp_dn_padmux),
-	SIRFSOC_PMX_FUNCTION("uart1_route_io_usb1",
-		uart1_route_io_usb1grp, uart1_route_io_usb1_padmux),
-	SIRFSOC_PMX_FUNCTION("pulse_count", pulse_countgrp, pulse_count_padmux),
-	SIRFSOC_PMX_FUNCTION("i2s_mclk", i2smclkgrp, i2s_mclk_padmux),
-	SIRFSOC_PMX_FUNCTION("i2s_ext_clk_input", i2s_ext_clk_inputgrp,
-						i2s_ext_clk_input_padmux),
-	SIRFSOC_PMX_FUNCTION("i2s", i2sgrp, i2s_padmux),
-	SIRFSOC_PMX_FUNCTION("i2s_no_din", i2s_no_dingrp, i2s_no_din_padmux),
-	SIRFSOC_PMX_FUNCTION("i2s_6chn", i2s_6chngrp, i2s_6chn_padmux),
-	SIRFSOC_PMX_FUNCTION("ac97", ac97grp, ac97_padmux),
-	SIRFSOC_PMX_FUNCTION("nand", nandgrp, nand_padmux),
-	SIRFSOC_PMX_FUNCTION("spi0", spi0grp, spi0_padmux),
-	SIRFSOC_PMX_FUNCTION("spi1", spi1grp, spi1_padmux),
-	SIRFSOC_PMX_FUNCTION("gps", gpsgrp, gps_padmux),
-};
-
-struct sirfsoc_pinctrl_data prima2_pinctrl_data = {
-	(struct pinctrl_pin_desc *)sirfsoc_pads,
-	ARRAY_SIZE(sirfsoc_pads),
-	(struct sirfsoc_pin_group *)sirfsoc_pin_groups,
-	ARRAY_SIZE(sirfsoc_pin_groups),
-	(struct sirfsoc_pmx_func *)sirfsoc_pmx_functions,
-	ARRAY_SIZE(sirfsoc_pmx_functions),
-};
-
diff --git a/drivers/pinctrl/sirf/pinctrl-sirf.c b/drivers/pinctrl/sirf/pinctrl-sirf.c
deleted file mode 100644
index 63a287d5795f..000000000000
--- a/drivers/pinctrl/sirf/pinctrl-sirf.c
+++ /dev/null
@@ -1,894 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-/*
- * pinmux driver for CSR SiRFprimaII
- *
- * Authors:
- *	Rongjun Ying <rongjun.ying@csr.com>
- *	Yuping Luo <yuping.luo@csr.com>
- *	Barry Song <baohua.song@csr.com>
- *
- * Copyright (c) 2011 - 2014 Cambridge Silicon Radio Limited, a CSR plc group
- * company.
- */
-
-#include <linux/init.h>
-#include <linux/irq.h>
-#include <linux/platform_device.h>
-#include <linux/io.h>
-#include <linux/slab.h>
-#include <linux/err.h>
-#include <linux/pinctrl/pinctrl.h>
-#include <linux/pinctrl/pinmux.h>
-#include <linux/pinctrl/consumer.h>
-#include <linux/pinctrl/machine.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-#include <linux/of_device.h>
-#include <linux/of_platform.h>
-#include <linux/bitops.h>
-#include <linux/gpio/driver.h>
-#include <linux/of_gpio.h>
-
-#include "pinctrl-sirf.h"
-
-#define DRIVER_NAME "pinmux-sirf"
-
-struct sirfsoc_gpio_bank {
-	int id;
-	int parent_irq;
-	spinlock_t lock;
-};
-
-struct sirfsoc_gpio_chip {
-	struct of_mm_gpio_chip chip;
-	struct sirfsoc_gpio_bank sgpio_bank[SIRFSOC_GPIO_NO_OF_BANKS];
-	spinlock_t lock;
-};
-
-static struct sirfsoc_pin_group *sirfsoc_pin_groups;
-static int sirfsoc_pingrp_cnt;
-
-static int sirfsoc_get_groups_count(struct pinctrl_dev *pctldev)
-{
-	return sirfsoc_pingrp_cnt;
-}
-
-static const char *sirfsoc_get_group_name(struct pinctrl_dev *pctldev,
-				       unsigned selector)
-{
-	return sirfsoc_pin_groups[selector].name;
-}
-
-static int sirfsoc_get_group_pins(struct pinctrl_dev *pctldev,
-				unsigned selector,
-				const unsigned **pins,
-				unsigned *num_pins)
-{
-	*pins = sirfsoc_pin_groups[selector].pins;
-	*num_pins = sirfsoc_pin_groups[selector].num_pins;
-	return 0;
-}
-
-static void sirfsoc_pin_dbg_show(struct pinctrl_dev *pctldev,
-				struct seq_file *s, unsigned offset)
-{
-	seq_printf(s, " " DRIVER_NAME);
-}
-
-static int sirfsoc_dt_node_to_map(struct pinctrl_dev *pctldev,
-				 struct device_node *np_config,
-				 struct pinctrl_map **map, unsigned *num_maps)
-{
-	struct sirfsoc_pmx *spmx = pinctrl_dev_get_drvdata(pctldev);
-	struct device_node *np;
-	struct property *prop;
-	const char *function, *group;
-	int ret, index = 0, count = 0;
-
-	/* calculate number of maps required */
-	for_each_child_of_node(np_config, np) {
-		ret = of_property_read_string(np, "sirf,function", &function);
-		if (ret < 0) {
-			of_node_put(np);
-			return ret;
-		}
-
-		ret = of_property_count_strings(np, "sirf,pins");
-		if (ret < 0) {
-			of_node_put(np);
-			return ret;
-		}
-
-		count += ret;
-	}
-
-	if (!count) {
-		dev_err(spmx->dev, "No child nodes passed via DT\n");
-		return -ENODEV;
-	}
-
-	*map = kcalloc(count, sizeof(**map), GFP_KERNEL);
-	if (!*map)
-		return -ENOMEM;
-
-	for_each_child_of_node(np_config, np) {
-		of_property_read_string(np, "sirf,function", &function);
-		of_property_for_each_string(np, "sirf,pins", prop, group) {
-			(*map)[index].type = PIN_MAP_TYPE_MUX_GROUP;
-			(*map)[index].data.mux.group = group;
-			(*map)[index].data.mux.function = function;
-			index++;
-		}
-	}
-
-	*num_maps = count;
-
-	return 0;
-}
-
-static void sirfsoc_dt_free_map(struct pinctrl_dev *pctldev,
-		struct pinctrl_map *map, unsigned num_maps)
-{
-	kfree(map);
-}
-
-static const struct pinctrl_ops sirfsoc_pctrl_ops = {
-	.get_groups_count = sirfsoc_get_groups_count,
-	.get_group_name = sirfsoc_get_group_name,
-	.get_group_pins = sirfsoc_get_group_pins,
-	.pin_dbg_show = sirfsoc_pin_dbg_show,
-	.dt_node_to_map = sirfsoc_dt_node_to_map,
-	.dt_free_map = sirfsoc_dt_free_map,
-};
-
-static struct sirfsoc_pmx_func *sirfsoc_pmx_functions;
-static int sirfsoc_pmxfunc_cnt;
-
-static void sirfsoc_pinmux_endisable(struct sirfsoc_pmx *spmx,
-					unsigned selector, bool enable)
-{
-	int i;
-	const struct sirfsoc_padmux *mux =
-		sirfsoc_pmx_functions[selector].padmux;
-	const struct sirfsoc_muxmask *mask = mux->muxmask;
-
-	for (i = 0; i < mux->muxmask_counts; i++) {
-		u32 muxval;
-		muxval = readl(spmx->gpio_virtbase +
-			SIRFSOC_GPIO_PAD_EN(mask[i].group));
-		if (enable)
-			muxval = muxval & ~mask[i].mask;
-		else
-			muxval = muxval | mask[i].mask;
-		writel(muxval, spmx->gpio_virtbase +
-			SIRFSOC_GPIO_PAD_EN(mask[i].group));
-	}
-
-	if (mux->funcmask && enable) {
-		u32 func_en_val;
-
-		func_en_val =
-			readl(spmx->rsc_virtbase + mux->ctrlreg);
-		func_en_val =
-			(func_en_val & ~mux->funcmask) | (mux->funcval);
-		writel(func_en_val, spmx->rsc_virtbase + mux->ctrlreg);
-	}
-}
-
-static int sirfsoc_pinmux_set_mux(struct pinctrl_dev *pmxdev,
-				unsigned selector,
-				unsigned group)
-{
-	struct sirfsoc_pmx *spmx;
-
-	spmx = pinctrl_dev_get_drvdata(pmxdev);
-	sirfsoc_pinmux_endisable(spmx, selector, true);
-
-	return 0;
-}
-
-static int sirfsoc_pinmux_get_funcs_count(struct pinctrl_dev *pmxdev)
-{
-	return sirfsoc_pmxfunc_cnt;
-}
-
-static const char *sirfsoc_pinmux_get_func_name(struct pinctrl_dev *pctldev,
-					  unsigned selector)
-{
-	return sirfsoc_pmx_functions[selector].name;
-}
-
-static int sirfsoc_pinmux_get_groups(struct pinctrl_dev *pctldev,
-				unsigned selector,
-				const char * const **groups,
-				unsigned * const num_groups)
-{
-	*groups = sirfsoc_pmx_functions[selector].groups;
-	*num_groups = sirfsoc_pmx_functions[selector].num_groups;
-	return 0;
-}
-
-static int sirfsoc_pinmux_request_gpio(struct pinctrl_dev *pmxdev,
-	struct pinctrl_gpio_range *range, unsigned offset)
-{
-	struct sirfsoc_pmx *spmx;
-
-	int group = range->id;
-
-	u32 muxval;
-
-	spmx = pinctrl_dev_get_drvdata(pmxdev);
-
-	muxval = readl(spmx->gpio_virtbase +
-		SIRFSOC_GPIO_PAD_EN(group));
-	muxval = muxval | (1 << (offset - range->pin_base));
-	writel(muxval, spmx->gpio_virtbase +
-		SIRFSOC_GPIO_PAD_EN(group));
-
-	return 0;
-}
-
-static const struct pinmux_ops sirfsoc_pinmux_ops = {
-	.set_mux = sirfsoc_pinmux_set_mux,
-	.get_functions_count = sirfsoc_pinmux_get_funcs_count,
-	.get_function_name = sirfsoc_pinmux_get_func_name,
-	.get_function_groups = sirfsoc_pinmux_get_groups,
-	.gpio_request_enable = sirfsoc_pinmux_request_gpio,
-};
-
-static struct pinctrl_desc sirfsoc_pinmux_desc = {
-	.name = DRIVER_NAME,
-	.pctlops = &sirfsoc_pctrl_ops,
-	.pmxops = &sirfsoc_pinmux_ops,
-	.owner = THIS_MODULE,
-};
-
-static void __iomem *sirfsoc_rsc_of_iomap(void)
-{
-	const struct of_device_id rsc_ids[]  = {
-		{ .compatible = "sirf,prima2-rsc" },
-		{}
-	};
-	struct device_node *np;
-
-	np = of_find_matching_node(NULL, rsc_ids);
-	if (!np)
-		panic("unable to find compatible rsc node in dtb\n");
-
-	return of_iomap(np, 0);
-}
-
-static int sirfsoc_gpio_of_xlate(struct gpio_chip *gc,
-	const struct of_phandle_args *gpiospec,
-	u32 *flags)
-{
-	if (gpiospec->args[0] > SIRFSOC_GPIO_NO_OF_BANKS * SIRFSOC_GPIO_BANK_SIZE)
-		return -EINVAL;
-
-	if (flags)
-		*flags = gpiospec->args[1];
-
-	return gpiospec->args[0];
-}
-
-static const struct of_device_id pinmux_ids[] = {
-	{ .compatible = "sirf,prima2-pinctrl", .data = &prima2_pinctrl_data, },
-	{ .compatible = "sirf,atlas6-pinctrl", .data = &atlas6_pinctrl_data, },
-	{}
-};
-
-static int sirfsoc_pinmux_probe(struct platform_device *pdev)
-{
-	int ret;
-	struct sirfsoc_pmx *spmx;
-	struct device_node *np = pdev->dev.of_node;
-	const struct sirfsoc_pinctrl_data *pdata;
-
-	/* Create state holders etc for this driver */
-	spmx = devm_kzalloc(&pdev->dev, sizeof(*spmx), GFP_KERNEL);
-	if (!spmx)
-		return -ENOMEM;
-
-	spmx->dev = &pdev->dev;
-
-	platform_set_drvdata(pdev, spmx);
-
-	spmx->gpio_virtbase = of_iomap(np, 0);
-	if (!spmx->gpio_virtbase) {
-		dev_err(&pdev->dev, "can't map gpio registers\n");
-		return -ENOMEM;
-	}
-
-	spmx->rsc_virtbase = sirfsoc_rsc_of_iomap();
-	if (!spmx->rsc_virtbase) {
-		ret = -ENOMEM;
-		dev_err(&pdev->dev, "can't map rsc registers\n");
-		goto out_no_rsc_remap;
-	}
-
-	pdata = of_match_node(pinmux_ids, np)->data;
-	sirfsoc_pin_groups = pdata->grps;
-	sirfsoc_pingrp_cnt = pdata->grps_cnt;
-	sirfsoc_pmx_functions = pdata->funcs;
-	sirfsoc_pmxfunc_cnt = pdata->funcs_cnt;
-	sirfsoc_pinmux_desc.pins = pdata->pads;
-	sirfsoc_pinmux_desc.npins = pdata->pads_cnt;
-
-
-	/* Now register the pin controller and all pins it handles */
-	spmx->pmx = pinctrl_register(&sirfsoc_pinmux_desc, &pdev->dev, spmx);
-	if (IS_ERR(spmx->pmx)) {
-		dev_err(&pdev->dev, "could not register SIRFSOC pinmux driver\n");
-		ret = PTR_ERR(spmx->pmx);
-		goto out_no_pmx;
-	}
-
-	dev_info(&pdev->dev, "initialized SIRFSOC pinmux driver\n");
-
-	return 0;
-
-out_no_pmx:
-	iounmap(spmx->rsc_virtbase);
-out_no_rsc_remap:
-	iounmap(spmx->gpio_virtbase);
-	return ret;
-}
-
-#ifdef CONFIG_PM_SLEEP
-static int sirfsoc_pinmux_suspend_noirq(struct device *dev)
-{
-	int i, j;
-	struct sirfsoc_pmx *spmx = dev_get_drvdata(dev);
-
-	for (i = 0; i < SIRFSOC_GPIO_NO_OF_BANKS; i++) {
-		for (j = 0; j < SIRFSOC_GPIO_BANK_SIZE; j++) {
-			spmx->gpio_regs[i][j] = readl(spmx->gpio_virtbase +
-				SIRFSOC_GPIO_CTRL(i, j));
-		}
-		spmx->ints_regs[i] = readl(spmx->gpio_virtbase +
-			SIRFSOC_GPIO_INT_STATUS(i));
-		spmx->paden_regs[i] = readl(spmx->gpio_virtbase +
-			SIRFSOC_GPIO_PAD_EN(i));
-	}
-	spmx->dspen_regs = readl(spmx->gpio_virtbase + SIRFSOC_GPIO_DSP_EN0);
-
-	for (i = 0; i < 3; i++)
-		spmx->rsc_regs[i] = readl(spmx->rsc_virtbase + 4 * i);
-
-	return 0;
-}
-
-static int sirfsoc_pinmux_resume_noirq(struct device *dev)
-{
-	int i, j;
-	struct sirfsoc_pmx *spmx = dev_get_drvdata(dev);
-
-	for (i = 0; i < SIRFSOC_GPIO_NO_OF_BANKS; i++) {
-		for (j = 0; j < SIRFSOC_GPIO_BANK_SIZE; j++) {
-			writel(spmx->gpio_regs[i][j], spmx->gpio_virtbase +
-				SIRFSOC_GPIO_CTRL(i, j));
-		}
-		writel(spmx->ints_regs[i], spmx->gpio_virtbase +
-			SIRFSOC_GPIO_INT_STATUS(i));
-		writel(spmx->paden_regs[i], spmx->gpio_virtbase +
-			SIRFSOC_GPIO_PAD_EN(i));
-	}
-	writel(spmx->dspen_regs, spmx->gpio_virtbase + SIRFSOC_GPIO_DSP_EN0);
-
-	for (i = 0; i < 3; i++)
-		writel(spmx->rsc_regs[i], spmx->rsc_virtbase + 4 * i);
-
-	return 0;
-}
-
-static const struct dev_pm_ops sirfsoc_pinmux_pm_ops = {
-	.suspend_noirq = sirfsoc_pinmux_suspend_noirq,
-	.resume_noirq = sirfsoc_pinmux_resume_noirq,
-	.freeze_noirq = sirfsoc_pinmux_suspend_noirq,
-	.restore_noirq = sirfsoc_pinmux_resume_noirq,
-};
-#endif
-
-static struct platform_driver sirfsoc_pinmux_driver = {
-	.driver = {
-		.name = DRIVER_NAME,
-		.of_match_table = pinmux_ids,
-#ifdef CONFIG_PM_SLEEP
-		.pm = &sirfsoc_pinmux_pm_ops,
-#endif
-	},
-	.probe = sirfsoc_pinmux_probe,
-};
-
-static int __init sirfsoc_pinmux_init(void)
-{
-	return platform_driver_register(&sirfsoc_pinmux_driver);
-}
-arch_initcall(sirfsoc_pinmux_init);
-
-static inline struct sirfsoc_gpio_bank *
-sirfsoc_gpio_to_bank(struct sirfsoc_gpio_chip *sgpio, unsigned int offset)
-{
-	return &sgpio->sgpio_bank[offset / SIRFSOC_GPIO_BANK_SIZE];
-}
-
-static inline int sirfsoc_gpio_to_bankoff(unsigned int offset)
-{
-	return offset % SIRFSOC_GPIO_BANK_SIZE;
-}
-
-static void sirfsoc_gpio_irq_ack(struct irq_data *d)
-{
-	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
-	struct sirfsoc_gpio_chip *sgpio = gpiochip_get_data(gc);
-	struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, d->hwirq);
-	int idx = sirfsoc_gpio_to_bankoff(d->hwirq);
-	u32 val, offset;
-	unsigned long flags;
-
-	offset = SIRFSOC_GPIO_CTRL(bank->id, idx);
-
-	spin_lock_irqsave(&sgpio->lock, flags);
-
-	val = readl(sgpio->chip.regs + offset);
-
-	writel(val, sgpio->chip.regs + offset);
-
-	spin_unlock_irqrestore(&sgpio->lock, flags);
-}
-
-static void __sirfsoc_gpio_irq_mask(struct sirfsoc_gpio_chip *sgpio,
-				    struct sirfsoc_gpio_bank *bank,
-				    int idx)
-{
-	u32 val, offset;
-	unsigned long flags;
-
-	offset = SIRFSOC_GPIO_CTRL(bank->id, idx);
-
-	spin_lock_irqsave(&sgpio->lock, flags);
-
-	val = readl(sgpio->chip.regs + offset);
-	val &= ~SIRFSOC_GPIO_CTL_INTR_EN_MASK;
-	val &= ~SIRFSOC_GPIO_CTL_INTR_STS_MASK;
-	writel(val, sgpio->chip.regs + offset);
-
-	spin_unlock_irqrestore(&sgpio->lock, flags);
-}
-
-static void sirfsoc_gpio_irq_mask(struct irq_data *d)
-{
-	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
-	struct sirfsoc_gpio_chip *sgpio = gpiochip_get_data(gc);
-	struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, d->hwirq);
-
-	__sirfsoc_gpio_irq_mask(sgpio, bank, d->hwirq % SIRFSOC_GPIO_BANK_SIZE);
-}
-
-static void sirfsoc_gpio_irq_unmask(struct irq_data *d)
-{
-	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
-	struct sirfsoc_gpio_chip *sgpio = gpiochip_get_data(gc);
-	struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, d->hwirq);
-	int idx = sirfsoc_gpio_to_bankoff(d->hwirq);
-	u32 val, offset;
-	unsigned long flags;
-
-	offset = SIRFSOC_GPIO_CTRL(bank->id, idx);
-
-	spin_lock_irqsave(&sgpio->lock, flags);
-
-	val = readl(sgpio->chip.regs + offset);
-	val &= ~SIRFSOC_GPIO_CTL_INTR_STS_MASK;
-	val |= SIRFSOC_GPIO_CTL_INTR_EN_MASK;
-	writel(val, sgpio->chip.regs + offset);
-
-	spin_unlock_irqrestore(&sgpio->lock, flags);
-}
-
-static int sirfsoc_gpio_irq_type(struct irq_data *d, unsigned type)
-{
-	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
-	struct sirfsoc_gpio_chip *sgpio = gpiochip_get_data(gc);
-	struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, d->hwirq);
-	int idx = sirfsoc_gpio_to_bankoff(d->hwirq);
-	u32 val, offset;
-	unsigned long flags;
-
-	offset = SIRFSOC_GPIO_CTRL(bank->id, idx);
-
-	spin_lock_irqsave(&sgpio->lock, flags);
-
-	val = readl(sgpio->chip.regs + offset);
-	val &= ~(SIRFSOC_GPIO_CTL_INTR_STS_MASK | SIRFSOC_GPIO_CTL_OUT_EN_MASK);
-
-	switch (type) {
-	case IRQ_TYPE_NONE:
-		break;
-	case IRQ_TYPE_EDGE_RISING:
-		val |= SIRFSOC_GPIO_CTL_INTR_HIGH_MASK |
-			SIRFSOC_GPIO_CTL_INTR_TYPE_MASK;
-		val &= ~SIRFSOC_GPIO_CTL_INTR_LOW_MASK;
-		break;
-	case IRQ_TYPE_EDGE_FALLING:
-		val &= ~SIRFSOC_GPIO_CTL_INTR_HIGH_MASK;
-		val |= SIRFSOC_GPIO_CTL_INTR_LOW_MASK |
-			SIRFSOC_GPIO_CTL_INTR_TYPE_MASK;
-		break;
-	case IRQ_TYPE_EDGE_BOTH:
-		val |= SIRFSOC_GPIO_CTL_INTR_HIGH_MASK |
-			SIRFSOC_GPIO_CTL_INTR_LOW_MASK |
-			SIRFSOC_GPIO_CTL_INTR_TYPE_MASK;
-		break;
-	case IRQ_TYPE_LEVEL_LOW:
-		val &= ~(SIRFSOC_GPIO_CTL_INTR_HIGH_MASK |
-			SIRFSOC_GPIO_CTL_INTR_TYPE_MASK);
-		val |= SIRFSOC_GPIO_CTL_INTR_LOW_MASK;
-		break;
-	case IRQ_TYPE_LEVEL_HIGH:
-		val |= SIRFSOC_GPIO_CTL_INTR_HIGH_MASK;
-		val &= ~(SIRFSOC_GPIO_CTL_INTR_LOW_MASK |
-			SIRFSOC_GPIO_CTL_INTR_TYPE_MASK);
-		break;
-	}
-
-	writel(val, sgpio->chip.regs + offset);
-
-	spin_unlock_irqrestore(&sgpio->lock, flags);
-
-	return 0;
-}
-
-static struct irq_chip sirfsoc_irq_chip = {
-	.name = "sirf-gpio-irq",
-	.irq_ack = sirfsoc_gpio_irq_ack,
-	.irq_mask = sirfsoc_gpio_irq_mask,
-	.irq_unmask = sirfsoc_gpio_irq_unmask,
-	.irq_set_type = sirfsoc_gpio_irq_type,
-};
-
-static void sirfsoc_gpio_handle_irq(struct irq_desc *desc)
-{
-	unsigned int irq = irq_desc_get_irq(desc);
-	struct gpio_chip *gc = irq_desc_get_handler_data(desc);
-	struct sirfsoc_gpio_chip *sgpio = gpiochip_get_data(gc);
-	struct sirfsoc_gpio_bank *bank;
-	u32 status, ctrl;
-	int idx = 0;
-	struct irq_chip *chip = irq_desc_get_chip(desc);
-	int i;
-
-	for (i = 0; i < SIRFSOC_GPIO_NO_OF_BANKS; i++) {
-		bank = &sgpio->sgpio_bank[i];
-		if (bank->parent_irq == irq)
-			break;
-	}
-	BUG_ON(i == SIRFSOC_GPIO_NO_OF_BANKS);
-
-	chained_irq_enter(chip, desc);
-
-	status = readl(sgpio->chip.regs + SIRFSOC_GPIO_INT_STATUS(bank->id));
-	if (!status) {
-		printk(KERN_WARNING
-			"%s: gpio id %d status %#x no interrupt is flagged\n",
-			__func__, bank->id, status);
-		handle_bad_irq(desc);
-		return;
-	}
-
-	while (status) {
-		ctrl = readl(sgpio->chip.regs + SIRFSOC_GPIO_CTRL(bank->id, idx));
-
-		/*
-		 * Here we must check whether the corresponding GPIO's interrupt
-		 * has been enabled, otherwise just skip it
-		 */
-		if ((status & 0x1) && (ctrl & SIRFSOC_GPIO_CTL_INTR_EN_MASK)) {
-			pr_debug("%s: gpio id %d idx %d happens\n",
-				__func__, bank->id, idx);
-			generic_handle_irq(irq_find_mapping(gc->irq.domain, idx +
-					bank->id * SIRFSOC_GPIO_BANK_SIZE));
-		}
-
-		idx++;
-		status = status >> 1;
-	}
-
-	chained_irq_exit(chip, desc);
-}
-
-static inline void sirfsoc_gpio_set_input(struct sirfsoc_gpio_chip *sgpio,
-					  unsigned ctrl_offset)
-{
-	u32 val;
-
-	val = readl(sgpio->chip.regs + ctrl_offset);
-	val &= ~SIRFSOC_GPIO_CTL_OUT_EN_MASK;
-	writel(val, sgpio->chip.regs + ctrl_offset);
-}
-
-static int sirfsoc_gpio_request(struct gpio_chip *chip, unsigned offset)
-{
-	struct sirfsoc_gpio_chip *sgpio = gpiochip_get_data(chip);
-	struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, offset);
-	unsigned long flags;
-
-	if (pinctrl_gpio_request(chip->base + offset))
-		return -ENODEV;
-
-	spin_lock_irqsave(&bank->lock, flags);
-
-	/*
-	 * default status:
-	 * set direction as input and mask irq
-	 */
-	sirfsoc_gpio_set_input(sgpio, SIRFSOC_GPIO_CTRL(bank->id, offset));
-	__sirfsoc_gpio_irq_mask(sgpio, bank, offset);
-
-	spin_unlock_irqrestore(&bank->lock, flags);
-
-	return 0;
-}
-
-static void sirfsoc_gpio_free(struct gpio_chip *chip, unsigned offset)
-{
-	struct sirfsoc_gpio_chip *sgpio = gpiochip_get_data(chip);
-	struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, offset);
-	unsigned long flags;
-
-	spin_lock_irqsave(&bank->lock, flags);
-
-	__sirfsoc_gpio_irq_mask(sgpio, bank, offset);
-	sirfsoc_gpio_set_input(sgpio, SIRFSOC_GPIO_CTRL(bank->id, offset));
-
-	spin_unlock_irqrestore(&bank->lock, flags);
-
-	pinctrl_gpio_free(chip->base + offset);
-}
-
-static int sirfsoc_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
-{
-	struct sirfsoc_gpio_chip *sgpio = gpiochip_get_data(chip);
-	struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, gpio);
-	int idx = sirfsoc_gpio_to_bankoff(gpio);
-	unsigned long flags;
-	unsigned offset;
-
-	offset = SIRFSOC_GPIO_CTRL(bank->id, idx);
-
-	spin_lock_irqsave(&bank->lock, flags);
-
-	sirfsoc_gpio_set_input(sgpio, offset);
-
-	spin_unlock_irqrestore(&bank->lock, flags);
-
-	return 0;
-}
-
-static inline void sirfsoc_gpio_set_output(struct sirfsoc_gpio_chip *sgpio,
-					   struct sirfsoc_gpio_bank *bank,
-					   unsigned offset,
-					   int value)
-{
-	u32 out_ctrl;
-	unsigned long flags;
-
-	spin_lock_irqsave(&bank->lock, flags);
-
-	out_ctrl = readl(sgpio->chip.regs + offset);
-	if (value)
-		out_ctrl |= SIRFSOC_GPIO_CTL_DATAOUT_MASK;
-	else
-		out_ctrl &= ~SIRFSOC_GPIO_CTL_DATAOUT_MASK;
-
-	out_ctrl &= ~SIRFSOC_GPIO_CTL_INTR_EN_MASK;
-	out_ctrl |= SIRFSOC_GPIO_CTL_OUT_EN_MASK;
-	writel(out_ctrl, sgpio->chip.regs + offset);
-
-	spin_unlock_irqrestore(&bank->lock, flags);
-}
-
-static int sirfsoc_gpio_direction_output(struct gpio_chip *chip,
-	unsigned gpio, int value)
-{
-	struct sirfsoc_gpio_chip *sgpio = gpiochip_get_data(chip);
-	struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, gpio);
-	int idx = sirfsoc_gpio_to_bankoff(gpio);
-	u32 offset;
-	unsigned long flags;
-
-	offset = SIRFSOC_GPIO_CTRL(bank->id, idx);
-
-	spin_lock_irqsave(&sgpio->lock, flags);
-
-	sirfsoc_gpio_set_output(sgpio, bank, offset, value);
-
-	spin_unlock_irqrestore(&sgpio->lock, flags);
-
-	return 0;
-}
-
-static int sirfsoc_gpio_get_value(struct gpio_chip *chip, unsigned offset)
-{
-	struct sirfsoc_gpio_chip *sgpio = gpiochip_get_data(chip);
-	struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, offset);
-	u32 val;
-	unsigned long flags;
-
-	spin_lock_irqsave(&bank->lock, flags);
-
-	val = readl(sgpio->chip.regs + SIRFSOC_GPIO_CTRL(bank->id, offset));
-
-	spin_unlock_irqrestore(&bank->lock, flags);
-
-	return !!(val & SIRFSOC_GPIO_CTL_DATAIN_MASK);
-}
-
-static void sirfsoc_gpio_set_value(struct gpio_chip *chip, unsigned offset,
-	int value)
-{
-	struct sirfsoc_gpio_chip *sgpio = gpiochip_get_data(chip);
-	struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, offset);
-	u32 ctrl;
-	unsigned long flags;
-
-	spin_lock_irqsave(&bank->lock, flags);
-
-	ctrl = readl(sgpio->chip.regs + SIRFSOC_GPIO_CTRL(bank->id, offset));
-	if (value)
-		ctrl |= SIRFSOC_GPIO_CTL_DATAOUT_MASK;
-	else
-		ctrl &= ~SIRFSOC_GPIO_CTL_DATAOUT_MASK;
-	writel(ctrl, sgpio->chip.regs + SIRFSOC_GPIO_CTRL(bank->id, offset));
-
-	spin_unlock_irqrestore(&bank->lock, flags);
-}
-
-static void sirfsoc_gpio_set_pullup(struct sirfsoc_gpio_chip *sgpio,
-				    const u32 *pullups)
-{
-	int i, n;
-	const unsigned long *p = (const unsigned long *)pullups;
-
-	for (i = 0; i < SIRFSOC_GPIO_NO_OF_BANKS; i++) {
-		for_each_set_bit(n, p + i, BITS_PER_LONG) {
-			u32 offset = SIRFSOC_GPIO_CTRL(i, n);
-			u32 val = readl(sgpio->chip.regs + offset);
-			val |= SIRFSOC_GPIO_CTL_PULL_MASK;
-			val |= SIRFSOC_GPIO_CTL_PULL_HIGH;
-			writel(val, sgpio->chip.regs + offset);
-		}
-	}
-}
-
-static void sirfsoc_gpio_set_pulldown(struct sirfsoc_gpio_chip *sgpio,
-				      const u32 *pulldowns)
-{
-	int i, n;
-	const unsigned long *p = (const unsigned long *)pulldowns;
-
-	for (i = 0; i < SIRFSOC_GPIO_NO_OF_BANKS; i++) {
-		for_each_set_bit(n, p + i, BITS_PER_LONG) {
-			u32 offset = SIRFSOC_GPIO_CTRL(i, n);
-			u32 val = readl(sgpio->chip.regs + offset);
-			val |= SIRFSOC_GPIO_CTL_PULL_MASK;
-			val &= ~SIRFSOC_GPIO_CTL_PULL_HIGH;
-			writel(val, sgpio->chip.regs + offset);
-		}
-	}
-}
-
-static int sirfsoc_gpio_probe(struct device_node *np)
-{
-	int i, err = 0;
-	struct sirfsoc_gpio_chip *sgpio;
-	struct sirfsoc_gpio_bank *bank;
-	void __iomem *regs;
-	struct platform_device *pdev;
-	struct gpio_irq_chip *girq;
-
-	u32 pullups[SIRFSOC_GPIO_NO_OF_BANKS], pulldowns[SIRFSOC_GPIO_NO_OF_BANKS];
-
-	pdev = of_find_device_by_node(np);
-	if (!pdev)
-		return -ENODEV;
-
-	sgpio = devm_kzalloc(&pdev->dev, sizeof(*sgpio), GFP_KERNEL);
-	if (!sgpio) {
-		err = -ENOMEM;
-		goto out_put_device;
-	}
-	spin_lock_init(&sgpio->lock);
-
-	regs = of_iomap(np, 0);
-	if (!regs) {
-		err = -ENOMEM;
-		goto out_put_device;
-	}
-
-	sgpio->chip.gc.request = sirfsoc_gpio_request;
-	sgpio->chip.gc.free = sirfsoc_gpio_free;
-	sgpio->chip.gc.direction_input = sirfsoc_gpio_direction_input;
-	sgpio->chip.gc.get = sirfsoc_gpio_get_value;
-	sgpio->chip.gc.direction_output = sirfsoc_gpio_direction_output;
-	sgpio->chip.gc.set = sirfsoc_gpio_set_value;
-	sgpio->chip.gc.base = 0;
-	sgpio->chip.gc.ngpio = SIRFSOC_GPIO_BANK_SIZE * SIRFSOC_GPIO_NO_OF_BANKS;
-	sgpio->chip.gc.label = kasprintf(GFP_KERNEL, "%pOF", np);
-	sgpio->chip.gc.of_node = np;
-	sgpio->chip.gc.of_xlate = sirfsoc_gpio_of_xlate;
-	sgpio->chip.gc.of_gpio_n_cells = 2;
-	sgpio->chip.gc.parent = &pdev->dev;
-	sgpio->chip.regs = regs;
-
-	girq = &sgpio->chip.gc.irq;
-	girq->chip = &sirfsoc_irq_chip;
-	girq->parent_handler = sirfsoc_gpio_handle_irq;
-	girq->num_parents = SIRFSOC_GPIO_NO_OF_BANKS;
-	girq->parents = devm_kcalloc(&pdev->dev, SIRFSOC_GPIO_NO_OF_BANKS,
-				     sizeof(*girq->parents),
-				     GFP_KERNEL);
-	if (!girq->parents) {
-		err = -ENOMEM;
-		goto out_put_device;
-	}
-	for (i = 0; i < SIRFSOC_GPIO_NO_OF_BANKS; i++) {
-		bank = &sgpio->sgpio_bank[i];
-		spin_lock_init(&bank->lock);
-		bank->parent_irq = platform_get_irq(pdev, i);
-		if (bank->parent_irq < 0) {
-			err = bank->parent_irq;
-			goto out;
-		}
-		girq->parents[i] = bank->parent_irq;
-	}
-	girq->default_type = IRQ_TYPE_NONE;
-	girq->handler = handle_level_irq;
-
-	err = gpiochip_add_data(&sgpio->chip.gc, sgpio);
-	if (err) {
-		dev_err(&pdev->dev, "%pOF: error in probe function with status %d\n",
-			np, err);
-		goto out;
-	}
-
-	err = gpiochip_add_pin_range(&sgpio->chip.gc, dev_name(&pdev->dev),
-		0, 0, SIRFSOC_GPIO_BANK_SIZE * SIRFSOC_GPIO_NO_OF_BANKS);
-	if (err) {
-		dev_err(&pdev->dev,
-			"could not add gpiochip pin range\n");
-		goto out_no_range;
-	}
-
-	if (!of_property_read_u32_array(np, "sirf,pullups", pullups,
-		SIRFSOC_GPIO_NO_OF_BANKS))
-		sirfsoc_gpio_set_pullup(sgpio, pullups);
-
-	if (!of_property_read_u32_array(np, "sirf,pulldowns", pulldowns,
-		SIRFSOC_GPIO_NO_OF_BANKS))
-		sirfsoc_gpio_set_pulldown(sgpio, pulldowns);
-
-	return 0;
-
-out_no_range:
-	gpiochip_remove(&sgpio->chip.gc);
-out:
-	iounmap(regs);
-out_put_device:
-	put_device(&pdev->dev);
-	return err;
-}
-
-static int __init sirfsoc_gpio_init(void)
-{
-
-	struct device_node *np;
-
-	np = of_find_matching_node(NULL, pinmux_ids);
-
-	if (!np)
-		return -ENODEV;
-
-	return sirfsoc_gpio_probe(np);
-}
-subsys_initcall(sirfsoc_gpio_init);
diff --git a/drivers/pinctrl/sirf/pinctrl-sirf.h b/drivers/pinctrl/sirf/pinctrl-sirf.h
deleted file mode 100644
index d7125b8773cc..000000000000
--- a/drivers/pinctrl/sirf/pinctrl-sirf.h
+++ /dev/null
@@ -1,116 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-/*
- * pinmux driver shared headfile for CSR SiRFsoc
- *
- * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
- */
-
-#ifndef __PINMUX_SIRF_H__
-#define __PINMUX_SIRF_H__
-
-#define SIRFSOC_NUM_PADS		622
-#define SIRFSOC_RSC_USB_UART_SHARE	0
-#define SIRFSOC_RSC_PIN_MUX		0x4
-
-#define SIRFSOC_GPIO_PAD_EN(g)		((g)*0x100 + 0x84)
-#define SIRFSOC_GPIO_PAD_EN_CLR(g)	((g)*0x100 + 0x90)
-#define SIRFSOC_GPIO_CTRL(g, i)			((g)*0x100 + (i)*4)
-#define SIRFSOC_GPIO_DSP_EN0			(0x80)
-#define SIRFSOC_GPIO_INT_STATUS(g)		((g)*0x100 + 0x8C)
-
-#define SIRFSOC_GPIO_CTL_INTR_LOW_MASK		0x1
-#define SIRFSOC_GPIO_CTL_INTR_HIGH_MASK		0x2
-#define SIRFSOC_GPIO_CTL_INTR_TYPE_MASK		0x4
-#define SIRFSOC_GPIO_CTL_INTR_EN_MASK		0x8
-#define SIRFSOC_GPIO_CTL_INTR_STS_MASK		0x10
-#define SIRFSOC_GPIO_CTL_OUT_EN_MASK		0x20
-#define SIRFSOC_GPIO_CTL_DATAOUT_MASK		0x40
-#define SIRFSOC_GPIO_CTL_DATAIN_MASK		0x80
-#define SIRFSOC_GPIO_CTL_PULL_MASK		0x100
-#define SIRFSOC_GPIO_CTL_PULL_HIGH		0x200
-#define SIRFSOC_GPIO_CTL_DSP_INT		0x400
-
-#define SIRFSOC_GPIO_NO_OF_BANKS        5
-#define SIRFSOC_GPIO_BANK_SIZE          32
-#define SIRFSOC_GPIO_NUM(bank, index)	(((bank)*(32)) + (index))
-
-/**
- * @dev: a pointer back to containing device
- * @virtbase: the offset to the controller in virtual memory
- */
-struct sirfsoc_pmx {
-	struct device *dev;
-	struct pinctrl_dev *pmx;
-	void __iomem *gpio_virtbase;
-	void __iomem *rsc_virtbase;
-	u32 gpio_regs[SIRFSOC_GPIO_NO_OF_BANKS][SIRFSOC_GPIO_BANK_SIZE];
-	u32 ints_regs[SIRFSOC_GPIO_NO_OF_BANKS];
-	u32 paden_regs[SIRFSOC_GPIO_NO_OF_BANKS];
-	u32 dspen_regs;
-	u32 rsc_regs[3];
-};
-
-/* SIRFSOC_GPIO_PAD_EN set */
-struct sirfsoc_muxmask {
-	unsigned long group;
-	unsigned long mask;
-};
-
-struct sirfsoc_padmux {
-	unsigned long muxmask_counts;
-	const struct sirfsoc_muxmask *muxmask;
-	/* RSC_PIN_MUX set */
-	unsigned long ctrlreg;
-	unsigned long funcmask;
-	unsigned long funcval;
-};
-
- /**
- * struct sirfsoc_pin_group - describes a SiRFprimaII pin group
- * @name: the name of this specific pin group
- * @pins: an array of discrete physical pins used in this group, taken
- *	from the driver-local pin enumeration space
- * @num_pins: the number of pins in this group array, i.e. the number of
- *	elements in .pins so we can iterate over that array
- */
-struct sirfsoc_pin_group {
-	const char *name;
-	const unsigned int *pins;
-	const unsigned num_pins;
-};
-
-#define SIRFSOC_PIN_GROUP(n, p)  \
-	{			\
-		.name = n,	\
-		.pins = p,	\
-		.num_pins = ARRAY_SIZE(p),	\
-	}
-
-struct sirfsoc_pmx_func {
-	const char *name;
-	const char * const *groups;
-	const unsigned num_groups;
-	const struct sirfsoc_padmux *padmux;
-};
-
-#define SIRFSOC_PMX_FUNCTION(n, g, m)		\
-	{					\
-		.name = n,			\
-		.groups = g,			\
-		.num_groups = ARRAY_SIZE(g),	\
-		.padmux = &m,			\
-	}
-
-struct sirfsoc_pinctrl_data {
-	struct pinctrl_pin_desc *pads;
-	int pads_cnt;
-	struct sirfsoc_pin_group *grps;
-	int grps_cnt;
-	struct sirfsoc_pmx_func *funcs;
-	int funcs_cnt;
-};
-
-extern struct sirfsoc_pinctrl_data prima2_pinctrl_data;
-extern struct sirfsoc_pinctrl_data atlas6_pinctrl_data;
-
-#endif
-- 
2.29.2


^ permalink raw reply related	[flat|nested] 22+ messages in thread

* [PATCH 4/5] pinctrl: remove coh901 driver
  2021-01-20 13:20 ` Arnd Bergmann
@ 2021-01-20 13:20   ` Arnd Bergmann
  -1 siblings, 0 replies; 22+ messages in thread
From: Arnd Bergmann @ 2021-01-20 13:20 UTC (permalink / raw)
  To: linux-arm-kernel, linux-kernel, linux-gpio, Linus Walleij
  Cc: Bartosz Golaszewski, Arnd Bergmann

From: Arnd Bergmann <arnd@arndb.de>

The ST-Ericsson U300 platform is getting removed, so this driver is no
longer needed.

Cc: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
---
 .../bindings/gpio/gpio-stericsson-coh901.txt  |   7 -
 drivers/pinctrl/Kconfig                       |  10 -
 drivers/pinctrl/Makefile                      |   1 -
 drivers/pinctrl/pinctrl-coh901.c              | 774 ------------------
 drivers/pinctrl/pinctrl-coh901.h              |   6 -
 5 files changed, 798 deletions(-)
 delete mode 100644 Documentation/devicetree/bindings/gpio/gpio-stericsson-coh901.txt
 delete mode 100644 drivers/pinctrl/pinctrl-coh901.c
 delete mode 100644 drivers/pinctrl/pinctrl-coh901.h

diff --git a/Documentation/devicetree/bindings/gpio/gpio-stericsson-coh901.txt b/Documentation/devicetree/bindings/gpio/gpio-stericsson-coh901.txt
deleted file mode 100644
index fd665b44d767..000000000000
--- a/Documentation/devicetree/bindings/gpio/gpio-stericsson-coh901.txt
+++ /dev/null
@@ -1,7 +0,0 @@
-ST-Ericsson COH 901 571/3 GPIO controller
-
-Required properties:
-- compatible: Compatible property value should be "stericsson,gpio-coh901"
-- reg: Physical base address of the controller and length of memory mapped
-  region.
-- interrupts: the 0...n interrupts assigned to the different GPIO ports/banks.
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index e176137dbf29..9ddbf14d9536 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -277,16 +277,6 @@ config PINCTRL_U300
 	select PINMUX
 	select GENERIC_PINCONF
 
-config PINCTRL_COH901
-	bool "ST-Ericsson U300 COH 901 335/571 GPIO"
-	depends on GPIOLIB && ARCH_U300 && PINCTRL_U300
-	select GPIOLIB_IRQCHIP
-	help
-	  Say yes here to support GPIO interface on ST-Ericsson U300.
-	  The names of the two IP block variants supported are
-	  COH 901 335 and COH 901 571/3. They contain 3, 5 or 7
-	  ports of 8 GPIO pins each.
-
 config PINCTRL_MAX77620
 	tristate "MAX77620/MAX20024 Pincontrol support"
 	depends on MFD_MAX77620 && OF
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index f414846abe2d..10643440b467 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -34,7 +34,6 @@ obj-$(CONFIG_PINCTRL_SINGLE)	+= pinctrl-single.o
 obj-$(CONFIG_PINCTRL_SX150X)	+= pinctrl-sx150x.o
 obj-$(CONFIG_ARCH_TEGRA)	+= tegra/
 obj-$(CONFIG_PINCTRL_U300)	+= pinctrl-u300.o
-obj-$(CONFIG_PINCTRL_COH901)	+= pinctrl-coh901.o
 obj-$(CONFIG_PINCTRL_XWAY)	+= pinctrl-xway.o
 obj-$(CONFIG_PINCTRL_LANTIQ)	+= pinctrl-lantiq.o
 obj-$(CONFIG_PINCTRL_LPC18XX)	+= pinctrl-lpc18xx.o
diff --git a/drivers/pinctrl/pinctrl-coh901.c b/drivers/pinctrl/pinctrl-coh901.c
deleted file mode 100644
index 2905348ff430..000000000000
--- a/drivers/pinctrl/pinctrl-coh901.c
+++ /dev/null
@@ -1,774 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * U300 GPIO module.
- *
- * Copyright (C) 2007-2012 ST-Ericsson AB
- * COH 901 571/3 - Used in DB3210 (U365 2.0) and DB3350 (U335 1.0)
- * Author: Linus Walleij <linus.walleij@linaro.org>
- * Author: Jonas Aaberg <jonas.aberg@stericsson.com>
- */
-#include <linux/module.h>
-#include <linux/interrupt.h>
-#include <linux/delay.h>
-#include <linux/errno.h>
-#include <linux/io.h>
-#include <linux/clk.h>
-#include <linux/err.h>
-#include <linux/platform_device.h>
-#include <linux/gpio/driver.h>
-#include <linux/slab.h>
-#include <linux/pinctrl/consumer.h>
-#include <linux/pinctrl/pinconf-generic.h>
-#include "pinctrl-coh901.h"
-
-#define U300_GPIO_PORT_STRIDE				(0x30)
-/*
- * Control Register 32bit (R/W)
- * bit 15-9 (mask 0x0000FE00) contains the number of cores. 8*cores
- * gives the number of GPIO pins.
- * bit 8-2  (mask 0x000001FC) contains the core version ID.
- */
-#define U300_GPIO_CR					(0x00)
-#define U300_GPIO_CR_SYNC_SEL_ENABLE			(0x00000002UL)
-#define U300_GPIO_CR_BLOCK_CLKRQ_ENABLE			(0x00000001UL)
-#define U300_GPIO_PXPDIR				(0x04)
-#define U300_GPIO_PXPDOR				(0x08)
-#define U300_GPIO_PXPCR					(0x0C)
-#define U300_GPIO_PXPCR_ALL_PINS_MODE_MASK		(0x0000FFFFUL)
-#define U300_GPIO_PXPCR_PIN_MODE_MASK			(0x00000003UL)
-#define U300_GPIO_PXPCR_PIN_MODE_SHIFT			(0x00000002UL)
-#define U300_GPIO_PXPCR_PIN_MODE_INPUT			(0x00000000UL)
-#define U300_GPIO_PXPCR_PIN_MODE_OUTPUT_PUSH_PULL	(0x00000001UL)
-#define U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_DRAIN	(0x00000002UL)
-#define U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_SOURCE	(0x00000003UL)
-#define U300_GPIO_PXPER					(0x10)
-#define U300_GPIO_PXPER_ALL_PULL_UP_DISABLE_MASK	(0x000000FFUL)
-#define U300_GPIO_PXPER_PULL_UP_DISABLE			(0x00000001UL)
-#define U300_GPIO_PXIEV					(0x14)
-#define U300_GPIO_PXIEN					(0x18)
-#define U300_GPIO_PXIFR					(0x1C)
-#define U300_GPIO_PXICR					(0x20)
-#define U300_GPIO_PXICR_ALL_IRQ_CONFIG_MASK		(0x000000FFUL)
-#define U300_GPIO_PXICR_IRQ_CONFIG_MASK			(0x00000001UL)
-#define U300_GPIO_PXICR_IRQ_CONFIG_FALLING_EDGE		(0x00000000UL)
-#define U300_GPIO_PXICR_IRQ_CONFIG_RISING_EDGE		(0x00000001UL)
-
-/* 8 bits per port, no version has more than 7 ports */
-#define U300_GPIO_NUM_PORTS 7
-#define U300_GPIO_PINS_PER_PORT 8
-#define U300_GPIO_MAX (U300_GPIO_PINS_PER_PORT * U300_GPIO_NUM_PORTS)
-
-struct u300_gpio_port {
-	struct u300_gpio *gpio;
-	char name[8];
-	int irq;
-	int number;
-	u8 toggle_edge_mode;
-};
-
-struct u300_gpio {
-	struct gpio_chip chip;
-	struct u300_gpio_port ports[U300_GPIO_NUM_PORTS];
-	struct clk *clk;
-	void __iomem *base;
-	struct device *dev;
-	u32 stride;
-	/* Register offsets */
-	u32 pcr;
-	u32 dor;
-	u32 dir;
-	u32 per;
-	u32 icr;
-	u32 ien;
-	u32 iev;
-};
-
-/*
- * Macro to expand to read a specific register found in the "gpio"
- * struct. It requires the struct u300_gpio *gpio variable to exist in
- * its context. It calculates the port offset from the given pin
- * offset, muliplies by the port stride and adds the register offset
- * so it provides a pointer to the desired register.
- */
-#define U300_PIN_REG(pin, reg) \
-	(gpio->base + (pin >> 3) * gpio->stride + gpio->reg)
-
-/*
- * Provides a bitmask for a specific gpio pin inside an 8-bit GPIO
- * register.
- */
-#define U300_PIN_BIT(pin) \
-	(1 << (pin & 0x07))
-
-struct u300_gpio_confdata {
-	u16 bias_mode;
-	bool output;
-	int outval;
-};
-
-#define U300_FLOATING_INPUT { \
-	.bias_mode = PIN_CONFIG_BIAS_HIGH_IMPEDANCE, \
-	.output = false, \
-}
-
-#define U300_PULL_UP_INPUT { \
-	.bias_mode = PIN_CONFIG_BIAS_PULL_UP, \
-	.output = false, \
-}
-
-#define U300_OUTPUT_LOW { \
-	.output = true, \
-	.outval = 0, \
-}
-
-#define U300_OUTPUT_HIGH { \
-	.output = true, \
-	.outval = 1, \
-}
-
-/* Initial configuration */
-static const struct u300_gpio_confdata __initconst
-bs335_gpio_config[U300_GPIO_NUM_PORTS][U300_GPIO_PINS_PER_PORT] = {
-	/* Port 0, pins 0-7 */
-	{
-		U300_FLOATING_INPUT,
-		U300_OUTPUT_HIGH,
-		U300_FLOATING_INPUT,
-		U300_OUTPUT_LOW,
-		U300_OUTPUT_LOW,
-		U300_OUTPUT_LOW,
-		U300_OUTPUT_LOW,
-		U300_OUTPUT_LOW,
-	},
-	/* Port 1, pins 0-7 */
-	{
-		U300_OUTPUT_LOW,
-		U300_OUTPUT_LOW,
-		U300_OUTPUT_LOW,
-		U300_PULL_UP_INPUT,
-		U300_FLOATING_INPUT,
-		U300_OUTPUT_HIGH,
-		U300_OUTPUT_LOW,
-		U300_OUTPUT_LOW,
-	},
-	/* Port 2, pins 0-7 */
-	{
-		U300_FLOATING_INPUT,
-		U300_FLOATING_INPUT,
-		U300_FLOATING_INPUT,
-		U300_FLOATING_INPUT,
-		U300_OUTPUT_LOW,
-		U300_PULL_UP_INPUT,
-		U300_OUTPUT_LOW,
-		U300_PULL_UP_INPUT,
-	},
-	/* Port 3, pins 0-7 */
-	{
-		U300_PULL_UP_INPUT,
-		U300_OUTPUT_LOW,
-		U300_FLOATING_INPUT,
-		U300_FLOATING_INPUT,
-		U300_FLOATING_INPUT,
-		U300_FLOATING_INPUT,
-		U300_FLOATING_INPUT,
-		U300_FLOATING_INPUT,
-	},
-	/* Port 4, pins 0-7 */
-	{
-		U300_FLOATING_INPUT,
-		U300_FLOATING_INPUT,
-		U300_FLOATING_INPUT,
-		U300_FLOATING_INPUT,
-		U300_FLOATING_INPUT,
-		U300_FLOATING_INPUT,
-		U300_FLOATING_INPUT,
-		U300_FLOATING_INPUT,
-	},
-	/* Port 5, pins 0-7 */
-	{
-		U300_FLOATING_INPUT,
-		U300_FLOATING_INPUT,
-		U300_FLOATING_INPUT,
-		U300_FLOATING_INPUT,
-		U300_FLOATING_INPUT,
-		U300_FLOATING_INPUT,
-		U300_FLOATING_INPUT,
-		U300_FLOATING_INPUT,
-	},
-	/* Port 6, pind 0-7 */
-	{
-		U300_FLOATING_INPUT,
-		U300_FLOATING_INPUT,
-		U300_FLOATING_INPUT,
-		U300_FLOATING_INPUT,
-		U300_FLOATING_INPUT,
-		U300_FLOATING_INPUT,
-		U300_FLOATING_INPUT,
-		U300_FLOATING_INPUT,
-	}
-};
-
-static int u300_gpio_get(struct gpio_chip *chip, unsigned offset)
-{
-	struct u300_gpio *gpio = gpiochip_get_data(chip);
-
-	return !!(readl(U300_PIN_REG(offset, dir)) & U300_PIN_BIT(offset));
-}
-
-static void u300_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
-{
-	struct u300_gpio *gpio = gpiochip_get_data(chip);
-	unsigned long flags;
-	u32 val;
-
-	local_irq_save(flags);
-
-	val = readl(U300_PIN_REG(offset, dor));
-	if (value)
-		writel(val | U300_PIN_BIT(offset), U300_PIN_REG(offset, dor));
-	else
-		writel(val & ~U300_PIN_BIT(offset), U300_PIN_REG(offset, dor));
-
-	local_irq_restore(flags);
-}
-
-static int u300_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
-{
-	struct u300_gpio *gpio = gpiochip_get_data(chip);
-	unsigned long flags;
-	u32 val;
-
-	local_irq_save(flags);
-	val = readl(U300_PIN_REG(offset, pcr));
-	/* Mask out this pin, note 2 bits per setting */
-	val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK << ((offset & 0x07) << 1));
-	writel(val, U300_PIN_REG(offset, pcr));
-	local_irq_restore(flags);
-	return 0;
-}
-
-static int u300_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
-				      int value)
-{
-	struct u300_gpio *gpio = gpiochip_get_data(chip);
-	unsigned long flags;
-	u32 oldmode;
-	u32 val;
-
-	local_irq_save(flags);
-	val = readl(U300_PIN_REG(offset, pcr));
-	/*
-	 * Drive mode must be set by the special mode set function, set
-	 * push/pull mode by default if no mode has been selected.
-	 */
-	oldmode = val & (U300_GPIO_PXPCR_PIN_MODE_MASK <<
-			 ((offset & 0x07) << 1));
-	/* mode = 0 means input, else some mode is already set */
-	if (oldmode == 0) {
-		val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK <<
-			 ((offset & 0x07) << 1));
-		val |= (U300_GPIO_PXPCR_PIN_MODE_OUTPUT_PUSH_PULL
-			<< ((offset & 0x07) << 1));
-		writel(val, U300_PIN_REG(offset, pcr));
-	}
-	u300_gpio_set(chip, offset, value);
-	local_irq_restore(flags);
-	return 0;
-}
-
-/* Returning -EINVAL means "supported but not available" */
-int u300_gpio_config_get(struct gpio_chip *chip,
-			 unsigned offset,
-			 unsigned long *config)
-{
-	struct u300_gpio *gpio = gpiochip_get_data(chip);
-	enum pin_config_param param = (enum pin_config_param) *config;
-	bool biasmode;
-	u32 drmode;
-
-	/* One bit per pin, clamp to bool range */
-	biasmode = !!(readl(U300_PIN_REG(offset, per)) & U300_PIN_BIT(offset));
-
-	/* Mask out the two bits for this pin and shift to bits 0,1 */
-	drmode = readl(U300_PIN_REG(offset, pcr));
-	drmode &= (U300_GPIO_PXPCR_PIN_MODE_MASK << ((offset & 0x07) << 1));
-	drmode >>= ((offset & 0x07) << 1);
-
-	switch (param) {
-	case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
-		*config = 0;
-		if (biasmode)
-			return 0;
-		else
-			return -EINVAL;
-		break;
-	case PIN_CONFIG_BIAS_PULL_UP:
-		*config = 0;
-		if (!biasmode)
-			return 0;
-		else
-			return -EINVAL;
-		break;
-	case PIN_CONFIG_DRIVE_PUSH_PULL:
-		*config = 0;
-		if (drmode == U300_GPIO_PXPCR_PIN_MODE_OUTPUT_PUSH_PULL)
-			return 0;
-		else
-			return -EINVAL;
-		break;
-	case PIN_CONFIG_DRIVE_OPEN_DRAIN:
-		*config = 0;
-		if (drmode == U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_DRAIN)
-			return 0;
-		else
-			return -EINVAL;
-		break;
-	case PIN_CONFIG_DRIVE_OPEN_SOURCE:
-		*config = 0;
-		if (drmode == U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_SOURCE)
-			return 0;
-		else
-			return -EINVAL;
-		break;
-	default:
-		break;
-	}
-	return -ENOTSUPP;
-}
-
-int u300_gpio_config_set(struct gpio_chip *chip, unsigned offset,
-			 enum pin_config_param param)
-{
-	struct u300_gpio *gpio = gpiochip_get_data(chip);
-	unsigned long flags;
-	u32 val;
-
-	local_irq_save(flags);
-	switch (param) {
-	case PIN_CONFIG_BIAS_DISABLE:
-	case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
-		val = readl(U300_PIN_REG(offset, per));
-		writel(val | U300_PIN_BIT(offset), U300_PIN_REG(offset, per));
-		break;
-	case PIN_CONFIG_BIAS_PULL_UP:
-		val = readl(U300_PIN_REG(offset, per));
-		writel(val & ~U300_PIN_BIT(offset), U300_PIN_REG(offset, per));
-		break;
-	case PIN_CONFIG_DRIVE_PUSH_PULL:
-		val = readl(U300_PIN_REG(offset, pcr));
-		val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK
-			 << ((offset & 0x07) << 1));
-		val |= (U300_GPIO_PXPCR_PIN_MODE_OUTPUT_PUSH_PULL
-			<< ((offset & 0x07) << 1));
-		writel(val, U300_PIN_REG(offset, pcr));
-		break;
-	case PIN_CONFIG_DRIVE_OPEN_DRAIN:
-		val = readl(U300_PIN_REG(offset, pcr));
-		val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK
-			 << ((offset & 0x07) << 1));
-		val |= (U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_DRAIN
-			<< ((offset & 0x07) << 1));
-		writel(val, U300_PIN_REG(offset, pcr));
-		break;
-	case PIN_CONFIG_DRIVE_OPEN_SOURCE:
-		val = readl(U300_PIN_REG(offset, pcr));
-		val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK
-			 << ((offset & 0x07) << 1));
-		val |= (U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_SOURCE
-			<< ((offset & 0x07) << 1));
-		writel(val, U300_PIN_REG(offset, pcr));
-		break;
-	default:
-		local_irq_restore(flags);
-		dev_err(gpio->dev, "illegal configuration requested\n");
-		return -EINVAL;
-	}
-	local_irq_restore(flags);
-	return 0;
-}
-
-static const struct gpio_chip u300_gpio_chip = {
-	.label			= "u300-gpio-chip",
-	.owner			= THIS_MODULE,
-	.request		= gpiochip_generic_request,
-	.free			= gpiochip_generic_free,
-	.get			= u300_gpio_get,
-	.set			= u300_gpio_set,
-	.direction_input	= u300_gpio_direction_input,
-	.direction_output	= u300_gpio_direction_output,
-};
-
-static void u300_toggle_trigger(struct u300_gpio *gpio, unsigned offset)
-{
-	u32 val;
-
-	val = readl(U300_PIN_REG(offset, icr));
-	/* Set mode depending on state */
-	if (u300_gpio_get(&gpio->chip, offset)) {
-		/* High now, let's trigger on falling edge next then */
-		writel(val & ~U300_PIN_BIT(offset), U300_PIN_REG(offset, icr));
-		dev_dbg(gpio->dev, "next IRQ on falling edge on pin %d\n",
-			offset);
-	} else {
-		/* Low now, let's trigger on rising edge next then */
-		writel(val | U300_PIN_BIT(offset), U300_PIN_REG(offset, icr));
-		dev_dbg(gpio->dev, "next IRQ on rising edge on pin %d\n",
-			offset);
-	}
-}
-
-static int u300_gpio_irq_type(struct irq_data *d, unsigned trigger)
-{
-	struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
-	struct u300_gpio *gpio = gpiochip_get_data(chip);
-	struct u300_gpio_port *port = &gpio->ports[d->hwirq >> 3];
-	int offset = d->hwirq;
-	u32 val;
-
-	if ((trigger & IRQF_TRIGGER_RISING) &&
-	    (trigger & IRQF_TRIGGER_FALLING)) {
-		/*
-		 * The GPIO block can only trigger on falling OR rising edges,
-		 * not both. So we need to toggle the mode whenever the pin
-		 * goes from one state to the other with a special state flag
-		 */
-		dev_dbg(gpio->dev,
-			"trigger on both rising and falling edge on pin %d\n",
-			offset);
-		port->toggle_edge_mode |= U300_PIN_BIT(offset);
-		u300_toggle_trigger(gpio, offset);
-	} else if (trigger & IRQF_TRIGGER_RISING) {
-		dev_dbg(gpio->dev, "trigger on rising edge on pin %d\n",
-			offset);
-		val = readl(U300_PIN_REG(offset, icr));
-		writel(val | U300_PIN_BIT(offset), U300_PIN_REG(offset, icr));
-		port->toggle_edge_mode &= ~U300_PIN_BIT(offset);
-	} else if (trigger & IRQF_TRIGGER_FALLING) {
-		dev_dbg(gpio->dev, "trigger on falling edge on pin %d\n",
-			offset);
-		val = readl(U300_PIN_REG(offset, icr));
-		writel(val & ~U300_PIN_BIT(offset), U300_PIN_REG(offset, icr));
-		port->toggle_edge_mode &= ~U300_PIN_BIT(offset);
-	}
-
-	return 0;
-}
-
-static void u300_gpio_irq_enable(struct irq_data *d)
-{
-	struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
-	struct u300_gpio *gpio = gpiochip_get_data(chip);
-	struct u300_gpio_port *port = &gpio->ports[d->hwirq >> 3];
-	int offset = d->hwirq;
-	u32 val;
-	unsigned long flags;
-
-	dev_dbg(gpio->dev, "enable IRQ for hwirq %lu on port %s, offset %d\n",
-		 d->hwirq, port->name, offset);
-	local_irq_save(flags);
-	val = readl(U300_PIN_REG(offset, ien));
-	writel(val | U300_PIN_BIT(offset), U300_PIN_REG(offset, ien));
-	local_irq_restore(flags);
-}
-
-static void u300_gpio_irq_disable(struct irq_data *d)
-{
-	struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
-	struct u300_gpio *gpio = gpiochip_get_data(chip);
-	int offset = d->hwirq;
-	u32 val;
-	unsigned long flags;
-
-	local_irq_save(flags);
-	val = readl(U300_PIN_REG(offset, ien));
-	writel(val & ~U300_PIN_BIT(offset), U300_PIN_REG(offset, ien));
-	local_irq_restore(flags);
-}
-
-static struct irq_chip u300_gpio_irqchip = {
-	.name			= "u300-gpio-irqchip",
-	.irq_enable		= u300_gpio_irq_enable,
-	.irq_disable		= u300_gpio_irq_disable,
-	.irq_set_type		= u300_gpio_irq_type,
-};
-
-static void u300_gpio_irq_handler(struct irq_desc *desc)
-{
-	unsigned int irq = irq_desc_get_irq(desc);
-	struct irq_chip *parent_chip = irq_desc_get_chip(desc);
-	struct gpio_chip *chip = irq_desc_get_handler_data(desc);
-	struct u300_gpio *gpio = gpiochip_get_data(chip);
-	struct u300_gpio_port *port = &gpio->ports[irq - chip->base];
-	int pinoffset = port->number << 3; /* get the right stride */
-	unsigned long val;
-
-	chained_irq_enter(parent_chip, desc);
-
-	/* Read event register */
-	val = readl(U300_PIN_REG(pinoffset, iev));
-	/* Mask relevant bits */
-	val &= 0xFFU; /* 8 bits per port */
-	/* ACK IRQ (clear event) */
-	writel(val, U300_PIN_REG(pinoffset, iev));
-
-	/* Call IRQ handler */
-	if (val != 0) {
-		int irqoffset;
-
-		for_each_set_bit(irqoffset, &val, U300_GPIO_PINS_PER_PORT) {
-			int offset = pinoffset + irqoffset;
-			int pin_irq = irq_find_mapping(chip->irq.domain, offset);
-
-			dev_dbg(gpio->dev, "GPIO IRQ %d on pin %d\n",
-				pin_irq, offset);
-			generic_handle_irq(pin_irq);
-			/*
-			 * Triggering IRQ on both rising and falling edge
-			 * needs mockery
-			 */
-			if (port->toggle_edge_mode & U300_PIN_BIT(offset))
-				u300_toggle_trigger(gpio, offset);
-		}
-	}
-
-	chained_irq_exit(parent_chip, desc);
-}
-
-static void __init u300_gpio_init_pin(struct u300_gpio *gpio,
-				      int offset,
-				      const struct u300_gpio_confdata *conf)
-{
-	/* Set mode: input or output */
-	if (conf->output) {
-		u300_gpio_direction_output(&gpio->chip, offset, conf->outval);
-
-		/* Deactivate bias mode for output */
-		u300_gpio_config_set(&gpio->chip, offset,
-				     PIN_CONFIG_BIAS_HIGH_IMPEDANCE);
-
-		/* Set drive mode for output */
-		u300_gpio_config_set(&gpio->chip, offset,
-				     PIN_CONFIG_DRIVE_PUSH_PULL);
-
-		dev_dbg(gpio->dev, "set up pin %d as output, value: %d\n",
-			offset, conf->outval);
-	} else {
-		u300_gpio_direction_input(&gpio->chip, offset);
-
-		/* Always set output low on input pins */
-		u300_gpio_set(&gpio->chip, offset, 0);
-
-		/* Set bias mode for input */
-		u300_gpio_config_set(&gpio->chip, offset, conf->bias_mode);
-
-		dev_dbg(gpio->dev, "set up pin %d as input, bias: %04x\n",
-			offset, conf->bias_mode);
-	}
-}
-
-static void __init u300_gpio_init_coh901571(struct u300_gpio *gpio)
-{
-	int i, j;
-
-	/* Write default config and values to all pins */
-	for (i = 0; i < U300_GPIO_NUM_PORTS; i++) {
-		for (j = 0; j < 8; j++) {
-			const struct u300_gpio_confdata *conf;
-			int offset = (i*8) + j;
-
-			conf = &bs335_gpio_config[i][j];
-			u300_gpio_init_pin(gpio, offset, conf);
-		}
-	}
-}
-
-/*
- * Here we map a GPIO in the local gpio_chip pin space to a pin in
- * the local pinctrl pin space. The pin controller used is
- * pinctrl-u300.
- */
-struct coh901_pinpair {
-	unsigned int offset;
-	unsigned int pin_base;
-};
-
-#define COH901_PINRANGE(a, b) { .offset = a, .pin_base = b }
-
-static struct coh901_pinpair coh901_pintable[] = {
-	COH901_PINRANGE(10, 426),
-	COH901_PINRANGE(11, 180),
-	COH901_PINRANGE(12, 165), /* MS/MMC card insertion */
-	COH901_PINRANGE(13, 179),
-	COH901_PINRANGE(14, 178),
-	COH901_PINRANGE(16, 194),
-	COH901_PINRANGE(17, 193),
-	COH901_PINRANGE(18, 192),
-	COH901_PINRANGE(19, 191),
-	COH901_PINRANGE(20, 186),
-	COH901_PINRANGE(21, 185),
-	COH901_PINRANGE(22, 184),
-	COH901_PINRANGE(23, 183),
-	COH901_PINRANGE(24, 182),
-	COH901_PINRANGE(25, 181),
-};
-
-static int __init u300_gpio_probe(struct platform_device *pdev)
-{
-	struct u300_gpio *gpio;
-	struct gpio_irq_chip *girq;
-	int err = 0;
-	int portno;
-	u32 val;
-	u32 ifr;
-	int i;
-
-	gpio = devm_kzalloc(&pdev->dev, sizeof(struct u300_gpio), GFP_KERNEL);
-	if (gpio == NULL)
-		return -ENOMEM;
-
-	gpio->chip = u300_gpio_chip;
-	gpio->chip.ngpio = U300_GPIO_NUM_PORTS * U300_GPIO_PINS_PER_PORT;
-	gpio->chip.parent = &pdev->dev;
-	gpio->chip.base = 0;
-	gpio->dev = &pdev->dev;
-
-	gpio->base = devm_platform_ioremap_resource(pdev, 0);
-	if (IS_ERR(gpio->base))
-		return PTR_ERR(gpio->base);
-
-	gpio->clk = devm_clk_get(gpio->dev, NULL);
-	if (IS_ERR(gpio->clk)) {
-		err = PTR_ERR(gpio->clk);
-		dev_err(gpio->dev, "could not get GPIO clock\n");
-		return err;
-	}
-
-	err = clk_prepare_enable(gpio->clk);
-	if (err) {
-		dev_err(gpio->dev, "could not enable GPIO clock\n");
-		return err;
-	}
-
-	dev_info(gpio->dev,
-		 "initializing GPIO Controller COH 901 571/3\n");
-	gpio->stride = U300_GPIO_PORT_STRIDE;
-	gpio->pcr = U300_GPIO_PXPCR;
-	gpio->dor = U300_GPIO_PXPDOR;
-	gpio->dir = U300_GPIO_PXPDIR;
-	gpio->per = U300_GPIO_PXPER;
-	gpio->icr = U300_GPIO_PXICR;
-	gpio->ien = U300_GPIO_PXIEN;
-	gpio->iev = U300_GPIO_PXIEV;
-	ifr = U300_GPIO_PXIFR;
-
-	val = readl(gpio->base + U300_GPIO_CR);
-	dev_info(gpio->dev, "COH901571/3 block version: %d, " \
-		 "number of cores: %d totalling %d pins\n",
-		 ((val & 0x000001FC) >> 2),
-		 ((val & 0x0000FE00) >> 9),
-		 ((val & 0x0000FE00) >> 9) * 8);
-	writel(U300_GPIO_CR_BLOCK_CLKRQ_ENABLE,
-	       gpio->base + U300_GPIO_CR);
-	u300_gpio_init_coh901571(gpio);
-
-	girq = &gpio->chip.irq;
-	girq->chip = &u300_gpio_irqchip;
-	girq->parent_handler = u300_gpio_irq_handler;
-	girq->num_parents = U300_GPIO_NUM_PORTS;
-	girq->parents = devm_kcalloc(gpio->dev, U300_GPIO_NUM_PORTS,
-				     sizeof(*girq->parents),
-				     GFP_KERNEL);
-	if (!girq->parents) {
-		err = -ENOMEM;
-		goto err_dis_clk;
-	}
-	for (portno = 0 ; portno < U300_GPIO_NUM_PORTS; portno++) {
-		struct u300_gpio_port *port = &gpio->ports[portno];
-
-		snprintf(port->name, 8, "gpio%d", portno);
-		port->number = portno;
-		port->gpio = gpio;
-
-		port->irq = platform_get_irq(pdev, portno);
-		girq->parents[portno] = port->irq;
-
-		/* Turns off irq force (test register) for this port */
-		writel(0x0, gpio->base + portno * gpio->stride + ifr);
-	}
-	girq->default_type = IRQ_TYPE_EDGE_FALLING;
-	girq->handler = handle_simple_irq;
-#ifdef CONFIG_OF_GPIO
-	gpio->chip.of_node = pdev->dev.of_node;
-#endif
-	err = gpiochip_add_data(&gpio->chip, gpio);
-	if (err) {
-		dev_err(gpio->dev, "unable to add gpiochip: %d\n", err);
-		goto err_dis_clk;
-	}
-
-	/*
-	 * Add pinctrl pin ranges, the pin controller must be registered
-	 * at this point
-	 */
-	for (i = 0; i < ARRAY_SIZE(coh901_pintable); i++) {
-		struct coh901_pinpair *p = &coh901_pintable[i];
-
-		err = gpiochip_add_pin_range(&gpio->chip, "pinctrl-u300",
-					     p->offset, p->pin_base, 1);
-		if (err)
-			goto err_no_range;
-	}
-
-	platform_set_drvdata(pdev, gpio);
-
-	return 0;
-
-err_no_range:
-	gpiochip_remove(&gpio->chip);
-err_dis_clk:
-	clk_disable_unprepare(gpio->clk);
-	dev_err(&pdev->dev, "module ERROR:%d\n", err);
-	return err;
-}
-
-static int __exit u300_gpio_remove(struct platform_device *pdev)
-{
-	struct u300_gpio *gpio = platform_get_drvdata(pdev);
-
-	/* Turn off the GPIO block */
-	writel(0x00000000U, gpio->base + U300_GPIO_CR);
-
-	gpiochip_remove(&gpio->chip);
-	clk_disable_unprepare(gpio->clk);
-	return 0;
-}
-
-static const struct of_device_id u300_gpio_match[] = {
-	{ .compatible = "stericsson,gpio-coh901" },
-	{},
-};
-
-static struct platform_driver u300_gpio_driver = {
-	.driver		= {
-		.name	= "u300-gpio",
-		.of_match_table = u300_gpio_match,
-	},
-	.remove		= __exit_p(u300_gpio_remove),
-};
-
-static int __init u300_gpio_init(void)
-{
-	return platform_driver_probe(&u300_gpio_driver, u300_gpio_probe);
-}
-
-static void __exit u300_gpio_exit(void)
-{
-	platform_driver_unregister(&u300_gpio_driver);
-}
-
-arch_initcall(u300_gpio_init);
-module_exit(u300_gpio_exit);
-
-MODULE_AUTHOR("Linus Walleij <linus.walleij@stericsson.com>");
-MODULE_DESCRIPTION("ST-Ericsson AB COH 901 335/COH 901 571/3 GPIO driver");
-MODULE_LICENSE("GPL");
diff --git a/drivers/pinctrl/pinctrl-coh901.h b/drivers/pinctrl/pinctrl-coh901.h
deleted file mode 100644
index ba2678665168..000000000000
--- a/drivers/pinctrl/pinctrl-coh901.h
+++ /dev/null
@@ -1,6 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-int u300_gpio_config_get(struct gpio_chip *chip,
-			 unsigned offset,
-			 unsigned long *config);
-int u300_gpio_config_set(struct gpio_chip *chip, unsigned offset,
-			 enum pin_config_param param);
-- 
2.29.2


^ permalink raw reply related	[flat|nested] 22+ messages in thread

* [PATCH 4/5] pinctrl: remove coh901 driver
@ 2021-01-20 13:20   ` Arnd Bergmann
  0 siblings, 0 replies; 22+ messages in thread
From: Arnd Bergmann @ 2021-01-20 13:20 UTC (permalink / raw)
  To: linux-arm-kernel, linux-kernel, linux-gpio, Linus Walleij
  Cc: Bartosz Golaszewski, Arnd Bergmann

From: Arnd Bergmann <arnd@arndb.de>

The ST-Ericsson U300 platform is getting removed, so this driver is no
longer needed.

Cc: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
---
 .../bindings/gpio/gpio-stericsson-coh901.txt  |   7 -
 drivers/pinctrl/Kconfig                       |  10 -
 drivers/pinctrl/Makefile                      |   1 -
 drivers/pinctrl/pinctrl-coh901.c              | 774 ------------------
 drivers/pinctrl/pinctrl-coh901.h              |   6 -
 5 files changed, 798 deletions(-)
 delete mode 100644 Documentation/devicetree/bindings/gpio/gpio-stericsson-coh901.txt
 delete mode 100644 drivers/pinctrl/pinctrl-coh901.c
 delete mode 100644 drivers/pinctrl/pinctrl-coh901.h

diff --git a/Documentation/devicetree/bindings/gpio/gpio-stericsson-coh901.txt b/Documentation/devicetree/bindings/gpio/gpio-stericsson-coh901.txt
deleted file mode 100644
index fd665b44d767..000000000000
--- a/Documentation/devicetree/bindings/gpio/gpio-stericsson-coh901.txt
+++ /dev/null
@@ -1,7 +0,0 @@
-ST-Ericsson COH 901 571/3 GPIO controller
-
-Required properties:
-- compatible: Compatible property value should be "stericsson,gpio-coh901"
-- reg: Physical base address of the controller and length of memory mapped
-  region.
-- interrupts: the 0...n interrupts assigned to the different GPIO ports/banks.
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index e176137dbf29..9ddbf14d9536 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -277,16 +277,6 @@ config PINCTRL_U300
 	select PINMUX
 	select GENERIC_PINCONF
 
-config PINCTRL_COH901
-	bool "ST-Ericsson U300 COH 901 335/571 GPIO"
-	depends on GPIOLIB && ARCH_U300 && PINCTRL_U300
-	select GPIOLIB_IRQCHIP
-	help
-	  Say yes here to support GPIO interface on ST-Ericsson U300.
-	  The names of the two IP block variants supported are
-	  COH 901 335 and COH 901 571/3. They contain 3, 5 or 7
-	  ports of 8 GPIO pins each.
-
 config PINCTRL_MAX77620
 	tristate "MAX77620/MAX20024 Pincontrol support"
 	depends on MFD_MAX77620 && OF
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index f414846abe2d..10643440b467 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -34,7 +34,6 @@ obj-$(CONFIG_PINCTRL_SINGLE)	+= pinctrl-single.o
 obj-$(CONFIG_PINCTRL_SX150X)	+= pinctrl-sx150x.o
 obj-$(CONFIG_ARCH_TEGRA)	+= tegra/
 obj-$(CONFIG_PINCTRL_U300)	+= pinctrl-u300.o
-obj-$(CONFIG_PINCTRL_COH901)	+= pinctrl-coh901.o
 obj-$(CONFIG_PINCTRL_XWAY)	+= pinctrl-xway.o
 obj-$(CONFIG_PINCTRL_LANTIQ)	+= pinctrl-lantiq.o
 obj-$(CONFIG_PINCTRL_LPC18XX)	+= pinctrl-lpc18xx.o
diff --git a/drivers/pinctrl/pinctrl-coh901.c b/drivers/pinctrl/pinctrl-coh901.c
deleted file mode 100644
index 2905348ff430..000000000000
--- a/drivers/pinctrl/pinctrl-coh901.c
+++ /dev/null
@@ -1,774 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * U300 GPIO module.
- *
- * Copyright (C) 2007-2012 ST-Ericsson AB
- * COH 901 571/3 - Used in DB3210 (U365 2.0) and DB3350 (U335 1.0)
- * Author: Linus Walleij <linus.walleij@linaro.org>
- * Author: Jonas Aaberg <jonas.aberg@stericsson.com>
- */
-#include <linux/module.h>
-#include <linux/interrupt.h>
-#include <linux/delay.h>
-#include <linux/errno.h>
-#include <linux/io.h>
-#include <linux/clk.h>
-#include <linux/err.h>
-#include <linux/platform_device.h>
-#include <linux/gpio/driver.h>
-#include <linux/slab.h>
-#include <linux/pinctrl/consumer.h>
-#include <linux/pinctrl/pinconf-generic.h>
-#include "pinctrl-coh901.h"
-
-#define U300_GPIO_PORT_STRIDE				(0x30)
-/*
- * Control Register 32bit (R/W)
- * bit 15-9 (mask 0x0000FE00) contains the number of cores. 8*cores
- * gives the number of GPIO pins.
- * bit 8-2  (mask 0x000001FC) contains the core version ID.
- */
-#define U300_GPIO_CR					(0x00)
-#define U300_GPIO_CR_SYNC_SEL_ENABLE			(0x00000002UL)
-#define U300_GPIO_CR_BLOCK_CLKRQ_ENABLE			(0x00000001UL)
-#define U300_GPIO_PXPDIR				(0x04)
-#define U300_GPIO_PXPDOR				(0x08)
-#define U300_GPIO_PXPCR					(0x0C)
-#define U300_GPIO_PXPCR_ALL_PINS_MODE_MASK		(0x0000FFFFUL)
-#define U300_GPIO_PXPCR_PIN_MODE_MASK			(0x00000003UL)
-#define U300_GPIO_PXPCR_PIN_MODE_SHIFT			(0x00000002UL)
-#define U300_GPIO_PXPCR_PIN_MODE_INPUT			(0x00000000UL)
-#define U300_GPIO_PXPCR_PIN_MODE_OUTPUT_PUSH_PULL	(0x00000001UL)
-#define U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_DRAIN	(0x00000002UL)
-#define U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_SOURCE	(0x00000003UL)
-#define U300_GPIO_PXPER					(0x10)
-#define U300_GPIO_PXPER_ALL_PULL_UP_DISABLE_MASK	(0x000000FFUL)
-#define U300_GPIO_PXPER_PULL_UP_DISABLE			(0x00000001UL)
-#define U300_GPIO_PXIEV					(0x14)
-#define U300_GPIO_PXIEN					(0x18)
-#define U300_GPIO_PXIFR					(0x1C)
-#define U300_GPIO_PXICR					(0x20)
-#define U300_GPIO_PXICR_ALL_IRQ_CONFIG_MASK		(0x000000FFUL)
-#define U300_GPIO_PXICR_IRQ_CONFIG_MASK			(0x00000001UL)
-#define U300_GPIO_PXICR_IRQ_CONFIG_FALLING_EDGE		(0x00000000UL)
-#define U300_GPIO_PXICR_IRQ_CONFIG_RISING_EDGE		(0x00000001UL)
-
-/* 8 bits per port, no version has more than 7 ports */
-#define U300_GPIO_NUM_PORTS 7
-#define U300_GPIO_PINS_PER_PORT 8
-#define U300_GPIO_MAX (U300_GPIO_PINS_PER_PORT * U300_GPIO_NUM_PORTS)
-
-struct u300_gpio_port {
-	struct u300_gpio *gpio;
-	char name[8];
-	int irq;
-	int number;
-	u8 toggle_edge_mode;
-};
-
-struct u300_gpio {
-	struct gpio_chip chip;
-	struct u300_gpio_port ports[U300_GPIO_NUM_PORTS];
-	struct clk *clk;
-	void __iomem *base;
-	struct device *dev;
-	u32 stride;
-	/* Register offsets */
-	u32 pcr;
-	u32 dor;
-	u32 dir;
-	u32 per;
-	u32 icr;
-	u32 ien;
-	u32 iev;
-};
-
-/*
- * Macro to expand to read a specific register found in the "gpio"
- * struct. It requires the struct u300_gpio *gpio variable to exist in
- * its context. It calculates the port offset from the given pin
- * offset, muliplies by the port stride and adds the register offset
- * so it provides a pointer to the desired register.
- */
-#define U300_PIN_REG(pin, reg) \
-	(gpio->base + (pin >> 3) * gpio->stride + gpio->reg)
-
-/*
- * Provides a bitmask for a specific gpio pin inside an 8-bit GPIO
- * register.
- */
-#define U300_PIN_BIT(pin) \
-	(1 << (pin & 0x07))
-
-struct u300_gpio_confdata {
-	u16 bias_mode;
-	bool output;
-	int outval;
-};
-
-#define U300_FLOATING_INPUT { \
-	.bias_mode = PIN_CONFIG_BIAS_HIGH_IMPEDANCE, \
-	.output = false, \
-}
-
-#define U300_PULL_UP_INPUT { \
-	.bias_mode = PIN_CONFIG_BIAS_PULL_UP, \
-	.output = false, \
-}
-
-#define U300_OUTPUT_LOW { \
-	.output = true, \
-	.outval = 0, \
-}
-
-#define U300_OUTPUT_HIGH { \
-	.output = true, \
-	.outval = 1, \
-}
-
-/* Initial configuration */
-static const struct u300_gpio_confdata __initconst
-bs335_gpio_config[U300_GPIO_NUM_PORTS][U300_GPIO_PINS_PER_PORT] = {
-	/* Port 0, pins 0-7 */
-	{
-		U300_FLOATING_INPUT,
-		U300_OUTPUT_HIGH,
-		U300_FLOATING_INPUT,
-		U300_OUTPUT_LOW,
-		U300_OUTPUT_LOW,
-		U300_OUTPUT_LOW,
-		U300_OUTPUT_LOW,
-		U300_OUTPUT_LOW,
-	},
-	/* Port 1, pins 0-7 */
-	{
-		U300_OUTPUT_LOW,
-		U300_OUTPUT_LOW,
-		U300_OUTPUT_LOW,
-		U300_PULL_UP_INPUT,
-		U300_FLOATING_INPUT,
-		U300_OUTPUT_HIGH,
-		U300_OUTPUT_LOW,
-		U300_OUTPUT_LOW,
-	},
-	/* Port 2, pins 0-7 */
-	{
-		U300_FLOATING_INPUT,
-		U300_FLOATING_INPUT,
-		U300_FLOATING_INPUT,
-		U300_FLOATING_INPUT,
-		U300_OUTPUT_LOW,
-		U300_PULL_UP_INPUT,
-		U300_OUTPUT_LOW,
-		U300_PULL_UP_INPUT,
-	},
-	/* Port 3, pins 0-7 */
-	{
-		U300_PULL_UP_INPUT,
-		U300_OUTPUT_LOW,
-		U300_FLOATING_INPUT,
-		U300_FLOATING_INPUT,
-		U300_FLOATING_INPUT,
-		U300_FLOATING_INPUT,
-		U300_FLOATING_INPUT,
-		U300_FLOATING_INPUT,
-	},
-	/* Port 4, pins 0-7 */
-	{
-		U300_FLOATING_INPUT,
-		U300_FLOATING_INPUT,
-		U300_FLOATING_INPUT,
-		U300_FLOATING_INPUT,
-		U300_FLOATING_INPUT,
-		U300_FLOATING_INPUT,
-		U300_FLOATING_INPUT,
-		U300_FLOATING_INPUT,
-	},
-	/* Port 5, pins 0-7 */
-	{
-		U300_FLOATING_INPUT,
-		U300_FLOATING_INPUT,
-		U300_FLOATING_INPUT,
-		U300_FLOATING_INPUT,
-		U300_FLOATING_INPUT,
-		U300_FLOATING_INPUT,
-		U300_FLOATING_INPUT,
-		U300_FLOATING_INPUT,
-	},
-	/* Port 6, pind 0-7 */
-	{
-		U300_FLOATING_INPUT,
-		U300_FLOATING_INPUT,
-		U300_FLOATING_INPUT,
-		U300_FLOATING_INPUT,
-		U300_FLOATING_INPUT,
-		U300_FLOATING_INPUT,
-		U300_FLOATING_INPUT,
-		U300_FLOATING_INPUT,
-	}
-};
-
-static int u300_gpio_get(struct gpio_chip *chip, unsigned offset)
-{
-	struct u300_gpio *gpio = gpiochip_get_data(chip);
-
-	return !!(readl(U300_PIN_REG(offset, dir)) & U300_PIN_BIT(offset));
-}
-
-static void u300_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
-{
-	struct u300_gpio *gpio = gpiochip_get_data(chip);
-	unsigned long flags;
-	u32 val;
-
-	local_irq_save(flags);
-
-	val = readl(U300_PIN_REG(offset, dor));
-	if (value)
-		writel(val | U300_PIN_BIT(offset), U300_PIN_REG(offset, dor));
-	else
-		writel(val & ~U300_PIN_BIT(offset), U300_PIN_REG(offset, dor));
-
-	local_irq_restore(flags);
-}
-
-static int u300_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
-{
-	struct u300_gpio *gpio = gpiochip_get_data(chip);
-	unsigned long flags;
-	u32 val;
-
-	local_irq_save(flags);
-	val = readl(U300_PIN_REG(offset, pcr));
-	/* Mask out this pin, note 2 bits per setting */
-	val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK << ((offset & 0x07) << 1));
-	writel(val, U300_PIN_REG(offset, pcr));
-	local_irq_restore(flags);
-	return 0;
-}
-
-static int u300_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
-				      int value)
-{
-	struct u300_gpio *gpio = gpiochip_get_data(chip);
-	unsigned long flags;
-	u32 oldmode;
-	u32 val;
-
-	local_irq_save(flags);
-	val = readl(U300_PIN_REG(offset, pcr));
-	/*
-	 * Drive mode must be set by the special mode set function, set
-	 * push/pull mode by default if no mode has been selected.
-	 */
-	oldmode = val & (U300_GPIO_PXPCR_PIN_MODE_MASK <<
-			 ((offset & 0x07) << 1));
-	/* mode = 0 means input, else some mode is already set */
-	if (oldmode == 0) {
-		val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK <<
-			 ((offset & 0x07) << 1));
-		val |= (U300_GPIO_PXPCR_PIN_MODE_OUTPUT_PUSH_PULL
-			<< ((offset & 0x07) << 1));
-		writel(val, U300_PIN_REG(offset, pcr));
-	}
-	u300_gpio_set(chip, offset, value);
-	local_irq_restore(flags);
-	return 0;
-}
-
-/* Returning -EINVAL means "supported but not available" */
-int u300_gpio_config_get(struct gpio_chip *chip,
-			 unsigned offset,
-			 unsigned long *config)
-{
-	struct u300_gpio *gpio = gpiochip_get_data(chip);
-	enum pin_config_param param = (enum pin_config_param) *config;
-	bool biasmode;
-	u32 drmode;
-
-	/* One bit per pin, clamp to bool range */
-	biasmode = !!(readl(U300_PIN_REG(offset, per)) & U300_PIN_BIT(offset));
-
-	/* Mask out the two bits for this pin and shift to bits 0,1 */
-	drmode = readl(U300_PIN_REG(offset, pcr));
-	drmode &= (U300_GPIO_PXPCR_PIN_MODE_MASK << ((offset & 0x07) << 1));
-	drmode >>= ((offset & 0x07) << 1);
-
-	switch (param) {
-	case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
-		*config = 0;
-		if (biasmode)
-			return 0;
-		else
-			return -EINVAL;
-		break;
-	case PIN_CONFIG_BIAS_PULL_UP:
-		*config = 0;
-		if (!biasmode)
-			return 0;
-		else
-			return -EINVAL;
-		break;
-	case PIN_CONFIG_DRIVE_PUSH_PULL:
-		*config = 0;
-		if (drmode == U300_GPIO_PXPCR_PIN_MODE_OUTPUT_PUSH_PULL)
-			return 0;
-		else
-			return -EINVAL;
-		break;
-	case PIN_CONFIG_DRIVE_OPEN_DRAIN:
-		*config = 0;
-		if (drmode == U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_DRAIN)
-			return 0;
-		else
-			return -EINVAL;
-		break;
-	case PIN_CONFIG_DRIVE_OPEN_SOURCE:
-		*config = 0;
-		if (drmode == U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_SOURCE)
-			return 0;
-		else
-			return -EINVAL;
-		break;
-	default:
-		break;
-	}
-	return -ENOTSUPP;
-}
-
-int u300_gpio_config_set(struct gpio_chip *chip, unsigned offset,
-			 enum pin_config_param param)
-{
-	struct u300_gpio *gpio = gpiochip_get_data(chip);
-	unsigned long flags;
-	u32 val;
-
-	local_irq_save(flags);
-	switch (param) {
-	case PIN_CONFIG_BIAS_DISABLE:
-	case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
-		val = readl(U300_PIN_REG(offset, per));
-		writel(val | U300_PIN_BIT(offset), U300_PIN_REG(offset, per));
-		break;
-	case PIN_CONFIG_BIAS_PULL_UP:
-		val = readl(U300_PIN_REG(offset, per));
-		writel(val & ~U300_PIN_BIT(offset), U300_PIN_REG(offset, per));
-		break;
-	case PIN_CONFIG_DRIVE_PUSH_PULL:
-		val = readl(U300_PIN_REG(offset, pcr));
-		val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK
-			 << ((offset & 0x07) << 1));
-		val |= (U300_GPIO_PXPCR_PIN_MODE_OUTPUT_PUSH_PULL
-			<< ((offset & 0x07) << 1));
-		writel(val, U300_PIN_REG(offset, pcr));
-		break;
-	case PIN_CONFIG_DRIVE_OPEN_DRAIN:
-		val = readl(U300_PIN_REG(offset, pcr));
-		val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK
-			 << ((offset & 0x07) << 1));
-		val |= (U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_DRAIN
-			<< ((offset & 0x07) << 1));
-		writel(val, U300_PIN_REG(offset, pcr));
-		break;
-	case PIN_CONFIG_DRIVE_OPEN_SOURCE:
-		val = readl(U300_PIN_REG(offset, pcr));
-		val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK
-			 << ((offset & 0x07) << 1));
-		val |= (U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_SOURCE
-			<< ((offset & 0x07) << 1));
-		writel(val, U300_PIN_REG(offset, pcr));
-		break;
-	default:
-		local_irq_restore(flags);
-		dev_err(gpio->dev, "illegal configuration requested\n");
-		return -EINVAL;
-	}
-	local_irq_restore(flags);
-	return 0;
-}
-
-static const struct gpio_chip u300_gpio_chip = {
-	.label			= "u300-gpio-chip",
-	.owner			= THIS_MODULE,
-	.request		= gpiochip_generic_request,
-	.free			= gpiochip_generic_free,
-	.get			= u300_gpio_get,
-	.set			= u300_gpio_set,
-	.direction_input	= u300_gpio_direction_input,
-	.direction_output	= u300_gpio_direction_output,
-};
-
-static void u300_toggle_trigger(struct u300_gpio *gpio, unsigned offset)
-{
-	u32 val;
-
-	val = readl(U300_PIN_REG(offset, icr));
-	/* Set mode depending on state */
-	if (u300_gpio_get(&gpio->chip, offset)) {
-		/* High now, let's trigger on falling edge next then */
-		writel(val & ~U300_PIN_BIT(offset), U300_PIN_REG(offset, icr));
-		dev_dbg(gpio->dev, "next IRQ on falling edge on pin %d\n",
-			offset);
-	} else {
-		/* Low now, let's trigger on rising edge next then */
-		writel(val | U300_PIN_BIT(offset), U300_PIN_REG(offset, icr));
-		dev_dbg(gpio->dev, "next IRQ on rising edge on pin %d\n",
-			offset);
-	}
-}
-
-static int u300_gpio_irq_type(struct irq_data *d, unsigned trigger)
-{
-	struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
-	struct u300_gpio *gpio = gpiochip_get_data(chip);
-	struct u300_gpio_port *port = &gpio->ports[d->hwirq >> 3];
-	int offset = d->hwirq;
-	u32 val;
-
-	if ((trigger & IRQF_TRIGGER_RISING) &&
-	    (trigger & IRQF_TRIGGER_FALLING)) {
-		/*
-		 * The GPIO block can only trigger on falling OR rising edges,
-		 * not both. So we need to toggle the mode whenever the pin
-		 * goes from one state to the other with a special state flag
-		 */
-		dev_dbg(gpio->dev,
-			"trigger on both rising and falling edge on pin %d\n",
-			offset);
-		port->toggle_edge_mode |= U300_PIN_BIT(offset);
-		u300_toggle_trigger(gpio, offset);
-	} else if (trigger & IRQF_TRIGGER_RISING) {
-		dev_dbg(gpio->dev, "trigger on rising edge on pin %d\n",
-			offset);
-		val = readl(U300_PIN_REG(offset, icr));
-		writel(val | U300_PIN_BIT(offset), U300_PIN_REG(offset, icr));
-		port->toggle_edge_mode &= ~U300_PIN_BIT(offset);
-	} else if (trigger & IRQF_TRIGGER_FALLING) {
-		dev_dbg(gpio->dev, "trigger on falling edge on pin %d\n",
-			offset);
-		val = readl(U300_PIN_REG(offset, icr));
-		writel(val & ~U300_PIN_BIT(offset), U300_PIN_REG(offset, icr));
-		port->toggle_edge_mode &= ~U300_PIN_BIT(offset);
-	}
-
-	return 0;
-}
-
-static void u300_gpio_irq_enable(struct irq_data *d)
-{
-	struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
-	struct u300_gpio *gpio = gpiochip_get_data(chip);
-	struct u300_gpio_port *port = &gpio->ports[d->hwirq >> 3];
-	int offset = d->hwirq;
-	u32 val;
-	unsigned long flags;
-
-	dev_dbg(gpio->dev, "enable IRQ for hwirq %lu on port %s, offset %d\n",
-		 d->hwirq, port->name, offset);
-	local_irq_save(flags);
-	val = readl(U300_PIN_REG(offset, ien));
-	writel(val | U300_PIN_BIT(offset), U300_PIN_REG(offset, ien));
-	local_irq_restore(flags);
-}
-
-static void u300_gpio_irq_disable(struct irq_data *d)
-{
-	struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
-	struct u300_gpio *gpio = gpiochip_get_data(chip);
-	int offset = d->hwirq;
-	u32 val;
-	unsigned long flags;
-
-	local_irq_save(flags);
-	val = readl(U300_PIN_REG(offset, ien));
-	writel(val & ~U300_PIN_BIT(offset), U300_PIN_REG(offset, ien));
-	local_irq_restore(flags);
-}
-
-static struct irq_chip u300_gpio_irqchip = {
-	.name			= "u300-gpio-irqchip",
-	.irq_enable		= u300_gpio_irq_enable,
-	.irq_disable		= u300_gpio_irq_disable,
-	.irq_set_type		= u300_gpio_irq_type,
-};
-
-static void u300_gpio_irq_handler(struct irq_desc *desc)
-{
-	unsigned int irq = irq_desc_get_irq(desc);
-	struct irq_chip *parent_chip = irq_desc_get_chip(desc);
-	struct gpio_chip *chip = irq_desc_get_handler_data(desc);
-	struct u300_gpio *gpio = gpiochip_get_data(chip);
-	struct u300_gpio_port *port = &gpio->ports[irq - chip->base];
-	int pinoffset = port->number << 3; /* get the right stride */
-	unsigned long val;
-
-	chained_irq_enter(parent_chip, desc);
-
-	/* Read event register */
-	val = readl(U300_PIN_REG(pinoffset, iev));
-	/* Mask relevant bits */
-	val &= 0xFFU; /* 8 bits per port */
-	/* ACK IRQ (clear event) */
-	writel(val, U300_PIN_REG(pinoffset, iev));
-
-	/* Call IRQ handler */
-	if (val != 0) {
-		int irqoffset;
-
-		for_each_set_bit(irqoffset, &val, U300_GPIO_PINS_PER_PORT) {
-			int offset = pinoffset + irqoffset;
-			int pin_irq = irq_find_mapping(chip->irq.domain, offset);
-
-			dev_dbg(gpio->dev, "GPIO IRQ %d on pin %d\n",
-				pin_irq, offset);
-			generic_handle_irq(pin_irq);
-			/*
-			 * Triggering IRQ on both rising and falling edge
-			 * needs mockery
-			 */
-			if (port->toggle_edge_mode & U300_PIN_BIT(offset))
-				u300_toggle_trigger(gpio, offset);
-		}
-	}
-
-	chained_irq_exit(parent_chip, desc);
-}
-
-static void __init u300_gpio_init_pin(struct u300_gpio *gpio,
-				      int offset,
-				      const struct u300_gpio_confdata *conf)
-{
-	/* Set mode: input or output */
-	if (conf->output) {
-		u300_gpio_direction_output(&gpio->chip, offset, conf->outval);
-
-		/* Deactivate bias mode for output */
-		u300_gpio_config_set(&gpio->chip, offset,
-				     PIN_CONFIG_BIAS_HIGH_IMPEDANCE);
-
-		/* Set drive mode for output */
-		u300_gpio_config_set(&gpio->chip, offset,
-				     PIN_CONFIG_DRIVE_PUSH_PULL);
-
-		dev_dbg(gpio->dev, "set up pin %d as output, value: %d\n",
-			offset, conf->outval);
-	} else {
-		u300_gpio_direction_input(&gpio->chip, offset);
-
-		/* Always set output low on input pins */
-		u300_gpio_set(&gpio->chip, offset, 0);
-
-		/* Set bias mode for input */
-		u300_gpio_config_set(&gpio->chip, offset, conf->bias_mode);
-
-		dev_dbg(gpio->dev, "set up pin %d as input, bias: %04x\n",
-			offset, conf->bias_mode);
-	}
-}
-
-static void __init u300_gpio_init_coh901571(struct u300_gpio *gpio)
-{
-	int i, j;
-
-	/* Write default config and values to all pins */
-	for (i = 0; i < U300_GPIO_NUM_PORTS; i++) {
-		for (j = 0; j < 8; j++) {
-			const struct u300_gpio_confdata *conf;
-			int offset = (i*8) + j;
-
-			conf = &bs335_gpio_config[i][j];
-			u300_gpio_init_pin(gpio, offset, conf);
-		}
-	}
-}
-
-/*
- * Here we map a GPIO in the local gpio_chip pin space to a pin in
- * the local pinctrl pin space. The pin controller used is
- * pinctrl-u300.
- */
-struct coh901_pinpair {
-	unsigned int offset;
-	unsigned int pin_base;
-};
-
-#define COH901_PINRANGE(a, b) { .offset = a, .pin_base = b }
-
-static struct coh901_pinpair coh901_pintable[] = {
-	COH901_PINRANGE(10, 426),
-	COH901_PINRANGE(11, 180),
-	COH901_PINRANGE(12, 165), /* MS/MMC card insertion */
-	COH901_PINRANGE(13, 179),
-	COH901_PINRANGE(14, 178),
-	COH901_PINRANGE(16, 194),
-	COH901_PINRANGE(17, 193),
-	COH901_PINRANGE(18, 192),
-	COH901_PINRANGE(19, 191),
-	COH901_PINRANGE(20, 186),
-	COH901_PINRANGE(21, 185),
-	COH901_PINRANGE(22, 184),
-	COH901_PINRANGE(23, 183),
-	COH901_PINRANGE(24, 182),
-	COH901_PINRANGE(25, 181),
-};
-
-static int __init u300_gpio_probe(struct platform_device *pdev)
-{
-	struct u300_gpio *gpio;
-	struct gpio_irq_chip *girq;
-	int err = 0;
-	int portno;
-	u32 val;
-	u32 ifr;
-	int i;
-
-	gpio = devm_kzalloc(&pdev->dev, sizeof(struct u300_gpio), GFP_KERNEL);
-	if (gpio == NULL)
-		return -ENOMEM;
-
-	gpio->chip = u300_gpio_chip;
-	gpio->chip.ngpio = U300_GPIO_NUM_PORTS * U300_GPIO_PINS_PER_PORT;
-	gpio->chip.parent = &pdev->dev;
-	gpio->chip.base = 0;
-	gpio->dev = &pdev->dev;
-
-	gpio->base = devm_platform_ioremap_resource(pdev, 0);
-	if (IS_ERR(gpio->base))
-		return PTR_ERR(gpio->base);
-
-	gpio->clk = devm_clk_get(gpio->dev, NULL);
-	if (IS_ERR(gpio->clk)) {
-		err = PTR_ERR(gpio->clk);
-		dev_err(gpio->dev, "could not get GPIO clock\n");
-		return err;
-	}
-
-	err = clk_prepare_enable(gpio->clk);
-	if (err) {
-		dev_err(gpio->dev, "could not enable GPIO clock\n");
-		return err;
-	}
-
-	dev_info(gpio->dev,
-		 "initializing GPIO Controller COH 901 571/3\n");
-	gpio->stride = U300_GPIO_PORT_STRIDE;
-	gpio->pcr = U300_GPIO_PXPCR;
-	gpio->dor = U300_GPIO_PXPDOR;
-	gpio->dir = U300_GPIO_PXPDIR;
-	gpio->per = U300_GPIO_PXPER;
-	gpio->icr = U300_GPIO_PXICR;
-	gpio->ien = U300_GPIO_PXIEN;
-	gpio->iev = U300_GPIO_PXIEV;
-	ifr = U300_GPIO_PXIFR;
-
-	val = readl(gpio->base + U300_GPIO_CR);
-	dev_info(gpio->dev, "COH901571/3 block version: %d, " \
-		 "number of cores: %d totalling %d pins\n",
-		 ((val & 0x000001FC) >> 2),
-		 ((val & 0x0000FE00) >> 9),
-		 ((val & 0x0000FE00) >> 9) * 8);
-	writel(U300_GPIO_CR_BLOCK_CLKRQ_ENABLE,
-	       gpio->base + U300_GPIO_CR);
-	u300_gpio_init_coh901571(gpio);
-
-	girq = &gpio->chip.irq;
-	girq->chip = &u300_gpio_irqchip;
-	girq->parent_handler = u300_gpio_irq_handler;
-	girq->num_parents = U300_GPIO_NUM_PORTS;
-	girq->parents = devm_kcalloc(gpio->dev, U300_GPIO_NUM_PORTS,
-				     sizeof(*girq->parents),
-				     GFP_KERNEL);
-	if (!girq->parents) {
-		err = -ENOMEM;
-		goto err_dis_clk;
-	}
-	for (portno = 0 ; portno < U300_GPIO_NUM_PORTS; portno++) {
-		struct u300_gpio_port *port = &gpio->ports[portno];
-
-		snprintf(port->name, 8, "gpio%d", portno);
-		port->number = portno;
-		port->gpio = gpio;
-
-		port->irq = platform_get_irq(pdev, portno);
-		girq->parents[portno] = port->irq;
-
-		/* Turns off irq force (test register) for this port */
-		writel(0x0, gpio->base + portno * gpio->stride + ifr);
-	}
-	girq->default_type = IRQ_TYPE_EDGE_FALLING;
-	girq->handler = handle_simple_irq;
-#ifdef CONFIG_OF_GPIO
-	gpio->chip.of_node = pdev->dev.of_node;
-#endif
-	err = gpiochip_add_data(&gpio->chip, gpio);
-	if (err) {
-		dev_err(gpio->dev, "unable to add gpiochip: %d\n", err);
-		goto err_dis_clk;
-	}
-
-	/*
-	 * Add pinctrl pin ranges, the pin controller must be registered
-	 * at this point
-	 */
-	for (i = 0; i < ARRAY_SIZE(coh901_pintable); i++) {
-		struct coh901_pinpair *p = &coh901_pintable[i];
-
-		err = gpiochip_add_pin_range(&gpio->chip, "pinctrl-u300",
-					     p->offset, p->pin_base, 1);
-		if (err)
-			goto err_no_range;
-	}
-
-	platform_set_drvdata(pdev, gpio);
-
-	return 0;
-
-err_no_range:
-	gpiochip_remove(&gpio->chip);
-err_dis_clk:
-	clk_disable_unprepare(gpio->clk);
-	dev_err(&pdev->dev, "module ERROR:%d\n", err);
-	return err;
-}
-
-static int __exit u300_gpio_remove(struct platform_device *pdev)
-{
-	struct u300_gpio *gpio = platform_get_drvdata(pdev);
-
-	/* Turn off the GPIO block */
-	writel(0x00000000U, gpio->base + U300_GPIO_CR);
-
-	gpiochip_remove(&gpio->chip);
-	clk_disable_unprepare(gpio->clk);
-	return 0;
-}
-
-static const struct of_device_id u300_gpio_match[] = {
-	{ .compatible = "stericsson,gpio-coh901" },
-	{},
-};
-
-static struct platform_driver u300_gpio_driver = {
-	.driver		= {
-		.name	= "u300-gpio",
-		.of_match_table = u300_gpio_match,
-	},
-	.remove		= __exit_p(u300_gpio_remove),
-};
-
-static int __init u300_gpio_init(void)
-{
-	return platform_driver_probe(&u300_gpio_driver, u300_gpio_probe);
-}
-
-static void __exit u300_gpio_exit(void)
-{
-	platform_driver_unregister(&u300_gpio_driver);
-}
-
-arch_initcall(u300_gpio_init);
-module_exit(u300_gpio_exit);
-
-MODULE_AUTHOR("Linus Walleij <linus.walleij@stericsson.com>");
-MODULE_DESCRIPTION("ST-Ericsson AB COH 901 335/COH 901 571/3 GPIO driver");
-MODULE_LICENSE("GPL");
diff --git a/drivers/pinctrl/pinctrl-coh901.h b/drivers/pinctrl/pinctrl-coh901.h
deleted file mode 100644
index ba2678665168..000000000000
--- a/drivers/pinctrl/pinctrl-coh901.h
+++ /dev/null
@@ -1,6 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-int u300_gpio_config_get(struct gpio_chip *chip,
-			 unsigned offset,
-			 unsigned long *config);
-int u300_gpio_config_set(struct gpio_chip *chip, unsigned offset,
-			 enum pin_config_param param);
-- 
2.29.2


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^ permalink raw reply related	[flat|nested] 22+ messages in thread

* [PATCH 5/5] pinctrl: remove ste u300 driver
  2021-01-20 13:20 ` Arnd Bergmann
@ 2021-01-20 13:20   ` Arnd Bergmann
  -1 siblings, 0 replies; 22+ messages in thread
From: Arnd Bergmann @ 2021-01-20 13:20 UTC (permalink / raw)
  To: linux-arm-kernel, linux-kernel, linux-gpio, Linus Walleij
  Cc: Bartosz Golaszewski, Arnd Bergmann

From: Arnd Bergmann <arnd@arndb.de>

The ST-Ericsson U300 platform is getting removed, so this driver is no
longer needed.

Cc: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
---
 drivers/pinctrl/Kconfig        |    6 -
 drivers/pinctrl/Makefile       |    1 -
 drivers/pinctrl/pinctrl-u300.c | 1111 --------------------------------
 3 files changed, 1118 deletions(-)
 delete mode 100644 drivers/pinctrl/pinctrl-u300.c

diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index 9ddbf14d9536..03c62e1cb395 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -271,12 +271,6 @@ config PINCTRL_STMFX
 	  and configuring push-pull, open-drain, and can also be used as
 	  interrupt-controller.
 
-config PINCTRL_U300
-	bool "U300 pin controller driver"
-	depends on ARCH_U300
-	select PINMUX
-	select GENERIC_PINCONF
-
 config PINCTRL_MAX77620
 	tristate "MAX77620/MAX20024 Pincontrol support"
 	depends on MFD_MAX77620 && OF
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index 10643440b467..efc96f25c8db 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -33,7 +33,6 @@ obj-$(CONFIG_PINCTRL_ROCKCHIP)	+= pinctrl-rockchip.o
 obj-$(CONFIG_PINCTRL_SINGLE)	+= pinctrl-single.o
 obj-$(CONFIG_PINCTRL_SX150X)	+= pinctrl-sx150x.o
 obj-$(CONFIG_ARCH_TEGRA)	+= tegra/
-obj-$(CONFIG_PINCTRL_U300)	+= pinctrl-u300.o
 obj-$(CONFIG_PINCTRL_XWAY)	+= pinctrl-xway.o
 obj-$(CONFIG_PINCTRL_LANTIQ)	+= pinctrl-lantiq.o
 obj-$(CONFIG_PINCTRL_LPC18XX)	+= pinctrl-lpc18xx.o
diff --git a/drivers/pinctrl/pinctrl-u300.c b/drivers/pinctrl/pinctrl-u300.c
deleted file mode 100644
index cc306448259e..000000000000
--- a/drivers/pinctrl/pinctrl-u300.c
+++ /dev/null
@@ -1,1111 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Driver for the U300 pin controller
- *
- * Based on the original U300 padmux functions
- * Copyright (C) 2009-2011 ST-Ericsson AB
- * Author: Martin Persson <martin.persson@stericsson.com>
- * Author: Linus Walleij <linus.walleij@linaro.org>
- *
- * The DB3350 design and control registers are oriented around pads rather than
- * pins, so we enumerate the pads we can mux rather than actual pins. The pads
- * are connected to different pins in different packaging types, so it would
- * be confusing.
- */
-#include <linux/init.h>
-#include <linux/module.h>
-#include <linux/mod_devicetable.h>
-#include <linux/platform_device.h>
-#include <linux/io.h>
-#include <linux/slab.h>
-#include <linux/err.h>
-#include <linux/pinctrl/pinctrl.h>
-#include <linux/pinctrl/pinmux.h>
-#include <linux/pinctrl/pinconf.h>
-#include <linux/pinctrl/pinconf-generic.h>
-#include "pinctrl-coh901.h"
-
-/*
- * Register definitions for the U300 Padmux control registers in the
- * system controller
- */
-
-/* PAD MUX Control register 1 (LOW) 16bit (R/W) */
-#define U300_SYSCON_PMC1LR					0x007C
-#define U300_SYSCON_PMC1LR_MASK					0xFFFF
-#define U300_SYSCON_PMC1LR_CDI_MASK				0xC000
-#define U300_SYSCON_PMC1LR_CDI_CDI				0x0000
-#define U300_SYSCON_PMC1LR_CDI_EMIF				0x4000
-/* For BS335 */
-#define U300_SYSCON_PMC1LR_CDI_CDI2				0x8000
-#define U300_SYSCON_PMC1LR_CDI_WCDMA_APP_GPIO			0xC000
-/* For BS365 */
-#define U300_SYSCON_PMC1LR_CDI_GPIO				0x8000
-#define U300_SYSCON_PMC1LR_CDI_WCDMA				0xC000
-/* Common defs */
-#define U300_SYSCON_PMC1LR_PDI_MASK				0x3000
-#define U300_SYSCON_PMC1LR_PDI_PDI				0x0000
-#define U300_SYSCON_PMC1LR_PDI_EGG				0x1000
-#define U300_SYSCON_PMC1LR_PDI_WCDMA				0x3000
-#define U300_SYSCON_PMC1LR_MMCSD_MASK				0x0C00
-#define U300_SYSCON_PMC1LR_MMCSD_MMCSD				0x0000
-#define U300_SYSCON_PMC1LR_MMCSD_MSPRO				0x0400
-#define U300_SYSCON_PMC1LR_MMCSD_DSP				0x0800
-#define U300_SYSCON_PMC1LR_MMCSD_WCDMA				0x0C00
-#define U300_SYSCON_PMC1LR_ETM_MASK				0x0300
-#define U300_SYSCON_PMC1LR_ETM_ACC				0x0000
-#define U300_SYSCON_PMC1LR_ETM_APP				0x0100
-#define U300_SYSCON_PMC1LR_EMIF_1_CS2_MASK			0x00C0
-#define U300_SYSCON_PMC1LR_EMIF_1_CS2_STATIC			0x0000
-#define U300_SYSCON_PMC1LR_EMIF_1_CS2_NFIF			0x0040
-#define U300_SYSCON_PMC1LR_EMIF_1_CS2_SDRAM			0x0080
-#define U300_SYSCON_PMC1LR_EMIF_1_CS2_STATIC_2GB		0x00C0
-#define U300_SYSCON_PMC1LR_EMIF_1_CS1_MASK			0x0030
-#define U300_SYSCON_PMC1LR_EMIF_1_CS1_STATIC			0x0000
-#define U300_SYSCON_PMC1LR_EMIF_1_CS1_NFIF			0x0010
-#define U300_SYSCON_PMC1LR_EMIF_1_CS1_SDRAM			0x0020
-#define U300_SYSCON_PMC1LR_EMIF_1_CS1_SEMI			0x0030
-#define U300_SYSCON_PMC1LR_EMIF_1_CS0_MASK			0x000C
-#define U300_SYSCON_PMC1LR_EMIF_1_CS0_STATIC			0x0000
-#define U300_SYSCON_PMC1LR_EMIF_1_CS0_NFIF			0x0004
-#define U300_SYSCON_PMC1LR_EMIF_1_CS0_SDRAM			0x0008
-#define U300_SYSCON_PMC1LR_EMIF_1_CS0_SEMI			0x000C
-#define U300_SYSCON_PMC1LR_EMIF_1_MASK				0x0003
-#define U300_SYSCON_PMC1LR_EMIF_1_STATIC			0x0000
-#define U300_SYSCON_PMC1LR_EMIF_1_SDRAM0			0x0001
-#define U300_SYSCON_PMC1LR_EMIF_1_SDRAM1			0x0002
-#define U300_SYSCON_PMC1LR_EMIF_1				0x0003
-/* PAD MUX Control register 2 (HIGH) 16bit (R/W) */
-#define U300_SYSCON_PMC1HR					0x007E
-#define U300_SYSCON_PMC1HR_MASK					0xFFFF
-#define U300_SYSCON_PMC1HR_MISC_2_MASK				0xC000
-#define U300_SYSCON_PMC1HR_MISC_2_APP_GPIO			0x0000
-#define U300_SYSCON_PMC1HR_MISC_2_MSPRO				0x4000
-#define U300_SYSCON_PMC1HR_MISC_2_DSP				0x8000
-#define U300_SYSCON_PMC1HR_MISC_2_AAIF				0xC000
-#define U300_SYSCON_PMC1HR_APP_GPIO_2_MASK			0x3000
-#define U300_SYSCON_PMC1HR_APP_GPIO_2_APP_GPIO			0x0000
-#define U300_SYSCON_PMC1HR_APP_GPIO_2_NFIF			0x1000
-#define U300_SYSCON_PMC1HR_APP_GPIO_2_DSP			0x2000
-#define U300_SYSCON_PMC1HR_APP_GPIO_2_AAIF			0x3000
-#define U300_SYSCON_PMC1HR_APP_GPIO_1_MASK			0x0C00
-#define U300_SYSCON_PMC1HR_APP_GPIO_1_APP_GPIO			0x0000
-#define U300_SYSCON_PMC1HR_APP_GPIO_1_MMC			0x0400
-#define U300_SYSCON_PMC1HR_APP_GPIO_1_DSP			0x0800
-#define U300_SYSCON_PMC1HR_APP_GPIO_1_AAIF			0x0C00
-#define U300_SYSCON_PMC1HR_APP_SPI_CS_2_MASK			0x0300
-#define U300_SYSCON_PMC1HR_APP_SPI_CS_2_APP_GPIO		0x0000
-#define U300_SYSCON_PMC1HR_APP_SPI_CS_2_SPI			0x0100
-#define U300_SYSCON_PMC1HR_APP_SPI_CS_2_AAIF			0x0300
-#define U300_SYSCON_PMC1HR_APP_SPI_CS_1_MASK			0x00C0
-#define U300_SYSCON_PMC1HR_APP_SPI_CS_1_APP_GPIO		0x0000
-#define U300_SYSCON_PMC1HR_APP_SPI_CS_1_SPI			0x0040
-#define U300_SYSCON_PMC1HR_APP_SPI_CS_1_AAIF			0x00C0
-#define U300_SYSCON_PMC1HR_APP_SPI_2_MASK			0x0030
-#define U300_SYSCON_PMC1HR_APP_SPI_2_APP_GPIO			0x0000
-#define U300_SYSCON_PMC1HR_APP_SPI_2_SPI			0x0010
-#define U300_SYSCON_PMC1HR_APP_SPI_2_DSP			0x0020
-#define U300_SYSCON_PMC1HR_APP_SPI_2_AAIF			0x0030
-#define U300_SYSCON_PMC1HR_APP_UART0_2_MASK			0x000C
-#define U300_SYSCON_PMC1HR_APP_UART0_2_APP_GPIO			0x0000
-#define U300_SYSCON_PMC1HR_APP_UART0_2_UART0			0x0004
-#define U300_SYSCON_PMC1HR_APP_UART0_2_NFIF_CS			0x0008
-#define U300_SYSCON_PMC1HR_APP_UART0_2_AAIF			0x000C
-#define U300_SYSCON_PMC1HR_APP_UART0_1_MASK			0x0003
-#define U300_SYSCON_PMC1HR_APP_UART0_1_APP_GPIO			0x0000
-#define U300_SYSCON_PMC1HR_APP_UART0_1_UART0			0x0001
-#define U300_SYSCON_PMC1HR_APP_UART0_1_AAIF			0x0003
-/* Padmux 2 control */
-#define U300_SYSCON_PMC2R					0x100
-#define U300_SYSCON_PMC2R_APP_MISC_0_MASK			0x00C0
-#define U300_SYSCON_PMC2R_APP_MISC_0_APP_GPIO			0x0000
-#define U300_SYSCON_PMC2R_APP_MISC_0_EMIF_SDRAM			0x0040
-#define U300_SYSCON_PMC2R_APP_MISC_0_MMC			0x0080
-#define U300_SYSCON_PMC2R_APP_MISC_0_CDI2			0x00C0
-#define U300_SYSCON_PMC2R_APP_MISC_1_MASK			0x0300
-#define U300_SYSCON_PMC2R_APP_MISC_1_APP_GPIO			0x0000
-#define U300_SYSCON_PMC2R_APP_MISC_1_EMIF_SDRAM			0x0100
-#define U300_SYSCON_PMC2R_APP_MISC_1_MMC			0x0200
-#define U300_SYSCON_PMC2R_APP_MISC_1_CDI2			0x0300
-#define U300_SYSCON_PMC2R_APP_MISC_2_MASK			0x0C00
-#define U300_SYSCON_PMC2R_APP_MISC_2_APP_GPIO			0x0000
-#define U300_SYSCON_PMC2R_APP_MISC_2_EMIF_SDRAM			0x0400
-#define U300_SYSCON_PMC2R_APP_MISC_2_MMC			0x0800
-#define U300_SYSCON_PMC2R_APP_MISC_2_CDI2			0x0C00
-#define U300_SYSCON_PMC2R_APP_MISC_3_MASK			0x3000
-#define U300_SYSCON_PMC2R_APP_MISC_3_APP_GPIO			0x0000
-#define U300_SYSCON_PMC2R_APP_MISC_3_EMIF_SDRAM			0x1000
-#define U300_SYSCON_PMC2R_APP_MISC_3_MMC			0x2000
-#define U300_SYSCON_PMC2R_APP_MISC_3_CDI2			0x3000
-#define U300_SYSCON_PMC2R_APP_MISC_4_MASK			0xC000
-#define U300_SYSCON_PMC2R_APP_MISC_4_APP_GPIO			0x0000
-#define U300_SYSCON_PMC2R_APP_MISC_4_EMIF_SDRAM			0x4000
-#define U300_SYSCON_PMC2R_APP_MISC_4_MMC			0x8000
-#define U300_SYSCON_PMC2R_APP_MISC_4_ACC_GPIO			0xC000
-/* TODO: More SYSCON registers missing */
-#define U300_SYSCON_PMC3R					0x10C
-#define U300_SYSCON_PMC3R_APP_MISC_11_MASK			0xC000
-#define U300_SYSCON_PMC3R_APP_MISC_11_SPI			0x4000
-#define U300_SYSCON_PMC3R_APP_MISC_10_MASK			0x3000
-#define U300_SYSCON_PMC3R_APP_MISC_10_SPI			0x1000
-/* TODO: Missing other configs */
-#define U300_SYSCON_PMC4R					0x168
-#define U300_SYSCON_PMC4R_APP_MISC_12_MASK			0x0003
-#define U300_SYSCON_PMC4R_APP_MISC_12_APP_GPIO			0x0000
-#define U300_SYSCON_PMC4R_APP_MISC_13_MASK			0x000C
-#define U300_SYSCON_PMC4R_APP_MISC_13_CDI			0x0000
-#define U300_SYSCON_PMC4R_APP_MISC_13_SMIA			0x0004
-#define U300_SYSCON_PMC4R_APP_MISC_13_SMIA2			0x0008
-#define U300_SYSCON_PMC4R_APP_MISC_13_APP_GPIO			0x000C
-#define U300_SYSCON_PMC4R_APP_MISC_14_MASK			0x0030
-#define U300_SYSCON_PMC4R_APP_MISC_14_CDI			0x0000
-#define U300_SYSCON_PMC4R_APP_MISC_14_SMIA			0x0010
-#define U300_SYSCON_PMC4R_APP_MISC_14_CDI2			0x0020
-#define U300_SYSCON_PMC4R_APP_MISC_14_APP_GPIO			0x0030
-#define U300_SYSCON_PMC4R_APP_MISC_16_MASK			0x0300
-#define U300_SYSCON_PMC4R_APP_MISC_16_APP_GPIO_13		0x0000
-#define U300_SYSCON_PMC4R_APP_MISC_16_APP_UART1_CTS		0x0100
-#define U300_SYSCON_PMC4R_APP_MISC_16_EMIF_1_STATIC_CS5_N	0x0200
-
-#define DRIVER_NAME "pinctrl-u300"
-
-/*
- * The DB3350 has 467 pads, I have enumerated the pads clockwise around the
- * edges of the silicon, finger by finger. LTCORNER upper left is pad 0.
- * Data taken from the PadRing chart, arranged like this:
- *
- *   0 ..... 104
- * 466        105
- *   .        .
- *   .        .
- * 358        224
- *  357 .... 225
- */
-#define U300_NUM_PADS 467
-
-/* Pad names for the pinmux subsystem */
-static const struct pinctrl_pin_desc u300_pads[] = {
-	/* Pads along the top edge of the chip */
-	PINCTRL_PIN(0, "P PAD VDD 28"),
-	PINCTRL_PIN(1, "P PAD GND 28"),
-	PINCTRL_PIN(2, "PO SIM RST N"),
-	PINCTRL_PIN(3, "VSSIO 25"),
-	PINCTRL_PIN(4, "VSSA ADDA ESDSUB"),
-	PINCTRL_PIN(5, "PWR VSSCOMMON"),
-	PINCTRL_PIN(6, "PI ADC I1 POS"),
-	PINCTRL_PIN(7, "PI ADC I1 NEG"),
-	PINCTRL_PIN(8, "PWR VSSAD0"),
-	PINCTRL_PIN(9, "PWR VCCAD0"),
-	PINCTRL_PIN(10, "PI ADC Q1 NEG"),
-	PINCTRL_PIN(11, "PI ADC Q1 POS"),
-	PINCTRL_PIN(12, "PWR VDDAD"),
-	PINCTRL_PIN(13, "PWR GNDAD"),
-	PINCTRL_PIN(14, "PI ADC I2 POS"),
-	PINCTRL_PIN(15, "PI ADC I2 NEG"),
-	PINCTRL_PIN(16, "PWR VSSAD1"),
-	PINCTRL_PIN(17, "PWR VCCAD1"),
-	PINCTRL_PIN(18, "PI ADC Q2 NEG"),
-	PINCTRL_PIN(19, "PI ADC Q2 POS"),
-	PINCTRL_PIN(20, "VSSA ADDA ESDSUB"),
-	PINCTRL_PIN(21, "PWR VCCGPAD"),
-	PINCTRL_PIN(22, "PI TX POW"),
-	PINCTRL_PIN(23, "PWR VSSGPAD"),
-	PINCTRL_PIN(24, "PO DAC I POS"),
-	PINCTRL_PIN(25, "PO DAC I NEG"),
-	PINCTRL_PIN(26, "PO DAC Q POS"),
-	PINCTRL_PIN(27, "PO DAC Q NEG"),
-	PINCTRL_PIN(28, "PWR VSSDA"),
-	PINCTRL_PIN(29, "PWR VCCDA"),
-	PINCTRL_PIN(30, "VSSA ADDA ESDSUB"),
-	PINCTRL_PIN(31, "P PAD VDDIO 11"),
-	PINCTRL_PIN(32, "PI PLL 26 FILTVDD"),
-	PINCTRL_PIN(33, "PI PLL 26 VCONT"),
-	PINCTRL_PIN(34, "PWR AGNDPLL2V5 32 13"),
-	PINCTRL_PIN(35, "PWR AVDDPLL2V5 32 13"),
-	PINCTRL_PIN(36, "VDDA PLL ESD"),
-	PINCTRL_PIN(37, "VSSA PLL ESD"),
-	PINCTRL_PIN(38, "VSS PLL"),
-	PINCTRL_PIN(39, "VDDC PLL"),
-	PINCTRL_PIN(40, "PWR AGNDPLL2V5 26 60"),
-	PINCTRL_PIN(41, "PWR AVDDPLL2V5 26 60"),
-	PINCTRL_PIN(42, "PWR AVDDPLL2V5 26 208"),
-	PINCTRL_PIN(43, "PWR AGNDPLL2V5 26 208"),
-	PINCTRL_PIN(44, "PWR AVDDPLL2V5 13 208"),
-	PINCTRL_PIN(45, "PWR AGNDPLL2V5 13 208"),
-	PINCTRL_PIN(46, "P PAD VSSIO 11"),
-	PINCTRL_PIN(47, "P PAD VSSIO 12"),
-	PINCTRL_PIN(48, "PI POW RST N"),
-	PINCTRL_PIN(49, "VDDC IO"),
-	PINCTRL_PIN(50, "P PAD VDDIO 16"),
-	PINCTRL_PIN(51, "PO RF WCDMA EN 4"),
-	PINCTRL_PIN(52, "PO RF WCDMA EN 3"),
-	PINCTRL_PIN(53, "PO RF WCDMA EN 2"),
-	PINCTRL_PIN(54, "PO RF WCDMA EN 1"),
-	PINCTRL_PIN(55, "PO RF WCDMA EN 0"),
-	PINCTRL_PIN(56, "PO GSM PA ENABLE"),
-	PINCTRL_PIN(57, "PO RF DATA STRB"),
-	PINCTRL_PIN(58, "PO RF DATA2"),
-	PINCTRL_PIN(59, "PIO RF DATA1"),
-	PINCTRL_PIN(60, "PIO RF DATA0"),
-	PINCTRL_PIN(61, "P PAD VDD 11"),
-	PINCTRL_PIN(62, "P PAD GND 11"),
-	PINCTRL_PIN(63, "P PAD VSSIO 16"),
-	PINCTRL_PIN(64, "P PAD VDDIO 18"),
-	PINCTRL_PIN(65, "PO RF CTRL STRB2"),
-	PINCTRL_PIN(66, "PO RF CTRL STRB1"),
-	PINCTRL_PIN(67, "PO RF CTRL STRB0"),
-	PINCTRL_PIN(68, "PIO RF CTRL DATA"),
-	PINCTRL_PIN(69, "PO RF CTRL CLK"),
-	PINCTRL_PIN(70, "PO TX ADC STRB"),
-	PINCTRL_PIN(71, "PO ANT SW 2"),
-	PINCTRL_PIN(72, "PO ANT SW 3"),
-	PINCTRL_PIN(73, "PO ANT SW 0"),
-	PINCTRL_PIN(74, "PO ANT SW 1"),
-	PINCTRL_PIN(75, "PO M CLKRQ"),
-	PINCTRL_PIN(76, "PI M CLK"),
-	PINCTRL_PIN(77, "PI RTC CLK"),
-	PINCTRL_PIN(78, "P PAD VDD 8"),
-	PINCTRL_PIN(79, "P PAD GND 8"),
-	PINCTRL_PIN(80, "P PAD VSSIO 13"),
-	PINCTRL_PIN(81, "P PAD VDDIO 13"),
-	PINCTRL_PIN(82, "PO SYS 1 CLK"),
-	PINCTRL_PIN(83, "PO SYS 2 CLK"),
-	PINCTRL_PIN(84, "PO SYS 0 CLK"),
-	PINCTRL_PIN(85, "PI SYS 0 CLKRQ"),
-	PINCTRL_PIN(86, "PO PWR MNGT CTRL 1"),
-	PINCTRL_PIN(87, "PO PWR MNGT CTRL 0"),
-	PINCTRL_PIN(88, "PO RESOUT2 RST N"),
-	PINCTRL_PIN(89, "PO RESOUT1 RST N"),
-	PINCTRL_PIN(90, "PO RESOUT0 RST N"),
-	PINCTRL_PIN(91, "PI SERVICE N"),
-	PINCTRL_PIN(92, "P PAD VDD 29"),
-	PINCTRL_PIN(93, "P PAD GND 29"),
-	PINCTRL_PIN(94, "P PAD VSSIO 8"),
-	PINCTRL_PIN(95, "P PAD VDDIO 8"),
-	PINCTRL_PIN(96, "PI EXT IRQ1 N"),
-	PINCTRL_PIN(97, "PI EXT IRQ0 N"),
-	PINCTRL_PIN(98, "PIO DC ON"),
-	PINCTRL_PIN(99, "PIO ACC APP I2C DATA"),
-	PINCTRL_PIN(100, "PIO ACC APP I2C CLK"),
-	PINCTRL_PIN(101, "P PAD VDD 12"),
-	PINCTRL_PIN(102, "P PAD GND 12"),
-	PINCTRL_PIN(103, "P PAD VSSIO 14"),
-	PINCTRL_PIN(104, "P PAD VDDIO 14"),
-	/* Pads along the right edge of the chip */
-	PINCTRL_PIN(105, "PIO APP I2C1 DATA"),
-	PINCTRL_PIN(106, "PIO APP I2C1 CLK"),
-	PINCTRL_PIN(107, "PO KEY OUT0"),
-	PINCTRL_PIN(108, "PO KEY OUT1"),
-	PINCTRL_PIN(109, "PO KEY OUT2"),
-	PINCTRL_PIN(110, "PO KEY OUT3"),
-	PINCTRL_PIN(111, "PO KEY OUT4"),
-	PINCTRL_PIN(112, "PI KEY IN0"),
-	PINCTRL_PIN(113, "PI KEY IN1"),
-	PINCTRL_PIN(114, "PI KEY IN2"),
-	PINCTRL_PIN(115, "P PAD VDDIO 15"),
-	PINCTRL_PIN(116, "P PAD VSSIO 15"),
-	PINCTRL_PIN(117, "P PAD GND 13"),
-	PINCTRL_PIN(118, "P PAD VDD 13"),
-	PINCTRL_PIN(119, "PI KEY IN3"),
-	PINCTRL_PIN(120, "PI KEY IN4"),
-	PINCTRL_PIN(121, "PI KEY IN5"),
-	PINCTRL_PIN(122, "PIO APP PCM I2S1 DATA B"),
-	PINCTRL_PIN(123, "PIO APP PCM I2S1 DATA A"),
-	PINCTRL_PIN(124, "PIO APP PCM I2S1 WS"),
-	PINCTRL_PIN(125, "PIO APP PCM I2S1 CLK"),
-	PINCTRL_PIN(126, "PIO APP PCM I2S0 DATA B"),
-	PINCTRL_PIN(127, "PIO APP PCM I2S0 DATA A"),
-	PINCTRL_PIN(128, "PIO APP PCM I2S0 WS"),
-	PINCTRL_PIN(129, "PIO APP PCM I2S0 CLK"),
-	PINCTRL_PIN(130, "P PAD VDD 17"),
-	PINCTRL_PIN(131, "P PAD GND 17"),
-	PINCTRL_PIN(132, "P PAD VSSIO 19"),
-	PINCTRL_PIN(133, "P PAD VDDIO 19"),
-	PINCTRL_PIN(134, "UART0 RTS"),
-	PINCTRL_PIN(135, "UART0 CTS"),
-	PINCTRL_PIN(136, "UART0 TX"),
-	PINCTRL_PIN(137, "UART0 RX"),
-	PINCTRL_PIN(138, "PIO ACC SPI DO"),
-	PINCTRL_PIN(139, "PIO ACC SPI DI"),
-	PINCTRL_PIN(140, "PIO ACC SPI CS0 N"),
-	PINCTRL_PIN(141, "PIO ACC SPI CS1 N"),
-	PINCTRL_PIN(142, "PIO ACC SPI CS2 N"),
-	PINCTRL_PIN(143, "PIO ACC SPI CLK"),
-	PINCTRL_PIN(144, "PO PDI EXT RST N"),
-	PINCTRL_PIN(145, "P PAD VDDIO 22"),
-	PINCTRL_PIN(146, "P PAD VSSIO 22"),
-	PINCTRL_PIN(147, "P PAD GND 18"),
-	PINCTRL_PIN(148, "P PAD VDD 18"),
-	PINCTRL_PIN(149, "PIO PDI C0"),
-	PINCTRL_PIN(150, "PIO PDI C1"),
-	PINCTRL_PIN(151, "PIO PDI C2"),
-	PINCTRL_PIN(152, "PIO PDI C3"),
-	PINCTRL_PIN(153, "PIO PDI C4"),
-	PINCTRL_PIN(154, "PIO PDI C5"),
-	PINCTRL_PIN(155, "PIO PDI D0"),
-	PINCTRL_PIN(156, "PIO PDI D1"),
-	PINCTRL_PIN(157, "PIO PDI D2"),
-	PINCTRL_PIN(158, "PIO PDI D3"),
-	PINCTRL_PIN(159, "P PAD VDDIO 21"),
-	PINCTRL_PIN(160, "P PAD VSSIO 21"),
-	PINCTRL_PIN(161, "PIO PDI D4"),
-	PINCTRL_PIN(162, "PIO PDI D5"),
-	PINCTRL_PIN(163, "PIO PDI D6"),
-	PINCTRL_PIN(164, "PIO PDI D7"),
-	PINCTRL_PIN(165, "PIO MS INS"),
-	PINCTRL_PIN(166, "MMC DATA DIR LS"),
-	PINCTRL_PIN(167, "MMC DATA 3"),
-	PINCTRL_PIN(168, "MMC DATA 2"),
-	PINCTRL_PIN(169, "MMC DATA 1"),
-	PINCTRL_PIN(170, "MMC DATA 0"),
-	PINCTRL_PIN(171, "MMC CMD DIR LS"),
-	PINCTRL_PIN(172, "P PAD VDD 27"),
-	PINCTRL_PIN(173, "P PAD GND 27"),
-	PINCTRL_PIN(174, "P PAD VSSIO 20"),
-	PINCTRL_PIN(175, "P PAD VDDIO 20"),
-	PINCTRL_PIN(176, "MMC CMD"),
-	PINCTRL_PIN(177, "MMC CLK"),
-	PINCTRL_PIN(178, "PIO APP GPIO 14"),
-	PINCTRL_PIN(179, "PIO APP GPIO 13"),
-	PINCTRL_PIN(180, "PIO APP GPIO 11"),
-	PINCTRL_PIN(181, "PIO APP GPIO 25"),
-	PINCTRL_PIN(182, "PIO APP GPIO 24"),
-	PINCTRL_PIN(183, "PIO APP GPIO 23"),
-	PINCTRL_PIN(184, "PIO APP GPIO 22"),
-	PINCTRL_PIN(185, "PIO APP GPIO 21"),
-	PINCTRL_PIN(186, "PIO APP GPIO 20"),
-	PINCTRL_PIN(187, "P PAD VDD 19"),
-	PINCTRL_PIN(188, "P PAD GND 19"),
-	PINCTRL_PIN(189, "P PAD VSSIO 23"),
-	PINCTRL_PIN(190, "P PAD VDDIO 23"),
-	PINCTRL_PIN(191, "PIO APP GPIO 19"),
-	PINCTRL_PIN(192, "PIO APP GPIO 18"),
-	PINCTRL_PIN(193, "PIO APP GPIO 17"),
-	PINCTRL_PIN(194, "PIO APP GPIO 16"),
-	PINCTRL_PIN(195, "PI CI D1"),
-	PINCTRL_PIN(196, "PI CI D0"),
-	PINCTRL_PIN(197, "PI CI HSYNC"),
-	PINCTRL_PIN(198, "PI CI VSYNC"),
-	PINCTRL_PIN(199, "PI CI EXT CLK"),
-	PINCTRL_PIN(200, "PO CI EXT RST N"),
-	PINCTRL_PIN(201, "P PAD VSSIO 43"),
-	PINCTRL_PIN(202, "P PAD VDDIO 43"),
-	PINCTRL_PIN(203, "PI CI D6"),
-	PINCTRL_PIN(204, "PI CI D7"),
-	PINCTRL_PIN(205, "PI CI D2"),
-	PINCTRL_PIN(206, "PI CI D3"),
-	PINCTRL_PIN(207, "PI CI D4"),
-	PINCTRL_PIN(208, "PI CI D5"),
-	PINCTRL_PIN(209, "PI CI D8"),
-	PINCTRL_PIN(210, "PI CI D9"),
-	PINCTRL_PIN(211, "P PAD VDD 20"),
-	PINCTRL_PIN(212, "P PAD GND 20"),
-	PINCTRL_PIN(213, "P PAD VSSIO 24"),
-	PINCTRL_PIN(214, "P PAD VDDIO 24"),
-	PINCTRL_PIN(215, "P PAD VDDIO 26"),
-	PINCTRL_PIN(216, "PO EMIF 1 A26"),
-	PINCTRL_PIN(217, "PO EMIF 1 A25"),
-	PINCTRL_PIN(218, "P PAD VSSIO 26"),
-	PINCTRL_PIN(219, "PO EMIF 1 A24"),
-	PINCTRL_PIN(220, "PO EMIF 1 A23"),
-	/* Pads along the bottom edge of the chip */
-	PINCTRL_PIN(221, "PO EMIF 1 A22"),
-	PINCTRL_PIN(222, "PO EMIF 1 A21"),
-	PINCTRL_PIN(223, "P PAD VDD 21"),
-	PINCTRL_PIN(224, "P PAD GND 21"),
-	PINCTRL_PIN(225, "P PAD VSSIO 27"),
-	PINCTRL_PIN(226, "P PAD VDDIO 27"),
-	PINCTRL_PIN(227, "PO EMIF 1 A20"),
-	PINCTRL_PIN(228, "PO EMIF 1 A19"),
-	PINCTRL_PIN(229, "PO EMIF 1 A18"),
-	PINCTRL_PIN(230, "PO EMIF 1 A17"),
-	PINCTRL_PIN(231, "P PAD VDDIO 28"),
-	PINCTRL_PIN(232, "P PAD VSSIO 28"),
-	PINCTRL_PIN(233, "PO EMIF 1 A16"),
-	PINCTRL_PIN(234, "PIO EMIF 1 D15"),
-	PINCTRL_PIN(235, "PO EMIF 1 A15"),
-	PINCTRL_PIN(236, "PIO EMIF 1 D14"),
-	PINCTRL_PIN(237, "P PAD VDD 22"),
-	PINCTRL_PIN(238, "P PAD GND 22"),
-	PINCTRL_PIN(239, "P PAD VSSIO 29"),
-	PINCTRL_PIN(240, "P PAD VDDIO 29"),
-	PINCTRL_PIN(241, "PO EMIF 1 A14"),
-	PINCTRL_PIN(242, "PIO EMIF 1 D13"),
-	PINCTRL_PIN(243, "PO EMIF 1 A13"),
-	PINCTRL_PIN(244, "PIO EMIF 1 D12"),
-	PINCTRL_PIN(245, "P PAD VSSIO 30"),
-	PINCTRL_PIN(246, "P PAD VDDIO 30"),
-	PINCTRL_PIN(247, "PO EMIF 1 A12"),
-	PINCTRL_PIN(248, "PIO EMIF 1 D11"),
-	PINCTRL_PIN(249, "PO EMIF 1 A11"),
-	PINCTRL_PIN(250, "PIO EMIF 1 D10"),
-	PINCTRL_PIN(251, "P PAD VSSIO 31"),
-	PINCTRL_PIN(252, "P PAD VDDIO 31"),
-	PINCTRL_PIN(253, "PO EMIF 1 A10"),
-	PINCTRL_PIN(254, "PIO EMIF 1 D09"),
-	PINCTRL_PIN(255, "PO EMIF 1 A09"),
-	PINCTRL_PIN(256, "P PAD VDDIO 32"),
-	PINCTRL_PIN(257, "P PAD VSSIO 32"),
-	PINCTRL_PIN(258, "P PAD GND 24"),
-	PINCTRL_PIN(259, "P PAD VDD 24"),
-	PINCTRL_PIN(260, "PIO EMIF 1 D08"),
-	PINCTRL_PIN(261, "PO EMIF 1 A08"),
-	PINCTRL_PIN(262, "PIO EMIF 1 D07"),
-	PINCTRL_PIN(263, "PO EMIF 1 A07"),
-	PINCTRL_PIN(264, "P PAD VDDIO 33"),
-	PINCTRL_PIN(265, "P PAD VSSIO 33"),
-	PINCTRL_PIN(266, "PIO EMIF 1 D06"),
-	PINCTRL_PIN(267, "PO EMIF 1 A06"),
-	PINCTRL_PIN(268, "PIO EMIF 1 D05"),
-	PINCTRL_PIN(269, "PO EMIF 1 A05"),
-	PINCTRL_PIN(270, "P PAD VDDIO 34"),
-	PINCTRL_PIN(271, "P PAD VSSIO 34"),
-	PINCTRL_PIN(272, "PIO EMIF 1 D04"),
-	PINCTRL_PIN(273, "PO EMIF 1 A04"),
-	PINCTRL_PIN(274, "PIO EMIF 1 D03"),
-	PINCTRL_PIN(275, "PO EMIF 1 A03"),
-	PINCTRL_PIN(276, "P PAD VDDIO 35"),
-	PINCTRL_PIN(277, "P PAD VSSIO 35"),
-	PINCTRL_PIN(278, "P PAD GND 23"),
-	PINCTRL_PIN(279, "P PAD VDD 23"),
-	PINCTRL_PIN(280, "PIO EMIF 1 D02"),
-	PINCTRL_PIN(281, "PO EMIF 1 A02"),
-	PINCTRL_PIN(282, "PIO EMIF 1 D01"),
-	PINCTRL_PIN(283, "PO EMIF 1 A01"),
-	PINCTRL_PIN(284, "P PAD VDDIO 36"),
-	PINCTRL_PIN(285, "P PAD VSSIO 36"),
-	PINCTRL_PIN(286, "PIO EMIF 1 D00"),
-	PINCTRL_PIN(287, "PO EMIF 1 BE1 N"),
-	PINCTRL_PIN(288, "PO EMIF 1 BE0 N"),
-	PINCTRL_PIN(289, "PO EMIF 1 ADV N"),
-	PINCTRL_PIN(290, "P PAD VDDIO 37"),
-	PINCTRL_PIN(291, "P PAD VSSIO 37"),
-	PINCTRL_PIN(292, "PO EMIF 1 SD CKE0"),
-	PINCTRL_PIN(293, "PO EMIF 1 OE N"),
-	PINCTRL_PIN(294, "PO EMIF 1 WE N"),
-	PINCTRL_PIN(295, "P PAD VDDIO 38"),
-	PINCTRL_PIN(296, "P PAD VSSIO 38"),
-	PINCTRL_PIN(297, "PO EMIF 1 CLK"),
-	PINCTRL_PIN(298, "PIO EMIF 1 SD CLK"),
-	PINCTRL_PIN(299, "P PAD VSSIO 45 (not bonded)"),
-	PINCTRL_PIN(300, "P PAD VDDIO 42"),
-	PINCTRL_PIN(301, "P PAD VSSIO 42"),
-	PINCTRL_PIN(302, "P PAD GND 31"),
-	PINCTRL_PIN(303, "P PAD VDD 31"),
-	PINCTRL_PIN(304, "PI EMIF 1 RET CLK"),
-	PINCTRL_PIN(305, "PI EMIF 1 WAIT N"),
-	PINCTRL_PIN(306, "PI EMIF 1 NFIF READY"),
-	PINCTRL_PIN(307, "PO EMIF 1 SD CKE1"),
-	PINCTRL_PIN(308, "PO EMIF 1 CS3 N"),
-	PINCTRL_PIN(309, "P PAD VDD 25"),
-	PINCTRL_PIN(310, "P PAD GND 25"),
-	PINCTRL_PIN(311, "P PAD VSSIO 39"),
-	PINCTRL_PIN(312, "P PAD VDDIO 39"),
-	PINCTRL_PIN(313, "PO EMIF 1 CS2 N"),
-	PINCTRL_PIN(314, "PO EMIF 1 CS1 N"),
-	PINCTRL_PIN(315, "PO EMIF 1 CS0 N"),
-	PINCTRL_PIN(316, "PO ETM TRACE PKT0"),
-	PINCTRL_PIN(317, "PO ETM TRACE PKT1"),
-	PINCTRL_PIN(318, "PO ETM TRACE PKT2"),
-	PINCTRL_PIN(319, "P PAD VDD 30"),
-	PINCTRL_PIN(320, "P PAD GND 30"),
-	PINCTRL_PIN(321, "P PAD VSSIO 44"),
-	PINCTRL_PIN(322, "P PAD VDDIO 44"),
-	PINCTRL_PIN(323, "PO ETM TRACE PKT3"),
-	PINCTRL_PIN(324, "PO ETM TRACE PKT4"),
-	PINCTRL_PIN(325, "PO ETM TRACE PKT5"),
-	PINCTRL_PIN(326, "PO ETM TRACE PKT6"),
-	PINCTRL_PIN(327, "PO ETM TRACE PKT7"),
-	PINCTRL_PIN(328, "PO ETM PIPE STAT0"),
-	PINCTRL_PIN(329, "P PAD VDD 26"),
-	PINCTRL_PIN(330, "P PAD GND 26"),
-	PINCTRL_PIN(331, "P PAD VSSIO 40"),
-	PINCTRL_PIN(332, "P PAD VDDIO 40"),
-	PINCTRL_PIN(333, "PO ETM PIPE STAT1"),
-	PINCTRL_PIN(334, "PO ETM PIPE STAT2"),
-	PINCTRL_PIN(335, "PO ETM TRACE CLK"),
-	PINCTRL_PIN(336, "PO ETM TRACE SYNC"),
-	PINCTRL_PIN(337, "PIO ACC GPIO 33"),
-	PINCTRL_PIN(338, "PIO ACC GPIO 32"),
-	PINCTRL_PIN(339, "PIO ACC GPIO 30"),
-	PINCTRL_PIN(340, "PIO ACC GPIO 29"),
-	PINCTRL_PIN(341, "P PAD VDDIO 17"),
-	PINCTRL_PIN(342, "P PAD VSSIO 17"),
-	PINCTRL_PIN(343, "P PAD GND 15"),
-	PINCTRL_PIN(344, "P PAD VDD 15"),
-	PINCTRL_PIN(345, "PIO ACC GPIO 28"),
-	PINCTRL_PIN(346, "PIO ACC GPIO 27"),
-	PINCTRL_PIN(347, "PIO ACC GPIO 16"),
-	PINCTRL_PIN(348, "PI TAP TMS"),
-	PINCTRL_PIN(349, "PI TAP TDI"),
-	PINCTRL_PIN(350, "PO TAP TDO"),
-	PINCTRL_PIN(351, "PI TAP RST N"),
-	/* Pads along the left edge of the chip */
-	PINCTRL_PIN(352, "PI EMU MODE 0"),
-	PINCTRL_PIN(353, "PO TAP RET CLK"),
-	PINCTRL_PIN(354, "PI TAP CLK"),
-	PINCTRL_PIN(355, "PO EMIF 0 SD CS N"),
-	PINCTRL_PIN(356, "PO EMIF 0 SD CAS N"),
-	PINCTRL_PIN(357, "PO EMIF 0 SD WE N"),
-	PINCTRL_PIN(358, "P PAD VDDIO 1"),
-	PINCTRL_PIN(359, "P PAD VSSIO 1"),
-	PINCTRL_PIN(360, "P PAD GND 1"),
-	PINCTRL_PIN(361, "P PAD VDD 1"),
-	PINCTRL_PIN(362, "PO EMIF 0 SD CKE"),
-	PINCTRL_PIN(363, "PO EMIF 0 SD DQML"),
-	PINCTRL_PIN(364, "PO EMIF 0 SD DQMU"),
-	PINCTRL_PIN(365, "PO EMIF 0 SD RAS N"),
-	PINCTRL_PIN(366, "PIO EMIF 0 D15"),
-	PINCTRL_PIN(367, "PO EMIF 0 A15"),
-	PINCTRL_PIN(368, "PIO EMIF 0 D14"),
-	PINCTRL_PIN(369, "PO EMIF 0 A14"),
-	PINCTRL_PIN(370, "PIO EMIF 0 D13"),
-	PINCTRL_PIN(371, "PO EMIF 0 A13"),
-	PINCTRL_PIN(372, "P PAD VDDIO 2"),
-	PINCTRL_PIN(373, "P PAD VSSIO 2"),
-	PINCTRL_PIN(374, "P PAD GND 2"),
-	PINCTRL_PIN(375, "P PAD VDD 2"),
-	PINCTRL_PIN(376, "PIO EMIF 0 D12"),
-	PINCTRL_PIN(377, "PO EMIF 0 A12"),
-	PINCTRL_PIN(378, "PIO EMIF 0 D11"),
-	PINCTRL_PIN(379, "PO EMIF 0 A11"),
-	PINCTRL_PIN(380, "PIO EMIF 0 D10"),
-	PINCTRL_PIN(381, "PO EMIF 0 A10"),
-	PINCTRL_PIN(382, "PIO EMIF 0 D09"),
-	PINCTRL_PIN(383, "PO EMIF 0 A09"),
-	PINCTRL_PIN(384, "PIO EMIF 0 D08"),
-	PINCTRL_PIN(385, "PO EMIF 0 A08"),
-	PINCTRL_PIN(386, "PIO EMIF 0 D07"),
-	PINCTRL_PIN(387, "PO EMIF 0 A07"),
-	PINCTRL_PIN(388, "P PAD VDDIO 3"),
-	PINCTRL_PIN(389, "P PAD VSSIO 3"),
-	PINCTRL_PIN(390, "P PAD GND 3"),
-	PINCTRL_PIN(391, "P PAD VDD 3"),
-	PINCTRL_PIN(392, "PO EFUSE RDOUT1"),
-	PINCTRL_PIN(393, "PIO EMIF 0 D06"),
-	PINCTRL_PIN(394, "PO EMIF 0 A06"),
-	PINCTRL_PIN(395, "PIO EMIF 0 D05"),
-	PINCTRL_PIN(396, "PO EMIF 0 A05"),
-	PINCTRL_PIN(397, "PIO EMIF 0 D04"),
-	PINCTRL_PIN(398, "PO EMIF 0 A04"),
-	PINCTRL_PIN(399, "A PADS/A VDDCO1v82v5 GND 80U SF LIN VDDCO AF"),
-	PINCTRL_PIN(400, "PWR VDDCO AF"),
-	PINCTRL_PIN(401, "PWR EFUSE HV1"),
-	PINCTRL_PIN(402, "P PAD VSSIO 4"),
-	PINCTRL_PIN(403, "P PAD VDDIO 4"),
-	PINCTRL_PIN(404, "P PAD GND 4"),
-	PINCTRL_PIN(405, "P PAD VDD 4"),
-	PINCTRL_PIN(406, "PIO EMIF 0 D03"),
-	PINCTRL_PIN(407, "PO EMIF 0 A03"),
-	PINCTRL_PIN(408, "PWR EFUSE HV2"),
-	PINCTRL_PIN(409, "PWR EFUSE HV3"),
-	PINCTRL_PIN(410, "PIO EMIF 0 D02"),
-	PINCTRL_PIN(411, "PO EMIF 0 A02"),
-	PINCTRL_PIN(412, "PIO EMIF 0 D01"),
-	PINCTRL_PIN(413, "P PAD VDDIO 5"),
-	PINCTRL_PIN(414, "P PAD VSSIO 5"),
-	PINCTRL_PIN(415, "P PAD GND 5"),
-	PINCTRL_PIN(416, "P PAD VDD 5"),
-	PINCTRL_PIN(417, "PO EMIF 0 A01"),
-	PINCTRL_PIN(418, "PIO EMIF 0 D00"),
-	PINCTRL_PIN(419, "IF 0 SD CLK"),
-	PINCTRL_PIN(420, "APP SPI CLK"),
-	PINCTRL_PIN(421, "APP SPI DO"),
-	PINCTRL_PIN(422, "APP SPI DI"),
-	PINCTRL_PIN(423, "APP SPI CS0"),
-	PINCTRL_PIN(424, "APP SPI CS1"),
-	PINCTRL_PIN(425, "APP SPI CS2"),
-	PINCTRL_PIN(426, "PIO APP GPIO 10"),
-	PINCTRL_PIN(427, "P PAD VDDIO 41"),
-	PINCTRL_PIN(428, "P PAD VSSIO 41"),
-	PINCTRL_PIN(429, "P PAD GND 6"),
-	PINCTRL_PIN(430, "P PAD VDD 6"),
-	PINCTRL_PIN(431, "PIO ACC SDIO0 CMD"),
-	PINCTRL_PIN(432, "PIO ACC SDIO0 CK"),
-	PINCTRL_PIN(433, "PIO ACC SDIO0 D3"),
-	PINCTRL_PIN(434, "PIO ACC SDIO0 D2"),
-	PINCTRL_PIN(435, "PIO ACC SDIO0 D1"),
-	PINCTRL_PIN(436, "PIO ACC SDIO0 D0"),
-	PINCTRL_PIN(437, "PIO USB PU"),
-	PINCTRL_PIN(438, "PIO USB SP"),
-	PINCTRL_PIN(439, "PIO USB DAT VP"),
-	PINCTRL_PIN(440, "PIO USB SE0 VM"),
-	PINCTRL_PIN(441, "PIO USB OE"),
-	PINCTRL_PIN(442, "PIO USB SUSP"),
-	PINCTRL_PIN(443, "P PAD VSSIO 6"),
-	PINCTRL_PIN(444, "P PAD VDDIO 6"),
-	PINCTRL_PIN(445, "PIO USB PUEN"),
-	PINCTRL_PIN(446, "PIO ACC UART0 RX"),
-	PINCTRL_PIN(447, "PIO ACC UART0 TX"),
-	PINCTRL_PIN(448, "PIO ACC UART0 CTS"),
-	PINCTRL_PIN(449, "PIO ACC UART0 RTS"),
-	PINCTRL_PIN(450, "PIO ACC UART3 RX"),
-	PINCTRL_PIN(451, "PIO ACC UART3 TX"),
-	PINCTRL_PIN(452, "PIO ACC UART3 CTS"),
-	PINCTRL_PIN(453, "PIO ACC UART3 RTS"),
-	PINCTRL_PIN(454, "PIO ACC IRDA TX"),
-	PINCTRL_PIN(455, "P PAD VDDIO 7"),
-	PINCTRL_PIN(456, "P PAD VSSIO 7"),
-	PINCTRL_PIN(457, "P PAD GND 7"),
-	PINCTRL_PIN(458, "P PAD VDD 7"),
-	PINCTRL_PIN(459, "PIO ACC IRDA RX"),
-	PINCTRL_PIN(460, "PIO ACC PCM I2S CLK"),
-	PINCTRL_PIN(461, "PIO ACC PCM I2S WS"),
-	PINCTRL_PIN(462, "PIO ACC PCM I2S DATA A"),
-	PINCTRL_PIN(463, "PIO ACC PCM I2S DATA B"),
-	PINCTRL_PIN(464, "PO SIM CLK"),
-	PINCTRL_PIN(465, "PIO ACC IRDA SD"),
-	PINCTRL_PIN(466, "PIO SIM DATA"),
-};
-
-/**
- * @dev: a pointer back to containing device
- * @virtbase: the offset to the controller in virtual memory
- */
-struct u300_pmx {
-	struct device *dev;
-	struct pinctrl_dev *pctl;
-	void __iomem *virtbase;
-};
-
-/**
- * u300_pmx_registers - the array of registers read/written for each pinmux
- * shunt setting
- */
-static const u32 u300_pmx_registers[] = {
-	U300_SYSCON_PMC1LR,
-	U300_SYSCON_PMC1HR,
-	U300_SYSCON_PMC2R,
-	U300_SYSCON_PMC3R,
-	U300_SYSCON_PMC4R,
-};
-
-/**
- * struct u300_pin_group - describes a U300 pin group
- * @name: the name of this specific pin group
- * @pins: an array of discrete physical pins used in this group, taken
- *	from the driver-local pin enumeration space
- * @num_pins: the number of pins in this group array, i.e. the number of
- *	elements in .pins so we can iterate over that array
- */
-struct u300_pin_group {
-	const char *name;
-	const unsigned int *pins;
-	const unsigned num_pins;
-};
-
-/**
- * struct pmx_onmask - mask bits to enable/disable padmux
- * @mask: mask bits to disable
- * @val: mask bits to enable
- *
- * onmask lazy dog:
- * onmask = {
- *   {"PMC1LR" mask, "PMC1LR" value},
- *   {"PMC1HR" mask, "PMC1HR" value},
- *   {"PMC2R"  mask, "PMC2R"  value},
- *   {"PMC3R"  mask, "PMC3R"  value},
- *   {"PMC4R"  mask, "PMC4R"  value}
- * }
- */
-struct u300_pmx_mask {
-	u16 mask;
-	u16 bits;
-};
-
-/* The chip power pins are VDD, GND, VDDIO and VSSIO */
-static const unsigned power_pins[] = { 0, 1, 3, 31, 46, 47, 49, 50, 61, 62, 63,
-	64, 78, 79, 80, 81, 92, 93, 94, 95, 101, 102, 103, 104, 115, 116, 117,
-	118, 130, 131, 132, 133, 145, 146, 147, 148, 159, 160, 172, 173, 174,
-	175, 187, 188, 189, 190, 201, 202, 211, 212, 213, 214, 215, 218, 223,
-	224, 225, 226, 231, 232, 237, 238, 239, 240, 245, 246, 251, 252, 256,
-	257, 258, 259, 264, 265, 270, 271, 276, 277, 278, 279, 284, 285, 290,
-	291, 295, 296, 299, 300, 301, 302, 303, 309, 310, 311, 312, 319, 320,
-	321, 322, 329, 330, 331, 332, 341, 342, 343, 344, 358, 359, 360, 361,
-	372, 373, 374, 375, 388, 389, 390, 391, 402, 403, 404, 405, 413, 414,
-	415, 416, 427, 428, 429, 430, 443, 444, 455, 456, 457, 458 };
-static const unsigned emif0_pins[] = { 355, 356, 357, 362, 363, 364, 365, 366,
-	367, 368, 369, 370, 371, 376, 377, 378, 379, 380, 381, 382, 383, 384,
-	385, 386, 387, 393, 394, 395, 396, 397, 398, 406, 407, 410, 411, 412,
-	417, 418 };
-static const unsigned emif1_pins[] = { 216, 217, 219, 220, 221, 222, 227, 228,
-	229, 230, 233, 234, 235, 236, 241, 242, 243, 244, 247, 248, 249, 250,
-	253, 254, 255, 260, 261, 262, 263, 266, 267, 268, 269, 272, 273, 274,
-	275, 280, 281, 282, 283, 286, 287, 288, 289, 292, 293, 294, 297, 298,
-	304, 305, 306, 307, 308, 313, 314, 315 };
-static const unsigned uart0_pins[] = { 134, 135, 136, 137 };
-static const unsigned mmc0_pins[] = { 166, 167, 168, 169, 170, 171, 176, 177 };
-static const unsigned spi0_pins[] = { 420, 421, 422, 423, 424, 425 };
-
-static const struct u300_pmx_mask emif0_mask[] = {
-	{0, 0},
-	{0, 0},
-	{0, 0},
-	{0, 0},
-	{0, 0},
-};
-
-static const struct u300_pmx_mask emif1_mask[] = {
-	/*
-	 * This connects the SDRAM to CS2 and a NAND flash to
-	 * CS0 on the EMIF.
-	 */
-	{
-		U300_SYSCON_PMC1LR_EMIF_1_CS2_MASK |
-		U300_SYSCON_PMC1LR_EMIF_1_CS1_MASK |
-		U300_SYSCON_PMC1LR_EMIF_1_CS0_MASK |
-		U300_SYSCON_PMC1LR_EMIF_1_MASK,
-		U300_SYSCON_PMC1LR_EMIF_1_CS2_SDRAM |
-		U300_SYSCON_PMC1LR_EMIF_1_CS1_STATIC |
-		U300_SYSCON_PMC1LR_EMIF_1_CS0_NFIF |
-		U300_SYSCON_PMC1LR_EMIF_1_SDRAM0
-	},
-	{0, 0},
-	{0, 0},
-	{0, 0},
-	{0, 0},
-};
-
-static const struct u300_pmx_mask uart0_mask[] = {
-	{0, 0},
-	{
-		U300_SYSCON_PMC1HR_APP_UART0_1_MASK |
-		U300_SYSCON_PMC1HR_APP_UART0_2_MASK,
-		U300_SYSCON_PMC1HR_APP_UART0_1_UART0 |
-		U300_SYSCON_PMC1HR_APP_UART0_2_UART0
-	},
-	{0, 0},
-	{0, 0},
-	{0, 0},
-};
-
-static const struct u300_pmx_mask mmc0_mask[] = {
-	{ U300_SYSCON_PMC1LR_MMCSD_MASK, U300_SYSCON_PMC1LR_MMCSD_MMCSD},
-	{0, 0},
-	{0, 0},
-	{0, 0},
-	{ U300_SYSCON_PMC4R_APP_MISC_12_MASK,
-	  U300_SYSCON_PMC4R_APP_MISC_12_APP_GPIO }
-};
-
-static const struct u300_pmx_mask spi0_mask[] = {
-	{0, 0},
-	{
-		U300_SYSCON_PMC1HR_APP_SPI_2_MASK |
-		U300_SYSCON_PMC1HR_APP_SPI_CS_1_MASK |
-		U300_SYSCON_PMC1HR_APP_SPI_CS_2_MASK,
-		U300_SYSCON_PMC1HR_APP_SPI_2_SPI |
-		U300_SYSCON_PMC1HR_APP_SPI_CS_1_SPI |
-		U300_SYSCON_PMC1HR_APP_SPI_CS_2_SPI
-	},
-	{0, 0},
-	{0, 0},
-	{0, 0}
-};
-
-static const struct u300_pin_group u300_pin_groups[] = {
-	{
-		.name = "powergrp",
-		.pins = power_pins,
-		.num_pins = ARRAY_SIZE(power_pins),
-	},
-	{
-		.name = "emif0grp",
-		.pins = emif0_pins,
-		.num_pins = ARRAY_SIZE(emif0_pins),
-	},
-	{
-		.name = "emif1grp",
-		.pins = emif1_pins,
-		.num_pins = ARRAY_SIZE(emif1_pins),
-	},
-	{
-		.name = "uart0grp",
-		.pins = uart0_pins,
-		.num_pins = ARRAY_SIZE(uart0_pins),
-	},
-	{
-		.name = "mmc0grp",
-		.pins = mmc0_pins,
-		.num_pins = ARRAY_SIZE(mmc0_pins),
-	},
-	{
-		.name = "spi0grp",
-		.pins = spi0_pins,
-		.num_pins = ARRAY_SIZE(spi0_pins),
-	},
-};
-
-static int u300_get_groups_count(struct pinctrl_dev *pctldev)
-{
-	return ARRAY_SIZE(u300_pin_groups);
-}
-
-static const char *u300_get_group_name(struct pinctrl_dev *pctldev,
-				       unsigned selector)
-{
-	return u300_pin_groups[selector].name;
-}
-
-static int u300_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
-			       const unsigned **pins,
-			       unsigned *num_pins)
-{
-	*pins = u300_pin_groups[selector].pins;
-	*num_pins = u300_pin_groups[selector].num_pins;
-	return 0;
-}
-
-static void u300_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
-		   unsigned offset)
-{
-	seq_printf(s, " " DRIVER_NAME);
-}
-
-static const struct pinctrl_ops u300_pctrl_ops = {
-	.get_groups_count = u300_get_groups_count,
-	.get_group_name = u300_get_group_name,
-	.get_group_pins = u300_get_group_pins,
-	.pin_dbg_show = u300_pin_dbg_show,
-};
-
-/*
- * Here we define the available functions and their corresponding pin groups
- */
-
-/**
- * struct u300_pmx_func - describes U300 pinmux functions
- * @name: the name of this specific function
- * @groups: corresponding pin groups
- * @onmask: bits to set to enable this when doing pin muxing
- */
-struct u300_pmx_func {
-	const char *name;
-	const char * const *groups;
-	const unsigned num_groups;
-	const struct u300_pmx_mask *mask;
-};
-
-static const char * const powergrps[] = { "powergrp" };
-static const char * const emif0grps[] = { "emif0grp" };
-static const char * const emif1grps[] = { "emif1grp" };
-static const char * const uart0grps[] = { "uart0grp" };
-static const char * const mmc0grps[] = { "mmc0grp" };
-static const char * const spi0grps[] = { "spi0grp" };
-
-static const struct u300_pmx_func u300_pmx_functions[] = {
-	{
-		.name = "power",
-		.groups = powergrps,
-		.num_groups = ARRAY_SIZE(powergrps),
-		/* Mask is N/A */
-	},
-	{
-		.name = "emif0",
-		.groups = emif0grps,
-		.num_groups = ARRAY_SIZE(emif0grps),
-		.mask = emif0_mask,
-	},
-	{
-		.name = "emif1",
-		.groups = emif1grps,
-		.num_groups = ARRAY_SIZE(emif1grps),
-		.mask = emif1_mask,
-	},
-	{
-		.name = "uart0",
-		.groups = uart0grps,
-		.num_groups = ARRAY_SIZE(uart0grps),
-		.mask = uart0_mask,
-	},
-	{
-		.name = "mmc0",
-		.groups = mmc0grps,
-		.num_groups = ARRAY_SIZE(mmc0grps),
-		.mask = mmc0_mask,
-	},
-	{
-		.name = "spi0",
-		.groups = spi0grps,
-		.num_groups = ARRAY_SIZE(spi0grps),
-		.mask = spi0_mask,
-	},
-};
-
-static void u300_pmx_endisable(struct u300_pmx *upmx, unsigned selector,
-			       bool enable)
-{
-	u16 regval, val, mask;
-	int i;
-	const struct u300_pmx_mask *upmx_mask;
-
-	upmx_mask = u300_pmx_functions[selector].mask;
-	for (i = 0; i < ARRAY_SIZE(u300_pmx_registers); i++) {
-		if (enable)
-			val = upmx_mask->bits;
-		else
-			val = 0;
-
-		mask = upmx_mask->mask;
-		if (mask != 0) {
-			regval = readw(upmx->virtbase + u300_pmx_registers[i]);
-			regval &= ~mask;
-			regval |= val;
-			writew(regval, upmx->virtbase + u300_pmx_registers[i]);
-		}
-		upmx_mask++;
-	}
-}
-
-static int u300_pmx_set_mux(struct pinctrl_dev *pctldev, unsigned selector,
-			    unsigned group)
-{
-	struct u300_pmx *upmx;
-
-	/* There is nothing to do with the power pins */
-	if (selector == 0)
-		return 0;
-
-	upmx = pinctrl_dev_get_drvdata(pctldev);
-	u300_pmx_endisable(upmx, selector, true);
-
-	return 0;
-}
-
-static int u300_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
-{
-	return ARRAY_SIZE(u300_pmx_functions);
-}
-
-static const char *u300_pmx_get_func_name(struct pinctrl_dev *pctldev,
-					  unsigned selector)
-{
-	return u300_pmx_functions[selector].name;
-}
-
-static int u300_pmx_get_groups(struct pinctrl_dev *pctldev, unsigned selector,
-			       const char * const **groups,
-			       unsigned * const num_groups)
-{
-	*groups = u300_pmx_functions[selector].groups;
-	*num_groups = u300_pmx_functions[selector].num_groups;
-	return 0;
-}
-
-static const struct pinmux_ops u300_pmx_ops = {
-	.get_functions_count = u300_pmx_get_funcs_count,
-	.get_function_name = u300_pmx_get_func_name,
-	.get_function_groups = u300_pmx_get_groups,
-	.set_mux = u300_pmx_set_mux,
-};
-
-static int u300_pin_config_get(struct pinctrl_dev *pctldev, unsigned pin,
-			       unsigned long *config)
-{
-	struct pinctrl_gpio_range *range =
-		pinctrl_find_gpio_range_from_pin(pctldev, pin);
-
-	/* We get config for those pins we CAN get it for and that's it */
-	if (!range)
-		return -ENOTSUPP;
-
-	return u300_gpio_config_get(range->gc,
-				    (pin - range->pin_base + range->base),
-				    config);
-}
-
-static int u300_pin_config_set(struct pinctrl_dev *pctldev, unsigned pin,
-			       unsigned long *configs, unsigned num_configs)
-{
-	struct pinctrl_gpio_range *range =
-		pinctrl_find_gpio_range_from_pin(pctldev, pin);
-	int ret, i;
-
-	if (!range)
-		return -EINVAL;
-
-	for (i = 0; i < num_configs; i++) {
-		/* Note: none of these configurations take any argument */
-		ret = u300_gpio_config_set(range->gc,
-			(pin - range->pin_base + range->base),
-			pinconf_to_config_param(configs[i]));
-		if (ret)
-			return ret;
-	} /* for each config */
-
-	return 0;
-}
-
-static const struct pinconf_ops u300_pconf_ops = {
-	.is_generic = true,
-	.pin_config_get = u300_pin_config_get,
-	.pin_config_set = u300_pin_config_set,
-};
-
-static struct pinctrl_desc u300_pmx_desc = {
-	.name = DRIVER_NAME,
-	.pins = u300_pads,
-	.npins = ARRAY_SIZE(u300_pads),
-	.pctlops = &u300_pctrl_ops,
-	.pmxops = &u300_pmx_ops,
-	.confops = &u300_pconf_ops,
-	.owner = THIS_MODULE,
-};
-
-static int u300_pmx_probe(struct platform_device *pdev)
-{
-	struct u300_pmx *upmx;
-
-	/* Create state holders etc for this driver */
-	upmx = devm_kzalloc(&pdev->dev, sizeof(*upmx), GFP_KERNEL);
-	if (!upmx)
-		return -ENOMEM;
-
-	upmx->dev = &pdev->dev;
-
-	upmx->virtbase = devm_platform_ioremap_resource(pdev, 0);
-	if (IS_ERR(upmx->virtbase))
-		return PTR_ERR(upmx->virtbase);
-
-	upmx->pctl = devm_pinctrl_register(&pdev->dev, &u300_pmx_desc, upmx);
-	if (IS_ERR(upmx->pctl)) {
-		dev_err(&pdev->dev, "could not register U300 pinmux driver\n");
-		return PTR_ERR(upmx->pctl);
-	}
-
-	platform_set_drvdata(pdev, upmx);
-
-	dev_info(&pdev->dev, "initialized U300 pin control driver\n");
-
-	return 0;
-}
-
-static const struct of_device_id u300_pinctrl_match[] = {
-	{ .compatible = "stericsson,pinctrl-u300" },
-	{},
-};
-
-
-static struct platform_driver u300_pmx_driver = {
-	.driver = {
-		.name = DRIVER_NAME,
-		.of_match_table = u300_pinctrl_match,
-	},
-	.probe = u300_pmx_probe,
-};
-
-static int __init u300_pmx_init(void)
-{
-	return platform_driver_register(&u300_pmx_driver);
-}
-arch_initcall(u300_pmx_init);
-
-static void __exit u300_pmx_exit(void)
-{
-	platform_driver_unregister(&u300_pmx_driver);
-}
-module_exit(u300_pmx_exit);
-
-MODULE_AUTHOR("Linus Walleij <linus.walleij@linaro.org>");
-MODULE_DESCRIPTION("U300 pin control driver");
-MODULE_LICENSE("GPL v2");
-- 
2.29.2


^ permalink raw reply related	[flat|nested] 22+ messages in thread

* [PATCH 5/5] pinctrl: remove ste u300 driver
@ 2021-01-20 13:20   ` Arnd Bergmann
  0 siblings, 0 replies; 22+ messages in thread
From: Arnd Bergmann @ 2021-01-20 13:20 UTC (permalink / raw)
  To: linux-arm-kernel, linux-kernel, linux-gpio, Linus Walleij
  Cc: Bartosz Golaszewski, Arnd Bergmann

From: Arnd Bergmann <arnd@arndb.de>

The ST-Ericsson U300 platform is getting removed, so this driver is no
longer needed.

Cc: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
---
 drivers/pinctrl/Kconfig        |    6 -
 drivers/pinctrl/Makefile       |    1 -
 drivers/pinctrl/pinctrl-u300.c | 1111 --------------------------------
 3 files changed, 1118 deletions(-)
 delete mode 100644 drivers/pinctrl/pinctrl-u300.c

diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index 9ddbf14d9536..03c62e1cb395 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -271,12 +271,6 @@ config PINCTRL_STMFX
 	  and configuring push-pull, open-drain, and can also be used as
 	  interrupt-controller.
 
-config PINCTRL_U300
-	bool "U300 pin controller driver"
-	depends on ARCH_U300
-	select PINMUX
-	select GENERIC_PINCONF
-
 config PINCTRL_MAX77620
 	tristate "MAX77620/MAX20024 Pincontrol support"
 	depends on MFD_MAX77620 && OF
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index 10643440b467..efc96f25c8db 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -33,7 +33,6 @@ obj-$(CONFIG_PINCTRL_ROCKCHIP)	+= pinctrl-rockchip.o
 obj-$(CONFIG_PINCTRL_SINGLE)	+= pinctrl-single.o
 obj-$(CONFIG_PINCTRL_SX150X)	+= pinctrl-sx150x.o
 obj-$(CONFIG_ARCH_TEGRA)	+= tegra/
-obj-$(CONFIG_PINCTRL_U300)	+= pinctrl-u300.o
 obj-$(CONFIG_PINCTRL_XWAY)	+= pinctrl-xway.o
 obj-$(CONFIG_PINCTRL_LANTIQ)	+= pinctrl-lantiq.o
 obj-$(CONFIG_PINCTRL_LPC18XX)	+= pinctrl-lpc18xx.o
diff --git a/drivers/pinctrl/pinctrl-u300.c b/drivers/pinctrl/pinctrl-u300.c
deleted file mode 100644
index cc306448259e..000000000000
--- a/drivers/pinctrl/pinctrl-u300.c
+++ /dev/null
@@ -1,1111 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Driver for the U300 pin controller
- *
- * Based on the original U300 padmux functions
- * Copyright (C) 2009-2011 ST-Ericsson AB
- * Author: Martin Persson <martin.persson@stericsson.com>
- * Author: Linus Walleij <linus.walleij@linaro.org>
- *
- * The DB3350 design and control registers are oriented around pads rather than
- * pins, so we enumerate the pads we can mux rather than actual pins. The pads
- * are connected to different pins in different packaging types, so it would
- * be confusing.
- */
-#include <linux/init.h>
-#include <linux/module.h>
-#include <linux/mod_devicetable.h>
-#include <linux/platform_device.h>
-#include <linux/io.h>
-#include <linux/slab.h>
-#include <linux/err.h>
-#include <linux/pinctrl/pinctrl.h>
-#include <linux/pinctrl/pinmux.h>
-#include <linux/pinctrl/pinconf.h>
-#include <linux/pinctrl/pinconf-generic.h>
-#include "pinctrl-coh901.h"
-
-/*
- * Register definitions for the U300 Padmux control registers in the
- * system controller
- */
-
-/* PAD MUX Control register 1 (LOW) 16bit (R/W) */
-#define U300_SYSCON_PMC1LR					0x007C
-#define U300_SYSCON_PMC1LR_MASK					0xFFFF
-#define U300_SYSCON_PMC1LR_CDI_MASK				0xC000
-#define U300_SYSCON_PMC1LR_CDI_CDI				0x0000
-#define U300_SYSCON_PMC1LR_CDI_EMIF				0x4000
-/* For BS335 */
-#define U300_SYSCON_PMC1LR_CDI_CDI2				0x8000
-#define U300_SYSCON_PMC1LR_CDI_WCDMA_APP_GPIO			0xC000
-/* For BS365 */
-#define U300_SYSCON_PMC1LR_CDI_GPIO				0x8000
-#define U300_SYSCON_PMC1LR_CDI_WCDMA				0xC000
-/* Common defs */
-#define U300_SYSCON_PMC1LR_PDI_MASK				0x3000
-#define U300_SYSCON_PMC1LR_PDI_PDI				0x0000
-#define U300_SYSCON_PMC1LR_PDI_EGG				0x1000
-#define U300_SYSCON_PMC1LR_PDI_WCDMA				0x3000
-#define U300_SYSCON_PMC1LR_MMCSD_MASK				0x0C00
-#define U300_SYSCON_PMC1LR_MMCSD_MMCSD				0x0000
-#define U300_SYSCON_PMC1LR_MMCSD_MSPRO				0x0400
-#define U300_SYSCON_PMC1LR_MMCSD_DSP				0x0800
-#define U300_SYSCON_PMC1LR_MMCSD_WCDMA				0x0C00
-#define U300_SYSCON_PMC1LR_ETM_MASK				0x0300
-#define U300_SYSCON_PMC1LR_ETM_ACC				0x0000
-#define U300_SYSCON_PMC1LR_ETM_APP				0x0100
-#define U300_SYSCON_PMC1LR_EMIF_1_CS2_MASK			0x00C0
-#define U300_SYSCON_PMC1LR_EMIF_1_CS2_STATIC			0x0000
-#define U300_SYSCON_PMC1LR_EMIF_1_CS2_NFIF			0x0040
-#define U300_SYSCON_PMC1LR_EMIF_1_CS2_SDRAM			0x0080
-#define U300_SYSCON_PMC1LR_EMIF_1_CS2_STATIC_2GB		0x00C0
-#define U300_SYSCON_PMC1LR_EMIF_1_CS1_MASK			0x0030
-#define U300_SYSCON_PMC1LR_EMIF_1_CS1_STATIC			0x0000
-#define U300_SYSCON_PMC1LR_EMIF_1_CS1_NFIF			0x0010
-#define U300_SYSCON_PMC1LR_EMIF_1_CS1_SDRAM			0x0020
-#define U300_SYSCON_PMC1LR_EMIF_1_CS1_SEMI			0x0030
-#define U300_SYSCON_PMC1LR_EMIF_1_CS0_MASK			0x000C
-#define U300_SYSCON_PMC1LR_EMIF_1_CS0_STATIC			0x0000
-#define U300_SYSCON_PMC1LR_EMIF_1_CS0_NFIF			0x0004
-#define U300_SYSCON_PMC1LR_EMIF_1_CS0_SDRAM			0x0008
-#define U300_SYSCON_PMC1LR_EMIF_1_CS0_SEMI			0x000C
-#define U300_SYSCON_PMC1LR_EMIF_1_MASK				0x0003
-#define U300_SYSCON_PMC1LR_EMIF_1_STATIC			0x0000
-#define U300_SYSCON_PMC1LR_EMIF_1_SDRAM0			0x0001
-#define U300_SYSCON_PMC1LR_EMIF_1_SDRAM1			0x0002
-#define U300_SYSCON_PMC1LR_EMIF_1				0x0003
-/* PAD MUX Control register 2 (HIGH) 16bit (R/W) */
-#define U300_SYSCON_PMC1HR					0x007E
-#define U300_SYSCON_PMC1HR_MASK					0xFFFF
-#define U300_SYSCON_PMC1HR_MISC_2_MASK				0xC000
-#define U300_SYSCON_PMC1HR_MISC_2_APP_GPIO			0x0000
-#define U300_SYSCON_PMC1HR_MISC_2_MSPRO				0x4000
-#define U300_SYSCON_PMC1HR_MISC_2_DSP				0x8000
-#define U300_SYSCON_PMC1HR_MISC_2_AAIF				0xC000
-#define U300_SYSCON_PMC1HR_APP_GPIO_2_MASK			0x3000
-#define U300_SYSCON_PMC1HR_APP_GPIO_2_APP_GPIO			0x0000
-#define U300_SYSCON_PMC1HR_APP_GPIO_2_NFIF			0x1000
-#define U300_SYSCON_PMC1HR_APP_GPIO_2_DSP			0x2000
-#define U300_SYSCON_PMC1HR_APP_GPIO_2_AAIF			0x3000
-#define U300_SYSCON_PMC1HR_APP_GPIO_1_MASK			0x0C00
-#define U300_SYSCON_PMC1HR_APP_GPIO_1_APP_GPIO			0x0000
-#define U300_SYSCON_PMC1HR_APP_GPIO_1_MMC			0x0400
-#define U300_SYSCON_PMC1HR_APP_GPIO_1_DSP			0x0800
-#define U300_SYSCON_PMC1HR_APP_GPIO_1_AAIF			0x0C00
-#define U300_SYSCON_PMC1HR_APP_SPI_CS_2_MASK			0x0300
-#define U300_SYSCON_PMC1HR_APP_SPI_CS_2_APP_GPIO		0x0000
-#define U300_SYSCON_PMC1HR_APP_SPI_CS_2_SPI			0x0100
-#define U300_SYSCON_PMC1HR_APP_SPI_CS_2_AAIF			0x0300
-#define U300_SYSCON_PMC1HR_APP_SPI_CS_1_MASK			0x00C0
-#define U300_SYSCON_PMC1HR_APP_SPI_CS_1_APP_GPIO		0x0000
-#define U300_SYSCON_PMC1HR_APP_SPI_CS_1_SPI			0x0040
-#define U300_SYSCON_PMC1HR_APP_SPI_CS_1_AAIF			0x00C0
-#define U300_SYSCON_PMC1HR_APP_SPI_2_MASK			0x0030
-#define U300_SYSCON_PMC1HR_APP_SPI_2_APP_GPIO			0x0000
-#define U300_SYSCON_PMC1HR_APP_SPI_2_SPI			0x0010
-#define U300_SYSCON_PMC1HR_APP_SPI_2_DSP			0x0020
-#define U300_SYSCON_PMC1HR_APP_SPI_2_AAIF			0x0030
-#define U300_SYSCON_PMC1HR_APP_UART0_2_MASK			0x000C
-#define U300_SYSCON_PMC1HR_APP_UART0_2_APP_GPIO			0x0000
-#define U300_SYSCON_PMC1HR_APP_UART0_2_UART0			0x0004
-#define U300_SYSCON_PMC1HR_APP_UART0_2_NFIF_CS			0x0008
-#define U300_SYSCON_PMC1HR_APP_UART0_2_AAIF			0x000C
-#define U300_SYSCON_PMC1HR_APP_UART0_1_MASK			0x0003
-#define U300_SYSCON_PMC1HR_APP_UART0_1_APP_GPIO			0x0000
-#define U300_SYSCON_PMC1HR_APP_UART0_1_UART0			0x0001
-#define U300_SYSCON_PMC1HR_APP_UART0_1_AAIF			0x0003
-/* Padmux 2 control */
-#define U300_SYSCON_PMC2R					0x100
-#define U300_SYSCON_PMC2R_APP_MISC_0_MASK			0x00C0
-#define U300_SYSCON_PMC2R_APP_MISC_0_APP_GPIO			0x0000
-#define U300_SYSCON_PMC2R_APP_MISC_0_EMIF_SDRAM			0x0040
-#define U300_SYSCON_PMC2R_APP_MISC_0_MMC			0x0080
-#define U300_SYSCON_PMC2R_APP_MISC_0_CDI2			0x00C0
-#define U300_SYSCON_PMC2R_APP_MISC_1_MASK			0x0300
-#define U300_SYSCON_PMC2R_APP_MISC_1_APP_GPIO			0x0000
-#define U300_SYSCON_PMC2R_APP_MISC_1_EMIF_SDRAM			0x0100
-#define U300_SYSCON_PMC2R_APP_MISC_1_MMC			0x0200
-#define U300_SYSCON_PMC2R_APP_MISC_1_CDI2			0x0300
-#define U300_SYSCON_PMC2R_APP_MISC_2_MASK			0x0C00
-#define U300_SYSCON_PMC2R_APP_MISC_2_APP_GPIO			0x0000
-#define U300_SYSCON_PMC2R_APP_MISC_2_EMIF_SDRAM			0x0400
-#define U300_SYSCON_PMC2R_APP_MISC_2_MMC			0x0800
-#define U300_SYSCON_PMC2R_APP_MISC_2_CDI2			0x0C00
-#define U300_SYSCON_PMC2R_APP_MISC_3_MASK			0x3000
-#define U300_SYSCON_PMC2R_APP_MISC_3_APP_GPIO			0x0000
-#define U300_SYSCON_PMC2R_APP_MISC_3_EMIF_SDRAM			0x1000
-#define U300_SYSCON_PMC2R_APP_MISC_3_MMC			0x2000
-#define U300_SYSCON_PMC2R_APP_MISC_3_CDI2			0x3000
-#define U300_SYSCON_PMC2R_APP_MISC_4_MASK			0xC000
-#define U300_SYSCON_PMC2R_APP_MISC_4_APP_GPIO			0x0000
-#define U300_SYSCON_PMC2R_APP_MISC_4_EMIF_SDRAM			0x4000
-#define U300_SYSCON_PMC2R_APP_MISC_4_MMC			0x8000
-#define U300_SYSCON_PMC2R_APP_MISC_4_ACC_GPIO			0xC000
-/* TODO: More SYSCON registers missing */
-#define U300_SYSCON_PMC3R					0x10C
-#define U300_SYSCON_PMC3R_APP_MISC_11_MASK			0xC000
-#define U300_SYSCON_PMC3R_APP_MISC_11_SPI			0x4000
-#define U300_SYSCON_PMC3R_APP_MISC_10_MASK			0x3000
-#define U300_SYSCON_PMC3R_APP_MISC_10_SPI			0x1000
-/* TODO: Missing other configs */
-#define U300_SYSCON_PMC4R					0x168
-#define U300_SYSCON_PMC4R_APP_MISC_12_MASK			0x0003
-#define U300_SYSCON_PMC4R_APP_MISC_12_APP_GPIO			0x0000
-#define U300_SYSCON_PMC4R_APP_MISC_13_MASK			0x000C
-#define U300_SYSCON_PMC4R_APP_MISC_13_CDI			0x0000
-#define U300_SYSCON_PMC4R_APP_MISC_13_SMIA			0x0004
-#define U300_SYSCON_PMC4R_APP_MISC_13_SMIA2			0x0008
-#define U300_SYSCON_PMC4R_APP_MISC_13_APP_GPIO			0x000C
-#define U300_SYSCON_PMC4R_APP_MISC_14_MASK			0x0030
-#define U300_SYSCON_PMC4R_APP_MISC_14_CDI			0x0000
-#define U300_SYSCON_PMC4R_APP_MISC_14_SMIA			0x0010
-#define U300_SYSCON_PMC4R_APP_MISC_14_CDI2			0x0020
-#define U300_SYSCON_PMC4R_APP_MISC_14_APP_GPIO			0x0030
-#define U300_SYSCON_PMC4R_APP_MISC_16_MASK			0x0300
-#define U300_SYSCON_PMC4R_APP_MISC_16_APP_GPIO_13		0x0000
-#define U300_SYSCON_PMC4R_APP_MISC_16_APP_UART1_CTS		0x0100
-#define U300_SYSCON_PMC4R_APP_MISC_16_EMIF_1_STATIC_CS5_N	0x0200
-
-#define DRIVER_NAME "pinctrl-u300"
-
-/*
- * The DB3350 has 467 pads, I have enumerated the pads clockwise around the
- * edges of the silicon, finger by finger. LTCORNER upper left is pad 0.
- * Data taken from the PadRing chart, arranged like this:
- *
- *   0 ..... 104
- * 466        105
- *   .        .
- *   .        .
- * 358        224
- *  357 .... 225
- */
-#define U300_NUM_PADS 467
-
-/* Pad names for the pinmux subsystem */
-static const struct pinctrl_pin_desc u300_pads[] = {
-	/* Pads along the top edge of the chip */
-	PINCTRL_PIN(0, "P PAD VDD 28"),
-	PINCTRL_PIN(1, "P PAD GND 28"),
-	PINCTRL_PIN(2, "PO SIM RST N"),
-	PINCTRL_PIN(3, "VSSIO 25"),
-	PINCTRL_PIN(4, "VSSA ADDA ESDSUB"),
-	PINCTRL_PIN(5, "PWR VSSCOMMON"),
-	PINCTRL_PIN(6, "PI ADC I1 POS"),
-	PINCTRL_PIN(7, "PI ADC I1 NEG"),
-	PINCTRL_PIN(8, "PWR VSSAD0"),
-	PINCTRL_PIN(9, "PWR VCCAD0"),
-	PINCTRL_PIN(10, "PI ADC Q1 NEG"),
-	PINCTRL_PIN(11, "PI ADC Q1 POS"),
-	PINCTRL_PIN(12, "PWR VDDAD"),
-	PINCTRL_PIN(13, "PWR GNDAD"),
-	PINCTRL_PIN(14, "PI ADC I2 POS"),
-	PINCTRL_PIN(15, "PI ADC I2 NEG"),
-	PINCTRL_PIN(16, "PWR VSSAD1"),
-	PINCTRL_PIN(17, "PWR VCCAD1"),
-	PINCTRL_PIN(18, "PI ADC Q2 NEG"),
-	PINCTRL_PIN(19, "PI ADC Q2 POS"),
-	PINCTRL_PIN(20, "VSSA ADDA ESDSUB"),
-	PINCTRL_PIN(21, "PWR VCCGPAD"),
-	PINCTRL_PIN(22, "PI TX POW"),
-	PINCTRL_PIN(23, "PWR VSSGPAD"),
-	PINCTRL_PIN(24, "PO DAC I POS"),
-	PINCTRL_PIN(25, "PO DAC I NEG"),
-	PINCTRL_PIN(26, "PO DAC Q POS"),
-	PINCTRL_PIN(27, "PO DAC Q NEG"),
-	PINCTRL_PIN(28, "PWR VSSDA"),
-	PINCTRL_PIN(29, "PWR VCCDA"),
-	PINCTRL_PIN(30, "VSSA ADDA ESDSUB"),
-	PINCTRL_PIN(31, "P PAD VDDIO 11"),
-	PINCTRL_PIN(32, "PI PLL 26 FILTVDD"),
-	PINCTRL_PIN(33, "PI PLL 26 VCONT"),
-	PINCTRL_PIN(34, "PWR AGNDPLL2V5 32 13"),
-	PINCTRL_PIN(35, "PWR AVDDPLL2V5 32 13"),
-	PINCTRL_PIN(36, "VDDA PLL ESD"),
-	PINCTRL_PIN(37, "VSSA PLL ESD"),
-	PINCTRL_PIN(38, "VSS PLL"),
-	PINCTRL_PIN(39, "VDDC PLL"),
-	PINCTRL_PIN(40, "PWR AGNDPLL2V5 26 60"),
-	PINCTRL_PIN(41, "PWR AVDDPLL2V5 26 60"),
-	PINCTRL_PIN(42, "PWR AVDDPLL2V5 26 208"),
-	PINCTRL_PIN(43, "PWR AGNDPLL2V5 26 208"),
-	PINCTRL_PIN(44, "PWR AVDDPLL2V5 13 208"),
-	PINCTRL_PIN(45, "PWR AGNDPLL2V5 13 208"),
-	PINCTRL_PIN(46, "P PAD VSSIO 11"),
-	PINCTRL_PIN(47, "P PAD VSSIO 12"),
-	PINCTRL_PIN(48, "PI POW RST N"),
-	PINCTRL_PIN(49, "VDDC IO"),
-	PINCTRL_PIN(50, "P PAD VDDIO 16"),
-	PINCTRL_PIN(51, "PO RF WCDMA EN 4"),
-	PINCTRL_PIN(52, "PO RF WCDMA EN 3"),
-	PINCTRL_PIN(53, "PO RF WCDMA EN 2"),
-	PINCTRL_PIN(54, "PO RF WCDMA EN 1"),
-	PINCTRL_PIN(55, "PO RF WCDMA EN 0"),
-	PINCTRL_PIN(56, "PO GSM PA ENABLE"),
-	PINCTRL_PIN(57, "PO RF DATA STRB"),
-	PINCTRL_PIN(58, "PO RF DATA2"),
-	PINCTRL_PIN(59, "PIO RF DATA1"),
-	PINCTRL_PIN(60, "PIO RF DATA0"),
-	PINCTRL_PIN(61, "P PAD VDD 11"),
-	PINCTRL_PIN(62, "P PAD GND 11"),
-	PINCTRL_PIN(63, "P PAD VSSIO 16"),
-	PINCTRL_PIN(64, "P PAD VDDIO 18"),
-	PINCTRL_PIN(65, "PO RF CTRL STRB2"),
-	PINCTRL_PIN(66, "PO RF CTRL STRB1"),
-	PINCTRL_PIN(67, "PO RF CTRL STRB0"),
-	PINCTRL_PIN(68, "PIO RF CTRL DATA"),
-	PINCTRL_PIN(69, "PO RF CTRL CLK"),
-	PINCTRL_PIN(70, "PO TX ADC STRB"),
-	PINCTRL_PIN(71, "PO ANT SW 2"),
-	PINCTRL_PIN(72, "PO ANT SW 3"),
-	PINCTRL_PIN(73, "PO ANT SW 0"),
-	PINCTRL_PIN(74, "PO ANT SW 1"),
-	PINCTRL_PIN(75, "PO M CLKRQ"),
-	PINCTRL_PIN(76, "PI M CLK"),
-	PINCTRL_PIN(77, "PI RTC CLK"),
-	PINCTRL_PIN(78, "P PAD VDD 8"),
-	PINCTRL_PIN(79, "P PAD GND 8"),
-	PINCTRL_PIN(80, "P PAD VSSIO 13"),
-	PINCTRL_PIN(81, "P PAD VDDIO 13"),
-	PINCTRL_PIN(82, "PO SYS 1 CLK"),
-	PINCTRL_PIN(83, "PO SYS 2 CLK"),
-	PINCTRL_PIN(84, "PO SYS 0 CLK"),
-	PINCTRL_PIN(85, "PI SYS 0 CLKRQ"),
-	PINCTRL_PIN(86, "PO PWR MNGT CTRL 1"),
-	PINCTRL_PIN(87, "PO PWR MNGT CTRL 0"),
-	PINCTRL_PIN(88, "PO RESOUT2 RST N"),
-	PINCTRL_PIN(89, "PO RESOUT1 RST N"),
-	PINCTRL_PIN(90, "PO RESOUT0 RST N"),
-	PINCTRL_PIN(91, "PI SERVICE N"),
-	PINCTRL_PIN(92, "P PAD VDD 29"),
-	PINCTRL_PIN(93, "P PAD GND 29"),
-	PINCTRL_PIN(94, "P PAD VSSIO 8"),
-	PINCTRL_PIN(95, "P PAD VDDIO 8"),
-	PINCTRL_PIN(96, "PI EXT IRQ1 N"),
-	PINCTRL_PIN(97, "PI EXT IRQ0 N"),
-	PINCTRL_PIN(98, "PIO DC ON"),
-	PINCTRL_PIN(99, "PIO ACC APP I2C DATA"),
-	PINCTRL_PIN(100, "PIO ACC APP I2C CLK"),
-	PINCTRL_PIN(101, "P PAD VDD 12"),
-	PINCTRL_PIN(102, "P PAD GND 12"),
-	PINCTRL_PIN(103, "P PAD VSSIO 14"),
-	PINCTRL_PIN(104, "P PAD VDDIO 14"),
-	/* Pads along the right edge of the chip */
-	PINCTRL_PIN(105, "PIO APP I2C1 DATA"),
-	PINCTRL_PIN(106, "PIO APP I2C1 CLK"),
-	PINCTRL_PIN(107, "PO KEY OUT0"),
-	PINCTRL_PIN(108, "PO KEY OUT1"),
-	PINCTRL_PIN(109, "PO KEY OUT2"),
-	PINCTRL_PIN(110, "PO KEY OUT3"),
-	PINCTRL_PIN(111, "PO KEY OUT4"),
-	PINCTRL_PIN(112, "PI KEY IN0"),
-	PINCTRL_PIN(113, "PI KEY IN1"),
-	PINCTRL_PIN(114, "PI KEY IN2"),
-	PINCTRL_PIN(115, "P PAD VDDIO 15"),
-	PINCTRL_PIN(116, "P PAD VSSIO 15"),
-	PINCTRL_PIN(117, "P PAD GND 13"),
-	PINCTRL_PIN(118, "P PAD VDD 13"),
-	PINCTRL_PIN(119, "PI KEY IN3"),
-	PINCTRL_PIN(120, "PI KEY IN4"),
-	PINCTRL_PIN(121, "PI KEY IN5"),
-	PINCTRL_PIN(122, "PIO APP PCM I2S1 DATA B"),
-	PINCTRL_PIN(123, "PIO APP PCM I2S1 DATA A"),
-	PINCTRL_PIN(124, "PIO APP PCM I2S1 WS"),
-	PINCTRL_PIN(125, "PIO APP PCM I2S1 CLK"),
-	PINCTRL_PIN(126, "PIO APP PCM I2S0 DATA B"),
-	PINCTRL_PIN(127, "PIO APP PCM I2S0 DATA A"),
-	PINCTRL_PIN(128, "PIO APP PCM I2S0 WS"),
-	PINCTRL_PIN(129, "PIO APP PCM I2S0 CLK"),
-	PINCTRL_PIN(130, "P PAD VDD 17"),
-	PINCTRL_PIN(131, "P PAD GND 17"),
-	PINCTRL_PIN(132, "P PAD VSSIO 19"),
-	PINCTRL_PIN(133, "P PAD VDDIO 19"),
-	PINCTRL_PIN(134, "UART0 RTS"),
-	PINCTRL_PIN(135, "UART0 CTS"),
-	PINCTRL_PIN(136, "UART0 TX"),
-	PINCTRL_PIN(137, "UART0 RX"),
-	PINCTRL_PIN(138, "PIO ACC SPI DO"),
-	PINCTRL_PIN(139, "PIO ACC SPI DI"),
-	PINCTRL_PIN(140, "PIO ACC SPI CS0 N"),
-	PINCTRL_PIN(141, "PIO ACC SPI CS1 N"),
-	PINCTRL_PIN(142, "PIO ACC SPI CS2 N"),
-	PINCTRL_PIN(143, "PIO ACC SPI CLK"),
-	PINCTRL_PIN(144, "PO PDI EXT RST N"),
-	PINCTRL_PIN(145, "P PAD VDDIO 22"),
-	PINCTRL_PIN(146, "P PAD VSSIO 22"),
-	PINCTRL_PIN(147, "P PAD GND 18"),
-	PINCTRL_PIN(148, "P PAD VDD 18"),
-	PINCTRL_PIN(149, "PIO PDI C0"),
-	PINCTRL_PIN(150, "PIO PDI C1"),
-	PINCTRL_PIN(151, "PIO PDI C2"),
-	PINCTRL_PIN(152, "PIO PDI C3"),
-	PINCTRL_PIN(153, "PIO PDI C4"),
-	PINCTRL_PIN(154, "PIO PDI C5"),
-	PINCTRL_PIN(155, "PIO PDI D0"),
-	PINCTRL_PIN(156, "PIO PDI D1"),
-	PINCTRL_PIN(157, "PIO PDI D2"),
-	PINCTRL_PIN(158, "PIO PDI D3"),
-	PINCTRL_PIN(159, "P PAD VDDIO 21"),
-	PINCTRL_PIN(160, "P PAD VSSIO 21"),
-	PINCTRL_PIN(161, "PIO PDI D4"),
-	PINCTRL_PIN(162, "PIO PDI D5"),
-	PINCTRL_PIN(163, "PIO PDI D6"),
-	PINCTRL_PIN(164, "PIO PDI D7"),
-	PINCTRL_PIN(165, "PIO MS INS"),
-	PINCTRL_PIN(166, "MMC DATA DIR LS"),
-	PINCTRL_PIN(167, "MMC DATA 3"),
-	PINCTRL_PIN(168, "MMC DATA 2"),
-	PINCTRL_PIN(169, "MMC DATA 1"),
-	PINCTRL_PIN(170, "MMC DATA 0"),
-	PINCTRL_PIN(171, "MMC CMD DIR LS"),
-	PINCTRL_PIN(172, "P PAD VDD 27"),
-	PINCTRL_PIN(173, "P PAD GND 27"),
-	PINCTRL_PIN(174, "P PAD VSSIO 20"),
-	PINCTRL_PIN(175, "P PAD VDDIO 20"),
-	PINCTRL_PIN(176, "MMC CMD"),
-	PINCTRL_PIN(177, "MMC CLK"),
-	PINCTRL_PIN(178, "PIO APP GPIO 14"),
-	PINCTRL_PIN(179, "PIO APP GPIO 13"),
-	PINCTRL_PIN(180, "PIO APP GPIO 11"),
-	PINCTRL_PIN(181, "PIO APP GPIO 25"),
-	PINCTRL_PIN(182, "PIO APP GPIO 24"),
-	PINCTRL_PIN(183, "PIO APP GPIO 23"),
-	PINCTRL_PIN(184, "PIO APP GPIO 22"),
-	PINCTRL_PIN(185, "PIO APP GPIO 21"),
-	PINCTRL_PIN(186, "PIO APP GPIO 20"),
-	PINCTRL_PIN(187, "P PAD VDD 19"),
-	PINCTRL_PIN(188, "P PAD GND 19"),
-	PINCTRL_PIN(189, "P PAD VSSIO 23"),
-	PINCTRL_PIN(190, "P PAD VDDIO 23"),
-	PINCTRL_PIN(191, "PIO APP GPIO 19"),
-	PINCTRL_PIN(192, "PIO APP GPIO 18"),
-	PINCTRL_PIN(193, "PIO APP GPIO 17"),
-	PINCTRL_PIN(194, "PIO APP GPIO 16"),
-	PINCTRL_PIN(195, "PI CI D1"),
-	PINCTRL_PIN(196, "PI CI D0"),
-	PINCTRL_PIN(197, "PI CI HSYNC"),
-	PINCTRL_PIN(198, "PI CI VSYNC"),
-	PINCTRL_PIN(199, "PI CI EXT CLK"),
-	PINCTRL_PIN(200, "PO CI EXT RST N"),
-	PINCTRL_PIN(201, "P PAD VSSIO 43"),
-	PINCTRL_PIN(202, "P PAD VDDIO 43"),
-	PINCTRL_PIN(203, "PI CI D6"),
-	PINCTRL_PIN(204, "PI CI D7"),
-	PINCTRL_PIN(205, "PI CI D2"),
-	PINCTRL_PIN(206, "PI CI D3"),
-	PINCTRL_PIN(207, "PI CI D4"),
-	PINCTRL_PIN(208, "PI CI D5"),
-	PINCTRL_PIN(209, "PI CI D8"),
-	PINCTRL_PIN(210, "PI CI D9"),
-	PINCTRL_PIN(211, "P PAD VDD 20"),
-	PINCTRL_PIN(212, "P PAD GND 20"),
-	PINCTRL_PIN(213, "P PAD VSSIO 24"),
-	PINCTRL_PIN(214, "P PAD VDDIO 24"),
-	PINCTRL_PIN(215, "P PAD VDDIO 26"),
-	PINCTRL_PIN(216, "PO EMIF 1 A26"),
-	PINCTRL_PIN(217, "PO EMIF 1 A25"),
-	PINCTRL_PIN(218, "P PAD VSSIO 26"),
-	PINCTRL_PIN(219, "PO EMIF 1 A24"),
-	PINCTRL_PIN(220, "PO EMIF 1 A23"),
-	/* Pads along the bottom edge of the chip */
-	PINCTRL_PIN(221, "PO EMIF 1 A22"),
-	PINCTRL_PIN(222, "PO EMIF 1 A21"),
-	PINCTRL_PIN(223, "P PAD VDD 21"),
-	PINCTRL_PIN(224, "P PAD GND 21"),
-	PINCTRL_PIN(225, "P PAD VSSIO 27"),
-	PINCTRL_PIN(226, "P PAD VDDIO 27"),
-	PINCTRL_PIN(227, "PO EMIF 1 A20"),
-	PINCTRL_PIN(228, "PO EMIF 1 A19"),
-	PINCTRL_PIN(229, "PO EMIF 1 A18"),
-	PINCTRL_PIN(230, "PO EMIF 1 A17"),
-	PINCTRL_PIN(231, "P PAD VDDIO 28"),
-	PINCTRL_PIN(232, "P PAD VSSIO 28"),
-	PINCTRL_PIN(233, "PO EMIF 1 A16"),
-	PINCTRL_PIN(234, "PIO EMIF 1 D15"),
-	PINCTRL_PIN(235, "PO EMIF 1 A15"),
-	PINCTRL_PIN(236, "PIO EMIF 1 D14"),
-	PINCTRL_PIN(237, "P PAD VDD 22"),
-	PINCTRL_PIN(238, "P PAD GND 22"),
-	PINCTRL_PIN(239, "P PAD VSSIO 29"),
-	PINCTRL_PIN(240, "P PAD VDDIO 29"),
-	PINCTRL_PIN(241, "PO EMIF 1 A14"),
-	PINCTRL_PIN(242, "PIO EMIF 1 D13"),
-	PINCTRL_PIN(243, "PO EMIF 1 A13"),
-	PINCTRL_PIN(244, "PIO EMIF 1 D12"),
-	PINCTRL_PIN(245, "P PAD VSSIO 30"),
-	PINCTRL_PIN(246, "P PAD VDDIO 30"),
-	PINCTRL_PIN(247, "PO EMIF 1 A12"),
-	PINCTRL_PIN(248, "PIO EMIF 1 D11"),
-	PINCTRL_PIN(249, "PO EMIF 1 A11"),
-	PINCTRL_PIN(250, "PIO EMIF 1 D10"),
-	PINCTRL_PIN(251, "P PAD VSSIO 31"),
-	PINCTRL_PIN(252, "P PAD VDDIO 31"),
-	PINCTRL_PIN(253, "PO EMIF 1 A10"),
-	PINCTRL_PIN(254, "PIO EMIF 1 D09"),
-	PINCTRL_PIN(255, "PO EMIF 1 A09"),
-	PINCTRL_PIN(256, "P PAD VDDIO 32"),
-	PINCTRL_PIN(257, "P PAD VSSIO 32"),
-	PINCTRL_PIN(258, "P PAD GND 24"),
-	PINCTRL_PIN(259, "P PAD VDD 24"),
-	PINCTRL_PIN(260, "PIO EMIF 1 D08"),
-	PINCTRL_PIN(261, "PO EMIF 1 A08"),
-	PINCTRL_PIN(262, "PIO EMIF 1 D07"),
-	PINCTRL_PIN(263, "PO EMIF 1 A07"),
-	PINCTRL_PIN(264, "P PAD VDDIO 33"),
-	PINCTRL_PIN(265, "P PAD VSSIO 33"),
-	PINCTRL_PIN(266, "PIO EMIF 1 D06"),
-	PINCTRL_PIN(267, "PO EMIF 1 A06"),
-	PINCTRL_PIN(268, "PIO EMIF 1 D05"),
-	PINCTRL_PIN(269, "PO EMIF 1 A05"),
-	PINCTRL_PIN(270, "P PAD VDDIO 34"),
-	PINCTRL_PIN(271, "P PAD VSSIO 34"),
-	PINCTRL_PIN(272, "PIO EMIF 1 D04"),
-	PINCTRL_PIN(273, "PO EMIF 1 A04"),
-	PINCTRL_PIN(274, "PIO EMIF 1 D03"),
-	PINCTRL_PIN(275, "PO EMIF 1 A03"),
-	PINCTRL_PIN(276, "P PAD VDDIO 35"),
-	PINCTRL_PIN(277, "P PAD VSSIO 35"),
-	PINCTRL_PIN(278, "P PAD GND 23"),
-	PINCTRL_PIN(279, "P PAD VDD 23"),
-	PINCTRL_PIN(280, "PIO EMIF 1 D02"),
-	PINCTRL_PIN(281, "PO EMIF 1 A02"),
-	PINCTRL_PIN(282, "PIO EMIF 1 D01"),
-	PINCTRL_PIN(283, "PO EMIF 1 A01"),
-	PINCTRL_PIN(284, "P PAD VDDIO 36"),
-	PINCTRL_PIN(285, "P PAD VSSIO 36"),
-	PINCTRL_PIN(286, "PIO EMIF 1 D00"),
-	PINCTRL_PIN(287, "PO EMIF 1 BE1 N"),
-	PINCTRL_PIN(288, "PO EMIF 1 BE0 N"),
-	PINCTRL_PIN(289, "PO EMIF 1 ADV N"),
-	PINCTRL_PIN(290, "P PAD VDDIO 37"),
-	PINCTRL_PIN(291, "P PAD VSSIO 37"),
-	PINCTRL_PIN(292, "PO EMIF 1 SD CKE0"),
-	PINCTRL_PIN(293, "PO EMIF 1 OE N"),
-	PINCTRL_PIN(294, "PO EMIF 1 WE N"),
-	PINCTRL_PIN(295, "P PAD VDDIO 38"),
-	PINCTRL_PIN(296, "P PAD VSSIO 38"),
-	PINCTRL_PIN(297, "PO EMIF 1 CLK"),
-	PINCTRL_PIN(298, "PIO EMIF 1 SD CLK"),
-	PINCTRL_PIN(299, "P PAD VSSIO 45 (not bonded)"),
-	PINCTRL_PIN(300, "P PAD VDDIO 42"),
-	PINCTRL_PIN(301, "P PAD VSSIO 42"),
-	PINCTRL_PIN(302, "P PAD GND 31"),
-	PINCTRL_PIN(303, "P PAD VDD 31"),
-	PINCTRL_PIN(304, "PI EMIF 1 RET CLK"),
-	PINCTRL_PIN(305, "PI EMIF 1 WAIT N"),
-	PINCTRL_PIN(306, "PI EMIF 1 NFIF READY"),
-	PINCTRL_PIN(307, "PO EMIF 1 SD CKE1"),
-	PINCTRL_PIN(308, "PO EMIF 1 CS3 N"),
-	PINCTRL_PIN(309, "P PAD VDD 25"),
-	PINCTRL_PIN(310, "P PAD GND 25"),
-	PINCTRL_PIN(311, "P PAD VSSIO 39"),
-	PINCTRL_PIN(312, "P PAD VDDIO 39"),
-	PINCTRL_PIN(313, "PO EMIF 1 CS2 N"),
-	PINCTRL_PIN(314, "PO EMIF 1 CS1 N"),
-	PINCTRL_PIN(315, "PO EMIF 1 CS0 N"),
-	PINCTRL_PIN(316, "PO ETM TRACE PKT0"),
-	PINCTRL_PIN(317, "PO ETM TRACE PKT1"),
-	PINCTRL_PIN(318, "PO ETM TRACE PKT2"),
-	PINCTRL_PIN(319, "P PAD VDD 30"),
-	PINCTRL_PIN(320, "P PAD GND 30"),
-	PINCTRL_PIN(321, "P PAD VSSIO 44"),
-	PINCTRL_PIN(322, "P PAD VDDIO 44"),
-	PINCTRL_PIN(323, "PO ETM TRACE PKT3"),
-	PINCTRL_PIN(324, "PO ETM TRACE PKT4"),
-	PINCTRL_PIN(325, "PO ETM TRACE PKT5"),
-	PINCTRL_PIN(326, "PO ETM TRACE PKT6"),
-	PINCTRL_PIN(327, "PO ETM TRACE PKT7"),
-	PINCTRL_PIN(328, "PO ETM PIPE STAT0"),
-	PINCTRL_PIN(329, "P PAD VDD 26"),
-	PINCTRL_PIN(330, "P PAD GND 26"),
-	PINCTRL_PIN(331, "P PAD VSSIO 40"),
-	PINCTRL_PIN(332, "P PAD VDDIO 40"),
-	PINCTRL_PIN(333, "PO ETM PIPE STAT1"),
-	PINCTRL_PIN(334, "PO ETM PIPE STAT2"),
-	PINCTRL_PIN(335, "PO ETM TRACE CLK"),
-	PINCTRL_PIN(336, "PO ETM TRACE SYNC"),
-	PINCTRL_PIN(337, "PIO ACC GPIO 33"),
-	PINCTRL_PIN(338, "PIO ACC GPIO 32"),
-	PINCTRL_PIN(339, "PIO ACC GPIO 30"),
-	PINCTRL_PIN(340, "PIO ACC GPIO 29"),
-	PINCTRL_PIN(341, "P PAD VDDIO 17"),
-	PINCTRL_PIN(342, "P PAD VSSIO 17"),
-	PINCTRL_PIN(343, "P PAD GND 15"),
-	PINCTRL_PIN(344, "P PAD VDD 15"),
-	PINCTRL_PIN(345, "PIO ACC GPIO 28"),
-	PINCTRL_PIN(346, "PIO ACC GPIO 27"),
-	PINCTRL_PIN(347, "PIO ACC GPIO 16"),
-	PINCTRL_PIN(348, "PI TAP TMS"),
-	PINCTRL_PIN(349, "PI TAP TDI"),
-	PINCTRL_PIN(350, "PO TAP TDO"),
-	PINCTRL_PIN(351, "PI TAP RST N"),
-	/* Pads along the left edge of the chip */
-	PINCTRL_PIN(352, "PI EMU MODE 0"),
-	PINCTRL_PIN(353, "PO TAP RET CLK"),
-	PINCTRL_PIN(354, "PI TAP CLK"),
-	PINCTRL_PIN(355, "PO EMIF 0 SD CS N"),
-	PINCTRL_PIN(356, "PO EMIF 0 SD CAS N"),
-	PINCTRL_PIN(357, "PO EMIF 0 SD WE N"),
-	PINCTRL_PIN(358, "P PAD VDDIO 1"),
-	PINCTRL_PIN(359, "P PAD VSSIO 1"),
-	PINCTRL_PIN(360, "P PAD GND 1"),
-	PINCTRL_PIN(361, "P PAD VDD 1"),
-	PINCTRL_PIN(362, "PO EMIF 0 SD CKE"),
-	PINCTRL_PIN(363, "PO EMIF 0 SD DQML"),
-	PINCTRL_PIN(364, "PO EMIF 0 SD DQMU"),
-	PINCTRL_PIN(365, "PO EMIF 0 SD RAS N"),
-	PINCTRL_PIN(366, "PIO EMIF 0 D15"),
-	PINCTRL_PIN(367, "PO EMIF 0 A15"),
-	PINCTRL_PIN(368, "PIO EMIF 0 D14"),
-	PINCTRL_PIN(369, "PO EMIF 0 A14"),
-	PINCTRL_PIN(370, "PIO EMIF 0 D13"),
-	PINCTRL_PIN(371, "PO EMIF 0 A13"),
-	PINCTRL_PIN(372, "P PAD VDDIO 2"),
-	PINCTRL_PIN(373, "P PAD VSSIO 2"),
-	PINCTRL_PIN(374, "P PAD GND 2"),
-	PINCTRL_PIN(375, "P PAD VDD 2"),
-	PINCTRL_PIN(376, "PIO EMIF 0 D12"),
-	PINCTRL_PIN(377, "PO EMIF 0 A12"),
-	PINCTRL_PIN(378, "PIO EMIF 0 D11"),
-	PINCTRL_PIN(379, "PO EMIF 0 A11"),
-	PINCTRL_PIN(380, "PIO EMIF 0 D10"),
-	PINCTRL_PIN(381, "PO EMIF 0 A10"),
-	PINCTRL_PIN(382, "PIO EMIF 0 D09"),
-	PINCTRL_PIN(383, "PO EMIF 0 A09"),
-	PINCTRL_PIN(384, "PIO EMIF 0 D08"),
-	PINCTRL_PIN(385, "PO EMIF 0 A08"),
-	PINCTRL_PIN(386, "PIO EMIF 0 D07"),
-	PINCTRL_PIN(387, "PO EMIF 0 A07"),
-	PINCTRL_PIN(388, "P PAD VDDIO 3"),
-	PINCTRL_PIN(389, "P PAD VSSIO 3"),
-	PINCTRL_PIN(390, "P PAD GND 3"),
-	PINCTRL_PIN(391, "P PAD VDD 3"),
-	PINCTRL_PIN(392, "PO EFUSE RDOUT1"),
-	PINCTRL_PIN(393, "PIO EMIF 0 D06"),
-	PINCTRL_PIN(394, "PO EMIF 0 A06"),
-	PINCTRL_PIN(395, "PIO EMIF 0 D05"),
-	PINCTRL_PIN(396, "PO EMIF 0 A05"),
-	PINCTRL_PIN(397, "PIO EMIF 0 D04"),
-	PINCTRL_PIN(398, "PO EMIF 0 A04"),
-	PINCTRL_PIN(399, "A PADS/A VDDCO1v82v5 GND 80U SF LIN VDDCO AF"),
-	PINCTRL_PIN(400, "PWR VDDCO AF"),
-	PINCTRL_PIN(401, "PWR EFUSE HV1"),
-	PINCTRL_PIN(402, "P PAD VSSIO 4"),
-	PINCTRL_PIN(403, "P PAD VDDIO 4"),
-	PINCTRL_PIN(404, "P PAD GND 4"),
-	PINCTRL_PIN(405, "P PAD VDD 4"),
-	PINCTRL_PIN(406, "PIO EMIF 0 D03"),
-	PINCTRL_PIN(407, "PO EMIF 0 A03"),
-	PINCTRL_PIN(408, "PWR EFUSE HV2"),
-	PINCTRL_PIN(409, "PWR EFUSE HV3"),
-	PINCTRL_PIN(410, "PIO EMIF 0 D02"),
-	PINCTRL_PIN(411, "PO EMIF 0 A02"),
-	PINCTRL_PIN(412, "PIO EMIF 0 D01"),
-	PINCTRL_PIN(413, "P PAD VDDIO 5"),
-	PINCTRL_PIN(414, "P PAD VSSIO 5"),
-	PINCTRL_PIN(415, "P PAD GND 5"),
-	PINCTRL_PIN(416, "P PAD VDD 5"),
-	PINCTRL_PIN(417, "PO EMIF 0 A01"),
-	PINCTRL_PIN(418, "PIO EMIF 0 D00"),
-	PINCTRL_PIN(419, "IF 0 SD CLK"),
-	PINCTRL_PIN(420, "APP SPI CLK"),
-	PINCTRL_PIN(421, "APP SPI DO"),
-	PINCTRL_PIN(422, "APP SPI DI"),
-	PINCTRL_PIN(423, "APP SPI CS0"),
-	PINCTRL_PIN(424, "APP SPI CS1"),
-	PINCTRL_PIN(425, "APP SPI CS2"),
-	PINCTRL_PIN(426, "PIO APP GPIO 10"),
-	PINCTRL_PIN(427, "P PAD VDDIO 41"),
-	PINCTRL_PIN(428, "P PAD VSSIO 41"),
-	PINCTRL_PIN(429, "P PAD GND 6"),
-	PINCTRL_PIN(430, "P PAD VDD 6"),
-	PINCTRL_PIN(431, "PIO ACC SDIO0 CMD"),
-	PINCTRL_PIN(432, "PIO ACC SDIO0 CK"),
-	PINCTRL_PIN(433, "PIO ACC SDIO0 D3"),
-	PINCTRL_PIN(434, "PIO ACC SDIO0 D2"),
-	PINCTRL_PIN(435, "PIO ACC SDIO0 D1"),
-	PINCTRL_PIN(436, "PIO ACC SDIO0 D0"),
-	PINCTRL_PIN(437, "PIO USB PU"),
-	PINCTRL_PIN(438, "PIO USB SP"),
-	PINCTRL_PIN(439, "PIO USB DAT VP"),
-	PINCTRL_PIN(440, "PIO USB SE0 VM"),
-	PINCTRL_PIN(441, "PIO USB OE"),
-	PINCTRL_PIN(442, "PIO USB SUSP"),
-	PINCTRL_PIN(443, "P PAD VSSIO 6"),
-	PINCTRL_PIN(444, "P PAD VDDIO 6"),
-	PINCTRL_PIN(445, "PIO USB PUEN"),
-	PINCTRL_PIN(446, "PIO ACC UART0 RX"),
-	PINCTRL_PIN(447, "PIO ACC UART0 TX"),
-	PINCTRL_PIN(448, "PIO ACC UART0 CTS"),
-	PINCTRL_PIN(449, "PIO ACC UART0 RTS"),
-	PINCTRL_PIN(450, "PIO ACC UART3 RX"),
-	PINCTRL_PIN(451, "PIO ACC UART3 TX"),
-	PINCTRL_PIN(452, "PIO ACC UART3 CTS"),
-	PINCTRL_PIN(453, "PIO ACC UART3 RTS"),
-	PINCTRL_PIN(454, "PIO ACC IRDA TX"),
-	PINCTRL_PIN(455, "P PAD VDDIO 7"),
-	PINCTRL_PIN(456, "P PAD VSSIO 7"),
-	PINCTRL_PIN(457, "P PAD GND 7"),
-	PINCTRL_PIN(458, "P PAD VDD 7"),
-	PINCTRL_PIN(459, "PIO ACC IRDA RX"),
-	PINCTRL_PIN(460, "PIO ACC PCM I2S CLK"),
-	PINCTRL_PIN(461, "PIO ACC PCM I2S WS"),
-	PINCTRL_PIN(462, "PIO ACC PCM I2S DATA A"),
-	PINCTRL_PIN(463, "PIO ACC PCM I2S DATA B"),
-	PINCTRL_PIN(464, "PO SIM CLK"),
-	PINCTRL_PIN(465, "PIO ACC IRDA SD"),
-	PINCTRL_PIN(466, "PIO SIM DATA"),
-};
-
-/**
- * @dev: a pointer back to containing device
- * @virtbase: the offset to the controller in virtual memory
- */
-struct u300_pmx {
-	struct device *dev;
-	struct pinctrl_dev *pctl;
-	void __iomem *virtbase;
-};
-
-/**
- * u300_pmx_registers - the array of registers read/written for each pinmux
- * shunt setting
- */
-static const u32 u300_pmx_registers[] = {
-	U300_SYSCON_PMC1LR,
-	U300_SYSCON_PMC1HR,
-	U300_SYSCON_PMC2R,
-	U300_SYSCON_PMC3R,
-	U300_SYSCON_PMC4R,
-};
-
-/**
- * struct u300_pin_group - describes a U300 pin group
- * @name: the name of this specific pin group
- * @pins: an array of discrete physical pins used in this group, taken
- *	from the driver-local pin enumeration space
- * @num_pins: the number of pins in this group array, i.e. the number of
- *	elements in .pins so we can iterate over that array
- */
-struct u300_pin_group {
-	const char *name;
-	const unsigned int *pins;
-	const unsigned num_pins;
-};
-
-/**
- * struct pmx_onmask - mask bits to enable/disable padmux
- * @mask: mask bits to disable
- * @val: mask bits to enable
- *
- * onmask lazy dog:
- * onmask = {
- *   {"PMC1LR" mask, "PMC1LR" value},
- *   {"PMC1HR" mask, "PMC1HR" value},
- *   {"PMC2R"  mask, "PMC2R"  value},
- *   {"PMC3R"  mask, "PMC3R"  value},
- *   {"PMC4R"  mask, "PMC4R"  value}
- * }
- */
-struct u300_pmx_mask {
-	u16 mask;
-	u16 bits;
-};
-
-/* The chip power pins are VDD, GND, VDDIO and VSSIO */
-static const unsigned power_pins[] = { 0, 1, 3, 31, 46, 47, 49, 50, 61, 62, 63,
-	64, 78, 79, 80, 81, 92, 93, 94, 95, 101, 102, 103, 104, 115, 116, 117,
-	118, 130, 131, 132, 133, 145, 146, 147, 148, 159, 160, 172, 173, 174,
-	175, 187, 188, 189, 190, 201, 202, 211, 212, 213, 214, 215, 218, 223,
-	224, 225, 226, 231, 232, 237, 238, 239, 240, 245, 246, 251, 252, 256,
-	257, 258, 259, 264, 265, 270, 271, 276, 277, 278, 279, 284, 285, 290,
-	291, 295, 296, 299, 300, 301, 302, 303, 309, 310, 311, 312, 319, 320,
-	321, 322, 329, 330, 331, 332, 341, 342, 343, 344, 358, 359, 360, 361,
-	372, 373, 374, 375, 388, 389, 390, 391, 402, 403, 404, 405, 413, 414,
-	415, 416, 427, 428, 429, 430, 443, 444, 455, 456, 457, 458 };
-static const unsigned emif0_pins[] = { 355, 356, 357, 362, 363, 364, 365, 366,
-	367, 368, 369, 370, 371, 376, 377, 378, 379, 380, 381, 382, 383, 384,
-	385, 386, 387, 393, 394, 395, 396, 397, 398, 406, 407, 410, 411, 412,
-	417, 418 };
-static const unsigned emif1_pins[] = { 216, 217, 219, 220, 221, 222, 227, 228,
-	229, 230, 233, 234, 235, 236, 241, 242, 243, 244, 247, 248, 249, 250,
-	253, 254, 255, 260, 261, 262, 263, 266, 267, 268, 269, 272, 273, 274,
-	275, 280, 281, 282, 283, 286, 287, 288, 289, 292, 293, 294, 297, 298,
-	304, 305, 306, 307, 308, 313, 314, 315 };
-static const unsigned uart0_pins[] = { 134, 135, 136, 137 };
-static const unsigned mmc0_pins[] = { 166, 167, 168, 169, 170, 171, 176, 177 };
-static const unsigned spi0_pins[] = { 420, 421, 422, 423, 424, 425 };
-
-static const struct u300_pmx_mask emif0_mask[] = {
-	{0, 0},
-	{0, 0},
-	{0, 0},
-	{0, 0},
-	{0, 0},
-};
-
-static const struct u300_pmx_mask emif1_mask[] = {
-	/*
-	 * This connects the SDRAM to CS2 and a NAND flash to
-	 * CS0 on the EMIF.
-	 */
-	{
-		U300_SYSCON_PMC1LR_EMIF_1_CS2_MASK |
-		U300_SYSCON_PMC1LR_EMIF_1_CS1_MASK |
-		U300_SYSCON_PMC1LR_EMIF_1_CS0_MASK |
-		U300_SYSCON_PMC1LR_EMIF_1_MASK,
-		U300_SYSCON_PMC1LR_EMIF_1_CS2_SDRAM |
-		U300_SYSCON_PMC1LR_EMIF_1_CS1_STATIC |
-		U300_SYSCON_PMC1LR_EMIF_1_CS0_NFIF |
-		U300_SYSCON_PMC1LR_EMIF_1_SDRAM0
-	},
-	{0, 0},
-	{0, 0},
-	{0, 0},
-	{0, 0},
-};
-
-static const struct u300_pmx_mask uart0_mask[] = {
-	{0, 0},
-	{
-		U300_SYSCON_PMC1HR_APP_UART0_1_MASK |
-		U300_SYSCON_PMC1HR_APP_UART0_2_MASK,
-		U300_SYSCON_PMC1HR_APP_UART0_1_UART0 |
-		U300_SYSCON_PMC1HR_APP_UART0_2_UART0
-	},
-	{0, 0},
-	{0, 0},
-	{0, 0},
-};
-
-static const struct u300_pmx_mask mmc0_mask[] = {
-	{ U300_SYSCON_PMC1LR_MMCSD_MASK, U300_SYSCON_PMC1LR_MMCSD_MMCSD},
-	{0, 0},
-	{0, 0},
-	{0, 0},
-	{ U300_SYSCON_PMC4R_APP_MISC_12_MASK,
-	  U300_SYSCON_PMC4R_APP_MISC_12_APP_GPIO }
-};
-
-static const struct u300_pmx_mask spi0_mask[] = {
-	{0, 0},
-	{
-		U300_SYSCON_PMC1HR_APP_SPI_2_MASK |
-		U300_SYSCON_PMC1HR_APP_SPI_CS_1_MASK |
-		U300_SYSCON_PMC1HR_APP_SPI_CS_2_MASK,
-		U300_SYSCON_PMC1HR_APP_SPI_2_SPI |
-		U300_SYSCON_PMC1HR_APP_SPI_CS_1_SPI |
-		U300_SYSCON_PMC1HR_APP_SPI_CS_2_SPI
-	},
-	{0, 0},
-	{0, 0},
-	{0, 0}
-};
-
-static const struct u300_pin_group u300_pin_groups[] = {
-	{
-		.name = "powergrp",
-		.pins = power_pins,
-		.num_pins = ARRAY_SIZE(power_pins),
-	},
-	{
-		.name = "emif0grp",
-		.pins = emif0_pins,
-		.num_pins = ARRAY_SIZE(emif0_pins),
-	},
-	{
-		.name = "emif1grp",
-		.pins = emif1_pins,
-		.num_pins = ARRAY_SIZE(emif1_pins),
-	},
-	{
-		.name = "uart0grp",
-		.pins = uart0_pins,
-		.num_pins = ARRAY_SIZE(uart0_pins),
-	},
-	{
-		.name = "mmc0grp",
-		.pins = mmc0_pins,
-		.num_pins = ARRAY_SIZE(mmc0_pins),
-	},
-	{
-		.name = "spi0grp",
-		.pins = spi0_pins,
-		.num_pins = ARRAY_SIZE(spi0_pins),
-	},
-};
-
-static int u300_get_groups_count(struct pinctrl_dev *pctldev)
-{
-	return ARRAY_SIZE(u300_pin_groups);
-}
-
-static const char *u300_get_group_name(struct pinctrl_dev *pctldev,
-				       unsigned selector)
-{
-	return u300_pin_groups[selector].name;
-}
-
-static int u300_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
-			       const unsigned **pins,
-			       unsigned *num_pins)
-{
-	*pins = u300_pin_groups[selector].pins;
-	*num_pins = u300_pin_groups[selector].num_pins;
-	return 0;
-}
-
-static void u300_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
-		   unsigned offset)
-{
-	seq_printf(s, " " DRIVER_NAME);
-}
-
-static const struct pinctrl_ops u300_pctrl_ops = {
-	.get_groups_count = u300_get_groups_count,
-	.get_group_name = u300_get_group_name,
-	.get_group_pins = u300_get_group_pins,
-	.pin_dbg_show = u300_pin_dbg_show,
-};
-
-/*
- * Here we define the available functions and their corresponding pin groups
- */
-
-/**
- * struct u300_pmx_func - describes U300 pinmux functions
- * @name: the name of this specific function
- * @groups: corresponding pin groups
- * @onmask: bits to set to enable this when doing pin muxing
- */
-struct u300_pmx_func {
-	const char *name;
-	const char * const *groups;
-	const unsigned num_groups;
-	const struct u300_pmx_mask *mask;
-};
-
-static const char * const powergrps[] = { "powergrp" };
-static const char * const emif0grps[] = { "emif0grp" };
-static const char * const emif1grps[] = { "emif1grp" };
-static const char * const uart0grps[] = { "uart0grp" };
-static const char * const mmc0grps[] = { "mmc0grp" };
-static const char * const spi0grps[] = { "spi0grp" };
-
-static const struct u300_pmx_func u300_pmx_functions[] = {
-	{
-		.name = "power",
-		.groups = powergrps,
-		.num_groups = ARRAY_SIZE(powergrps),
-		/* Mask is N/A */
-	},
-	{
-		.name = "emif0",
-		.groups = emif0grps,
-		.num_groups = ARRAY_SIZE(emif0grps),
-		.mask = emif0_mask,
-	},
-	{
-		.name = "emif1",
-		.groups = emif1grps,
-		.num_groups = ARRAY_SIZE(emif1grps),
-		.mask = emif1_mask,
-	},
-	{
-		.name = "uart0",
-		.groups = uart0grps,
-		.num_groups = ARRAY_SIZE(uart0grps),
-		.mask = uart0_mask,
-	},
-	{
-		.name = "mmc0",
-		.groups = mmc0grps,
-		.num_groups = ARRAY_SIZE(mmc0grps),
-		.mask = mmc0_mask,
-	},
-	{
-		.name = "spi0",
-		.groups = spi0grps,
-		.num_groups = ARRAY_SIZE(spi0grps),
-		.mask = spi0_mask,
-	},
-};
-
-static void u300_pmx_endisable(struct u300_pmx *upmx, unsigned selector,
-			       bool enable)
-{
-	u16 regval, val, mask;
-	int i;
-	const struct u300_pmx_mask *upmx_mask;
-
-	upmx_mask = u300_pmx_functions[selector].mask;
-	for (i = 0; i < ARRAY_SIZE(u300_pmx_registers); i++) {
-		if (enable)
-			val = upmx_mask->bits;
-		else
-			val = 0;
-
-		mask = upmx_mask->mask;
-		if (mask != 0) {
-			regval = readw(upmx->virtbase + u300_pmx_registers[i]);
-			regval &= ~mask;
-			regval |= val;
-			writew(regval, upmx->virtbase + u300_pmx_registers[i]);
-		}
-		upmx_mask++;
-	}
-}
-
-static int u300_pmx_set_mux(struct pinctrl_dev *pctldev, unsigned selector,
-			    unsigned group)
-{
-	struct u300_pmx *upmx;
-
-	/* There is nothing to do with the power pins */
-	if (selector == 0)
-		return 0;
-
-	upmx = pinctrl_dev_get_drvdata(pctldev);
-	u300_pmx_endisable(upmx, selector, true);
-
-	return 0;
-}
-
-static int u300_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
-{
-	return ARRAY_SIZE(u300_pmx_functions);
-}
-
-static const char *u300_pmx_get_func_name(struct pinctrl_dev *pctldev,
-					  unsigned selector)
-{
-	return u300_pmx_functions[selector].name;
-}
-
-static int u300_pmx_get_groups(struct pinctrl_dev *pctldev, unsigned selector,
-			       const char * const **groups,
-			       unsigned * const num_groups)
-{
-	*groups = u300_pmx_functions[selector].groups;
-	*num_groups = u300_pmx_functions[selector].num_groups;
-	return 0;
-}
-
-static const struct pinmux_ops u300_pmx_ops = {
-	.get_functions_count = u300_pmx_get_funcs_count,
-	.get_function_name = u300_pmx_get_func_name,
-	.get_function_groups = u300_pmx_get_groups,
-	.set_mux = u300_pmx_set_mux,
-};
-
-static int u300_pin_config_get(struct pinctrl_dev *pctldev, unsigned pin,
-			       unsigned long *config)
-{
-	struct pinctrl_gpio_range *range =
-		pinctrl_find_gpio_range_from_pin(pctldev, pin);
-
-	/* We get config for those pins we CAN get it for and that's it */
-	if (!range)
-		return -ENOTSUPP;
-
-	return u300_gpio_config_get(range->gc,
-				    (pin - range->pin_base + range->base),
-				    config);
-}
-
-static int u300_pin_config_set(struct pinctrl_dev *pctldev, unsigned pin,
-			       unsigned long *configs, unsigned num_configs)
-{
-	struct pinctrl_gpio_range *range =
-		pinctrl_find_gpio_range_from_pin(pctldev, pin);
-	int ret, i;
-
-	if (!range)
-		return -EINVAL;
-
-	for (i = 0; i < num_configs; i++) {
-		/* Note: none of these configurations take any argument */
-		ret = u300_gpio_config_set(range->gc,
-			(pin - range->pin_base + range->base),
-			pinconf_to_config_param(configs[i]));
-		if (ret)
-			return ret;
-	} /* for each config */
-
-	return 0;
-}
-
-static const struct pinconf_ops u300_pconf_ops = {
-	.is_generic = true,
-	.pin_config_get = u300_pin_config_get,
-	.pin_config_set = u300_pin_config_set,
-};
-
-static struct pinctrl_desc u300_pmx_desc = {
-	.name = DRIVER_NAME,
-	.pins = u300_pads,
-	.npins = ARRAY_SIZE(u300_pads),
-	.pctlops = &u300_pctrl_ops,
-	.pmxops = &u300_pmx_ops,
-	.confops = &u300_pconf_ops,
-	.owner = THIS_MODULE,
-};
-
-static int u300_pmx_probe(struct platform_device *pdev)
-{
-	struct u300_pmx *upmx;
-
-	/* Create state holders etc for this driver */
-	upmx = devm_kzalloc(&pdev->dev, sizeof(*upmx), GFP_KERNEL);
-	if (!upmx)
-		return -ENOMEM;
-
-	upmx->dev = &pdev->dev;
-
-	upmx->virtbase = devm_platform_ioremap_resource(pdev, 0);
-	if (IS_ERR(upmx->virtbase))
-		return PTR_ERR(upmx->virtbase);
-
-	upmx->pctl = devm_pinctrl_register(&pdev->dev, &u300_pmx_desc, upmx);
-	if (IS_ERR(upmx->pctl)) {
-		dev_err(&pdev->dev, "could not register U300 pinmux driver\n");
-		return PTR_ERR(upmx->pctl);
-	}
-
-	platform_set_drvdata(pdev, upmx);
-
-	dev_info(&pdev->dev, "initialized U300 pin control driver\n");
-
-	return 0;
-}
-
-static const struct of_device_id u300_pinctrl_match[] = {
-	{ .compatible = "stericsson,pinctrl-u300" },
-	{},
-};
-
-
-static struct platform_driver u300_pmx_driver = {
-	.driver = {
-		.name = DRIVER_NAME,
-		.of_match_table = u300_pinctrl_match,
-	},
-	.probe = u300_pmx_probe,
-};
-
-static int __init u300_pmx_init(void)
-{
-	return platform_driver_register(&u300_pmx_driver);
-}
-arch_initcall(u300_pmx_init);
-
-static void __exit u300_pmx_exit(void)
-{
-	platform_driver_unregister(&u300_pmx_driver);
-}
-module_exit(u300_pmx_exit);
-
-MODULE_AUTHOR("Linus Walleij <linus.walleij@linaro.org>");
-MODULE_DESCRIPTION("U300 pin control driver");
-MODULE_LICENSE("GPL v2");
-- 
2.29.2


_______________________________________________
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^ permalink raw reply related	[flat|nested] 22+ messages in thread

* Re: [PATCH 3/5] pinctrl: remove sirf atlas/prima drivers
  2021-01-20 13:20 ` [PATCH 3/5] pinctrl: remove sirf atlas/prima drivers Arnd Bergmann
@ 2021-01-20 21:30   ` Barry Song
  0 siblings, 0 replies; 22+ messages in thread
From: Barry Song @ 2021-01-20 21:30 UTC (permalink / raw)
  To: Arnd Bergmann
  Cc: linux-arm-kernel, LKML, Linux GPIO List, Linus Walleij,
	Bartosz Golaszewski, Arnd Bergmann

Arnd Bergmann <arnd@kernel.org> 于2021年1月21日周四 上午2:20写道:
>
> From: Arnd Bergmann <arnd@arndb.de>
>
> The CSR SiRF prima2/atlas platforms are getting removed, so this driver
> is no longer needed.
>
> Cc: Barry Song <baohua@kernel.org>
> Signed-off-by: Arnd Bergmann <arnd@arndb.de>

Acked-by: Barry Song <baohua@kernel.org>

> ---
>  .../devicetree/bindings/gpio/gpio-atlas7.txt  |   50 -
>  .../bindings/pinctrl/pinctrl-atlas7.txt       |  109 -
>  drivers/pinctrl/Kconfig                       |    8 -
>  drivers/pinctrl/Makefile                      |    1 -
>  drivers/pinctrl/sirf/Makefile                 |    7 -
>  drivers/pinctrl/sirf/pinctrl-atlas6.c         | 1137 ---
>  drivers/pinctrl/sirf/pinctrl-atlas7.c         | 6157 -----------------
>  drivers/pinctrl/sirf/pinctrl-prima2.c         | 1131 ---
>  drivers/pinctrl/sirf/pinctrl-sirf.c           |  894 ---
>  drivers/pinctrl/sirf/pinctrl-sirf.h           |  116 -
>  10 files changed, 9610 deletions(-)
>  delete mode 100644 Documentation/devicetree/bindings/gpio/gpio-atlas7.txt
>  delete mode 100644 Documentation/devicetree/bindings/pinctrl/pinctrl-atlas7.txt
>  delete mode 100644 drivers/pinctrl/sirf/Makefile
>  delete mode 100644 drivers/pinctrl/sirf/pinctrl-atlas6.c
>  delete mode 100644 drivers/pinctrl/sirf/pinctrl-atlas7.c
>  delete mode 100644 drivers/pinctrl/sirf/pinctrl-prima2.c
>  delete mode 100644 drivers/pinctrl/sirf/pinctrl-sirf.c
>  delete mode 100644 drivers/pinctrl/sirf/pinctrl-sirf.h
>
> diff --git a/Documentation/devicetree/bindings/gpio/gpio-atlas7.txt b/Documentation/devicetree/bindings/gpio/gpio-atlas7.txt
> deleted file mode 100644
> index d7e123fc90b5..000000000000
> --- a/Documentation/devicetree/bindings/gpio/gpio-atlas7.txt
> +++ /dev/null
> @@ -1,50 +0,0 @@
> -CSR SiRFatlas7 GPIO controller bindings
> -
> -Required properties:
> -- compatible   : "sirf,atlas7-gpio"
> -- reg          : Address range of the pinctrl registers
> -- interrupts   : Interrupts used by every GPIO group
> -- gpio-banks   : How many gpio banks on this controller
> -- gpio-controller : Indicates this device is a GPIO controller
> -- interrupt-controller  : Marks the device node as an interrupt controller
> -
> -The GPIO controller also acts as an interrupt controller. It uses the default
> -two cells specifier as described in Documentation/devicetree/bindings/
> -interrupt-controller/interrupts.txt.
> -
> -Example:
> -
> -       gpio_0: gpio_mediam@17040000 {
> -               compatible = "sirf,atlas7-gpio";
> -               reg = <0x17040000 0x1000>;
> -               interrupts = <0 13 0>, <0 14 0>;
> -
> -               #gpio-cells = <2>;
> -               #interrupt-cells = <2>;
> -
> -               gpio-controller;
> -               interrupt-controller;
> -
> -               gpio-banks = <2>;
> -               gpio-ranges = <&pinctrl 0 0 0>,
> -                               <&pinctrl 32 0 0>;
> -               gpio-ranges-group-names = "lvds_gpio_grp",
> -                                       "uart_nand_gpio_grp";
> -       };
> -
> -       leds {
> -               compatible = "gpio-leds";
> -
> -               led1 {
> -                       gpios = <&gpio_1 15 0>;
> -                       ...
> -               };
> -
> -               led2 {
> -                       gpios = <&gpio_2 34 0>;
> -                       ...
> -               };
> -       };
> -
> -Please refer to gpio.txt in this directory for details of the common
> -gpio properties used by devices.
> diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-atlas7.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-atlas7.txt
> deleted file mode 100644
> index fbdd1a716a1e..000000000000
> --- a/Documentation/devicetree/bindings/pinctrl/pinctrl-atlas7.txt
> +++ /dev/null
> @@ -1,109 +0,0 @@
> -CSR SiRFatlas7 pinmux controller
> -
> -Required properties:
> -- compatible   : "sirf,atlas7-ioc"
> -- reg          : Address range of the pinctrl registers
> -
> -For example, pinctrl might have properties like the following:
> -       pinctrl: ioc@18880000 {
> -                       compatible = "sirf,atlas7-ioc";
> -                       reg = <0x18880000 0x1000>;
> -
> -                       a_ac97_pmx: ac97@0 {
> -                               ac97 {
> -                                       groups = "audio_ac97_grp";
> -                                       function = "audio_ac97";
> -                               };
> -                       };
> -
> -                       ...
> -
> -                       sd2_pmx: sd2@0 {
> -                               sd2 {
> -                                       groups = "sd2_grp0";
> -                                       function = "sd2";
> -                               };
> -                       };
> -
> -                       ...
> -
> -
> -                       sample0_cfg: sample0@0 {
> -                               sample0 {
> -                                       pins = "ldd_0", "ldd_1";
> -                                       bias-pull-up;
> -                               };
> -                       };
> -
> -                       sample1_cfg: sample1@0 {
> -                               sample1 {
> -                                       pins = "ldd_2", "ldd_3";
> -                                       input-schmitt-enable;
> -                               };
> -                       };
> -
> -                       sample2_cfg: sample2@0 {
> -                               sample2 {
> -                                       groups = "uart4_nopause_grp";
> -                                       bias-pull-down;
> -                               };
> -                       };
> -
> -                       sample3_cfg: sample3@0 {
> -                               sample3 {
> -                                       pins = "ldd_4", "ldd_5";
> -                                       drive-strength = <2>;
> -                               };
> -                       };
> -       };
> -
> -Please refer to pinctrl-bindings.txt in this directory for details of the common
> -pinctrl bindings used by client devices.
> -
> -SiRFatlas7's pinmux nodes act as a container for an arbitrary number of subnodes.
> -Each of these subnodes represents some desired configuration for a group of pins.
> -
> -Required subnode-properties:
> -- groups : An array of strings. Each string contains the name of a group.
> -- function: A string containing the name of the function to mux to the
> -  group.
> -
> -  Valid values for group and function names can be found from looking at the
> -  group and function arrays in driver files:
> -  drivers/pinctrl/pinctrl-sirf.c
> -
> -For example, pinctrl might have subnodes like the following:
> -       sd0_pmx: sd0@0 {
> -               sd0 {
> -                       groups = "sd0_grp";
> -                       function = "sd0";
> -               };
> -       };
> -
> -       sd1_pmx0: sd1@0 {
> -               sd1 {
> -                       groups = "sd1_grp0";
> -                       function = "sd1_m0";
> -               };
> -       };
> -
> -       sd1_pmx1: sd1@1 {
> -               sd1 {
> -                       groups = "sd1_grp1";
> -                       function = "sd1_m1";
> -               };
> -       };
> -
> -For a specific board, if it wants to use sd1,
> -it can add the following to its board-specific .dts file.
> -sd1: sd@12340000 {
> -       pinctrl-names = "default";
> -       pinctrl-0 = <&sd1_pmx0>;
> -}
> -
> -or
> -
> -sd1: sd@12340000 {
> -       pinctrl-names = "default";
> -       pinctrl-0 = <&sd1_pmx1>;
> -}
> diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
> index 1c1fa681b96d..e176137dbf29 100644
> --- a/drivers/pinctrl/Kconfig
> +++ b/drivers/pinctrl/Kconfig
> @@ -226,14 +226,6 @@ config PINCTRL_SINGLE
>         help
>           This selects the device tree based generic pinctrl driver.
>
> -config PINCTRL_SIRF
> -       bool "CSR SiRFprimaII pin controller driver"
> -       depends on ARCH_SIRF
> -       select PINMUX
> -       select PINCONF
> -       select GENERIC_PINCONF
> -       select GPIOLIB_IRQCHIP
> -
>  config PINCTRL_SX150X
>         bool "Semtech SX150x I2C GPIO expander pinctrl driver"
>         depends on I2C=y
> diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
> index fef92794900d..f414846abe2d 100644
> --- a/drivers/pinctrl/Makefile
> +++ b/drivers/pinctrl/Makefile
> @@ -31,7 +31,6 @@ obj-$(CONFIG_PINCTRL_PIC32)   += pinctrl-pic32.o
>  obj-$(CONFIG_PINCTRL_PISTACHIO)        += pinctrl-pistachio.o
>  obj-$(CONFIG_PINCTRL_ROCKCHIP) += pinctrl-rockchip.o
>  obj-$(CONFIG_PINCTRL_SINGLE)   += pinctrl-single.o
> -obj-$(CONFIG_PINCTRL_SIRF)     += sirf/
>  obj-$(CONFIG_PINCTRL_SX150X)   += pinctrl-sx150x.o
>  obj-$(CONFIG_ARCH_TEGRA)       += tegra/
>  obj-$(CONFIG_PINCTRL_U300)     += pinctrl-u300.o
> diff --git a/drivers/pinctrl/sirf/Makefile b/drivers/pinctrl/sirf/Makefile
> deleted file mode 100644
> index 1ab0742075f6..000000000000
> --- a/drivers/pinctrl/sirf/Makefile
> +++ /dev/null
> @@ -1,7 +0,0 @@
> -# SPDX-License-Identifier: GPL-2.0-only
> -# CSR SiRFsoc pinmux support
> -
> -obj-y  += pinctrl-sirf.o
> -obj-y  += pinctrl-prima2.o
> -obj-y  += pinctrl-atlas6.o
> -obj-y  += pinctrl-atlas7.o
> diff --git a/drivers/pinctrl/sirf/pinctrl-atlas6.c b/drivers/pinctrl/sirf/pinctrl-atlas6.c
> deleted file mode 100644
> index ab35d59bfa04..000000000000
> --- a/drivers/pinctrl/sirf/pinctrl-atlas6.c
> +++ /dev/null
> @@ -1,1137 +0,0 @@
> -// SPDX-License-Identifier: GPL-2.0-or-later
> -/*
> - * pinctrl pads, groups, functions for CSR SiRFatlasVI
> - *
> - * Copyright (c) 2011 - 2014 Cambridge Silicon Radio Limited, a CSR plc group
> - * company.
> - */
> -
> -#include <linux/pinctrl/pinctrl.h>
> -#include <linux/bitops.h>
> -
> -#include "pinctrl-sirf.h"
> -
> -/*
> - * pad list for the pinmux subsystem
> - * refer to atlasVI_io_table_v0.93.xls
> - */
> -static const struct pinctrl_pin_desc sirfsoc_pads[] = {
> -       PINCTRL_PIN(0, "gpio0-0"),
> -       PINCTRL_PIN(1, "gpio0-1"),
> -       PINCTRL_PIN(2, "gpio0-2"),
> -       PINCTRL_PIN(3, "gpio0-3"),
> -       PINCTRL_PIN(4, "pwm0"),
> -       PINCTRL_PIN(5, "pwm1"),
> -       PINCTRL_PIN(6, "pwm2"),
> -       PINCTRL_PIN(7, "pwm3"),
> -       PINCTRL_PIN(8, "warm_rst_b"),
> -       PINCTRL_PIN(9, "odo_0"),
> -       PINCTRL_PIN(10, "odo_1"),
> -       PINCTRL_PIN(11, "dr_dir"),
> -       PINCTRL_PIN(12, "rts_0"),
> -       PINCTRL_PIN(13, "scl_1"),
> -       PINCTRL_PIN(14, "ntrst"),
> -       PINCTRL_PIN(15, "sda_1"),
> -       PINCTRL_PIN(16, "x_ldd[16]"),
> -       PINCTRL_PIN(17, "x_ldd[17]"),
> -       PINCTRL_PIN(18, "x_ldd[18]"),
> -       PINCTRL_PIN(19, "x_ldd[19]"),
> -       PINCTRL_PIN(20, "x_ldd[20]"),
> -       PINCTRL_PIN(21, "x_ldd[21]"),
> -       PINCTRL_PIN(22, "x_ldd[22]"),
> -       PINCTRL_PIN(23, "x_ldd[23]"),
> -       PINCTRL_PIN(24, "gps_sgn"),
> -       PINCTRL_PIN(25, "gps_mag"),
> -       PINCTRL_PIN(26, "gps_clk"),
> -       PINCTRL_PIN(27, "sd_cd_b_2"),
> -       PINCTRL_PIN(28, "sd_vcc_on_2"),
> -       PINCTRL_PIN(29, "sd_wp_b_2"),
> -       PINCTRL_PIN(30, "sd_clk_3"),
> -       PINCTRL_PIN(31, "sd_cmd_3"),
> -
> -       PINCTRL_PIN(32, "x_sd_dat_3[0]"),
> -       PINCTRL_PIN(33, "x_sd_dat_3[1]"),
> -       PINCTRL_PIN(34, "x_sd_dat_3[2]"),
> -       PINCTRL_PIN(35, "x_sd_dat_3[3]"),
> -       PINCTRL_PIN(36, "usb_clk"),
> -       PINCTRL_PIN(37, "usb_dir"),
> -       PINCTRL_PIN(38, "usb_nxt"),
> -       PINCTRL_PIN(39, "usb_stp"),
> -       PINCTRL_PIN(40, "usb_dat[7]"),
> -       PINCTRL_PIN(41, "usb_dat[6]"),
> -       PINCTRL_PIN(42, "x_cko_1"),
> -       PINCTRL_PIN(43, "spi_clk_1"),
> -       PINCTRL_PIN(44, "spi_dout_1"),
> -       PINCTRL_PIN(45, "spi_din_1"),
> -       PINCTRL_PIN(46, "spi_en_1"),
> -       PINCTRL_PIN(47, "x_txd_1"),
> -       PINCTRL_PIN(48, "x_txd_2"),
> -       PINCTRL_PIN(49, "x_rxd_1"),
> -       PINCTRL_PIN(50, "x_rxd_2"),
> -       PINCTRL_PIN(51, "x_usclk_0"),
> -       PINCTRL_PIN(52, "x_utxd_0"),
> -       PINCTRL_PIN(53, "x_urxd_0"),
> -       PINCTRL_PIN(54, "x_utfs_0"),
> -       PINCTRL_PIN(55, "x_urfs_0"),
> -       PINCTRL_PIN(56, "usb_dat5"),
> -       PINCTRL_PIN(57, "usb_dat4"),
> -       PINCTRL_PIN(58, "usb_dat3"),
> -       PINCTRL_PIN(59, "usb_dat2"),
> -       PINCTRL_PIN(60, "usb_dat1"),
> -       PINCTRL_PIN(61, "usb_dat0"),
> -       PINCTRL_PIN(62, "x_ldd[14]"),
> -       PINCTRL_PIN(63, "x_ldd[15]"),
> -
> -       PINCTRL_PIN(64, "x_gps_gpio"),
> -       PINCTRL_PIN(65, "x_ldd[13]"),
> -       PINCTRL_PIN(66, "x_df_we_b"),
> -       PINCTRL_PIN(67, "x_df_re_b"),
> -       PINCTRL_PIN(68, "x_txd_0"),
> -       PINCTRL_PIN(69, "x_rxd_0"),
> -       PINCTRL_PIN(70, "x_l_lck"),
> -       PINCTRL_PIN(71, "x_l_fck"),
> -       PINCTRL_PIN(72, "x_l_de"),
> -       PINCTRL_PIN(73, "x_ldd[0]"),
> -       PINCTRL_PIN(74, "x_ldd[1]"),
> -       PINCTRL_PIN(75, "x_ldd[2]"),
> -       PINCTRL_PIN(76, "x_ldd[3]"),
> -       PINCTRL_PIN(77, "x_ldd[4]"),
> -       PINCTRL_PIN(78, "x_cko_0"),
> -       PINCTRL_PIN(79, "x_ldd[5]"),
> -       PINCTRL_PIN(80, "x_ldd[6]"),
> -       PINCTRL_PIN(81, "x_ldd[7]"),
> -       PINCTRL_PIN(82, "x_ldd[8]"),
> -       PINCTRL_PIN(83, "x_ldd[9]"),
> -       PINCTRL_PIN(84, "x_ldd[10]"),
> -       PINCTRL_PIN(85, "x_ldd[11]"),
> -       PINCTRL_PIN(86, "x_ldd[12]"),
> -       PINCTRL_PIN(87, "x_vip_vsync"),
> -       PINCTRL_PIN(88, "x_vip_hsync"),
> -       PINCTRL_PIN(89, "x_vip_pxclk"),
> -       PINCTRL_PIN(90, "x_sda_0"),
> -       PINCTRL_PIN(91, "x_scl_0"),
> -       PINCTRL_PIN(92, "x_df_ry_by"),
> -       PINCTRL_PIN(93, "x_df_cs_b[1]"),
> -       PINCTRL_PIN(94, "x_df_cs_b[0]"),
> -       PINCTRL_PIN(95, "x_l_pclk"),
> -
> -       PINCTRL_PIN(96, "x_df_dqs"),
> -       PINCTRL_PIN(97, "x_df_wp_b"),
> -       PINCTRL_PIN(98, "ac97_sync"),
> -       PINCTRL_PIN(99, "ac97_bit_clk "),
> -       PINCTRL_PIN(100, "ac97_dout"),
> -       PINCTRL_PIN(101, "ac97_din"),
> -       PINCTRL_PIN(102, "x_rtc_io"),
> -
> -       PINCTRL_PIN(103, "x_usb1_dp"),
> -       PINCTRL_PIN(104, "x_usb1_dn"),
> -};
> -
> -static const struct sirfsoc_muxmask lcd_16bits_sirfsoc_muxmask[] = {
> -       {
> -               .group = 1,
> -               .mask = BIT(30) | BIT(31),
> -       }, {
> -               .group = 2,
> -               .mask = BIT(1) | BIT(6) | BIT(7) | BIT(8) | BIT(9) |
> -                       BIT(10) | BIT(11) | BIT(12) | BIT(13) | BIT(15) |
> -                       BIT(16) | BIT(17) | BIT(18) | BIT(19) |
> -                       BIT(20) | BIT(21) | BIT(22) | BIT(31),
> -       },
> -};
> -
> -static const struct sirfsoc_padmux lcd_16bits_padmux = {
> -       .muxmask_counts = ARRAY_SIZE(lcd_16bits_sirfsoc_muxmask),
> -       .muxmask = lcd_16bits_sirfsoc_muxmask,
> -       .ctrlreg = SIRFSOC_RSC_PIN_MUX,
> -       .funcmask = BIT(4),
> -       .funcval = 0,
> -};
> -
> -static const unsigned lcd_16bits_pins[] = { 62, 63, 65, 70, 71, 72, 73, 74, 75,
> -       76, 77, 79, 80, 81, 82, 83, 84, 85, 86, 95 };
> -
> -static const struct sirfsoc_muxmask lcd_18bits_muxmask[] = {
> -       {
> -               .group = 2,
> -               .mask = BIT(1) | BIT(6) | BIT(7) | BIT(8) | BIT(9) |
> -                       BIT(10) | BIT(11) | BIT(12) | BIT(13) | BIT(15) |
> -                       BIT(16) | BIT(17) | BIT(18) | BIT(19) |
> -                       BIT(20) | BIT(21) | BIT(22) | BIT(31),
> -       }, {
> -               .group = 1,
> -               .mask = BIT(30) | BIT(31),
> -       }, {
> -               .group = 0,
> -               .mask = BIT(16) | BIT(17),
> -       },
> -};
> -
> -static const struct sirfsoc_padmux lcd_18bits_padmux = {
> -       .muxmask_counts = ARRAY_SIZE(lcd_18bits_muxmask),
> -       .muxmask = lcd_18bits_muxmask,
> -       .ctrlreg = SIRFSOC_RSC_PIN_MUX,
> -       .funcmask = BIT(4) | BIT(15),
> -       .funcval = 0,
> -};
> -
> -static const unsigned lcd_18bits_pins[] = { 16, 17, 62, 63, 65, 70, 71, 72, 73,
> -       74, 75, 76, 77, 79, 80, 81, 82, 83, 84, 85, 86, 95 };
> -
> -static const struct sirfsoc_muxmask lcd_24bits_muxmask[] = {
> -       {
> -               .group = 2,
> -               .mask = BIT(1) | BIT(6) | BIT(7) | BIT(8) | BIT(9) |
> -                       BIT(10) | BIT(11) | BIT(12) | BIT(13) | BIT(15) |
> -                       BIT(16) | BIT(17) | BIT(18) | BIT(19) |
> -                       BIT(20) | BIT(21) | BIT(22) | BIT(31),
> -       }, {
> -               .group = 1,
> -               .mask = BIT(30) | BIT(31),
> -       }, {
> -               .group = 0,
> -               .mask = BIT(16) | BIT(17) | BIT(18) | BIT(19) | BIT(20) |
> -                       BIT(21) | BIT(22) | BIT(23),
> -       },
> -};
> -
> -static const struct sirfsoc_padmux lcd_24bits_padmux = {
> -       .muxmask_counts = ARRAY_SIZE(lcd_24bits_muxmask),
> -       .muxmask = lcd_24bits_muxmask,
> -       .ctrlreg = SIRFSOC_RSC_PIN_MUX,
> -       .funcmask = BIT(4) | BIT(15),
> -       .funcval = 0,
> -};
> -
> -static const unsigned lcd_24bits_pins[] = { 16, 17, 18, 19, 20, 21, 22, 23, 62,
> -       63, 65, 70, 71, 72, 73, 74, 75, 76, 77, 79, 80, 81, 82, 83, 84,
> -       85, 86, 95};
> -
> -static const struct sirfsoc_muxmask lcdrom_muxmask[] = {
> -       {
> -               .group = 2,
> -               .mask = BIT(1) | BIT(6) | BIT(7) | BIT(8) | BIT(9) | BIT(10) |
> -                       BIT(11) | BIT(12) | BIT(13) | BIT(15) | BIT(16) |
> -                       BIT(17) | BIT(18) | BIT(19) |
> -                       BIT(20) | BIT(21) | BIT(22) | BIT(31),
> -       }, {
> -               .group = 1,
> -               .mask = BIT(30) | BIT(31),
> -       }, {
> -               .group = 0,
> -               .mask = BIT(8),
> -       },
> -};
> -
> -static const struct sirfsoc_padmux lcdrom_padmux = {
> -       .muxmask_counts = ARRAY_SIZE(lcdrom_muxmask),
> -       .muxmask = lcdrom_muxmask,
> -       .ctrlreg = SIRFSOC_RSC_PIN_MUX,
> -       .funcmask = BIT(4),
> -       .funcval = BIT(4),
> -};
> -
> -static const unsigned lcdrom_pins[] = { 8, 62, 63, 65, 70, 71, 72, 73, 74, 75,
> -       76, 77, 79, 80, 81, 82, 83, 84, 85, 86, 95};
> -
> -static const struct sirfsoc_muxmask uart0_muxmask[] = {
> -       {
> -               .group = 0,
> -               .mask = BIT(12),
> -       }, {
> -               .group = 1,
> -               .mask = BIT(23),
> -       }, {
> -               .group = 2,
> -               .mask = BIT(4) | BIT(5),
> -       },
> -};
> -
> -static const struct sirfsoc_padmux uart0_padmux = {
> -       .muxmask_counts = ARRAY_SIZE(uart0_muxmask),
> -       .muxmask = uart0_muxmask,
> -       .ctrlreg = SIRFSOC_RSC_PIN_MUX,
> -       .funcmask = BIT(9),
> -       .funcval = BIT(9),
> -};
> -
> -static const unsigned uart0_pins[] = { 12, 55, 68, 69 };
> -
> -static const struct sirfsoc_muxmask uart0_nostreamctrl_muxmask[] = {
> -       {
> -               .group = 2,
> -               .mask = BIT(4) | BIT(5),
> -       },
> -};
> -
> -static const struct sirfsoc_padmux uart0_nostreamctrl_padmux = {
> -       .muxmask_counts = ARRAY_SIZE(uart0_nostreamctrl_muxmask),
> -       .muxmask = uart0_nostreamctrl_muxmask,
> -};
> -
> -static const unsigned uart0_nostreamctrl_pins[] = { 68, 69 };
> -
> -static const struct sirfsoc_muxmask uart1_muxmask[] = {
> -       {
> -               .group = 1,
> -               .mask = BIT(15) | BIT(17),
> -       },
> -};
> -
> -static const struct sirfsoc_padmux uart1_padmux = {
> -       .muxmask_counts = ARRAY_SIZE(uart1_muxmask),
> -       .muxmask = uart1_muxmask,
> -};
> -
> -static const unsigned uart1_pins[] = { 47, 49 };
> -
> -static const struct sirfsoc_muxmask uart2_muxmask[] = {
> -       {
> -               .group = 0,
> -               .mask = BIT(10) | BIT(14),
> -       }, {
> -               .group = 1,
> -               .mask = BIT(16) | BIT(18),
> -       },
> -};
> -
> -static const struct sirfsoc_padmux uart2_padmux = {
> -       .muxmask_counts = ARRAY_SIZE(uart2_muxmask),
> -       .muxmask = uart2_muxmask,
> -       .ctrlreg = SIRFSOC_RSC_PIN_MUX,
> -       .funcmask = BIT(10),
> -       .funcval = BIT(10),
> -};
> -
> -static const unsigned uart2_pins[] = { 10, 14, 48, 50 };
> -
> -static const struct sirfsoc_muxmask uart2_nostreamctrl_muxmask[] = {
> -       {
> -               .group = 1,
> -               .mask = BIT(16) | BIT(18),
> -       },
> -};
> -
> -static const struct sirfsoc_padmux uart2_nostreamctrl_padmux = {
> -       .muxmask_counts = ARRAY_SIZE(uart2_nostreamctrl_muxmask),
> -       .muxmask = uart2_nostreamctrl_muxmask,
> -};
> -
> -static const unsigned uart2_nostreamctrl_pins[] = { 48, 50 };
> -
> -static const struct sirfsoc_muxmask sdmmc3_muxmask[] = {
> -       {
> -               .group = 0,
> -               .mask = BIT(30) | BIT(31),
> -       }, {
> -               .group = 1,
> -               .mask = BIT(0) | BIT(1) | BIT(2) | BIT(3),
> -       },
> -};
> -
> -static const struct sirfsoc_padmux sdmmc3_padmux = {
> -       .muxmask_counts = ARRAY_SIZE(sdmmc3_muxmask),
> -       .muxmask = sdmmc3_muxmask,
> -       .ctrlreg = SIRFSOC_RSC_PIN_MUX,
> -       .funcmask = BIT(7),
> -       .funcval = 0,
> -};
> -
> -static const unsigned sdmmc3_pins[] = { 30, 31, 32, 33, 34, 35 };
> -
> -static const struct sirfsoc_muxmask spi0_muxmask[] = {
> -       {
> -               .group = 0,
> -               .mask = BIT(30),
> -       }, {
> -               .group = 1,
> -               .mask = BIT(0) | BIT(2) | BIT(3),
> -       },
> -};
> -
> -static const struct sirfsoc_padmux spi0_padmux = {
> -       .muxmask_counts = ARRAY_SIZE(spi0_muxmask),
> -       .muxmask = spi0_muxmask,
> -       .ctrlreg = SIRFSOC_RSC_PIN_MUX,
> -       .funcmask = BIT(7),
> -       .funcval = BIT(7),
> -};
> -
> -static const unsigned spi0_pins[] = { 30, 32, 34, 35 };
> -
> -static const struct sirfsoc_muxmask cko1_muxmask[] = {
> -       {
> -               .group = 1,
> -               .mask = BIT(10),
> -       },
> -};
> -
> -static const struct sirfsoc_padmux cko1_padmux = {
> -       .muxmask_counts = ARRAY_SIZE(cko1_muxmask),
> -       .muxmask = cko1_muxmask,
> -       .ctrlreg = SIRFSOC_RSC_PIN_MUX,
> -       .funcmask = BIT(3),
> -       .funcval = 0,
> -};
> -
> -static const unsigned cko1_pins[] = { 42 };
> -
> -static const struct sirfsoc_muxmask i2s_mclk_muxmask[] = {
> -       {
> -               .group = 1,
> -               .mask = BIT(10),
> -       },
> -};
> -
> -static const struct sirfsoc_padmux i2s_mclk_padmux = {
> -       .muxmask_counts = ARRAY_SIZE(i2s_mclk_muxmask),
> -       .muxmask = i2s_mclk_muxmask,
> -       .ctrlreg = SIRFSOC_RSC_PIN_MUX,
> -       .funcmask = BIT(3),
> -       .funcval = BIT(3),
> -};
> -
> -static const unsigned i2s_mclk_pins[] = { 42 };
> -
> -static const struct sirfsoc_muxmask i2s_ext_clk_input_muxmask[] = {
> -       {
> -               .group = 1,
> -               .mask = BIT(19),
> -       },
> -};
> -
> -static const struct sirfsoc_padmux i2s_ext_clk_input_padmux = {
> -       .muxmask_counts = ARRAY_SIZE(i2s_ext_clk_input_muxmask),
> -       .muxmask = i2s_ext_clk_input_muxmask,
> -       .ctrlreg = SIRFSOC_RSC_PIN_MUX,
> -       .funcmask = BIT(2),
> -       .funcval = BIT(2),
> -};
> -
> -static const unsigned i2s_ext_clk_input_pins[] = { 51 };
> -
> -static const struct sirfsoc_muxmask i2s_muxmask[] = {
> -       {
> -               .group = 3,
> -               .mask = BIT(2) | BIT(3) | BIT(4) | BIT(5),
> -       },
> -};
> -
> -static const struct sirfsoc_padmux i2s_padmux = {
> -       .muxmask_counts = ARRAY_SIZE(i2s_muxmask),
> -       .muxmask = i2s_muxmask,
> -       .ctrlreg = SIRFSOC_RSC_PIN_MUX,
> -};
> -
> -static const unsigned i2s_pins[] = { 98, 99, 100, 101 };
> -
> -static const struct sirfsoc_muxmask i2s_no_din_muxmask[] = {
> -       {
> -               .group = 3,
> -               .mask = BIT(2) | BIT(3) | BIT(4),
> -       },
> -};
> -
> -static const struct sirfsoc_padmux i2s_no_din_padmux = {
> -       .muxmask_counts = ARRAY_SIZE(i2s_no_din_muxmask),
> -       .muxmask = i2s_no_din_muxmask,
> -       .ctrlreg = SIRFSOC_RSC_PIN_MUX,
> -};
> -
> -static const unsigned i2s_no_din_pins[] = { 98, 99, 100 };
> -
> -static const struct sirfsoc_muxmask i2s_6chn_muxmask[] = {
> -       {
> -               .group = 3,
> -               .mask = BIT(2) | BIT(3) | BIT(4) | BIT(5),
> -       },
> -};
> -
> -static const struct sirfsoc_padmux i2s_6chn_padmux = {
> -       .muxmask_counts = ARRAY_SIZE(i2s_6chn_muxmask),
> -       .muxmask = i2s_6chn_muxmask,
> -       .ctrlreg = SIRFSOC_RSC_PIN_MUX,
> -       .funcmask = BIT(1) | BIT(9),
> -       .funcval = BIT(1) | BIT(9),
> -};
> -
> -static const unsigned i2s_6chn_pins[] = { 52, 55, 98, 99, 100, 101 };
> -
> -static const struct sirfsoc_muxmask ac97_muxmask[] = {
> -       {
> -               .group = 3,
> -               .mask = BIT(2) | BIT(3) | BIT(4) | BIT(5),
> -       },
> -};
> -
> -static const struct sirfsoc_padmux ac97_padmux = {
> -       .muxmask_counts = ARRAY_SIZE(ac97_muxmask),
> -       .muxmask = ac97_muxmask,
> -};
> -
> -static const unsigned ac97_pins[] = { 98, 99, 100, 101 };
> -
> -static const struct sirfsoc_muxmask spi1_muxmask[] = {
> -       {
> -               .group = 1,
> -               .mask = BIT(11) | BIT(12) | BIT(13) | BIT(14),
> -       },
> -};
> -
> -static const struct sirfsoc_padmux spi1_padmux = {
> -       .muxmask_counts = ARRAY_SIZE(spi1_muxmask),
> -       .muxmask = spi1_muxmask,
> -       .ctrlreg = SIRFSOC_RSC_PIN_MUX,
> -       .funcmask = BIT(16),
> -       .funcval = 0,
> -};
> -
> -static const unsigned spi1_pins[] = { 43, 44, 45, 46 };
> -
> -static const struct sirfsoc_muxmask sdmmc1_muxmask[] = {
> -       {
> -               .group = 2,
> -               .mask = BIT(2) | BIT(3),
> -       },
> -};
> -
> -static const struct sirfsoc_padmux sdmmc1_padmux = {
> -       .muxmask_counts = ARRAY_SIZE(sdmmc1_muxmask),
> -       .muxmask = sdmmc1_muxmask,
> -       .ctrlreg = SIRFSOC_RSC_PIN_MUX,
> -       .funcmask = BIT(5),
> -       .funcval = BIT(5),
> -};
> -
> -static const unsigned sdmmc1_pins[] = { 66, 67 };
> -
> -static const struct sirfsoc_muxmask gps_muxmask[] = {
> -       {
> -               .group = 0,
> -               .mask = BIT(24) | BIT(25) | BIT(26),
> -       },
> -};
> -
> -static const struct sirfsoc_padmux gps_padmux = {
> -       .muxmask_counts = ARRAY_SIZE(gps_muxmask),
> -       .muxmask = gps_muxmask,
> -       .ctrlreg = SIRFSOC_RSC_PIN_MUX,
> -       .funcmask = BIT(13),
> -       .funcval = 0,
> -};
> -
> -static const unsigned gps_pins[] = { 24, 25, 26 };
> -
> -static const struct sirfsoc_muxmask sdmmc5_muxmask[] = {
> -       {
> -               .group = 0,
> -               .mask = BIT(24) | BIT(25) | BIT(26),
> -       },
> -};
> -
> -static const struct sirfsoc_padmux sdmmc5_padmux = {
> -       .muxmask_counts = ARRAY_SIZE(sdmmc5_muxmask),
> -       .muxmask = sdmmc5_muxmask,
> -       .ctrlreg = SIRFSOC_RSC_PIN_MUX,
> -       .funcmask = BIT(13),
> -       .funcval = BIT(13),
> -};
> -
> -static const unsigned sdmmc5_pins[] = { 24, 25, 26 };
> -
> -static const struct sirfsoc_muxmask usp0_muxmask[] = {
> -       {
> -               .group = 1,
> -               .mask = BIT(19) | BIT(20) | BIT(21) | BIT(22) | BIT(23),
> -       },
> -};
> -
> -static const struct sirfsoc_padmux usp0_padmux = {
> -       .muxmask_counts = ARRAY_SIZE(usp0_muxmask),
> -       .muxmask = usp0_muxmask,
> -       .ctrlreg = SIRFSOC_RSC_PIN_MUX,
> -       .funcmask = BIT(1) | BIT(2) | BIT(9),
> -       .funcval = 0,
> -};
> -
> -static const unsigned usp0_pins[] = { 51, 52, 53, 54, 55 };
> -
> -static const struct sirfsoc_muxmask usp0_only_utfs_muxmask[] = {
> -       {
> -               .group = 1,
> -               .mask = BIT(19) | BIT(20) | BIT(21) | BIT(22),
> -       },
> -};
> -
> -static const struct sirfsoc_padmux usp0_only_utfs_padmux = {
> -       .muxmask_counts = ARRAY_SIZE(usp0_only_utfs_muxmask),
> -       .muxmask = usp0_only_utfs_muxmask,
> -       .ctrlreg = SIRFSOC_RSC_PIN_MUX,
> -       .funcmask = BIT(1) | BIT(2) | BIT(6),
> -       .funcval = 0,
> -};
> -
> -static const unsigned usp0_only_utfs_pins[] = { 51, 52, 53, 54 };
> -
> -static const struct sirfsoc_muxmask usp0_only_urfs_muxmask[] = {
> -       {
> -               .group = 1,
> -               .mask = BIT(19) | BIT(20) | BIT(21) | BIT(23),
> -       },
> -};
> -
> -static const struct sirfsoc_padmux usp0_only_urfs_padmux = {
> -       .muxmask_counts = ARRAY_SIZE(usp0_only_urfs_muxmask),
> -       .muxmask = usp0_only_urfs_muxmask,
> -       .ctrlreg = SIRFSOC_RSC_PIN_MUX,
> -       .funcmask = BIT(1) | BIT(2) | BIT(9),
> -       .funcval = 0,
> -};
> -
> -static const unsigned usp0_only_urfs_pins[] = { 51, 52, 53, 55 };
> -
> -static const struct sirfsoc_muxmask usp0_uart_nostreamctrl_muxmask[] = {
> -       {
> -               .group = 1,
> -               .mask = BIT(20) | BIT(21),
> -       },
> -};
> -
> -static const struct sirfsoc_padmux usp0_uart_nostreamctrl_padmux = {
> -       .muxmask_counts = ARRAY_SIZE(usp0_uart_nostreamctrl_muxmask),
> -       .muxmask = usp0_uart_nostreamctrl_muxmask,
> -};
> -
> -static const unsigned usp0_uart_nostreamctrl_pins[] = { 52, 53 };
> -static const struct sirfsoc_muxmask usp1_muxmask[] = {
> -       {
> -               .group = 0,
> -               .mask = BIT(15),
> -       }, {
> -               .group = 1,
> -               .mask = BIT(11) | BIT(12) | BIT(13) | BIT(14),
> -       },
> -};
> -
> -static const struct sirfsoc_padmux usp1_padmux = {
> -       .muxmask_counts = ARRAY_SIZE(usp1_muxmask),
> -       .muxmask = usp1_muxmask,
> -       .ctrlreg = SIRFSOC_RSC_PIN_MUX,
> -       .funcmask = BIT(16),
> -       .funcval = BIT(16),
> -};
> -
> -static const unsigned usp1_pins[] = { 15, 43, 44, 45, 46 };
> -
> -static const struct sirfsoc_muxmask usp1_uart_nostreamctrl_muxmask[] = {
> -       {
> -               .group = 1,
> -               .mask = BIT(12) | BIT(13),
> -       },
> -};
> -
> -static const struct sirfsoc_padmux usp1_uart_nostreamctrl_padmux = {
> -       .muxmask_counts = ARRAY_SIZE(usp1_uart_nostreamctrl_muxmask),
> -       .muxmask = usp1_uart_nostreamctrl_muxmask,
> -       .ctrlreg = SIRFSOC_RSC_PIN_MUX,
> -       .funcmask = BIT(16),
> -       .funcval = BIT(16),
> -};
> -
> -static const unsigned usp1_uart_nostreamctrl_pins[] = { 44, 45 };
> -
> -static const struct sirfsoc_muxmask nand_muxmask[] = {
> -       {
> -               .group = 2,
> -               .mask = BIT(2) | BIT(3) | BIT(28) | BIT(29) | BIT(30),
> -       }, {
> -               .group = 3,
> -               .mask = BIT(0) | BIT(1),
> -       },
> -};
> -
> -static const struct sirfsoc_padmux nand_padmux = {
> -       .muxmask_counts = ARRAY_SIZE(nand_muxmask),
> -       .muxmask = nand_muxmask,
> -       .ctrlreg = SIRFSOC_RSC_PIN_MUX,
> -       .funcmask = BIT(5) | BIT(19),
> -       .funcval = 0,
> -};
> -
> -static const unsigned nand_pins[] = { 66, 67, 92, 93, 94, 96, 97 };
> -
> -static const struct sirfsoc_muxmask sdmmc0_muxmask[] = {
> -       {
> -               .group = 3,
> -               .mask = BIT(1),
> -       },
> -};
> -
> -static const struct sirfsoc_padmux sdmmc0_padmux = {
> -       .muxmask_counts = ARRAY_SIZE(sdmmc0_muxmask),
> -       .muxmask = sdmmc0_muxmask,
> -       .ctrlreg = SIRFSOC_RSC_PIN_MUX,
> -       .funcmask = BIT(5) | BIT(19),
> -       .funcval = BIT(19),
> -};
> -
> -static const unsigned sdmmc0_pins[] = { 97 };
> -
> -static const struct sirfsoc_muxmask sdmmc2_muxmask[] = {
> -       {
> -               .group = 0,
> -               .mask = BIT(27) | BIT(28) | BIT(29),
> -       },
> -};
> -
> -static const struct sirfsoc_padmux sdmmc2_padmux = {
> -       .muxmask_counts = ARRAY_SIZE(sdmmc2_muxmask),
> -       .muxmask = sdmmc2_muxmask,
> -       .ctrlreg = SIRFSOC_RSC_PIN_MUX,
> -       .funcmask = BIT(11),
> -       .funcval = 0,
> -};
> -
> -static const unsigned sdmmc2_pins[] = { 27, 28, 29 };
> -
> -static const struct sirfsoc_muxmask sdmmc2_nowp_muxmask[] = {
> -       {
> -               .group = 0,
> -               .mask = BIT(27) | BIT(28),
> -       },
> -};
> -
> -static const struct sirfsoc_padmux sdmmc2_nowp_padmux = {
> -       .muxmask_counts = ARRAY_SIZE(sdmmc2_nowp_muxmask),
> -       .muxmask = sdmmc2_nowp_muxmask,
> -       .ctrlreg = SIRFSOC_RSC_PIN_MUX,
> -       .funcmask = BIT(11),
> -       .funcval = 0,
> -};
> -
> -static const unsigned sdmmc2_nowp_pins[] = { 27, 28 };
> -
> -static const struct sirfsoc_muxmask cko0_muxmask[] = {
> -       {
> -               .group = 2,
> -               .mask = BIT(14),
> -       },
> -};
> -
> -static const struct sirfsoc_padmux cko0_padmux = {
> -       .muxmask_counts = ARRAY_SIZE(cko0_muxmask),
> -       .muxmask = cko0_muxmask,
> -};
> -
> -static const unsigned cko0_pins[] = { 78 };
> -
> -static const struct sirfsoc_muxmask vip_muxmask[] = {
> -       {
> -               .group = 1,
> -               .mask = BIT(4) | BIT(5) | BIT(6) | BIT(8) | BIT(9)
> -                       | BIT(24) | BIT(25) | BIT(26) | BIT(27) | BIT(28) |
> -                       BIT(29),
> -       },
> -};
> -
> -static const struct sirfsoc_padmux vip_padmux = {
> -       .muxmask_counts = ARRAY_SIZE(vip_muxmask),
> -       .muxmask = vip_muxmask,
> -       .ctrlreg = SIRFSOC_RSC_PIN_MUX,
> -       .funcmask = BIT(18),
> -       .funcval = BIT(18),
> -};
> -
> -static const unsigned vip_pins[] = { 36, 37, 38, 40, 41, 56, 57, 58, 59,
> -       60, 61 };
> -
> -static const struct sirfsoc_muxmask vip_noupli_muxmask[] = {
> -       {
> -               .group = 0,
> -               .mask = BIT(16) | BIT(17) | BIT(18) | BIT(19) | BIT(20)
> -                       | BIT(21) | BIT(22) | BIT(23),
> -       }, {
> -               .group = 2,
> -               .mask = BIT(23) | BIT(24) | BIT(25),
> -       },
> -};
> -
> -static const struct sirfsoc_padmux vip_noupli_padmux = {
> -       .muxmask_counts = ARRAY_SIZE(vip_noupli_muxmask),
> -       .muxmask = vip_noupli_muxmask,
> -       .ctrlreg = SIRFSOC_RSC_PIN_MUX,
> -       .funcmask = BIT(15),
> -       .funcval = BIT(15),
> -};
> -
> -static const unsigned vip_noupli_pins[] = { 16, 17, 18, 19, 20, 21, 22, 23,
> -       87, 88, 89 };
> -
> -static const struct sirfsoc_muxmask i2c0_muxmask[] = {
> -       {
> -               .group = 2,
> -               .mask = BIT(26) | BIT(27),
> -       },
> -};
> -
> -static const struct sirfsoc_padmux i2c0_padmux = {
> -       .muxmask_counts = ARRAY_SIZE(i2c0_muxmask),
> -       .muxmask = i2c0_muxmask,
> -};
> -
> -static const unsigned i2c0_pins[] = { 90, 91 };
> -
> -static const struct sirfsoc_muxmask i2c1_muxmask[] = {
> -       {
> -               .group = 0,
> -               .mask = BIT(13) | BIT(15),
> -       },
> -};
> -
> -static const struct sirfsoc_padmux i2c1_padmux = {
> -       .muxmask_counts = ARRAY_SIZE(i2c1_muxmask),
> -       .muxmask = i2c1_muxmask,
> -       .ctrlreg = SIRFSOC_RSC_PIN_MUX,
> -       .funcmask = BIT(16),
> -       .funcval = 0,
> -};
> -
> -static const unsigned i2c1_pins[] = { 13, 15 };
> -
> -static const struct sirfsoc_muxmask pwm0_muxmask[] = {
> -       {
> -               .group = 0,
> -               .mask = BIT(4),
> -       },
> -};
> -
> -static const struct sirfsoc_padmux pwm0_padmux = {
> -       .muxmask_counts = ARRAY_SIZE(pwm0_muxmask),
> -       .muxmask = pwm0_muxmask,
> -       .ctrlreg = SIRFSOC_RSC_PIN_MUX,
> -       .funcmask = BIT(12),
> -       .funcval = 0,
> -};
> -
> -static const unsigned pwm0_pins[] = { 4 };
> -
> -static const struct sirfsoc_muxmask pwm1_muxmask[] = {
> -       {
> -               .group = 0,
> -               .mask = BIT(5),
> -       },
> -};
> -
> -static const struct sirfsoc_padmux pwm1_padmux = {
> -       .muxmask_counts = ARRAY_SIZE(pwm1_muxmask),
> -       .muxmask = pwm1_muxmask,
> -};
> -
> -static const unsigned pwm1_pins[] = { 5 };
> -
> -static const struct sirfsoc_muxmask pwm2_muxmask[] = {
> -       {
> -               .group = 0,
> -               .mask = BIT(6),
> -       },
> -};
> -
> -static const struct sirfsoc_padmux pwm2_padmux = {
> -       .muxmask_counts = ARRAY_SIZE(pwm2_muxmask),
> -       .muxmask = pwm2_muxmask,
> -};
> -
> -static const unsigned pwm2_pins[] = { 6 };
> -
> -static const struct sirfsoc_muxmask pwm3_muxmask[] = {
> -       {
> -               .group = 0,
> -               .mask = BIT(7),
> -       },
> -};
> -
> -static const struct sirfsoc_padmux pwm3_padmux = {
> -       .muxmask_counts = ARRAY_SIZE(pwm3_muxmask),
> -       .muxmask = pwm3_muxmask,
> -};
> -
> -static const unsigned pwm3_pins[] = { 7 };
> -
> -static const struct sirfsoc_muxmask pwm4_muxmask[] = {
> -       {
> -               .group = 2,
> -               .mask = BIT(14),
> -       },
> -};
> -
> -static const struct sirfsoc_padmux pwm4_padmux = {
> -       .muxmask_counts = ARRAY_SIZE(pwm4_muxmask),
> -       .muxmask = pwm4_muxmask,
> -};
> -
> -static const unsigned pwm4_pins[] = { 78 };
> -
> -static const struct sirfsoc_muxmask warm_rst_muxmask[] = {
> -       {
> -               .group = 0,
> -               .mask = BIT(8),
> -       },
> -};
> -
> -static const struct sirfsoc_padmux warm_rst_padmux = {
> -       .muxmask_counts = ARRAY_SIZE(warm_rst_muxmask),
> -       .muxmask = warm_rst_muxmask,
> -       .ctrlreg = SIRFSOC_RSC_PIN_MUX,
> -       .funcmask = BIT(4),
> -       .funcval = 0,
> -};
> -
> -static const unsigned warm_rst_pins[] = { 8 };
> -
> -static const struct sirfsoc_muxmask usb0_upli_drvbus_muxmask[] = {
> -       {
> -               .group = 1,
> -               .mask = BIT(4) | BIT(5) | BIT(6) | BIT(7) | BIT(8)
> -                       | BIT(9) | BIT(24) | BIT(25) | BIT(26) |
> -                       BIT(27) | BIT(28) | BIT(29),
> -       },
> -};
> -static const struct sirfsoc_padmux usb0_upli_drvbus_padmux = {
> -       .muxmask_counts = ARRAY_SIZE(usb0_upli_drvbus_muxmask),
> -       .muxmask = usb0_upli_drvbus_muxmask,
> -       .ctrlreg = SIRFSOC_RSC_PIN_MUX,
> -       .funcmask = BIT(18),
> -       .funcval = 0,
> -};
> -
> -static const unsigned usb0_upli_drvbus_pins[] = { 36, 37, 38, 39, 40,
> -       41, 56, 57, 58, 59, 60, 61 };
> -
> -static const struct sirfsoc_muxmask usb1_utmi_drvbus_muxmask[] = {
> -       {
> -               .group = 0,
> -               .mask = BIT(28),
> -       },
> -};
> -
> -static const struct sirfsoc_padmux usb1_utmi_drvbus_padmux = {
> -       .muxmask_counts = ARRAY_SIZE(usb1_utmi_drvbus_muxmask),
> -       .muxmask = usb1_utmi_drvbus_muxmask,
> -       .ctrlreg = SIRFSOC_RSC_PIN_MUX,
> -       .funcmask = BIT(11),
> -       .funcval = BIT(11), /* refer to PAD_UTMI_DRVVBUS1_ENABLE */
> -};
> -
> -static const unsigned usb1_utmi_drvbus_pins[] = { 28 };
> -
> -static const struct sirfsoc_padmux usb1_dp_dn_padmux = {
> -       .muxmask_counts = 0,
> -       .ctrlreg = SIRFSOC_RSC_USB_UART_SHARE,
> -       .funcmask = BIT(2),
> -       .funcval = BIT(2),
> -};
> -
> -static const unsigned usb1_dp_dn_pins[] = { 103, 104 };
> -
> -static const struct sirfsoc_padmux uart1_route_io_usb1_padmux = {
> -       .muxmask_counts = 0,
> -       .ctrlreg = SIRFSOC_RSC_USB_UART_SHARE,
> -       .funcmask = BIT(2),
> -       .funcval = 0,
> -};
> -
> -static const unsigned uart1_route_io_usb1_pins[] = { 103, 104 };
> -
> -static const struct sirfsoc_muxmask pulse_count_muxmask[] = {
> -       {
> -               .group = 0,
> -               .mask = BIT(9) | BIT(10) | BIT(11),
> -       },
> -};
> -
> -static const struct sirfsoc_padmux pulse_count_padmux = {
> -       .muxmask_counts = ARRAY_SIZE(pulse_count_muxmask),
> -       .muxmask = pulse_count_muxmask,
> -};
> -
> -static const unsigned pulse_count_pins[] = { 9, 10, 11 };
> -
> -static const struct sirfsoc_pin_group sirfsoc_pin_groups[] = {
> -       SIRFSOC_PIN_GROUP("lcd_16bitsgrp", lcd_16bits_pins),
> -       SIRFSOC_PIN_GROUP("lcd_18bitsgrp", lcd_18bits_pins),
> -       SIRFSOC_PIN_GROUP("lcd_24bitsgrp", lcd_24bits_pins),
> -       SIRFSOC_PIN_GROUP("lcdrom_grp", lcdrom_pins),
> -       SIRFSOC_PIN_GROUP("uart0grp", uart0_pins),
> -       SIRFSOC_PIN_GROUP("uart0_nostreamctrlgrp", uart0_nostreamctrl_pins),
> -       SIRFSOC_PIN_GROUP("uart1grp", uart1_pins),
> -       SIRFSOC_PIN_GROUP("uart2grp", uart2_pins),
> -       SIRFSOC_PIN_GROUP("uart2_nostreamctrlgrp", uart2_nostreamctrl_pins),
> -       SIRFSOC_PIN_GROUP("usp0grp", usp0_pins),
> -       SIRFSOC_PIN_GROUP("usp0_uart_nostreamctrl_grp",
> -                                       usp0_uart_nostreamctrl_pins),
> -       SIRFSOC_PIN_GROUP("usp0_only_utfs_grp", usp0_only_utfs_pins),
> -       SIRFSOC_PIN_GROUP("usp0_only_urfs_grp", usp0_only_urfs_pins),
> -       SIRFSOC_PIN_GROUP("usp1grp", usp1_pins),
> -       SIRFSOC_PIN_GROUP("usp1_uart_nostreamctrl_grp",
> -                                       usp1_uart_nostreamctrl_pins),
> -       SIRFSOC_PIN_GROUP("i2c0grp", i2c0_pins),
> -       SIRFSOC_PIN_GROUP("i2c1grp", i2c1_pins),
> -       SIRFSOC_PIN_GROUP("pwm0grp", pwm0_pins),
> -       SIRFSOC_PIN_GROUP("pwm1grp", pwm1_pins),
> -       SIRFSOC_PIN_GROUP("pwm2grp", pwm2_pins),
> -       SIRFSOC_PIN_GROUP("pwm3grp", pwm3_pins),
> -       SIRFSOC_PIN_GROUP("pwm4grp", pwm4_pins),
> -       SIRFSOC_PIN_GROUP("vipgrp", vip_pins),
> -       SIRFSOC_PIN_GROUP("vip_noupligrp", vip_noupli_pins),
> -       SIRFSOC_PIN_GROUP("warm_rstgrp", warm_rst_pins),
> -       SIRFSOC_PIN_GROUP("cko0grp", cko0_pins),
> -       SIRFSOC_PIN_GROUP("cko1grp", cko1_pins),
> -       SIRFSOC_PIN_GROUP("sdmmc0grp", sdmmc0_pins),
> -       SIRFSOC_PIN_GROUP("sdmmc1grp", sdmmc1_pins),
> -       SIRFSOC_PIN_GROUP("sdmmc2grp", sdmmc2_pins),
> -       SIRFSOC_PIN_GROUP("sdmmc2_nowpgrp", sdmmc2_nowp_pins),
> -       SIRFSOC_PIN_GROUP("sdmmc3grp", sdmmc3_pins),
> -       SIRFSOC_PIN_GROUP("sdmmc5grp", sdmmc5_pins),
> -       SIRFSOC_PIN_GROUP("usb0_upli_drvbusgrp", usb0_upli_drvbus_pins),
> -       SIRFSOC_PIN_GROUP("usb1_utmi_drvbusgrp", usb1_utmi_drvbus_pins),
> -       SIRFSOC_PIN_GROUP("usb1_dp_dngrp", usb1_dp_dn_pins),
> -       SIRFSOC_PIN_GROUP("uart1_route_io_usb1grp", uart1_route_io_usb1_pins),
> -       SIRFSOC_PIN_GROUP("pulse_countgrp", pulse_count_pins),
> -       SIRFSOC_PIN_GROUP("i2smclkgrp", i2s_mclk_pins),
> -       SIRFSOC_PIN_GROUP("i2s_ext_clk_inputgrp", i2s_ext_clk_input_pins),
> -       SIRFSOC_PIN_GROUP("i2sgrp", i2s_pins),
> -       SIRFSOC_PIN_GROUP("i2s_no_dingrp", i2s_no_din_pins),
> -       SIRFSOC_PIN_GROUP("i2s_6chngrp", i2s_6chn_pins),
> -       SIRFSOC_PIN_GROUP("ac97grp", ac97_pins),
> -       SIRFSOC_PIN_GROUP("nandgrp", nand_pins),
> -       SIRFSOC_PIN_GROUP("spi0grp", spi0_pins),
> -       SIRFSOC_PIN_GROUP("spi1grp", spi1_pins),
> -       SIRFSOC_PIN_GROUP("gpsgrp", gps_pins),
> -};
> -
> -static const char * const lcd_16bitsgrp[] = { "lcd_16bitsgrp" };
> -static const char * const lcd_18bitsgrp[] = { "lcd_18bitsgrp" };
> -static const char * const lcd_24bitsgrp[] = { "lcd_24bitsgrp" };
> -static const char * const lcdromgrp[] = { "lcdromgrp" };
> -static const char * const uart0grp[] = { "uart0grp" };
> -static const char * const uart0_nostreamctrlgrp[] = { "uart0_nostreamctrlgrp" };
> -static const char * const uart1grp[] = { "uart1grp" };
> -static const char * const uart2grp[] = { "uart2grp" };
> -static const char * const uart2_nostreamctrlgrp[] = { "uart2_nostreamctrlgrp" };
> -static const char * const usp0_uart_nostreamctrl_grp[] = {
> -                                       "usp0_uart_nostreamctrl_grp" };
> -static const char * const usp0grp[] = { "usp0grp" };
> -static const char * const usp0_only_utfs_grp[] = { "usp0_only_utfs_grp" };
> -static const char * const usp0_only_urfs_grp[] = { "usp0_only_urfs_grp" };
> -
> -static const char * const usp1grp[] = { "usp1grp" };
> -static const char * const usp1_uart_nostreamctrl_grp[] = {
> -                                       "usp1_uart_nostreamctrl_grp" };
> -static const char * const i2c0grp[] = { "i2c0grp" };
> -static const char * const i2c1grp[] = { "i2c1grp" };
> -static const char * const pwm0grp[] = { "pwm0grp" };
> -static const char * const pwm1grp[] = { "pwm1grp" };
> -static const char * const pwm2grp[] = { "pwm2grp" };
> -static const char * const pwm3grp[] = { "pwm3grp" };
> -static const char * const pwm4grp[] = { "pwm4grp" };
> -static const char * const vipgrp[] = { "vipgrp" };
> -static const char * const vip_noupligrp[] = { "vip_noupligrp" };
> -static const char * const warm_rstgrp[] = { "warm_rstgrp" };
> -static const char * const cko0grp[] = { "cko0grp" };
> -static const char * const cko1grp[] = { "cko1grp" };
> -static const char * const sdmmc0grp[] = { "sdmmc0grp" };
> -static const char * const sdmmc1grp[] = { "sdmmc1grp" };
> -static const char * const sdmmc2grp[] = { "sdmmc2grp" };
> -static const char * const sdmmc3grp[] = { "sdmmc3grp" };
> -static const char * const sdmmc5grp[] = { "sdmmc5grp" };
> -static const char * const sdmmc2_nowpgrp[] = { "sdmmc2_nowpgrp" };
> -static const char * const usb0_upli_drvbusgrp[] = { "usb0_upli_drvbusgrp" };
> -static const char * const usb1_utmi_drvbusgrp[] = { "usb1_utmi_drvbusgrp" };
> -static const char * const usb1_dp_dngrp[] = { "usb1_dp_dngrp" };
> -static const char * const
> -       uart1_route_io_usb1grp[] = { "uart1_route_io_usb1grp" };
> -static const char * const pulse_countgrp[] = { "pulse_countgrp" };
> -static const char * const i2smclkgrp[] = { "i2smclkgrp" };
> -static const char * const i2s_ext_clk_inputgrp[] = { "i2s_ext_clk_inputgrp" };
> -static const char * const i2sgrp[] = { "i2sgrp" };
> -static const char * const i2s_no_dingrp[] = { "i2s_no_dingrp" };
> -static const char * const i2s_6chngrp[] = { "i2s_6chngrp" };
> -static const char * const ac97grp[] = { "ac97grp" };
> -static const char * const nandgrp[] = { "nandgrp" };
> -static const char * const spi0grp[] = { "spi0grp" };
> -static const char * const spi1grp[] = { "spi1grp" };
> -static const char * const gpsgrp[] = { "gpsgrp" };
> -
> -static const struct sirfsoc_pmx_func sirfsoc_pmx_functions[] = {
> -       SIRFSOC_PMX_FUNCTION("lcd_16bits", lcd_16bitsgrp, lcd_16bits_padmux),
> -       SIRFSOC_PMX_FUNCTION("lcd_18bits", lcd_18bitsgrp, lcd_18bits_padmux),
> -       SIRFSOC_PMX_FUNCTION("lcd_24bits", lcd_24bitsgrp, lcd_24bits_padmux),
> -       SIRFSOC_PMX_FUNCTION("lcdrom", lcdromgrp, lcdrom_padmux),
> -       SIRFSOC_PMX_FUNCTION("uart0", uart0grp, uart0_padmux),
> -       SIRFSOC_PMX_FUNCTION("uart0_nostreamctrl", uart0_nostreamctrlgrp,
> -                                               uart0_nostreamctrl_padmux),
> -       SIRFSOC_PMX_FUNCTION("uart1", uart1grp, uart1_padmux),
> -       SIRFSOC_PMX_FUNCTION("uart2", uart2grp, uart2_padmux),
> -       SIRFSOC_PMX_FUNCTION("uart2_nostreamctrl",
> -               uart2_nostreamctrlgrp, uart2_nostreamctrl_padmux),
> -       SIRFSOC_PMX_FUNCTION("usp0", usp0grp, usp0_padmux),
> -       SIRFSOC_PMX_FUNCTION("usp0_uart_nostreamctrl",
> -                                               usp0_uart_nostreamctrl_grp,
> -                                               usp0_uart_nostreamctrl_padmux),
> -       SIRFSOC_PMX_FUNCTION("usp0_only_utfs", usp0_only_utfs_grp,
> -                                               usp0_only_utfs_padmux),
> -       SIRFSOC_PMX_FUNCTION("usp0_only_urfs", usp0_only_urfs_grp,
> -                                               usp0_only_urfs_padmux),
> -       SIRFSOC_PMX_FUNCTION("usp1", usp1grp, usp1_padmux),
> -       SIRFSOC_PMX_FUNCTION("usp1_uart_nostreamctrl",
> -                                               usp1_uart_nostreamctrl_grp,
> -                                               usp1_uart_nostreamctrl_padmux),
> -       SIRFSOC_PMX_FUNCTION("i2c0", i2c0grp, i2c0_padmux),
> -       SIRFSOC_PMX_FUNCTION("i2c1", i2c1grp, i2c1_padmux),
> -       SIRFSOC_PMX_FUNCTION("pwm0", pwm0grp, pwm0_padmux),
> -       SIRFSOC_PMX_FUNCTION("pwm1", pwm1grp, pwm1_padmux),
> -       SIRFSOC_PMX_FUNCTION("pwm2", pwm2grp, pwm2_padmux),
> -       SIRFSOC_PMX_FUNCTION("pwm3", pwm3grp, pwm3_padmux),
> -       SIRFSOC_PMX_FUNCTION("pwm4", pwm4grp, pwm4_padmux),
> -       SIRFSOC_PMX_FUNCTION("vip", vipgrp, vip_padmux),
> -       SIRFSOC_PMX_FUNCTION("vip_noupli", vip_noupligrp, vip_noupli_padmux),
> -       SIRFSOC_PMX_FUNCTION("warm_rst", warm_rstgrp, warm_rst_padmux),
> -       SIRFSOC_PMX_FUNCTION("cko0", cko0grp, cko0_padmux),
> -       SIRFSOC_PMX_FUNCTION("cko1", cko1grp, cko1_padmux),
> -       SIRFSOC_PMX_FUNCTION("sdmmc0", sdmmc0grp, sdmmc0_padmux),
> -       SIRFSOC_PMX_FUNCTION("sdmmc1", sdmmc1grp, sdmmc1_padmux),
> -       SIRFSOC_PMX_FUNCTION("sdmmc2", sdmmc2grp, sdmmc2_padmux),
> -       SIRFSOC_PMX_FUNCTION("sdmmc3", sdmmc3grp, sdmmc3_padmux),
> -       SIRFSOC_PMX_FUNCTION("sdmmc5", sdmmc5grp, sdmmc5_padmux),
> -       SIRFSOC_PMX_FUNCTION("sdmmc2_nowp",
> -               sdmmc2_nowpgrp, sdmmc2_nowp_padmux),
> -       SIRFSOC_PMX_FUNCTION("usb0_upli_drvbus",
> -               usb0_upli_drvbusgrp, usb0_upli_drvbus_padmux),
> -       SIRFSOC_PMX_FUNCTION("usb1_utmi_drvbus",
> -               usb1_utmi_drvbusgrp, usb1_utmi_drvbus_padmux),
> -       SIRFSOC_PMX_FUNCTION("usb1_dp_dn", usb1_dp_dngrp, usb1_dp_dn_padmux),
> -       SIRFSOC_PMX_FUNCTION("uart1_route_io_usb1",
> -               uart1_route_io_usb1grp, uart1_route_io_usb1_padmux),
> -       SIRFSOC_PMX_FUNCTION("pulse_count", pulse_countgrp, pulse_count_padmux),
> -       SIRFSOC_PMX_FUNCTION("i2s_mclk", i2smclkgrp, i2s_mclk_padmux),
> -       SIRFSOC_PMX_FUNCTION("i2s_ext_clk_input", i2s_ext_clk_inputgrp,
> -                                               i2s_ext_clk_input_padmux),
> -       SIRFSOC_PMX_FUNCTION("i2s", i2sgrp, i2s_padmux),
> -       SIRFSOC_PMX_FUNCTION("i2s_no_din", i2s_no_dingrp, i2s_no_din_padmux),
> -       SIRFSOC_PMX_FUNCTION("i2s_6chn", i2s_6chngrp, i2s_6chn_padmux),
> -       SIRFSOC_PMX_FUNCTION("ac97", ac97grp, ac97_padmux),
> -       SIRFSOC_PMX_FUNCTION("nand", nandgrp, nand_padmux),
> -       SIRFSOC_PMX_FUNCTION("spi0", spi0grp, spi0_padmux),
> -       SIRFSOC_PMX_FUNCTION("spi1", spi1grp, spi1_padmux),
> -       SIRFSOC_PMX_FUNCTION("gps", gpsgrp, gps_padmux),
> -};
> -
> -struct sirfsoc_pinctrl_data atlas6_pinctrl_data = {
> -       (struct pinctrl_pin_desc *)sirfsoc_pads,
> -       ARRAY_SIZE(sirfsoc_pads),
> -       (struct sirfsoc_pin_group *)sirfsoc_pin_groups,
> -       ARRAY_SIZE(sirfsoc_pin_groups),
> -       (struct sirfsoc_pmx_func *)sirfsoc_pmx_functions,
> -       ARRAY_SIZE(sirfsoc_pmx_functions),
> -};
> -
> diff --git a/drivers/pinctrl/sirf/pinctrl-atlas7.c b/drivers/pinctrl/sirf/pinctrl-atlas7.c
> deleted file mode 100644
> index e54a6e3cafd2..000000000000
> --- a/drivers/pinctrl/sirf/pinctrl-atlas7.c
> +++ /dev/null
> @@ -1,6157 +0,0 @@
> -// SPDX-License-Identifier: GPL-2.0-or-later
> -/*
> - * pinctrl pads, groups, functions for CSR SiRFatlasVII
> - *
> - * Copyright (c) 2011 - 2014 Cambridge Silicon Radio Limited, a CSR plc group
> - * company.
> - */
> -
> -#include <linux/init.h>
> -#include <linux/platform_device.h>
> -#include <linux/io.h>
> -#include <linux/bitops.h>
> -#include <linux/irq.h>
> -#include <linux/slab.h>
> -#include <linux/clk.h>
> -#include <linux/of.h>
> -#include <linux/of_address.h>
> -#include <linux/of_device.h>
> -#include <linux/of_platform.h>
> -#include <linux/of_irq.h>
> -#include <linux/pinctrl/machine.h>
> -#include <linux/pinctrl/pinconf.h>
> -#include <linux/pinctrl/pinctrl.h>
> -#include <linux/pinctrl/pinmux.h>
> -#include <linux/pinctrl/consumer.h>
> -#include <linux/pinctrl/pinconf-generic.h>
> -#include <linux/gpio/driver.h>
> -
> -/* Definition of Pad&Mux Properties */
> -#define N 0
> -
> -/* The Bank contains input-disable regisgers */
> -#define BANK_DS        0
> -
> -/* Clear Register offset */
> -#define CLR_REG(r)     ((r) + 0x04)
> -
> -/* Definition of multiple function select register */
> -#define FUNC_CLEAR_MASK                0x7
> -#define FUNC_GPIO              0
> -#define FUNC_ANALOGUE          0x8
> -#define ANA_CLEAR_MASK         0x1
> -
> -/* The Atlas7's Pad Type List */
> -enum altas7_pad_type {
> -       PAD_T_4WE_PD = 0,       /* ZIO_PAD3V_4WE_PD */
> -       PAD_T_4WE_PU,           /* ZIO_PAD3V_4WE_PD */
> -       PAD_T_16ST,             /* ZIO_PAD3V_SDCLK_PD */
> -       PAD_T_M31_0204_PD,      /* PRDW0204SDGZ_M311311_PD */
> -       PAD_T_M31_0204_PU,      /* PRDW0204SDGZ_M311311_PU */
> -       PAD_T_M31_0610_PD,      /* PRUW0610SDGZ_M311311_PD */
> -       PAD_T_M31_0610_PU,      /* PRUW0610SDGZ_M311311_PU */
> -       PAD_T_AD,               /* PRDWUWHW08SCDG_HZ */
> -};
> -
> -/* Raw value of Driver-Strength Bits */
> -#define DS3    BIT(3)
> -#define DS2    BIT(2)
> -#define DS1    BIT(1)
> -#define DS0    BIT(0)
> -#define DSZ    0
> -
> -/* Drive-Strength Intermediate Values */
> -#define DS_NULL                -1
> -#define DS_1BIT_IM_VAL  DS0
> -#define DS_1BIT_MASK   0x1
> -#define DS_2BIT_IM_VAL  (DS1 | DS0)
> -#define DS_2BIT_MASK   0x3
> -#define DS_4BIT_IM_VAL (DS3 | DS2 | DS1 | DS0)
> -#define DS_4BIT_MASK   0xf
> -
> -/* The Drive-Strength of 4WE Pad                DS1  0  CO */
> -#define DS_4WE_3   (DS1 | DS0)                 /* 1  1  3  */
> -#define DS_4WE_2   (DS1)                       /* 1  0  2  */
> -#define DS_4WE_1   (DS0)                       /* 0  1  1  */
> -#define DS_4WE_0   (DSZ)                       /* 0  0  0  */
> -
> -/* The Drive-Strength of 16st Pad               DS3  2  1  0  CO */
> -#define DS_16ST_15  (DS3 | DS2 | DS1 | DS0)    /* 1  1  1  1  15 */
> -#define DS_16ST_14  (DS3 | DS2 | DS0)          /* 1  1  0  1  13 */
> -#define DS_16ST_13  (DS3 | DS2 | DS1)          /* 1  1  1  0  14 */
> -#define DS_16ST_12  (DS2 | DS1 | DS0)          /* 0  1  1  1  7  */
> -#define DS_16ST_11  (DS2 | DS0)                        /* 0  1  0  1  5  */
> -#define DS_16ST_10  (DS3 | DS1 | DS0)          /* 1  0  1  1  11 */
> -#define DS_16ST_9   (DS3 | DS0)                        /* 1  0  0  1  9  */
> -#define DS_16ST_8   (DS1 | DS0)                        /* 0  0  1  1  3  */
> -#define DS_16ST_7   (DS2 | DS1)                        /* 0  1  1  0  6  */
> -#define DS_16ST_6   (DS3 | DS2)                        /* 1  1  0  0  12 */
> -#define DS_16ST_5   (DS2)                      /* 0  1  0  0  4  */
> -#define DS_16ST_4   (DS3 | DS1)                        /* 1  0  1  0  10 */
> -#define DS_16ST_3   (DS1)                      /* 0  0  1  0  2  */
> -#define DS_16ST_2   (DS0)                      /* 0  0  0  1  1  */
> -#define DS_16ST_1   (DSZ)                      /* 0  0  0  0  0  */
> -#define DS_16ST_0   (DS3)                      /* 1  0  0  0  8  */
> -
> -/* The Drive-Strength of M31 Pad                DS0  CO */
> -#define DS_M31_0   (DSZ)                       /* 0  0  */
> -#define DS_M31_1   (DS0)                       /* 1  1  */
> -
> -/* Raw values of Pull Option Bits */
> -#define PUN    BIT(1)
> -#define PD     BIT(0)
> -#define PE     BIT(0)
> -#define PZ     0
> -
> -/* Definition of Pull Types */
> -#define PULL_UP                0
> -#define HIGH_HYSTERESIS 1
> -#define HIGH_Z         2
> -#define PULL_DOWN      3
> -#define PULL_DISABLE   4
> -#define PULL_ENABLE    5
> -#define PULL_UNKNOWN   -1
> -
> -/* Pull Options for 4WE Pad                      PUN  PD  CO */
> -#define P4WE_PULL_MASK         0x3
> -#define P4WE_PULL_DOWN         (PUN | PD)      /* 1   1   3  */
> -#define P4WE_HIGH_Z            (PUN)           /* 1   0   2  */
> -#define P4WE_HIGH_HYSTERESIS   (PD)            /* 0   1   1  */
> -#define P4WE_PULL_UP           (PZ)            /* 0   0   0  */
> -
> -/* Pull Options for 16ST Pad                     PUN  PD  CO */
> -#define P16ST_PULL_MASK                0x3
> -#define P16ST_PULL_DOWN                (PUN | PD)      /* 1   1   3  */
> -#define P16ST_HIGH_Z           (PUN)           /* 1   0   2  */
> -#define P16ST_PULL_UP          (PZ)            /* 0   0   0  */
> -
> -/* Pull Options for M31 Pad                      PE */
> -#define PM31_PULL_MASK         0x1
> -#define PM31_PULL_ENABLED      (PE)            /* 1 */
> -#define PM31_PULL_DISABLED     (PZ)            /* 0 */
> -
> -/* Pull Options for A/D Pad                      PUN  PD  CO */
> -#define PANGD_PULL_MASK                0x3
> -#define PANGD_PULL_DOWN                (PUN | PD)      /* 1   1   3  */
> -#define PANGD_HIGH_Z           (PUN)           /* 1   0   2  */
> -#define PANGD_PULL_UP          (PZ)            /* 0   0   0  */
> -
> -/* Definition of Input Disable */
> -#define DI_MASK                0x1
> -#define DI_DISABLE     0x1
> -#define DI_ENABLE      0x0
> -
> -/* Definition of Input Disable Value */
> -#define DIV_MASK       0x1
> -#define DIV_DISABLE    0x1
> -#define DIV_ENABLE     0x0
> -
> -/* Number of Function input disable registers */
> -#define NUM_OF_IN_DISABLE_REG  0x2
> -
> -/* Offset of Function input disable registers */
> -#define IN_DISABLE_0_REG_SET           0x0A00
> -#define IN_DISABLE_0_REG_CLR           0x0A04
> -#define IN_DISABLE_1_REG_SET           0x0A08
> -#define IN_DISABLE_1_REG_CLR           0x0A0C
> -#define IN_DISABLE_VAL_0_REG_SET       0x0A80
> -#define IN_DISABLE_VAL_0_REG_CLR       0x0A84
> -#define IN_DISABLE_VAL_1_REG_SET       0x0A88
> -#define IN_DISABLE_VAL_1_REG_CLR       0x0A8C
> -
> -/* Offset of the SDIO9SEL*/
> -#define SYS2PCI_SDIO9SEL 0x14
> -
> -struct dt_params {
> -       const char *property;
> -       int value;
> -};
> -
> -/**
> - * struct atlas7_pad_conf - Atlas7 Pad Configuration
> - * @id:                        The ID of this Pad.
> - * @type:              The type of this Pad.
> - * @mux_reg:           The mux register offset.
> - *                     This register contains the mux.
> - * @pupd_reg:          The pull-up/down register offset.
> - * @drvstr_reg:                The drive-strength register offset.
> - * @ad_ctrl_reg:       The Analogue/Digital Control register.
> - *
> - * @mux_bit:           The start bit of mux register.
> - * @pupd_bit:          The start bit of pull-up/down register.
> - * @drvstr_bit:                The start bit of drive-strength register.
> - * @ad_ctrl_bit:       The start bit of analogue/digital register.
> - */
> -struct atlas7_pad_config {
> -       const u32 id;
> -       u32 type;
> -       u32 mux_reg;
> -       u32 pupd_reg;
> -       u32 drvstr_reg;
> -       u32 ad_ctrl_reg;
> -       /* bits in register */
> -       u8 mux_bit;
> -       u8 pupd_bit;
> -       u8 drvstr_bit;
> -       u8 ad_ctrl_bit;
> -};
> -
> -#define PADCONF(pad, t, mr, pr, dsr, adr, mb, pb, dsb, adb)    \
> -       {                                                       \
> -               .id = pad,                                      \
> -               .type = t,                                      \
> -               .mux_reg = mr,                                  \
> -               .pupd_reg = pr,                                 \
> -               .drvstr_reg = dsr,                              \
> -               .ad_ctrl_reg = adr,                             \
> -               .mux_bit = mb,                                  \
> -               .pupd_bit = pb,                                 \
> -               .drvstr_bit = dsb,                              \
> -               .ad_ctrl_bit = adb,                             \
> -       }
> -
> -/*
> - * struct atlas7_pad_status - Atlas7 Pad status
> - */
> -struct atlas7_pad_status {
> -       u8 func;
> -       u8 pull;
> -       u8 dstr;
> -       u8 reserved;
> -};
> -
> -/**
> - * struct atlas7_pad_mux - Atlas7 mux
> - * @bank:              The bank of this pad's registers on.
> - * @pin        :               The ID of this Pad.
> - * @func:              The mux func on this Pad.
> - * @dinput_reg:                The Input-Disable register offset.
> - * @dinput_bit:                The start bit of Input-Disable register.
> - * @dinput_val_reg:    The Input-Disable-value register offset.
> - *                     This register is used to set the value of this pad
> - *                     if this pad was disabled.
> - * @dinput_val_bit:    The start bit of Input-Disable Value register.
> - */
> -struct atlas7_pad_mux {
> -       u32 bank;
> -       u32 pin;
> -       u32 func;
> -       u32 dinput_reg;
> -       u32 dinput_bit;
> -       u32 dinput_val_reg;
> -       u32 dinput_val_bit;
> -};
> -
> -#define MUX(b, pad, f, dr, db, dvr, dvb)       \
> -       {                                       \
> -               .bank = b,                      \
> -               .pin = pad,                     \
> -               .func = f,                      \
> -               .dinput_reg = dr,               \
> -               .dinput_bit = db,               \
> -               .dinput_val_reg = dvr,          \
> -               .dinput_val_bit = dvb,          \
> -       }
> -
> -struct atlas7_grp_mux {
> -       unsigned int group;
> -       unsigned int pad_mux_count;
> -       const struct atlas7_pad_mux *pad_mux_list;
> -};
> -
> - /**
> - * struct sirfsoc_pin_group - describes a SiRFprimaII pin group
> - * @name: the name of this specific pin group
> - * @pins: an array of discrete physical pins used in this group, taken
> - *     from the driver-local pin enumeration space
> - * @num_pins: the number of pins in this group array, i.e. the number of
> - *     elements in .pins so we can iterate over that array
> - */
> -struct atlas7_pin_group {
> -       const char *name;
> -       const unsigned int *pins;
> -       const unsigned num_pins;
> -};
> -
> -#define GROUP(n, p)  \
> -       {                       \
> -               .name = n,      \
> -               .pins = p,      \
> -               .num_pins = ARRAY_SIZE(p),      \
> -       }
> -
> -struct atlas7_pmx_func {
> -       const char *name;
> -       const char * const *groups;
> -       const unsigned num_groups;
> -       const struct atlas7_grp_mux *grpmux;
> -};
> -
> -#define FUNCTION(n, g, m)              \
> -       {                                       \
> -               .name = n,                      \
> -               .groups = g,                    \
> -               .num_groups = ARRAY_SIZE(g),    \
> -               .grpmux = m,                    \
> -       }
> -
> -struct atlas7_pinctrl_data {
> -       struct pinctrl_pin_desc *pads;
> -       int pads_cnt;
> -       struct atlas7_pin_group *grps;
> -       int grps_cnt;
> -       struct atlas7_pmx_func *funcs;
> -       int funcs_cnt;
> -       struct atlas7_pad_config *confs;
> -       int confs_cnt;
> -};
> -
> -/* Platform info of atlas7 pinctrl */
> -#define ATLAS7_PINCTRL_REG_BANKS       2
> -#define ATLAS7_PINCTRL_BANK_0_PINS     18
> -#define ATLAS7_PINCTRL_BANK_1_PINS     141
> -#define ATLAS7_PINCTRL_TOTAL_PINS      \
> -       (ATLAS7_PINCTRL_BANK_0_PINS + ATLAS7_PINCTRL_BANK_1_PINS)
> -
> -/**
> - * Atlas7 GPIO Chip
> - */
> -
> -#define NGPIO_OF_BANK          32
> -#define GPIO_TO_BANK(gpio)     ((gpio) / NGPIO_OF_BANK)
> -
> -/* Registers of GPIO Controllers */
> -#define ATLAS7_GPIO_BASE(g, b)         ((g)->reg + 0x100 * (b))
> -#define ATLAS7_GPIO_CTRL(b, i)         ((b)->base + 4 * (i))
> -#define ATLAS7_GPIO_INT_STATUS(b)      ((b)->base + 0x8C)
> -
> -/* Definition bits of GPIO Control Registers */
> -#define ATLAS7_GPIO_CTL_INTR_LOW_MASK          BIT(0)
> -#define ATLAS7_GPIO_CTL_INTR_HIGH_MASK         BIT(1)
> -#define ATLAS7_GPIO_CTL_INTR_TYPE_MASK         BIT(2)
> -#define ATLAS7_GPIO_CTL_INTR_EN_MASK           BIT(3)
> -#define ATLAS7_GPIO_CTL_INTR_STATUS_MASK       BIT(4)
> -#define ATLAS7_GPIO_CTL_OUT_EN_MASK            BIT(5)
> -#define ATLAS7_GPIO_CTL_DATAOUT_MASK           BIT(6)
> -#define ATLAS7_GPIO_CTL_DATAIN_MASK            BIT(7)
> -
> -struct atlas7_gpio_bank {
> -       int id;
> -       int irq;
> -       void __iomem *base;
> -       unsigned int gpio_offset;
> -       unsigned int ngpio;
> -       const unsigned int *gpio_pins;
> -       u32 sleep_data[NGPIO_OF_BANK];
> -};
> -
> -struct atlas7_gpio_chip {
> -       const char *name;
> -       void __iomem *reg;
> -       struct clk *clk;
> -       int nbank;
> -       raw_spinlock_t lock;
> -       struct gpio_chip chip;
> -       struct atlas7_gpio_bank banks[];
> -};
> -
> -struct atlas7_pmx {
> -       struct device *dev;
> -       struct pinctrl_dev *pctl;
> -       struct pinctrl_desc pctl_desc;
> -       struct atlas7_pinctrl_data *pctl_data;
> -       void __iomem *regs[ATLAS7_PINCTRL_REG_BANKS];
> -       void __iomem *sys2pci_base;
> -       u32 status_ds[NUM_OF_IN_DISABLE_REG];
> -       u32 status_dsv[NUM_OF_IN_DISABLE_REG];
> -       struct atlas7_pad_status sleep_data[ATLAS7_PINCTRL_TOTAL_PINS];
> -};
> -
> -/*
> - * Pad list for the pinmux subsystem
> - * refer to A7DA IO Summary - CS-314158-DD-4E.xls
> - */
> -
> -/* Pads in IOC RTC & TOP */
> -static const struct pinctrl_pin_desc atlas7_ioc_pads[] = {
> -       /* RTC PADs */
> -       PINCTRL_PIN(0, "rtc_gpio_0"),
> -       PINCTRL_PIN(1, "rtc_gpio_1"),
> -       PINCTRL_PIN(2, "rtc_gpio_2"),
> -       PINCTRL_PIN(3, "rtc_gpio_3"),
> -       PINCTRL_PIN(4, "low_bat_ind_b"),
> -       PINCTRL_PIN(5, "on_key_b"),
> -       PINCTRL_PIN(6, "ext_on"),
> -       PINCTRL_PIN(7, "mem_on"),
> -       PINCTRL_PIN(8, "core_on"),
> -       PINCTRL_PIN(9, "io_on"),
> -       PINCTRL_PIN(10, "can0_tx"),
> -       PINCTRL_PIN(11, "can0_rx"),
> -       PINCTRL_PIN(12, "spi0_clk"),
> -       PINCTRL_PIN(13, "spi0_cs_b"),
> -       PINCTRL_PIN(14, "spi0_io_0"),
> -       PINCTRL_PIN(15, "spi0_io_1"),
> -       PINCTRL_PIN(16, "spi0_io_2"),
> -       PINCTRL_PIN(17, "spi0_io_3"),
> -
> -       /* TOP PADs */
> -       PINCTRL_PIN(18, "spi1_en"),
> -       PINCTRL_PIN(19, "spi1_clk"),
> -       PINCTRL_PIN(20, "spi1_din"),
> -       PINCTRL_PIN(21, "spi1_dout"),
> -       PINCTRL_PIN(22, "trg_spi_clk"),
> -       PINCTRL_PIN(23, "trg_spi_di"),
> -       PINCTRL_PIN(24, "trg_spi_do"),
> -       PINCTRL_PIN(25, "trg_spi_cs_b"),
> -       PINCTRL_PIN(26, "trg_acq_d1"),
> -       PINCTRL_PIN(27, "trg_irq_b"),
> -       PINCTRL_PIN(28, "trg_acq_d0"),
> -       PINCTRL_PIN(29, "trg_acq_clk"),
> -       PINCTRL_PIN(30, "trg_shutdown_b_out"),
> -       PINCTRL_PIN(31, "sdio2_clk"),
> -       PINCTRL_PIN(32, "sdio2_cmd"),
> -       PINCTRL_PIN(33, "sdio2_dat_0"),
> -       PINCTRL_PIN(34, "sdio2_dat_1"),
> -       PINCTRL_PIN(35, "sdio2_dat_2"),
> -       PINCTRL_PIN(36, "sdio2_dat_3"),
> -       PINCTRL_PIN(37, "df_ad_7"),
> -       PINCTRL_PIN(38, "df_ad_6"),
> -       PINCTRL_PIN(39, "df_ad_5"),
> -       PINCTRL_PIN(40, "df_ad_4"),
> -       PINCTRL_PIN(41, "df_ad_3"),
> -       PINCTRL_PIN(42, "df_ad_2"),
> -       PINCTRL_PIN(43, "df_ad_1"),
> -       PINCTRL_PIN(44, "df_ad_0"),
> -       PINCTRL_PIN(45, "df_dqs"),
> -       PINCTRL_PIN(46, "df_cle"),
> -       PINCTRL_PIN(47, "df_ale"),
> -       PINCTRL_PIN(48, "df_we_b"),
> -       PINCTRL_PIN(49, "df_re_b"),
> -       PINCTRL_PIN(50, "df_ry_by"),
> -       PINCTRL_PIN(51, "df_cs_b_1"),
> -       PINCTRL_PIN(52, "df_cs_b_0"),
> -       PINCTRL_PIN(53, "l_pclk"),
> -       PINCTRL_PIN(54, "l_lck"),
> -       PINCTRL_PIN(55, "l_fck"),
> -       PINCTRL_PIN(56, "l_de"),
> -       PINCTRL_PIN(57, "ldd_0"),
> -       PINCTRL_PIN(58, "ldd_1"),
> -       PINCTRL_PIN(59, "ldd_2"),
> -       PINCTRL_PIN(60, "ldd_3"),
> -       PINCTRL_PIN(61, "ldd_4"),
> -       PINCTRL_PIN(62, "ldd_5"),
> -       PINCTRL_PIN(63, "ldd_6"),
> -       PINCTRL_PIN(64, "ldd_7"),
> -       PINCTRL_PIN(65, "ldd_8"),
> -       PINCTRL_PIN(66, "ldd_9"),
> -       PINCTRL_PIN(67, "ldd_10"),
> -       PINCTRL_PIN(68, "ldd_11"),
> -       PINCTRL_PIN(69, "ldd_12"),
> -       PINCTRL_PIN(70, "ldd_13"),
> -       PINCTRL_PIN(71, "ldd_14"),
> -       PINCTRL_PIN(72, "ldd_15"),
> -       PINCTRL_PIN(73, "lcd_gpio_20"),
> -       PINCTRL_PIN(74, "vip_0"),
> -       PINCTRL_PIN(75, "vip_1"),
> -       PINCTRL_PIN(76, "vip_2"),
> -       PINCTRL_PIN(77, "vip_3"),
> -       PINCTRL_PIN(78, "vip_4"),
> -       PINCTRL_PIN(79, "vip_5"),
> -       PINCTRL_PIN(80, "vip_6"),
> -       PINCTRL_PIN(81, "vip_7"),
> -       PINCTRL_PIN(82, "vip_pxclk"),
> -       PINCTRL_PIN(83, "vip_hsync"),
> -       PINCTRL_PIN(84, "vip_vsync"),
> -       PINCTRL_PIN(85, "sdio3_clk"),
> -       PINCTRL_PIN(86, "sdio3_cmd"),
> -       PINCTRL_PIN(87, "sdio3_dat_0"),
> -       PINCTRL_PIN(88, "sdio3_dat_1"),
> -       PINCTRL_PIN(89, "sdio3_dat_2"),
> -       PINCTRL_PIN(90, "sdio3_dat_3"),
> -       PINCTRL_PIN(91, "sdio5_clk"),
> -       PINCTRL_PIN(92, "sdio5_cmd"),
> -       PINCTRL_PIN(93, "sdio5_dat_0"),
> -       PINCTRL_PIN(94, "sdio5_dat_1"),
> -       PINCTRL_PIN(95, "sdio5_dat_2"),
> -       PINCTRL_PIN(96, "sdio5_dat_3"),
> -       PINCTRL_PIN(97, "rgmii_txd_0"),
> -       PINCTRL_PIN(98, "rgmii_txd_1"),
> -       PINCTRL_PIN(99, "rgmii_txd_2"),
> -       PINCTRL_PIN(100, "rgmii_txd_3"),
> -       PINCTRL_PIN(101, "rgmii_txclk"),
> -       PINCTRL_PIN(102, "rgmii_tx_ctl"),
> -       PINCTRL_PIN(103, "rgmii_rxd_0"),
> -       PINCTRL_PIN(104, "rgmii_rxd_1"),
> -       PINCTRL_PIN(105, "rgmii_rxd_2"),
> -       PINCTRL_PIN(106, "rgmii_rxd_3"),
> -       PINCTRL_PIN(107, "rgmii_rx_clk"),
> -       PINCTRL_PIN(108, "rgmii_rxc_ctl"),
> -       PINCTRL_PIN(109, "rgmii_mdio"),
> -       PINCTRL_PIN(110, "rgmii_mdc"),
> -       PINCTRL_PIN(111, "rgmii_intr_n"),
> -       PINCTRL_PIN(112, "i2s_mclk"),
> -       PINCTRL_PIN(113, "i2s_bclk"),
> -       PINCTRL_PIN(114, "i2s_ws"),
> -       PINCTRL_PIN(115, "i2s_dout0"),
> -       PINCTRL_PIN(116, "i2s_dout1"),
> -       PINCTRL_PIN(117, "i2s_dout2"),
> -       PINCTRL_PIN(118, "i2s_din"),
> -       PINCTRL_PIN(119, "gpio_0"),
> -       PINCTRL_PIN(120, "gpio_1"),
> -       PINCTRL_PIN(121, "gpio_2"),
> -       PINCTRL_PIN(122, "gpio_3"),
> -       PINCTRL_PIN(123, "gpio_4"),
> -       PINCTRL_PIN(124, "gpio_5"),
> -       PINCTRL_PIN(125, "gpio_6"),
> -       PINCTRL_PIN(126, "gpio_7"),
> -       PINCTRL_PIN(127, "sda_0"),
> -       PINCTRL_PIN(128, "scl_0"),
> -       PINCTRL_PIN(129, "coex_pio_0"),
> -       PINCTRL_PIN(130, "coex_pio_1"),
> -       PINCTRL_PIN(131, "coex_pio_2"),
> -       PINCTRL_PIN(132, "coex_pio_3"),
> -       PINCTRL_PIN(133, "uart0_tx"),
> -       PINCTRL_PIN(134, "uart0_rx"),
> -       PINCTRL_PIN(135, "uart1_tx"),
> -       PINCTRL_PIN(136, "uart1_rx"),
> -       PINCTRL_PIN(137, "uart3_tx"),
> -       PINCTRL_PIN(138, "uart3_rx"),
> -       PINCTRL_PIN(139, "uart4_tx"),
> -       PINCTRL_PIN(140, "uart4_rx"),
> -       PINCTRL_PIN(141, "usp0_clk"),
> -       PINCTRL_PIN(142, "usp0_tx"),
> -       PINCTRL_PIN(143, "usp0_rx"),
> -       PINCTRL_PIN(144, "usp0_fs"),
> -       PINCTRL_PIN(145, "usp1_clk"),
> -       PINCTRL_PIN(146, "usp1_tx"),
> -       PINCTRL_PIN(147, "usp1_rx"),
> -       PINCTRL_PIN(148, "usp1_fs"),
> -       PINCTRL_PIN(149, "lvds_tx0d4p"),
> -       PINCTRL_PIN(150, "lvds_tx0d4n"),
> -       PINCTRL_PIN(151, "lvds_tx0d3p"),
> -       PINCTRL_PIN(152, "lvds_tx0d3n"),
> -       PINCTRL_PIN(153, "lvds_tx0d2p"),
> -       PINCTRL_PIN(154, "lvds_tx0d2n"),
> -       PINCTRL_PIN(155, "lvds_tx0d1p"),
> -       PINCTRL_PIN(156, "lvds_tx0d1n"),
> -       PINCTRL_PIN(157, "lvds_tx0d0p"),
> -       PINCTRL_PIN(158, "lvds_tx0d0n"),
> -       PINCTRL_PIN(159, "jtag_tdo"),
> -       PINCTRL_PIN(160, "jtag_tms"),
> -       PINCTRL_PIN(161, "jtag_tck"),
> -       PINCTRL_PIN(162, "jtag_tdi"),
> -       PINCTRL_PIN(163, "jtag_trstn"),
> -};
> -
> -static struct atlas7_pad_config atlas7_ioc_pad_confs[] = {
> -       /* The Configuration of IOC_RTC Pads */
> -       PADCONF(0, 3, 0x0, 0x100, 0x200, -1, 0, 0, 0, 0),
> -       PADCONF(1, 3, 0x0, 0x100, 0x200, -1, 4, 2, 2, 0),
> -       PADCONF(2, 3, 0x0, 0x100, 0x200, -1, 8, 4, 4, 0),
> -       PADCONF(3, 5, 0x0, 0x100, 0x200, -1, 12, 6, 6, 0),
> -       PADCONF(4, 4, 0x0, 0x100, 0x200, -1, 16, 8, 8, 0),
> -       PADCONF(5, 4, 0x0, 0x100, 0x200, -1, 20, 10, 10, 0),
> -       PADCONF(6, 3, 0x0, 0x100, 0x200, -1, 24, 12, 12, 0),
> -       PADCONF(7, 3, 0x0, 0x100, 0x200, -1, 28, 14, 14, 0),
> -       PADCONF(8, 3, 0x8, 0x100, 0x200, -1, 0, 16, 16, 0),
> -       PADCONF(9, 3, 0x8, 0x100, 0x200, -1, 4, 18, 18, 0),
> -       PADCONF(10, 4, 0x8, 0x100, 0x200, -1, 8, 20, 20, 0),
> -       PADCONF(11, 4, 0x8, 0x100, 0x200, -1, 12, 22, 22, 0),
> -       PADCONF(12, 5, 0x8, 0x100, 0x200, -1, 16, 24, 24, 0),
> -       PADCONF(13, 6, 0x8, 0x100, 0x200, -1, 20, 26, 26, 0),
> -       PADCONF(14, 5, 0x8, 0x100, 0x200, -1, 24, 28, 28, 0),
> -       PADCONF(15, 5, 0x8, 0x100, 0x200, -1, 28, 30, 30, 0),
> -       PADCONF(16, 5, 0x10, 0x108, 0x208, -1, 0, 0, 0, 0),
> -       PADCONF(17, 5, 0x10, 0x108, 0x208, -1, 4, 2, 2, 0),
> -       /* The Configuration of IOC_TOP Pads */
> -       PADCONF(18, 5, 0x80, 0x180, 0x300, -1, 0, 0, 0, 0),
> -       PADCONF(19, 5, 0x80, 0x180, 0x300, -1, 4, 2, 2, 0),
> -       PADCONF(20, 5, 0x80, 0x180, 0x300, -1, 8, 4, 4, 0),
> -       PADCONF(21, 5, 0x80, 0x180, 0x300, -1, 12, 6, 6, 0),
> -       PADCONF(22, 5, 0x88, 0x188, 0x308, -1, 0, 0, 0, 0),
> -       PADCONF(23, 5, 0x88, 0x188, 0x308, -1, 4, 2, 2, 0),
> -       PADCONF(24, 5, 0x88, 0x188, 0x308, -1, 8, 4, 4, 0),
> -       PADCONF(25, 6, 0x88, 0x188, 0x308, -1, 12, 6, 6, 0),
> -       PADCONF(26, 5, 0x88, 0x188, 0x308, -1, 16, 8, 8, 0),
> -       PADCONF(27, 6, 0x88, 0x188, 0x308, -1, 20, 10, 10, 0),
> -       PADCONF(28, 5, 0x88, 0x188, 0x308, -1, 24, 12, 12, 0),
> -       PADCONF(29, 5, 0x88, 0x188, 0x308, -1, 28, 14, 14, 0),
> -       PADCONF(30, 5, 0x90, 0x188, 0x308, -1, 0, 16, 16, 0),
> -       PADCONF(31, 2, 0x98, 0x190, 0x310, -1, 0, 0, 0, 0),
> -       PADCONF(32, 1, 0x98, 0x190, 0x310, -1, 4, 2, 4, 0),
> -       PADCONF(33, 1, 0x98, 0x190, 0x310, -1, 8, 4, 6, 0),
> -       PADCONF(34, 1, 0x98, 0x190, 0x310, -1, 12, 6, 8, 0),
> -       PADCONF(35, 1, 0x98, 0x190, 0x310, -1, 16, 8, 10, 0),
> -       PADCONF(36, 1, 0x98, 0x190, 0x310, -1, 20, 10, 12, 0),
> -       PADCONF(37, 1, 0xa0, 0x198, 0x318, -1, 0, 0, 0, 0),
> -       PADCONF(38, 1, 0xa0, 0x198, 0x318, -1, 4, 2, 2, 0),
> -       PADCONF(39, 1, 0xa0, 0x198, 0x318, -1, 8, 4, 4, 0),
> -       PADCONF(40, 1, 0xa0, 0x198, 0x318, -1, 12, 6, 6, 0),
> -       PADCONF(41, 1, 0xa0, 0x198, 0x318, -1, 16, 8, 8, 0),
> -       PADCONF(42, 1, 0xa0, 0x198, 0x318, -1, 20, 10, 10, 0),
> -       PADCONF(43, 1, 0xa0, 0x198, 0x318, -1, 24, 12, 12, 0),
> -       PADCONF(44, 1, 0xa0, 0x198, 0x318, -1, 28, 14, 14, 0),
> -       PADCONF(45, 0, 0xa8, 0x198, 0x318, -1, 0, 16, 16, 0),
> -       PADCONF(46, 0, 0xa8, 0x198, 0x318, -1, 4, 18, 18, 0),
> -       PADCONF(47, 1, 0xa8, 0x198, 0x318, -1, 8, 20, 20, 0),
> -       PADCONF(48, 1, 0xa8, 0x198, 0x318, -1, 12, 22, 22, 0),
> -       PADCONF(49, 1, 0xa8, 0x198, 0x318, -1, 16, 24, 24, 0),
> -       PADCONF(50, 1, 0xa8, 0x198, 0x318, -1, 20, 26, 26, 0),
> -       PADCONF(51, 1, 0xa8, 0x198, 0x318, -1, 24, 28, 28, 0),
> -       PADCONF(52, 1, 0xa8, 0x198, 0x318, -1, 28, 30, 30, 0),
> -       PADCONF(53, 0, 0xb0, 0x1a0, 0x320, -1, 0, 0, 0, 0),
> -       PADCONF(54, 0, 0xb0, 0x1a0, 0x320, -1, 4, 2, 2, 0),
> -       PADCONF(55, 0, 0xb0, 0x1a0, 0x320, -1, 8, 4, 4, 0),
> -       PADCONF(56, 0, 0xb0, 0x1a0, 0x320, -1, 12, 6, 6, 0),
> -       PADCONF(57, 0, 0xb0, 0x1a0, 0x320, -1, 16, 8, 8, 0),
> -       PADCONF(58, 0, 0xb0, 0x1a0, 0x320, -1, 20, 10, 10, 0),
> -       PADCONF(59, 0, 0xb0, 0x1a0, 0x320, -1, 24, 12, 12, 0),
> -       PADCONF(60, 0, 0xb0, 0x1a0, 0x320, -1, 28, 14, 14, 0),
> -       PADCONF(61, 0, 0xb8, 0x1a0, 0x320, -1, 0, 16, 16, 0),
> -       PADCONF(62, 0, 0xb8, 0x1a0, 0x320, -1, 4, 18, 18, 0),
> -       PADCONF(63, 0, 0xb8, 0x1a0, 0x320, -1, 8, 20, 20, 0),
> -       PADCONF(64, 0, 0xb8, 0x1a0, 0x320, -1, 12, 22, 22, 0),
> -       PADCONF(65, 0, 0xb8, 0x1a0, 0x320, -1, 16, 24, 24, 0),
> -       PADCONF(66, 0, 0xb8, 0x1a0, 0x320, -1, 20, 26, 26, 0),
> -       PADCONF(67, 0, 0xb8, 0x1a0, 0x320, -1, 24, 28, 28, 0),
> -       PADCONF(68, 0, 0xb8, 0x1a0, 0x320, -1, 28, 30, 30, 0),
> -       PADCONF(69, 0, 0xc0, 0x1a8, 0x328, -1, 0, 0, 0, 0),
> -       PADCONF(70, 0, 0xc0, 0x1a8, 0x328, -1, 4, 2, 2, 0),
> -       PADCONF(71, 0, 0xc0, 0x1a8, 0x328, -1, 8, 4, 4, 0),
> -       PADCONF(72, 0, 0xc0, 0x1a8, 0x328, -1, 12, 6, 6, 0),
> -       PADCONF(73, 0, 0xc0, 0x1a8, 0x328, -1, 16, 8, 8, 0),
> -       PADCONF(74, 0, 0xc8, 0x1b0, 0x330, -1, 0, 0, 0, 0),
> -       PADCONF(75, 0, 0xc8, 0x1b0, 0x330, -1, 4, 2, 2, 0),
> -       PADCONF(76, 0, 0xc8, 0x1b0, 0x330, -1, 8, 4, 4, 0),
> -       PADCONF(77, 0, 0xc8, 0x1b0, 0x330, -1, 12, 6, 6, 0),
> -       PADCONF(78, 0, 0xc8, 0x1b0, 0x330, -1, 16, 8, 8, 0),
> -       PADCONF(79, 0, 0xc8, 0x1b0, 0x330, -1, 20, 10, 10, 0),
> -       PADCONF(80, 0, 0xc8, 0x1b0, 0x330, -1, 24, 12, 12, 0),
> -       PADCONF(81, 0, 0xc8, 0x1b0, 0x330, -1, 28, 14, 14, 0),
> -       PADCONF(82, 0, 0xd0, 0x1b0, 0x330, -1, 0, 16, 16, 0),
> -       PADCONF(83, 0, 0xd0, 0x1b0, 0x330, -1, 4, 18, 18, 0),
> -       PADCONF(84, 0, 0xd0, 0x1b0, 0x330, -1, 8, 20, 20, 0),
> -       PADCONF(85, 2, 0xd8, 0x1b8, 0x338, -1, 0, 0, 0, 0),
> -       PADCONF(86, 1, 0xd8, 0x1b8, 0x338, -1, 4, 4, 4, 0),
> -       PADCONF(87, 1, 0xd8, 0x1b8, 0x338, -1, 8, 6, 6, 0),
> -       PADCONF(88, 1, 0xd8, 0x1b8, 0x338, -1, 12, 8, 8, 0),
> -       PADCONF(89, 1, 0xd8, 0x1b8, 0x338, -1, 16, 10, 10, 0),
> -       PADCONF(90, 1, 0xd8, 0x1b8, 0x338, -1, 20, 12, 12, 0),
> -       PADCONF(91, 2, 0xe0, 0x1c0, 0x340, -1, 0, 0, 0, 0),
> -       PADCONF(92, 1, 0xe0, 0x1c0, 0x340, -1, 4, 4, 4, 0),
> -       PADCONF(93, 1, 0xe0, 0x1c0, 0x340, -1, 8, 6, 6, 0),
> -       PADCONF(94, 1, 0xe0, 0x1c0, 0x340, -1, 12, 8, 8, 0),
> -       PADCONF(95, 1, 0xe0, 0x1c0, 0x340, -1, 16, 10, 10, 0),
> -       PADCONF(96, 1, 0xe0, 0x1c0, 0x340, -1, 20, 12, 12, 0),
> -       PADCONF(97, 0, 0xe8, 0x1c8, 0x348, -1, 0, 0, 0, 0),
> -       PADCONF(98, 0, 0xe8, 0x1c8, 0x348, -1, 4, 2, 2, 0),
> -       PADCONF(99, 0, 0xe8, 0x1c8, 0x348, -1, 8, 4, 4, 0),
> -       PADCONF(100, 0, 0xe8, 0x1c8, 0x348, -1, 12, 6, 6, 0),
> -       PADCONF(101, 2, 0xe8, 0x1c8, 0x348, -1, 16, 8, 8, 0),
> -       PADCONF(102, 0, 0xe8, 0x1c8, 0x348, -1, 20, 12, 12, 0),
> -       PADCONF(103, 0, 0xe8, 0x1c8, 0x348, -1, 24, 14, 14, 0),
> -       PADCONF(104, 0, 0xe8, 0x1c8, 0x348, -1, 28, 16, 16, 0),
> -       PADCONF(105, 0, 0xf0, 0x1c8, 0x348, -1, 0, 18, 18, 0),
> -       PADCONF(106, 0, 0xf0, 0x1c8, 0x348, -1, 4, 20, 20, 0),
> -       PADCONF(107, 0, 0xf0, 0x1c8, 0x348, -1, 8, 22, 22, 0),
> -       PADCONF(108, 0, 0xf0, 0x1c8, 0x348, -1, 12, 24, 24, 0),
> -       PADCONF(109, 1, 0xf0, 0x1c8, 0x348, -1, 16, 26, 26, 0),
> -       PADCONF(110, 0, 0xf0, 0x1c8, 0x348, -1, 20, 28, 28, 0),
> -       PADCONF(111, 1, 0xf0, 0x1c8, 0x348, -1, 24, 30, 30, 0),
> -       PADCONF(112, 5, 0xf8, 0x200, 0x350, -1, 0, 0, 0, 0),
> -       PADCONF(113, 5, 0xf8, 0x200, 0x350, -1, 4, 2, 2, 0),
> -       PADCONF(114, 5, 0xf8, 0x200, 0x350, -1, 8, 4, 4, 0),
> -       PADCONF(115, 5, 0xf8, 0x200, 0x350, -1, 12, 6, 6, 0),
> -       PADCONF(116, 5, 0xf8, 0x200, 0x350, -1, 16, 8, 8, 0),
> -       PADCONF(117, 5, 0xf8, 0x200, 0x350, -1, 20, 10, 10, 0),
> -       PADCONF(118, 5, 0xf8, 0x200, 0x350, -1, 24, 12, 12, 0),
> -       PADCONF(119, 5, 0x100, 0x250, 0x358, -1, 0, 0, 0, 0),
> -       PADCONF(120, 5, 0x100, 0x250, 0x358, -1, 4, 2, 2, 0),
> -       PADCONF(121, 5, 0x100, 0x250, 0x358, -1, 8, 4, 4, 0),
> -       PADCONF(122, 5, 0x100, 0x250, 0x358, -1, 12, 6, 6, 0),
> -       PADCONF(123, 6, 0x100, 0x250, 0x358, -1, 16, 8, 8, 0),
> -       PADCONF(124, 6, 0x100, 0x250, 0x358, -1, 20, 10, 10, 0),
> -       PADCONF(125, 6, 0x100, 0x250, 0x358, -1, 24, 12, 12, 0),
> -       PADCONF(126, 6, 0x100, 0x250, 0x358, -1, 28, 14, 14, 0),
> -       PADCONF(127, 6, 0x108, 0x250, 0x358, -1, 16, 24, 24, 0),
> -       PADCONF(128, 6, 0x108, 0x250, 0x358, -1, 20, 26, 26, 0),
> -       PADCONF(129, 0, 0x110, 0x258, 0x360, -1, 0, 0, 0, 0),
> -       PADCONF(130, 0, 0x110, 0x258, 0x360, -1, 4, 2, 2, 0),
> -       PADCONF(131, 0, 0x110, 0x258, 0x360, -1, 8, 4, 4, 0),
> -       PADCONF(132, 0, 0x110, 0x258, 0x360, -1, 12, 6, 6, 0),
> -       PADCONF(133, 6, 0x118, 0x260, 0x368, -1, 0, 0, 0, 0),
> -       PADCONF(134, 6, 0x118, 0x260, 0x368, -1, 4, 2, 2, 0),
> -       PADCONF(135, 6, 0x118, 0x260, 0x368, -1, 16, 8, 8, 0),
> -       PADCONF(136, 6, 0x118, 0x260, 0x368, -1, 20, 10, 10, 0),
> -       PADCONF(137, 6, 0x118, 0x260, 0x368, -1, 24, 12, 12, 0),
> -       PADCONF(138, 6, 0x118, 0x260, 0x368, -1, 28, 14, 14, 0),
> -       PADCONF(139, 6, 0x120, 0x260, 0x368, -1, 0, 16, 16, 0),
> -       PADCONF(140, 6, 0x120, 0x260, 0x368, -1, 4, 18, 18, 0),
> -       PADCONF(141, 5, 0x128, 0x268, 0x378, -1, 0, 0, 0, 0),
> -       PADCONF(142, 5, 0x128, 0x268, 0x378, -1, 4, 2, 2, 0),
> -       PADCONF(143, 5, 0x128, 0x268, 0x378, -1, 8, 4, 4, 0),
> -       PADCONF(144, 5, 0x128, 0x268, 0x378, -1, 12, 6, 6, 0),
> -       PADCONF(145, 5, 0x128, 0x268, 0x378, -1, 16, 8, 8, 0),
> -       PADCONF(146, 5, 0x128, 0x268, 0x378, -1, 20, 10, 10, 0),
> -       PADCONF(147, 5, 0x128, 0x268, 0x378, -1, 24, 12, 12, 0),
> -       PADCONF(148, 5, 0x128, 0x268, 0x378, -1, 28, 14, 14, 0),
> -       PADCONF(149, 7, 0x130, 0x270, -1, 0x480, 0, 0, 0, 0),
> -       PADCONF(150, 7, 0x130, 0x270, -1, 0x480, 4, 2, 0, 1),
> -       PADCONF(151, 7, 0x130, 0x270, -1, 0x480, 8, 4, 0, 2),
> -       PADCONF(152, 7, 0x130, 0x270, -1, 0x480, 12, 6, 0, 3),
> -       PADCONF(153, 7, 0x130, 0x270, -1, 0x480, 16, 8, 0, 4),
> -       PADCONF(154, 7, 0x130, 0x270, -1, 0x480, 20, 10, 0, 5),
> -       PADCONF(155, 7, 0x130, 0x270, -1, 0x480, 24, 12, 0, 6),
> -       PADCONF(156, 7, 0x130, 0x270, -1, 0x480, 28, 14, 0, 7),
> -       PADCONF(157, 7, 0x138, 0x278, -1, 0x480, 0, 0, 0, 8),
> -       PADCONF(158, 7, 0x138, 0x278, -1, 0x480, 4, 2, 0, 9),
> -       PADCONF(159, 5, 0x140, 0x280, 0x380, -1, 0, 0, 0, 0),
> -       PADCONF(160, 6, 0x140, 0x280, 0x380, -1, 4, 2, 2, 0),
> -       PADCONF(161, 5, 0x140, 0x280, 0x380, -1, 8, 4, 4, 0),
> -       PADCONF(162, 6, 0x140, 0x280, 0x380, -1, 12, 6, 6, 0),
> -       PADCONF(163, 6, 0x140, 0x280, 0x380, -1, 16, 8, 8, 0),
> -};
> -
> -/* pin list of each pin group */
> -static const unsigned int gnss_gpio_pins[] = { 119, 120, 121, 122, 123, 124,
> -               125, 126, 127, 128, 22, 23, 24, 25, 26, 27, 28, 29, 30, };
> -static const unsigned int lcd_vip_gpio_pins[] = { 74, 75, 76, 77, 78, 79, 80,
> -               81, 82, 83, 84, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63,
> -               64, 65, 66, 67, 68, 69, 70, 71, 72, 73, };
> -static const unsigned int sdio_i2s_gpio_pins[] = { 31, 32, 33, 34, 35, 36,
> -               85, 86, 87, 88, 89, 90, 129, 130, 131, 132, 91, 92, 93, 94,
> -               95, 96, 112, 113, 114, 115, 116, 117, 118, };
> -static const unsigned int sp_rgmii_gpio_pins[] = { 97, 98, 99, 100, 101, 102,
> -               103, 104, 105, 106, 107, 108, 109, 110, 111, 18, 19, 20, 21,
> -               141, 142, 143, 144, 145, 146, 147, 148, };
> -static const unsigned int lvds_gpio_pins[] = { 157, 158, 155, 156, 153, 154,
> -               151, 152, 149, 150, };
> -static const unsigned int jtag_uart_nand_gpio_pins[] = { 44, 43, 42, 41, 40,
> -               39, 38, 37, 46, 47, 48, 49, 50, 52, 51, 45, 133, 134, 135,
> -               136, 137, 138, 139, 140, 159, 160, 161, 162, 163, };
> -static const unsigned int rtc_gpio_pins[] = { 0, 1, 2, 3, 4, 10, 11, 12, 13,
> -               14, 15, 16, 17, 9, };
> -static const unsigned int audio_ac97_pins[] = { 113, 118, 115, 114, };
> -static const unsigned int audio_digmic_pins0[] = { 51, };
> -static const unsigned int audio_digmic_pins1[] = { 122, };
> -static const unsigned int audio_digmic_pins2[] = { 161, };
> -static const unsigned int audio_func_dbg_pins[] = { 141, 144, 44, 43, 42, 41,
> -               40, 39, 38, 37, 74, 75, 76, 77, 78, 79, 81, 113, 114, 118,
> -               115, 49, 50, 142, 143, 80, };
> -static const unsigned int audio_i2s_pins[] = { 118, 115, 116, 117, 112, 113,
> -               114, };
> -static const unsigned int audio_i2s_2ch_pins[] = { 118, 115, 112, 113, 114, };
> -static const unsigned int audio_i2s_extclk_pins[] = { 112, };
> -static const unsigned int audio_spdif_out_pins0[] = { 112, };
> -static const unsigned int audio_spdif_out_pins1[] = { 116, };
> -static const unsigned int audio_spdif_out_pins2[] = { 142, };
> -static const unsigned int audio_uart0_basic_pins[] = { 143, 142, 141, 144, };
> -static const unsigned int audio_uart0_urfs_pins0[] = { 117, };
> -static const unsigned int audio_uart0_urfs_pins1[] = { 139, };
> -static const unsigned int audio_uart0_urfs_pins2[] = { 163, };
> -static const unsigned int audio_uart0_urfs_pins3[] = { 162, };
> -static const unsigned int audio_uart1_basic_pins[] = { 147, 146, 145, 148, };
> -static const unsigned int audio_uart1_urfs_pins0[] = { 117, };
> -static const unsigned int audio_uart1_urfs_pins1[] = { 140, };
> -static const unsigned int audio_uart1_urfs_pins2[] = { 163, };
> -static const unsigned int audio_uart2_urfs_pins0[] = { 139, };
> -static const unsigned int audio_uart2_urfs_pins1[] = { 163, };
> -static const unsigned int audio_uart2_urfs_pins2[] = { 96, };
> -static const unsigned int audio_uart2_urxd_pins0[] = { 20, };
> -static const unsigned int audio_uart2_urxd_pins1[] = { 109, };
> -static const unsigned int audio_uart2_urxd_pins2[] = { 93, };
> -static const unsigned int audio_uart2_usclk_pins0[] = { 19, };
> -static const unsigned int audio_uart2_usclk_pins1[] = { 101, };
> -static const unsigned int audio_uart2_usclk_pins2[] = { 91, };
> -static const unsigned int audio_uart2_utfs_pins0[] = { 18, };
> -static const unsigned int audio_uart2_utfs_pins1[] = { 111, };
> -static const unsigned int audio_uart2_utfs_pins2[] = { 94, };
> -static const unsigned int audio_uart2_utxd_pins0[] = { 21, };
> -static const unsigned int audio_uart2_utxd_pins1[] = { 110, };
> -static const unsigned int audio_uart2_utxd_pins2[] = { 92, };
> -static const unsigned int c_can_trnsvr_en_pins0[] = { 2, };
> -static const unsigned int c_can_trnsvr_en_pins1[] = { 0, };
> -static const unsigned int c_can_trnsvr_intr_pins[] = { 1, };
> -static const unsigned int c_can_trnsvr_stb_n_pins[] = { 3, };
> -static const unsigned int c0_can_rxd_trnsv0_pins[] = { 11, };
> -static const unsigned int c0_can_rxd_trnsv1_pins[] = { 2, };
> -static const unsigned int c0_can_txd_trnsv0_pins[] = { 10, };
> -static const unsigned int c0_can_txd_trnsv1_pins[] = { 3, };
> -static const unsigned int c1_can_rxd_pins0[] = { 138, };
> -static const unsigned int c1_can_rxd_pins1[] = { 147, };
> -static const unsigned int c1_can_rxd_pins2[] = { 2, };
> -static const unsigned int c1_can_rxd_pins3[] = { 162, };
> -static const unsigned int c1_can_txd_pins0[] = { 137, };
> -static const unsigned int c1_can_txd_pins1[] = { 146, };
> -static const unsigned int c1_can_txd_pins2[] = { 3, };
> -static const unsigned int c1_can_txd_pins3[] = { 161, };
> -static const unsigned int ca_audio_lpc_pins[] = { 62, 63, 64, 65, 66, 67, 68,
> -               69, 70, 71, };
> -static const unsigned int ca_bt_lpc_pins[] = { 85, 86, 87, 88, 89, 90, };
> -static const unsigned int ca_coex_pins[] = { 129, 130, 131, 132, };
> -static const unsigned int ca_curator_lpc_pins[] = { 57, 58, 59, 60, };
> -static const unsigned int ca_pcm_debug_pins[] = { 91, 93, 94, 92, };
> -static const unsigned int ca_pio_pins[] = { 121, 122, 125, 126, 38, 37, 47,
> -               49, 50, 54, 55, 56, };
> -static const unsigned int ca_sdio_debug_pins[] = { 40, 39, 44, 43, 42, 41, };
> -static const unsigned int ca_spi_pins[] = { 82, 79, 80, 81, };
> -static const unsigned int ca_trb_pins[] = { 91, 93, 94, 95, 96, 78, 74, 75,
> -               76, 77, };
> -static const unsigned int ca_uart_debug_pins[] = { 136, 135, 134, 133, };
> -static const unsigned int clkc_pins0[] = { 30, 47, };
> -static const unsigned int clkc_pins1[] = { 78, 54, };
> -static const unsigned int gn_gnss_i2c_pins[] = { 128, 127, };
> -static const unsigned int gn_gnss_uart_nopause_pins[] = { 134, 133, };
> -static const unsigned int gn_gnss_uart_pins[] = { 134, 133, 136, 135, };
> -static const unsigned int gn_trg_spi_pins0[] = { 22, 25, 23, 24, };
> -static const unsigned int gn_trg_spi_pins1[] = { 82, 79, 80, 81, };
> -static const unsigned int cvbs_dbg_pins[] = { 54, 53, 82, 74, 75, 76, 77, 78,
> -               79, 80, 81, 83, 84, 73, 55, 56, };
> -static const unsigned int cvbs_dbg_test_pins0[] = { 57, };
> -static const unsigned int cvbs_dbg_test_pins1[] = { 58, };
> -static const unsigned int cvbs_dbg_test_pins2[] = { 59, };
> -static const unsigned int cvbs_dbg_test_pins3[] = { 60, };
> -static const unsigned int cvbs_dbg_test_pins4[] = { 61, };
> -static const unsigned int cvbs_dbg_test_pins5[] = { 62, };
> -static const unsigned int cvbs_dbg_test_pins6[] = { 63, };
> -static const unsigned int cvbs_dbg_test_pins7[] = { 64, };
> -static const unsigned int cvbs_dbg_test_pins8[] = { 65, };
> -static const unsigned int cvbs_dbg_test_pins9[] = { 66, };
> -static const unsigned int cvbs_dbg_test_pins10[] = { 67, };
> -static const unsigned int cvbs_dbg_test_pins11[] = { 68, };
> -static const unsigned int cvbs_dbg_test_pins12[] = { 69, };
> -static const unsigned int cvbs_dbg_test_pins13[] = { 70, };
> -static const unsigned int cvbs_dbg_test_pins14[] = { 71, };
> -static const unsigned int cvbs_dbg_test_pins15[] = { 72, };
> -static const unsigned int gn_gnss_power_pins[] = { 123, 124, 121, 122, 125,
> -               120, };
> -static const unsigned int gn_gnss_sw_status_pins[] = { 57, 58, 59, 60, 61,
> -               62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 53, 55, 56, 54, };
> -static const unsigned int gn_gnss_eclk_pins[] = { 113, };
> -static const unsigned int gn_gnss_irq1_pins0[] = { 112, };
> -static const unsigned int gn_gnss_irq2_pins0[] = { 118, };
> -static const unsigned int gn_gnss_tm_pins[] = { 115, };
> -static const unsigned int gn_gnss_tsync_pins[] = { 114, };
> -static const unsigned int gn_io_gnsssys_sw_cfg_pins[] = { 44, 43, 42, 41, 40,
> -               39, 38, 37, 49, 50, 91, 92, 93, 94, 95, 96, };
> -static const unsigned int gn_trg_pins0[] = { 29, 28, 26, 27, };
> -static const unsigned int gn_trg_pins1[] = { 77, 76, 74, 75, };
> -static const unsigned int gn_trg_shutdown_pins0[] = { 30, };
> -static const unsigned int gn_trg_shutdown_pins1[] = { 83, };
> -static const unsigned int gn_trg_shutdown_pins2[] = { 117, };
> -static const unsigned int gn_trg_shutdown_pins3[] = { 123, };
> -static const unsigned int i2c0_pins[] = { 128, 127, };
> -static const unsigned int i2c1_pins[] = { 126, 125, };
> -static const unsigned int i2s0_pins[] = { 91, 93, 94, 92, };
> -static const unsigned int i2s1_basic_pins[] = { 95, 96, };
> -static const unsigned int i2s1_rxd0_pins0[] = { 61, };
> -static const unsigned int i2s1_rxd0_pins1[] = { 131, };
> -static const unsigned int i2s1_rxd0_pins2[] = { 129, };
> -static const unsigned int i2s1_rxd0_pins3[] = { 117, };
> -static const unsigned int i2s1_rxd0_pins4[] = { 83, };
> -static const unsigned int i2s1_rxd1_pins0[] = { 72, };
> -static const unsigned int i2s1_rxd1_pins1[] = { 132, };
> -static const unsigned int i2s1_rxd1_pins2[] = { 130, };
> -static const unsigned int i2s1_rxd1_pins3[] = { 118, };
> -static const unsigned int i2s1_rxd1_pins4[] = { 84, };
> -static const unsigned int jtag_jt_dbg_nsrst_pins[] = { 125, };
> -static const unsigned int jtag_ntrst_pins0[] = { 4, };
> -static const unsigned int jtag_ntrst_pins1[] = { 163, };
> -static const unsigned int jtag_swdiotms_pins0[] = { 2, };
> -static const unsigned int jtag_swdiotms_pins1[] = { 160, };
> -static const unsigned int jtag_tck_pins0[] = { 0, };
> -static const unsigned int jtag_tck_pins1[] = { 161, };
> -static const unsigned int jtag_tdi_pins0[] = { 1, };
> -static const unsigned int jtag_tdi_pins1[] = { 162, };
> -static const unsigned int jtag_tdo_pins0[] = { 3, };
> -static const unsigned int jtag_tdo_pins1[] = { 159, };
> -static const unsigned int ks_kas_spi_pins0[] = { 141, 144, 143, 142, };
> -static const unsigned int ld_ldd_pins[] = { 57, 58, 59, 60, 61, 62, 63, 64,
> -               65, 66, 67, 68, 69, 70, 71, 72, 74, 75, 76, 77, 78, 79, 80,
> -               81, 56, 53, };
> -static const unsigned int ld_ldd_16bit_pins[] = { 57, 58, 59, 60, 61, 62, 63,
> -               64, 65, 66, 67, 68, 69, 70, 71, 72, 56, 53, };
> -static const unsigned int ld_ldd_fck_pins[] = { 55, };
> -static const unsigned int ld_ldd_lck_pins[] = { 54, };
> -static const unsigned int lr_lcdrom_pins[] = { 73, 54, 57, 58, 59, 60, 61,
> -               62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 56, 53, 55, };
> -static const unsigned int lvds_analog_pins[] = { 149, 150, 151, 152, 153, 154,
> -               155, 156, 157, 158, };
> -static const unsigned int nd_df_basic_pins[] = { 44, 43, 42, 41, 40, 39, 38,
> -               37, 47, 46, 52, 45, 49, 50, 48, };
> -static const unsigned int nd_df_wp_pins[] = { 124, };
> -static const unsigned int nd_df_cs_pins[] = { 51, };
> -static const unsigned int ps_pins[] = { 120, 119, 121, };
> -static const unsigned int ps_no_dir_pins[] = { 119, };
> -static const unsigned int pwc_core_on_pins[] = { 8, };
> -static const unsigned int pwc_ext_on_pins[] = { 6, };
> -static const unsigned int pwc_gpio3_clk_pins[] = { 3, };
> -static const unsigned int pwc_io_on_pins[] = { 9, };
> -static const unsigned int pwc_lowbatt_b_pins0[] = { 4, };
> -static const unsigned int pwc_mem_on_pins[] = { 7, };
> -static const unsigned int pwc_on_key_b_pins0[] = { 5, };
> -static const unsigned int pwc_wakeup_src0_pins[] = { 0, };
> -static const unsigned int pwc_wakeup_src1_pins[] = { 1, };
> -static const unsigned int pwc_wakeup_src2_pins[] = { 2, };
> -static const unsigned int pwc_wakeup_src3_pins[] = { 3, };
> -static const unsigned int pw_cko0_pins0[] = { 123, };
> -static const unsigned int pw_cko0_pins1[] = { 101, };
> -static const unsigned int pw_cko0_pins2[] = { 82, };
> -static const unsigned int pw_cko0_pins3[] = { 162, };
> -static const unsigned int pw_cko1_pins0[] = { 124, };
> -static const unsigned int pw_cko1_pins1[] = { 110, };
> -static const unsigned int pw_cko1_pins2[] = { 163, };
> -static const unsigned int pw_i2s01_clk_pins0[] = { 125, };
> -static const unsigned int pw_i2s01_clk_pins1[] = { 117, };
> -static const unsigned int pw_i2s01_clk_pins2[] = { 132, };
> -static const unsigned int pw_pwm0_pins0[] = { 119, };
> -static const unsigned int pw_pwm0_pins1[] = { 159, };
> -static const unsigned int pw_pwm1_pins0[] = { 120, };
> -static const unsigned int pw_pwm1_pins1[] = { 160, };
> -static const unsigned int pw_pwm1_pins2[] = { 131, };
> -static const unsigned int pw_pwm2_pins0[] = { 121, };
> -static const unsigned int pw_pwm2_pins1[] = { 98, };
> -static const unsigned int pw_pwm2_pins2[] = { 161, };
> -static const unsigned int pw_pwm3_pins0[] = { 122, };
> -static const unsigned int pw_pwm3_pins1[] = { 73, };
> -static const unsigned int pw_pwm_cpu_vol_pins0[] = { 121, };
> -static const unsigned int pw_pwm_cpu_vol_pins1[] = { 98, };
> -static const unsigned int pw_pwm_cpu_vol_pins2[] = { 161, };
> -static const unsigned int pw_backlight_pins0[] = { 122, };
> -static const unsigned int pw_backlight_pins1[] = { 73, };
> -static const unsigned int rg_eth_mac_pins[] = { 108, 103, 104, 105, 106, 107,
> -               102, 97, 98, 99, 100, 101, };
> -static const unsigned int rg_gmac_phy_intr_n_pins[] = { 111, };
> -static const unsigned int rg_rgmii_mac_pins[] = { 109, 110, };
> -static const unsigned int rg_rgmii_phy_ref_clk_pins0[] = { 111, };
> -static const unsigned int rg_rgmii_phy_ref_clk_pins1[] = { 53, };
> -static const unsigned int sd0_pins[] = { 46, 47, 44, 43, 42, 41, 40, 39, 38,
> -               37, };
> -static const unsigned int sd0_4bit_pins[] = { 46, 47, 44, 43, 42, 41, };
> -static const unsigned int sd1_pins[] = { 48, 49, 44, 43, 42, 41, 40, 39, 38,
> -               37, };
> -static const unsigned int sd1_4bit_pins0[] = { 48, 49, 44, 43, 42, 41, };
> -static const unsigned int sd1_4bit_pins1[] = { 48, 49, 40, 39, 38, 37, };
> -static const unsigned int sd2_basic_pins[] = { 31, 32, 33, 34, 35, 36, };
> -static const unsigned int sd2_cdb_pins0[] = { 124, };
> -static const unsigned int sd2_cdb_pins1[] = { 161, };
> -static const unsigned int sd2_wpb_pins0[] = { 123, };
> -static const unsigned int sd2_wpb_pins1[] = { 163, };
> -static const unsigned int sd3_9_pins[] = { 85, 86, 87, 88, 89, 90, };
> -static const unsigned int sd5_pins[] = { 91, 92, 93, 94, 95, 96, };
> -static const unsigned int sd6_pins0[] = { 79, 78, 74, 75, 76, 77, };
> -static const unsigned int sd6_pins1[] = { 101, 99, 100, 110, 109, 111, };
> -static const unsigned int sp0_ext_ldo_on_pins[] = { 4, };
> -static const unsigned int sp0_qspi_pins[] = { 12, 13, 14, 15, 16, 17, };
> -static const unsigned int sp1_spi_pins[] = { 19, 20, 21, 18, };
> -static const unsigned int tpiu_trace_pins[] = { 53, 56, 57, 58, 59, 60, 61,
> -               62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, };
> -static const unsigned int uart0_pins[] = { 121, 120, 134, 133, };
> -static const unsigned int uart0_nopause_pins[] = { 134, 133, };
> -static const unsigned int uart1_pins[] = { 136, 135, };
> -static const unsigned int uart2_cts_pins0[] = { 132, };
> -static const unsigned int uart2_cts_pins1[] = { 162, };
> -static const unsigned int uart2_rts_pins0[] = { 131, };
> -static const unsigned int uart2_rts_pins1[] = { 161, };
> -static const unsigned int uart2_rxd_pins0[] = { 11, };
> -static const unsigned int uart2_rxd_pins1[] = { 160, };
> -static const unsigned int uart2_rxd_pins2[] = { 130, };
> -static const unsigned int uart2_txd_pins0[] = { 10, };
> -static const unsigned int uart2_txd_pins1[] = { 159, };
> -static const unsigned int uart2_txd_pins2[] = { 129, };
> -static const unsigned int uart3_cts_pins0[] = { 125, };
> -static const unsigned int uart3_cts_pins1[] = { 111, };
> -static const unsigned int uart3_cts_pins2[] = { 140, };
> -static const unsigned int uart3_rts_pins0[] = { 126, };
> -static const unsigned int uart3_rts_pins1[] = { 109, };
> -static const unsigned int uart3_rts_pins2[] = { 139, };
> -static const unsigned int uart3_rxd_pins0[] = { 138, };
> -static const unsigned int uart3_rxd_pins1[] = { 84, };
> -static const unsigned int uart3_rxd_pins2[] = { 162, };
> -static const unsigned int uart3_txd_pins0[] = { 137, };
> -static const unsigned int uart3_txd_pins1[] = { 83, };
> -static const unsigned int uart3_txd_pins2[] = { 161, };
> -static const unsigned int uart4_basic_pins[] = { 140, 139, };
> -static const unsigned int uart4_cts_pins0[] = { 122, };
> -static const unsigned int uart4_cts_pins1[] = { 100, };
> -static const unsigned int uart4_cts_pins2[] = { 117, };
> -static const unsigned int uart4_rts_pins0[] = { 123, };
> -static const unsigned int uart4_rts_pins1[] = { 99, };
> -static const unsigned int uart4_rts_pins2[] = { 116, };
> -static const unsigned int usb0_drvvbus_pins0[] = { 51, };
> -static const unsigned int usb0_drvvbus_pins1[] = { 162, };
> -static const unsigned int usb1_drvvbus_pins0[] = { 134, };
> -static const unsigned int usb1_drvvbus_pins1[] = { 163, };
> -static const unsigned int visbus_dout_pins[] = { 57, 58, 59, 60, 61, 62, 63,
> -               64, 65, 66, 67, 68, 69, 70, 71, 72, 53, 54, 55, 56, 85, 86,
> -               87, 88, 89, 90, 91, 92, 93, 94, 95, 96, };
> -static const unsigned int vi_vip1_pins[] = { 74, 75, 76, 77, 78, 79, 80, 81,
> -               82, 83, 84, 103, 104, 105, 106, 107, 102, 97, 98, };
> -static const unsigned int vi_vip1_ext_pins[] = { 74, 75, 76, 77, 78, 79, 80,
> -               81, 82, 83, 84, 108, 103, 104, 105, 106, 107, 102, 97, 98,
> -               99, 100, };
> -static const unsigned int vi_vip1_low8bit_pins[] = { 74, 75, 76, 77, 78, 79,
> -               80, 81, 82, 83, 84, };
> -static const unsigned int vi_vip1_high8bit_pins[] = { 82, 83, 84, 103, 104,
> -               105, 106, 107, 102, 97, 98, };
> -
> -/* definition of pin group table */
> -static struct atlas7_pin_group altas7_pin_groups[] = {
> -       GROUP("gnss_gpio_grp", gnss_gpio_pins),
> -       GROUP("lcd_vip_gpio_grp", lcd_vip_gpio_pins),
> -       GROUP("sdio_i2s_gpio_grp", sdio_i2s_gpio_pins),
> -       GROUP("sp_rgmii_gpio_grp", sp_rgmii_gpio_pins),
> -       GROUP("lvds_gpio_grp", lvds_gpio_pins),
> -       GROUP("jtag_uart_nand_gpio_grp", jtag_uart_nand_gpio_pins),
> -       GROUP("rtc_gpio_grp", rtc_gpio_pins),
> -       GROUP("audio_ac97_grp", audio_ac97_pins),
> -       GROUP("audio_digmic_grp0", audio_digmic_pins0),
> -       GROUP("audio_digmic_grp1", audio_digmic_pins1),
> -       GROUP("audio_digmic_grp2", audio_digmic_pins2),
> -       GROUP("audio_func_dbg_grp", audio_func_dbg_pins),
> -       GROUP("audio_i2s_grp", audio_i2s_pins),
> -       GROUP("audio_i2s_2ch_grp", audio_i2s_2ch_pins),
> -       GROUP("audio_i2s_extclk_grp", audio_i2s_extclk_pins),
> -       GROUP("audio_spdif_out_grp0", audio_spdif_out_pins0),
> -       GROUP("audio_spdif_out_grp1", audio_spdif_out_pins1),
> -       GROUP("audio_spdif_out_grp2", audio_spdif_out_pins2),
> -       GROUP("audio_uart0_basic_grp", audio_uart0_basic_pins),
> -       GROUP("audio_uart0_urfs_grp0", audio_uart0_urfs_pins0),
> -       GROUP("audio_uart0_urfs_grp1", audio_uart0_urfs_pins1),
> -       GROUP("audio_uart0_urfs_grp2", audio_uart0_urfs_pins2),
> -       GROUP("audio_uart0_urfs_grp3", audio_uart0_urfs_pins3),
> -       GROUP("audio_uart1_basic_grp", audio_uart1_basic_pins),
> -       GROUP("audio_uart1_urfs_grp0", audio_uart1_urfs_pins0),
> -       GROUP("audio_uart1_urfs_grp1", audio_uart1_urfs_pins1),
> -       GROUP("audio_uart1_urfs_grp2", audio_uart1_urfs_pins2),
> -       GROUP("audio_uart2_urfs_grp0", audio_uart2_urfs_pins0),
> -       GROUP("audio_uart2_urfs_grp1", audio_uart2_urfs_pins1),
> -       GROUP("audio_uart2_urfs_grp2", audio_uart2_urfs_pins2),
> -       GROUP("audio_uart2_urxd_grp0", audio_uart2_urxd_pins0),
> -       GROUP("audio_uart2_urxd_grp1", audio_uart2_urxd_pins1),
> -       GROUP("audio_uart2_urxd_grp2", audio_uart2_urxd_pins2),
> -       GROUP("audio_uart2_usclk_grp0", audio_uart2_usclk_pins0),
> -       GROUP("audio_uart2_usclk_grp1", audio_uart2_usclk_pins1),
> -       GROUP("audio_uart2_usclk_grp2", audio_uart2_usclk_pins2),
> -       GROUP("audio_uart2_utfs_grp0", audio_uart2_utfs_pins0),
> -       GROUP("audio_uart2_utfs_grp1", audio_uart2_utfs_pins1),
> -       GROUP("audio_uart2_utfs_grp2", audio_uart2_utfs_pins2),
> -       GROUP("audio_uart2_utxd_grp0", audio_uart2_utxd_pins0),
> -       GROUP("audio_uart2_utxd_grp1", audio_uart2_utxd_pins1),
> -       GROUP("audio_uart2_utxd_grp2", audio_uart2_utxd_pins2),
> -       GROUP("c_can_trnsvr_en_grp0", c_can_trnsvr_en_pins0),
> -       GROUP("c_can_trnsvr_en_grp1", c_can_trnsvr_en_pins1),
> -       GROUP("c_can_trnsvr_intr_grp", c_can_trnsvr_intr_pins),
> -       GROUP("c_can_trnsvr_stb_n_grp", c_can_trnsvr_stb_n_pins),
> -       GROUP("c0_can_rxd_trnsv0_grp", c0_can_rxd_trnsv0_pins),
> -       GROUP("c0_can_rxd_trnsv1_grp", c0_can_rxd_trnsv1_pins),
> -       GROUP("c0_can_txd_trnsv0_grp", c0_can_txd_trnsv0_pins),
> -       GROUP("c0_can_txd_trnsv1_grp", c0_can_txd_trnsv1_pins),
> -       GROUP("c1_can_rxd_grp0", c1_can_rxd_pins0),
> -       GROUP("c1_can_rxd_grp1", c1_can_rxd_pins1),
> -       GROUP("c1_can_rxd_grp2", c1_can_rxd_pins2),
> -       GROUP("c1_can_rxd_grp3", c1_can_rxd_pins3),
> -       GROUP("c1_can_txd_grp0", c1_can_txd_pins0),
> -       GROUP("c1_can_txd_grp1", c1_can_txd_pins1),
> -       GROUP("c1_can_txd_grp2", c1_can_txd_pins2),
> -       GROUP("c1_can_txd_grp3", c1_can_txd_pins3),
> -       GROUP("ca_audio_lpc_grp", ca_audio_lpc_pins),
> -       GROUP("ca_bt_lpc_grp", ca_bt_lpc_pins),
> -       GROUP("ca_coex_grp", ca_coex_pins),
> -       GROUP("ca_curator_lpc_grp", ca_curator_lpc_pins),
> -       GROUP("ca_pcm_debug_grp", ca_pcm_debug_pins),
> -       GROUP("ca_pio_grp", ca_pio_pins),
> -       GROUP("ca_sdio_debug_grp", ca_sdio_debug_pins),
> -       GROUP("ca_spi_grp", ca_spi_pins),
> -       GROUP("ca_trb_grp", ca_trb_pins),
> -       GROUP("ca_uart_debug_grp", ca_uart_debug_pins),
> -       GROUP("clkc_grp0", clkc_pins0),
> -       GROUP("clkc_grp1", clkc_pins1),
> -       GROUP("gn_gnss_i2c_grp", gn_gnss_i2c_pins),
> -       GROUP("gn_gnss_uart_nopause_grp", gn_gnss_uart_nopause_pins),
> -       GROUP("gn_gnss_uart_grp", gn_gnss_uart_pins),
> -       GROUP("gn_trg_spi_grp0", gn_trg_spi_pins0),
> -       GROUP("gn_trg_spi_grp1", gn_trg_spi_pins1),
> -       GROUP("cvbs_dbg_grp", cvbs_dbg_pins),
> -       GROUP("cvbs_dbg_test_grp0", cvbs_dbg_test_pins0),
> -       GROUP("cvbs_dbg_test_grp1", cvbs_dbg_test_pins1),
> -       GROUP("cvbs_dbg_test_grp2", cvbs_dbg_test_pins2),
> -       GROUP("cvbs_dbg_test_grp3", cvbs_dbg_test_pins3),
> -       GROUP("cvbs_dbg_test_grp4", cvbs_dbg_test_pins4),
> -       GROUP("cvbs_dbg_test_grp5", cvbs_dbg_test_pins5),
> -       GROUP("cvbs_dbg_test_grp6", cvbs_dbg_test_pins6),
> -       GROUP("cvbs_dbg_test_grp7", cvbs_dbg_test_pins7),
> -       GROUP("cvbs_dbg_test_grp8", cvbs_dbg_test_pins8),
> -       GROUP("cvbs_dbg_test_grp9", cvbs_dbg_test_pins9),
> -       GROUP("cvbs_dbg_test_grp10", cvbs_dbg_test_pins10),
> -       GROUP("cvbs_dbg_test_grp11", cvbs_dbg_test_pins11),
> -       GROUP("cvbs_dbg_test_grp12", cvbs_dbg_test_pins12),
> -       GROUP("cvbs_dbg_test_grp13", cvbs_dbg_test_pins13),
> -       GROUP("cvbs_dbg_test_grp14", cvbs_dbg_test_pins14),
> -       GROUP("cvbs_dbg_test_grp15", cvbs_dbg_test_pins15),
> -       GROUP("gn_gnss_power_grp", gn_gnss_power_pins),
> -       GROUP("gn_gnss_sw_status_grp", gn_gnss_sw_status_pins),
> -       GROUP("gn_gnss_eclk_grp", gn_gnss_eclk_pins),
> -       GROUP("gn_gnss_irq1_grp0", gn_gnss_irq1_pins0),
> -       GROUP("gn_gnss_irq2_grp0", gn_gnss_irq2_pins0),
> -       GROUP("gn_gnss_tm_grp", gn_gnss_tm_pins),
> -       GROUP("gn_gnss_tsync_grp", gn_gnss_tsync_pins),
> -       GROUP("gn_io_gnsssys_sw_cfg_grp", gn_io_gnsssys_sw_cfg_pins),
> -       GROUP("gn_trg_grp0", gn_trg_pins0),
> -       GROUP("gn_trg_grp1", gn_trg_pins1),
> -       GROUP("gn_trg_shutdown_grp0", gn_trg_shutdown_pins0),
> -       GROUP("gn_trg_shutdown_grp1", gn_trg_shutdown_pins1),
> -       GROUP("gn_trg_shutdown_grp2", gn_trg_shutdown_pins2),
> -       GROUP("gn_trg_shutdown_grp3", gn_trg_shutdown_pins3),
> -       GROUP("i2c0_grp", i2c0_pins),
> -       GROUP("i2c1_grp", i2c1_pins),
> -       GROUP("i2s0_grp", i2s0_pins),
> -       GROUP("i2s1_basic_grp", i2s1_basic_pins),
> -       GROUP("i2s1_rxd0_grp0", i2s1_rxd0_pins0),
> -       GROUP("i2s1_rxd0_grp1", i2s1_rxd0_pins1),
> -       GROUP("i2s1_rxd0_grp2", i2s1_rxd0_pins2),
> -       GROUP("i2s1_rxd0_grp3", i2s1_rxd0_pins3),
> -       GROUP("i2s1_rxd0_grp4", i2s1_rxd0_pins4),
> -       GROUP("i2s1_rxd1_grp0", i2s1_rxd1_pins0),
> -       GROUP("i2s1_rxd1_grp1", i2s1_rxd1_pins1),
> -       GROUP("i2s1_rxd1_grp2", i2s1_rxd1_pins2),
> -       GROUP("i2s1_rxd1_grp3", i2s1_rxd1_pins3),
> -       GROUP("i2s1_rxd1_grp4", i2s1_rxd1_pins4),
> -       GROUP("jtag_jt_dbg_nsrst_grp", jtag_jt_dbg_nsrst_pins),
> -       GROUP("jtag_ntrst_grp0", jtag_ntrst_pins0),
> -       GROUP("jtag_ntrst_grp1", jtag_ntrst_pins1),
> -       GROUP("jtag_swdiotms_grp0", jtag_swdiotms_pins0),
> -       GROUP("jtag_swdiotms_grp1", jtag_swdiotms_pins1),
> -       GROUP("jtag_tck_grp0", jtag_tck_pins0),
> -       GROUP("jtag_tck_grp1", jtag_tck_pins1),
> -       GROUP("jtag_tdi_grp0", jtag_tdi_pins0),
> -       GROUP("jtag_tdi_grp1", jtag_tdi_pins1),
> -       GROUP("jtag_tdo_grp0", jtag_tdo_pins0),
> -       GROUP("jtag_tdo_grp1", jtag_tdo_pins1),
> -       GROUP("ks_kas_spi_grp0", ks_kas_spi_pins0),
> -       GROUP("ld_ldd_grp", ld_ldd_pins),
> -       GROUP("ld_ldd_16bit_grp", ld_ldd_16bit_pins),
> -       GROUP("ld_ldd_fck_grp", ld_ldd_fck_pins),
> -       GROUP("ld_ldd_lck_grp", ld_ldd_lck_pins),
> -       GROUP("lr_lcdrom_grp", lr_lcdrom_pins),
> -       GROUP("lvds_analog_grp", lvds_analog_pins),
> -       GROUP("nd_df_basic_grp", nd_df_basic_pins),
> -       GROUP("nd_df_wp_grp", nd_df_wp_pins),
> -       GROUP("nd_df_cs_grp", nd_df_cs_pins),
> -       GROUP("ps_grp", ps_pins),
> -       GROUP("ps_no_dir_grp", ps_no_dir_pins),
> -       GROUP("pwc_core_on_grp", pwc_core_on_pins),
> -       GROUP("pwc_ext_on_grp", pwc_ext_on_pins),
> -       GROUP("pwc_gpio3_clk_grp", pwc_gpio3_clk_pins),
> -       GROUP("pwc_io_on_grp", pwc_io_on_pins),
> -       GROUP("pwc_lowbatt_b_grp0", pwc_lowbatt_b_pins0),
> -       GROUP("pwc_mem_on_grp", pwc_mem_on_pins),
> -       GROUP("pwc_on_key_b_grp0", pwc_on_key_b_pins0),
> -       GROUP("pwc_wakeup_src0_grp", pwc_wakeup_src0_pins),
> -       GROUP("pwc_wakeup_src1_grp", pwc_wakeup_src1_pins),
> -       GROUP("pwc_wakeup_src2_grp", pwc_wakeup_src2_pins),
> -       GROUP("pwc_wakeup_src3_grp", pwc_wakeup_src3_pins),
> -       GROUP("pw_cko0_grp0", pw_cko0_pins0),
> -       GROUP("pw_cko0_grp1", pw_cko0_pins1),
> -       GROUP("pw_cko0_grp2", pw_cko0_pins2),
> -       GROUP("pw_cko0_grp3", pw_cko0_pins3),
> -       GROUP("pw_cko1_grp0", pw_cko1_pins0),
> -       GROUP("pw_cko1_grp1", pw_cko1_pins1),
> -       GROUP("pw_cko1_grp2", pw_cko1_pins2),
> -       GROUP("pw_i2s01_clk_grp0", pw_i2s01_clk_pins0),
> -       GROUP("pw_i2s01_clk_grp1", pw_i2s01_clk_pins1),
> -       GROUP("pw_i2s01_clk_grp2", pw_i2s01_clk_pins2),
> -       GROUP("pw_pwm0_grp0", pw_pwm0_pins0),
> -       GROUP("pw_pwm0_grp1", pw_pwm0_pins1),
> -       GROUP("pw_pwm1_grp0", pw_pwm1_pins0),
> -       GROUP("pw_pwm1_grp1", pw_pwm1_pins1),
> -       GROUP("pw_pwm1_grp2", pw_pwm1_pins2),
> -       GROUP("pw_pwm2_grp0", pw_pwm2_pins0),
> -       GROUP("pw_pwm2_grp1", pw_pwm2_pins1),
> -       GROUP("pw_pwm2_grp2", pw_pwm2_pins2),
> -       GROUP("pw_pwm3_grp0", pw_pwm3_pins0),
> -       GROUP("pw_pwm3_grp1", pw_pwm3_pins1),
> -       GROUP("pw_pwm_cpu_vol_grp0", pw_pwm_cpu_vol_pins0),
> -       GROUP("pw_pwm_cpu_vol_grp1", pw_pwm_cpu_vol_pins1),
> -       GROUP("pw_pwm_cpu_vol_grp2", pw_pwm_cpu_vol_pins2),
> -       GROUP("pw_backlight_grp0", pw_backlight_pins0),
> -       GROUP("pw_backlight_grp1", pw_backlight_pins1),
> -       GROUP("rg_eth_mac_grp", rg_eth_mac_pins),
> -       GROUP("rg_gmac_phy_intr_n_grp", rg_gmac_phy_intr_n_pins),
> -       GROUP("rg_rgmii_mac_grp", rg_rgmii_mac_pins),
> -       GROUP("rg_rgmii_phy_ref_clk_grp0", rg_rgmii_phy_ref_clk_pins0),
> -       GROUP("rg_rgmii_phy_ref_clk_grp1", rg_rgmii_phy_ref_clk_pins1),
> -       GROUP("sd0_grp", sd0_pins),
> -       GROUP("sd0_4bit_grp", sd0_4bit_pins),
> -       GROUP("sd1_grp", sd1_pins),
> -       GROUP("sd1_4bit_grp0", sd1_4bit_pins0),
> -       GROUP("sd1_4bit_grp1", sd1_4bit_pins1),
> -       GROUP("sd2_basic_grp", sd2_basic_pins),
> -       GROUP("sd2_cdb_grp0", sd2_cdb_pins0),
> -       GROUP("sd2_cdb_grp1", sd2_cdb_pins1),
> -       GROUP("sd2_wpb_grp0", sd2_wpb_pins0),
> -       GROUP("sd2_wpb_grp1", sd2_wpb_pins1),
> -       GROUP("sd3_9_grp", sd3_9_pins),
> -       GROUP("sd5_grp", sd5_pins),
> -       GROUP("sd6_grp0", sd6_pins0),
> -       GROUP("sd6_grp1", sd6_pins1),
> -       GROUP("sp0_ext_ldo_on_grp", sp0_ext_ldo_on_pins),
> -       GROUP("sp0_qspi_grp", sp0_qspi_pins),
> -       GROUP("sp1_spi_grp", sp1_spi_pins),
> -       GROUP("tpiu_trace_grp", tpiu_trace_pins),
> -       GROUP("uart0_grp", uart0_pins),
> -       GROUP("uart0_nopause_grp", uart0_nopause_pins),
> -       GROUP("uart1_grp", uart1_pins),
> -       GROUP("uart2_cts_grp0", uart2_cts_pins0),
> -       GROUP("uart2_cts_grp1", uart2_cts_pins1),
> -       GROUP("uart2_rts_grp0", uart2_rts_pins0),
> -       GROUP("uart2_rts_grp1", uart2_rts_pins1),
> -       GROUP("uart2_rxd_grp0", uart2_rxd_pins0),
> -       GROUP("uart2_rxd_grp1", uart2_rxd_pins1),
> -       GROUP("uart2_rxd_grp2", uart2_rxd_pins2),
> -       GROUP("uart2_txd_grp0", uart2_txd_pins0),
> -       GROUP("uart2_txd_grp1", uart2_txd_pins1),
> -       GROUP("uart2_txd_grp2", uart2_txd_pins2),
> -       GROUP("uart3_cts_grp0", uart3_cts_pins0),
> -       GROUP("uart3_cts_grp1", uart3_cts_pins1),
> -       GROUP("uart3_cts_grp2", uart3_cts_pins2),
> -       GROUP("uart3_rts_grp0", uart3_rts_pins0),
> -       GROUP("uart3_rts_grp1", uart3_rts_pins1),
> -       GROUP("uart3_rts_grp2", uart3_rts_pins2),
> -       GROUP("uart3_rxd_grp0", uart3_rxd_pins0),
> -       GROUP("uart3_rxd_grp1", uart3_rxd_pins1),
> -       GROUP("uart3_rxd_grp2", uart3_rxd_pins2),
> -       GROUP("uart3_txd_grp0", uart3_txd_pins0),
> -       GROUP("uart3_txd_grp1", uart3_txd_pins1),
> -       GROUP("uart3_txd_grp2", uart3_txd_pins2),
> -       GROUP("uart4_basic_grp", uart4_basic_pins),
> -       GROUP("uart4_cts_grp0", uart4_cts_pins0),
> -       GROUP("uart4_cts_grp1", uart4_cts_pins1),
> -       GROUP("uart4_cts_grp2", uart4_cts_pins2),
> -       GROUP("uart4_rts_grp0", uart4_rts_pins0),
> -       GROUP("uart4_rts_grp1", uart4_rts_pins1),
> -       GROUP("uart4_rts_grp2", uart4_rts_pins2),
> -       GROUP("usb0_drvvbus_grp0", usb0_drvvbus_pins0),
> -       GROUP("usb0_drvvbus_grp1", usb0_drvvbus_pins1),
> -       GROUP("usb1_drvvbus_grp0", usb1_drvvbus_pins0),
> -       GROUP("usb1_drvvbus_grp1", usb1_drvvbus_pins1),
> -       GROUP("visbus_dout_grp", visbus_dout_pins),
> -       GROUP("vi_vip1_grp", vi_vip1_pins),
> -       GROUP("vi_vip1_ext_grp", vi_vip1_ext_pins),
> -       GROUP("vi_vip1_low8bit_grp", vi_vip1_low8bit_pins),
> -       GROUP("vi_vip1_high8bit_grp", vi_vip1_high8bit_pins),
> -};
> -
> -/* How many groups that a function can use */
> -static const char * const gnss_gpio_grp[] = { "gnss_gpio_grp", };
> -static const char * const lcd_vip_gpio_grp[] = { "lcd_vip_gpio_grp", };
> -static const char * const sdio_i2s_gpio_grp[] = { "sdio_i2s_gpio_grp", };
> -static const char * const sp_rgmii_gpio_grp[] = { "sp_rgmii_gpio_grp", };
> -static const char * const lvds_gpio_grp[] = { "lvds_gpio_grp", };
> -static const char * const jtag_uart_nand_gpio_grp[] = {
> -                               "jtag_uart_nand_gpio_grp", };
> -static const char * const rtc_gpio_grp[] = { "rtc_gpio_grp", };
> -static const char * const audio_ac97_grp[] = { "audio_ac97_grp", };
> -static const char * const audio_digmic_grp0[] = { "audio_digmic_grp0", };
> -static const char * const audio_digmic_grp1[] = { "audio_digmic_grp1", };
> -static const char * const audio_digmic_grp2[] = { "audio_digmic_grp2", };
> -static const char * const audio_func_dbg_grp[] = { "audio_func_dbg_grp", };
> -static const char * const audio_i2s_grp[] = { "audio_i2s_grp", };
> -static const char * const audio_i2s_2ch_grp[] = { "audio_i2s_2ch_grp", };
> -static const char * const audio_i2s_extclk_grp[] = { "audio_i2s_extclk_grp", };
> -static const char * const audio_spdif_out_grp0[] = { "audio_spdif_out_grp0", };
> -static const char * const audio_spdif_out_grp1[] = { "audio_spdif_out_grp1", };
> -static const char * const audio_spdif_out_grp2[] = { "audio_spdif_out_grp2", };
> -static const char * const audio_uart0_basic_grp[] = {
> -                               "audio_uart0_basic_grp", };
> -static const char * const audio_uart0_urfs_grp0[] = {
> -                               "audio_uart0_urfs_grp0", };
> -static const char * const audio_uart0_urfs_grp1[] = {
> -                               "audio_uart0_urfs_grp1", };
> -static const char * const audio_uart0_urfs_grp2[] = {
> -                               "audio_uart0_urfs_grp2", };
> -static const char * const audio_uart0_urfs_grp3[] = {
> -                               "audio_uart0_urfs_grp3", };
> -static const char * const audio_uart1_basic_grp[] = {
> -                               "audio_uart1_basic_grp", };
> -static const char * const audio_uart1_urfs_grp0[] = {
> -                               "audio_uart1_urfs_grp0", };
> -static const char * const audio_uart1_urfs_grp1[] = {
> -                               "audio_uart1_urfs_grp1", };
> -static const char * const audio_uart1_urfs_grp2[] = {
> -                               "audio_uart1_urfs_grp2", };
> -static const char * const audio_uart2_urfs_grp0[] = {
> -                               "audio_uart2_urfs_grp0", };
> -static const char * const audio_uart2_urfs_grp1[] = {
> -                               "audio_uart2_urfs_grp1", };
> -static const char * const audio_uart2_urfs_grp2[] = {
> -                               "audio_uart2_urfs_grp2", };
> -static const char * const audio_uart2_urxd_grp0[] = {
> -                               "audio_uart2_urxd_grp0", };
> -static const char * const audio_uart2_urxd_grp1[] = {
> -                               "audio_uart2_urxd_grp1", };
> -static const char * const audio_uart2_urxd_grp2[] = {
> -                               "audio_uart2_urxd_grp2", };
> -static const char * const audio_uart2_usclk_grp0[] = {
> -                               "audio_uart2_usclk_grp0", };
> -static const char * const audio_uart2_usclk_grp1[] = {
> -                               "audio_uart2_usclk_grp1", };
> -static const char * const audio_uart2_usclk_grp2[] = {
> -                               "audio_uart2_usclk_grp2", };
> -static const char * const audio_uart2_utfs_grp0[] = {
> -                               "audio_uart2_utfs_grp0", };
> -static const char * const audio_uart2_utfs_grp1[] = {
> -                               "audio_uart2_utfs_grp1", };
> -static const char * const audio_uart2_utfs_grp2[] = {
> -                               "audio_uart2_utfs_grp2", };
> -static const char * const audio_uart2_utxd_grp0[] = {
> -                               "audio_uart2_utxd_grp0", };
> -static const char * const audio_uart2_utxd_grp1[] = {
> -                               "audio_uart2_utxd_grp1", };
> -static const char * const audio_uart2_utxd_grp2[] = {
> -                               "audio_uart2_utxd_grp2", };
> -static const char * const c_can_trnsvr_en_grp0[] = { "c_can_trnsvr_en_grp0", };
> -static const char * const c_can_trnsvr_en_grp1[] = { "c_can_trnsvr_en_grp1", };
> -static const char * const c_can_trnsvr_intr_grp[] = {
> -                               "c_can_trnsvr_intr_grp", };
> -static const char * const c_can_trnsvr_stb_n_grp[] = {
> -                               "c_can_trnsvr_stb_n_grp", };
> -static const char * const c0_can_rxd_trnsv0_grp[] = {
> -                               "c0_can_rxd_trnsv0_grp", };
> -static const char * const c0_can_rxd_trnsv1_grp[] = {
> -                               "c0_can_rxd_trnsv1_grp", };
> -static const char * const c0_can_txd_trnsv0_grp[] = {
> -                               "c0_can_txd_trnsv0_grp", };
> -static const char * const c0_can_txd_trnsv1_grp[] = {
> -                               "c0_can_txd_trnsv1_grp", };
> -static const char * const c1_can_rxd_grp0[] = { "c1_can_rxd_grp0", };
> -static const char * const c1_can_rxd_grp1[] = { "c1_can_rxd_grp1", };
> -static const char * const c1_can_rxd_grp2[] = { "c1_can_rxd_grp2", };
> -static const char * const c1_can_rxd_grp3[] = { "c1_can_rxd_grp3", };
> -static const char * const c1_can_txd_grp0[] = { "c1_can_txd_grp0", };
> -static const char * const c1_can_txd_grp1[] = { "c1_can_txd_grp1", };
> -static const char * const c1_can_txd_grp2[] = { "c1_can_txd_grp2", };
> -static const char * const c1_can_txd_grp3[] = { "c1_can_txd_grp3", };
> -static const char * const ca_audio_lpc_grp[] = { "ca_audio_lpc_grp", };
> -static const char * const ca_bt_lpc_grp[] = { "ca_bt_lpc_grp", };
> -static const char * const ca_coex_grp[] = { "ca_coex_grp", };
> -static const char * const ca_curator_lpc_grp[] = { "ca_curator_lpc_grp", };
> -static const char * const ca_pcm_debug_grp[] = { "ca_pcm_debug_grp", };
> -static const char * const ca_pio_grp[] = { "ca_pio_grp", };
> -static const char * const ca_sdio_debug_grp[] = { "ca_sdio_debug_grp", };
> -static const char * const ca_spi_grp[] = { "ca_spi_grp", };
> -static const char * const ca_trb_grp[] = { "ca_trb_grp", };
> -static const char * const ca_uart_debug_grp[] = { "ca_uart_debug_grp", };
> -static const char * const clkc_grp0[] = { "clkc_grp0", };
> -static const char * const clkc_grp1[] = { "clkc_grp1", };
> -static const char * const gn_gnss_i2c_grp[] = { "gn_gnss_i2c_grp", };
> -static const char * const gn_gnss_uart_nopause_grp[] = {
> -                               "gn_gnss_uart_nopause_grp", };
> -static const char * const gn_gnss_uart_grp[] = { "gn_gnss_uart_grp", };
> -static const char * const gn_trg_spi_grp0[] = { "gn_trg_spi_grp0", };
> -static const char * const gn_trg_spi_grp1[] = { "gn_trg_spi_grp1", };
> -static const char * const cvbs_dbg_grp[] = { "cvbs_dbg_grp", };
> -static const char * const cvbs_dbg_test_grp0[] = { "cvbs_dbg_test_grp0", };
> -static const char * const cvbs_dbg_test_grp1[] = { "cvbs_dbg_test_grp1", };
> -static const char * const cvbs_dbg_test_grp2[] = { "cvbs_dbg_test_grp2", };
> -static const char * const cvbs_dbg_test_grp3[] = { "cvbs_dbg_test_grp3", };
> -static const char * const cvbs_dbg_test_grp4[] = { "cvbs_dbg_test_grp4", };
> -static const char * const cvbs_dbg_test_grp5[] = { "cvbs_dbg_test_grp5", };
> -static const char * const cvbs_dbg_test_grp6[] = { "cvbs_dbg_test_grp6", };
> -static const char * const cvbs_dbg_test_grp7[] = { "cvbs_dbg_test_grp7", };
> -static const char * const cvbs_dbg_test_grp8[] = { "cvbs_dbg_test_grp8", };
> -static const char * const cvbs_dbg_test_grp9[] = { "cvbs_dbg_test_grp9", };
> -static const char * const cvbs_dbg_test_grp10[] = { "cvbs_dbg_test_grp10", };
> -static const char * const cvbs_dbg_test_grp11[] = { "cvbs_dbg_test_grp11", };
> -static const char * const cvbs_dbg_test_grp12[] = { "cvbs_dbg_test_grp12", };
> -static const char * const cvbs_dbg_test_grp13[] = { "cvbs_dbg_test_grp13", };
> -static const char * const cvbs_dbg_test_grp14[] = { "cvbs_dbg_test_grp14", };
> -static const char * const cvbs_dbg_test_grp15[] = { "cvbs_dbg_test_grp15", };
> -static const char * const gn_gnss_power_grp[] = { "gn_gnss_power_grp", };
> -static const char * const gn_gnss_sw_status_grp[] = {
> -                               "gn_gnss_sw_status_grp", };
> -static const char * const gn_gnss_eclk_grp[] = { "gn_gnss_eclk_grp", };
> -static const char * const gn_gnss_irq1_grp0[] = { "gn_gnss_irq1_grp0", };
> -static const char * const gn_gnss_irq2_grp0[] = { "gn_gnss_irq2_grp0", };
> -static const char * const gn_gnss_tm_grp[] = { "gn_gnss_tm_grp", };
> -static const char * const gn_gnss_tsync_grp[] = { "gn_gnss_tsync_grp", };
> -static const char * const gn_io_gnsssys_sw_cfg_grp[] = {
> -                               "gn_io_gnsssys_sw_cfg_grp", };
> -static const char * const gn_trg_grp0[] = { "gn_trg_grp0", };
> -static const char * const gn_trg_grp1[] = { "gn_trg_grp1", };
> -static const char * const gn_trg_shutdown_grp0[] = { "gn_trg_shutdown_grp0", };
> -static const char * const gn_trg_shutdown_grp1[] = { "gn_trg_shutdown_grp1", };
> -static const char * const gn_trg_shutdown_grp2[] = { "gn_trg_shutdown_grp2", };
> -static const char * const gn_trg_shutdown_grp3[] = { "gn_trg_shutdown_grp3", };
> -static const char * const i2c0_grp[] = { "i2c0_grp", };
> -static const char * const i2c1_grp[] = { "i2c1_grp", };
> -static const char * const i2s0_grp[] = { "i2s0_grp", };
> -static const char * const i2s1_basic_grp[] = { "i2s1_basic_grp", };
> -static const char * const i2s1_rxd0_grp0[] = { "i2s1_rxd0_grp0", };
> -static const char * const i2s1_rxd0_grp1[] = { "i2s1_rxd0_grp1", };
> -static const char * const i2s1_rxd0_grp2[] = { "i2s1_rxd0_grp2", };
> -static const char * const i2s1_rxd0_grp3[] = { "i2s1_rxd0_grp3", };
> -static const char * const i2s1_rxd0_grp4[] = { "i2s1_rxd0_grp4", };
> -static const char * const i2s1_rxd1_grp0[] = { "i2s1_rxd1_grp0", };
> -static const char * const i2s1_rxd1_grp1[] = { "i2s1_rxd1_grp1", };
> -static const char * const i2s1_rxd1_grp2[] = { "i2s1_rxd1_grp2", };
> -static const char * const i2s1_rxd1_grp3[] = { "i2s1_rxd1_grp3", };
> -static const char * const i2s1_rxd1_grp4[] = { "i2s1_rxd1_grp4", };
> -static const char * const jtag_jt_dbg_nsrst_grp[] = {
> -                               "jtag_jt_dbg_nsrst_grp", };
> -static const char * const jtag_ntrst_grp0[] = { "jtag_ntrst_grp0", };
> -static const char * const jtag_ntrst_grp1[] = { "jtag_ntrst_grp1", };
> -static const char * const jtag_swdiotms_grp0[] = { "jtag_swdiotms_grp0", };
> -static const char * const jtag_swdiotms_grp1[] = { "jtag_swdiotms_grp1", };
> -static const char * const jtag_tck_grp0[] = { "jtag_tck_grp0", };
> -static const char * const jtag_tck_grp1[] = { "jtag_tck_grp1", };
> -static const char * const jtag_tdi_grp0[] = { "jtag_tdi_grp0", };
> -static const char * const jtag_tdi_grp1[] = { "jtag_tdi_grp1", };
> -static const char * const jtag_tdo_grp0[] = { "jtag_tdo_grp0", };
> -static const char * const jtag_tdo_grp1[] = { "jtag_tdo_grp1", };
> -static const char * const ks_kas_spi_grp0[] = { "ks_kas_spi_grp0", };
> -static const char * const ld_ldd_grp[] = { "ld_ldd_grp", };
> -static const char * const ld_ldd_16bit_grp[] = { "ld_ldd_16bit_grp", };
> -static const char * const ld_ldd_fck_grp[] = { "ld_ldd_fck_grp", };
> -static const char * const ld_ldd_lck_grp[] = { "ld_ldd_lck_grp", };
> -static const char * const lr_lcdrom_grp[] = { "lr_lcdrom_grp", };
> -static const char * const lvds_analog_grp[] = { "lvds_analog_grp", };
> -static const char * const nd_df_basic_grp[] = { "nd_df_basic_grp", };
> -static const char * const nd_df_wp_grp[] = { "nd_df_wp_grp", };
> -static const char * const nd_df_cs_grp[] = { "nd_df_cs_grp", };
> -static const char * const ps_grp[] = { "ps_grp", };
> -static const char * const ps_no_dir_grp[] = { "ps_no_dir_grp", };
> -static const char * const pwc_core_on_grp[] = { "pwc_core_on_grp", };
> -static const char * const pwc_ext_on_grp[] = { "pwc_ext_on_grp", };
> -static const char * const pwc_gpio3_clk_grp[] = { "pwc_gpio3_clk_grp", };
> -static const char * const pwc_io_on_grp[] = { "pwc_io_on_grp", };
> -static const char * const pwc_lowbatt_b_grp0[] = { "pwc_lowbatt_b_grp0", };
> -static const char * const pwc_mem_on_grp[] = { "pwc_mem_on_grp", };
> -static const char * const pwc_on_key_b_grp0[] = { "pwc_on_key_b_grp0", };
> -static const char * const pwc_wakeup_src0_grp[] = { "pwc_wakeup_src0_grp", };
> -static const char * const pwc_wakeup_src1_grp[] = { "pwc_wakeup_src1_grp", };
> -static const char * const pwc_wakeup_src2_grp[] = { "pwc_wakeup_src2_grp", };
> -static const char * const pwc_wakeup_src3_grp[] = { "pwc_wakeup_src3_grp", };
> -static const char * const pw_cko0_grp0[] = { "pw_cko0_grp0", };
> -static const char * const pw_cko0_grp1[] = { "pw_cko0_grp1", };
> -static const char * const pw_cko0_grp2[] = { "pw_cko0_grp2", };
> -static const char * const pw_cko0_grp3[] = { "pw_cko0_grp3", };
> -static const char * const pw_cko1_grp0[] = { "pw_cko1_grp0", };
> -static const char * const pw_cko1_grp1[] = { "pw_cko1_grp1", };
> -static const char * const pw_cko1_grp2[] = { "pw_cko1_grp2", };
> -static const char * const pw_i2s01_clk_grp0[] = { "pw_i2s01_clk_grp0", };
> -static const char * const pw_i2s01_clk_grp1[] = { "pw_i2s01_clk_grp1", };
> -static const char * const pw_i2s01_clk_grp2[] = { "pw_i2s01_clk_grp2", };
> -static const char * const pw_pwm0_grp0[] = { "pw_pwm0_grp0", };
> -static const char * const pw_pwm0_grp1[] = { "pw_pwm0_grp1", };
> -static const char * const pw_pwm1_grp0[] = { "pw_pwm1_grp0", };
> -static const char * const pw_pwm1_grp1[] = { "pw_pwm1_grp1", };
> -static const char * const pw_pwm1_grp2[] = { "pw_pwm1_grp2", };
> -static const char * const pw_pwm2_grp0[] = { "pw_pwm2_grp0", };
> -static const char * const pw_pwm2_grp1[] = { "pw_pwm2_grp1", };
> -static const char * const pw_pwm2_grp2[] = { "pw_pwm2_grp2", };
> -static const char * const pw_pwm3_grp0[] = { "pw_pwm3_grp0", };
> -static const char * const pw_pwm3_grp1[] = { "pw_pwm3_grp1", };
> -static const char * const pw_pwm_cpu_vol_grp0[] = { "pw_pwm_cpu_vol_grp0", };
> -static const char * const pw_pwm_cpu_vol_grp1[] = { "pw_pwm_cpu_vol_grp1", };
> -static const char * const pw_pwm_cpu_vol_grp2[] = { "pw_pwm_cpu_vol_grp2", };
> -static const char * const pw_backlight_grp0[] = { "pw_backlight_grp0", };
> -static const char * const pw_backlight_grp1[] = { "pw_backlight_grp1", };
> -static const char * const rg_eth_mac_grp[] = { "rg_eth_mac_grp", };
> -static const char * const rg_gmac_phy_intr_n_grp[] = {
> -                               "rg_gmac_phy_intr_n_grp", };
> -static const char * const rg_rgmii_mac_grp[] = { "rg_rgmii_mac_grp", };
> -static const char * const rg_rgmii_phy_ref_clk_grp0[] = {
> -                               "rg_rgmii_phy_ref_clk_grp0", };
> -static const char * const rg_rgmii_phy_ref_clk_grp1[] = {
> -                               "rg_rgmii_phy_ref_clk_grp1", };
> -static const char * const sd0_grp[] = { "sd0_grp", };
> -static const char * const sd0_4bit_grp[] = { "sd0_4bit_grp", };
> -static const char * const sd1_grp[] = { "sd1_grp", };
> -static const char * const sd1_4bit_grp0[] = { "sd1_4bit_grp0", };
> -static const char * const sd1_4bit_grp1[] = { "sd1_4bit_grp1", };
> -static const char * const sd2_basic_grp[] = { "sd2_basic_grp", };
> -static const char * const sd2_cdb_grp0[] = { "sd2_cdb_grp0", };
> -static const char * const sd2_cdb_grp1[] = { "sd2_cdb_grp1", };
> -static const char * const sd2_wpb_grp0[] = { "sd2_wpb_grp0", };
> -static const char * const sd2_wpb_grp1[] = { "sd2_wpb_grp1", };
> -static const char * const sd3_9_grp[] = { "sd3_9_grp", };
> -static const char * const sd5_grp[] = { "sd5_grp", };
> -static const char * const sd6_grp0[] = { "sd6_grp0", };
> -static const char * const sd6_grp1[] = { "sd6_grp1", };
> -static const char * const sp0_ext_ldo_on_grp[] = { "sp0_ext_ldo_on_grp", };
> -static const char * const sp0_qspi_grp[] = { "sp0_qspi_grp", };
> -static const char * const sp1_spi_grp[] = { "sp1_spi_grp", };
> -static const char * const tpiu_trace_grp[] = { "tpiu_trace_grp", };
> -static const char * const uart0_grp[] = { "uart0_grp", };
> -static const char * const uart0_nopause_grp[] = { "uart0_nopause_grp", };
> -static const char * const uart1_grp[] = { "uart1_grp", };
> -static const char * const uart2_cts_grp0[] = { "uart2_cts_grp0", };
> -static const char * const uart2_cts_grp1[] = { "uart2_cts_grp1", };
> -static const char * const uart2_rts_grp0[] = { "uart2_rts_grp0", };
> -static const char * const uart2_rts_grp1[] = { "uart2_rts_grp1", };
> -static const char * const uart2_rxd_grp0[] = { "uart2_rxd_grp0", };
> -static const char * const uart2_rxd_grp1[] = { "uart2_rxd_grp1", };
> -static const char * const uart2_rxd_grp2[] = { "uart2_rxd_grp2", };
> -static const char * const uart2_txd_grp0[] = { "uart2_txd_grp0", };
> -static const char * const uart2_txd_grp1[] = { "uart2_txd_grp1", };
> -static const char * const uart2_txd_grp2[] = { "uart2_txd_grp2", };
> -static const char * const uart3_cts_grp0[] = { "uart3_cts_grp0", };
> -static const char * const uart3_cts_grp1[] = { "uart3_cts_grp1", };
> -static const char * const uart3_cts_grp2[] = { "uart3_cts_grp2", };
> -static const char * const uart3_rts_grp0[] = { "uart3_rts_grp0", };
> -static const char * const uart3_rts_grp1[] = { "uart3_rts_grp1", };
> -static const char * const uart3_rts_grp2[] = { "uart3_rts_grp2", };
> -static const char * const uart3_rxd_grp0[] = { "uart3_rxd_grp0", };
> -static const char * const uart3_rxd_grp1[] = { "uart3_rxd_grp1", };
> -static const char * const uart3_rxd_grp2[] = { "uart3_rxd_grp2", };
> -static const char * const uart3_txd_grp0[] = { "uart3_txd_grp0", };
> -static const char * const uart3_txd_grp1[] = { "uart3_txd_grp1", };
> -static const char * const uart3_txd_grp2[] = { "uart3_txd_grp2", };
> -static const char * const uart4_basic_grp[] = { "uart4_basic_grp", };
> -static const char * const uart4_cts_grp0[] = { "uart4_cts_grp0", };
> -static const char * const uart4_cts_grp1[] = { "uart4_cts_grp1", };
> -static const char * const uart4_cts_grp2[] = { "uart4_cts_grp2", };
> -static const char * const uart4_rts_grp0[] = { "uart4_rts_grp0", };
> -static const char * const uart4_rts_grp1[] = { "uart4_rts_grp1", };
> -static const char * const uart4_rts_grp2[] = { "uart4_rts_grp2", };
> -static const char * const usb0_drvvbus_grp0[] = { "usb0_drvvbus_grp0", };
> -static const char * const usb0_drvvbus_grp1[] = { "usb0_drvvbus_grp1", };
> -static const char * const usb1_drvvbus_grp0[] = { "usb1_drvvbus_grp0", };
> -static const char * const usb1_drvvbus_grp1[] = { "usb1_drvvbus_grp1", };
> -static const char * const visbus_dout_grp[] = { "visbus_dout_grp", };
> -static const char * const vi_vip1_grp[] = { "vi_vip1_grp", };
> -static const char * const vi_vip1_ext_grp[] = { "vi_vip1_ext_grp", };
> -static const char * const vi_vip1_low8bit_grp[] = { "vi_vip1_low8bit_grp", };
> -static const char * const vi_vip1_high8bit_grp[] = { "vi_vip1_high8bit_grp", };
> -
> -static struct atlas7_pad_mux gnss_gpio_grp_pad_mux[] = {
> -       MUX(1, 119, 0, N, N, N, N),
> -       MUX(1, 120, 0, N, N, N, N),
> -       MUX(1, 121, 0, N, N, N, N),
> -       MUX(1, 122, 0, N, N, N, N),
> -       MUX(1, 123, 0, N, N, N, N),
> -       MUX(1, 124, 0, N, N, N, N),
> -       MUX(1, 125, 0, N, N, N, N),
> -       MUX(1, 126, 0, N, N, N, N),
> -       MUX(1, 127, 0, N, N, N, N),
> -       MUX(1, 128, 0, N, N, N, N),
> -       MUX(1, 22, 0, N, N, N, N),
> -       MUX(1, 23, 0, N, N, N, N),
> -       MUX(1, 24, 0, N, N, N, N),
> -       MUX(1, 25, 0, N, N, N, N),
> -       MUX(1, 26, 0, N, N, N, N),
> -       MUX(1, 27, 0, N, N, N, N),
> -       MUX(1, 28, 0, N, N, N, N),
> -       MUX(1, 29, 0, N, N, N, N),
> -       MUX(1, 30, 0, N, N, N, N),
> -};
> -
> -static struct atlas7_grp_mux gnss_gpio_grp_mux = {
> -       .pad_mux_count = ARRAY_SIZE(gnss_gpio_grp_pad_mux),
> -       .pad_mux_list = gnss_gpio_grp_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux lcd_vip_gpio_grp_pad_mux[] = {
> -       MUX(1, 74, 0, N, N, N, N),
> -       MUX(1, 75, 0, N, N, N, N),
> -       MUX(1, 76, 0, N, N, N, N),
> -       MUX(1, 77, 0, N, N, N, N),
> -       MUX(1, 78, 0, N, N, N, N),
> -       MUX(1, 79, 0, N, N, N, N),
> -       MUX(1, 80, 0, N, N, N, N),
> -       MUX(1, 81, 0, N, N, N, N),
> -       MUX(1, 82, 0, N, N, N, N),
> -       MUX(1, 83, 0, N, N, N, N),
> -       MUX(1, 84, 0, N, N, N, N),
> -       MUX(1, 53, 0, N, N, N, N),
> -       MUX(1, 54, 0, N, N, N, N),
> -       MUX(1, 55, 0, N, N, N, N),
> -       MUX(1, 56, 0, N, N, N, N),
> -       MUX(1, 57, 0, N, N, N, N),
> -       MUX(1, 58, 0, N, N, N, N),
> -       MUX(1, 59, 0, N, N, N, N),
> -       MUX(1, 60, 0, N, N, N, N),
> -       MUX(1, 61, 0, N, N, N, N),
> -       MUX(1, 62, 0, N, N, N, N),
> -       MUX(1, 63, 0, N, N, N, N),
> -       MUX(1, 64, 0, N, N, N, N),
> -       MUX(1, 65, 0, N, N, N, N),
> -       MUX(1, 66, 0, N, N, N, N),
> -       MUX(1, 67, 0, N, N, N, N),
> -       MUX(1, 68, 0, N, N, N, N),
> -       MUX(1, 69, 0, N, N, N, N),
> -       MUX(1, 70, 0, N, N, N, N),
> -       MUX(1, 71, 0, N, N, N, N),
> -       MUX(1, 72, 0, N, N, N, N),
> -       MUX(1, 73, 0, N, N, N, N),
> -};
> -
> -static struct atlas7_grp_mux lcd_vip_gpio_grp_mux = {
> -       .pad_mux_count = ARRAY_SIZE(lcd_vip_gpio_grp_pad_mux),
> -       .pad_mux_list = lcd_vip_gpio_grp_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux sdio_i2s_gpio_grp_pad_mux[] = {
> -       MUX(1, 31, 0, N, N, N, N),
> -       MUX(1, 32, 0, N, N, N, N),
> -       MUX(1, 33, 0, N, N, N, N),
> -       MUX(1, 34, 0, N, N, N, N),
> -       MUX(1, 35, 0, N, N, N, N),
> -       MUX(1, 36, 0, N, N, N, N),
> -       MUX(1, 85, 0, N, N, N, N),
> -       MUX(1, 86, 0, N, N, N, N),
> -       MUX(1, 87, 0, N, N, N, N),
> -       MUX(1, 88, 0, N, N, N, N),
> -       MUX(1, 89, 0, N, N, N, N),
> -       MUX(1, 90, 0, N, N, N, N),
> -       MUX(1, 129, 0, N, N, N, N),
> -       MUX(1, 130, 0, N, N, N, N),
> -       MUX(1, 131, 0, N, N, N, N),
> -       MUX(1, 132, 0, N, N, N, N),
> -       MUX(1, 91, 0, N, N, N, N),
> -       MUX(1, 92, 0, N, N, N, N),
> -       MUX(1, 93, 0, N, N, N, N),
> -       MUX(1, 94, 0, N, N, N, N),
> -       MUX(1, 95, 0, N, N, N, N),
> -       MUX(1, 96, 0, N, N, N, N),
> -       MUX(1, 112, 0, N, N, N, N),
> -       MUX(1, 113, 0, N, N, N, N),
> -       MUX(1, 114, 0, N, N, N, N),
> -       MUX(1, 115, 0, N, N, N, N),
> -       MUX(1, 116, 0, N, N, N, N),
> -       MUX(1, 117, 0, N, N, N, N),
> -       MUX(1, 118, 0, N, N, N, N),
> -};
> -
> -static struct atlas7_grp_mux sdio_i2s_gpio_grp_mux = {
> -       .pad_mux_count = ARRAY_SIZE(sdio_i2s_gpio_grp_pad_mux),
> -       .pad_mux_list = sdio_i2s_gpio_grp_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux sp_rgmii_gpio_grp_pad_mux[] = {
> -       MUX(1, 97, 0, N, N, N, N),
> -       MUX(1, 98, 0, N, N, N, N),
> -       MUX(1, 99, 0, N, N, N, N),
> -       MUX(1, 100, 0, N, N, N, N),
> -       MUX(1, 101, 0, N, N, N, N),
> -       MUX(1, 102, 0, N, N, N, N),
> -       MUX(1, 103, 0, N, N, N, N),
> -       MUX(1, 104, 0, N, N, N, N),
> -       MUX(1, 105, 0, N, N, N, N),
> -       MUX(1, 106, 0, N, N, N, N),
> -       MUX(1, 107, 0, N, N, N, N),
> -       MUX(1, 108, 0, N, N, N, N),
> -       MUX(1, 109, 0, N, N, N, N),
> -       MUX(1, 110, 0, N, N, N, N),
> -       MUX(1, 111, 0, N, N, N, N),
> -       MUX(1, 18, 0, N, N, N, N),
> -       MUX(1, 19, 0, N, N, N, N),
> -       MUX(1, 20, 0, N, N, N, N),
> -       MUX(1, 21, 0, N, N, N, N),
> -       MUX(1, 141, 0, N, N, N, N),
> -       MUX(1, 142, 0, N, N, N, N),
> -       MUX(1, 143, 0, N, N, N, N),
> -       MUX(1, 144, 0, N, N, N, N),
> -       MUX(1, 145, 0, N, N, N, N),
> -       MUX(1, 146, 0, N, N, N, N),
> -       MUX(1, 147, 0, N, N, N, N),
> -       MUX(1, 148, 0, N, N, N, N),
> -};
> -
> -static struct atlas7_grp_mux sp_rgmii_gpio_grp_mux = {
> -       .pad_mux_count = ARRAY_SIZE(sp_rgmii_gpio_grp_pad_mux),
> -       .pad_mux_list = sp_rgmii_gpio_grp_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux lvds_gpio_grp_pad_mux[] = {
> -       MUX(1, 157, 0, N, N, N, N),
> -       MUX(1, 158, 0, N, N, N, N),
> -       MUX(1, 155, 0, N, N, N, N),
> -       MUX(1, 156, 0, N, N, N, N),
> -       MUX(1, 153, 0, N, N, N, N),
> -       MUX(1, 154, 0, N, N, N, N),
> -       MUX(1, 151, 0, N, N, N, N),
> -       MUX(1, 152, 0, N, N, N, N),
> -       MUX(1, 149, 0, N, N, N, N),
> -       MUX(1, 150, 0, N, N, N, N),
> -};
> -
> -static struct atlas7_grp_mux lvds_gpio_grp_mux = {
> -       .pad_mux_count = ARRAY_SIZE(lvds_gpio_grp_pad_mux),
> -       .pad_mux_list = lvds_gpio_grp_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux jtag_uart_nand_gpio_grp_pad_mux[] = {
> -       MUX(1, 44, 0, N, N, N, N),
> -       MUX(1, 43, 0, N, N, N, N),
> -       MUX(1, 42, 0, N, N, N, N),
> -       MUX(1, 41, 0, N, N, N, N),
> -       MUX(1, 40, 0, N, N, N, N),
> -       MUX(1, 39, 0, N, N, N, N),
> -       MUX(1, 38, 0, N, N, N, N),
> -       MUX(1, 37, 0, N, N, N, N),
> -       MUX(1, 46, 0, N, N, N, N),
> -       MUX(1, 47, 0, N, N, N, N),
> -       MUX(1, 48, 0, N, N, N, N),
> -       MUX(1, 49, 0, N, N, N, N),
> -       MUX(1, 50, 0, N, N, N, N),
> -       MUX(1, 52, 0, N, N, N, N),
> -       MUX(1, 51, 0, N, N, N, N),
> -       MUX(1, 45, 0, N, N, N, N),
> -       MUX(1, 133, 0, N, N, N, N),
> -       MUX(1, 134, 0, N, N, N, N),
> -       MUX(1, 135, 0, N, N, N, N),
> -       MUX(1, 136, 0, N, N, N, N),
> -       MUX(1, 137, 0, N, N, N, N),
> -       MUX(1, 138, 0, N, N, N, N),
> -       MUX(1, 139, 0, N, N, N, N),
> -       MUX(1, 140, 0, N, N, N, N),
> -       MUX(1, 159, 0, N, N, N, N),
> -       MUX(1, 160, 0, N, N, N, N),
> -       MUX(1, 161, 0, N, N, N, N),
> -       MUX(1, 162, 0, N, N, N, N),
> -       MUX(1, 163, 0, N, N, N, N),
> -};
> -
> -static struct atlas7_grp_mux jtag_uart_nand_gpio_grp_mux = {
> -       .pad_mux_count = ARRAY_SIZE(jtag_uart_nand_gpio_grp_pad_mux),
> -       .pad_mux_list = jtag_uart_nand_gpio_grp_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux rtc_gpio_grp_pad_mux[] = {
> -       MUX(0, 0, 0, N, N, N, N),
> -       MUX(0, 1, 0, N, N, N, N),
> -       MUX(0, 2, 0, N, N, N, N),
> -       MUX(0, 3, 0, N, N, N, N),
> -       MUX(0, 4, 0, N, N, N, N),
> -       MUX(0, 10, 0, N, N, N, N),
> -       MUX(0, 11, 0, N, N, N, N),
> -       MUX(0, 12, 0, N, N, N, N),
> -       MUX(0, 13, 0, N, N, N, N),
> -       MUX(0, 14, 0, N, N, N, N),
> -       MUX(0, 15, 0, N, N, N, N),
> -       MUX(0, 16, 0, N, N, N, N),
> -       MUX(0, 17, 0, N, N, N, N),
> -       MUX(0, 9, 0, N, N, N, N),
> -};
> -
> -static struct atlas7_grp_mux rtc_gpio_grp_mux = {
> -       .pad_mux_count = ARRAY_SIZE(rtc_gpio_grp_pad_mux),
> -       .pad_mux_list = rtc_gpio_grp_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux audio_ac97_grp_pad_mux[] = {
> -       MUX(1, 113, 2, N, N, N, N),
> -       MUX(1, 118, 2, N, N, N, N),
> -       MUX(1, 115, 2, N, N, N, N),
> -       MUX(1, 114, 2, N, N, N, N),
> -};
> -
> -static struct atlas7_grp_mux audio_ac97_grp_mux = {
> -       .pad_mux_count = ARRAY_SIZE(audio_ac97_grp_pad_mux),
> -       .pad_mux_list = audio_ac97_grp_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux audio_digmic_grp0_pad_mux[] = {
> -       MUX(1, 51, 3, 0xa10, 20, 0xa90, 20),
> -};
> -
> -static struct atlas7_grp_mux audio_digmic_grp0_mux = {
> -       .pad_mux_count = ARRAY_SIZE(audio_digmic_grp0_pad_mux),
> -       .pad_mux_list = audio_digmic_grp0_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux audio_digmic_grp1_pad_mux[] = {
> -       MUX(1, 122, 5, 0xa10, 20, 0xa90, 20),
> -};
> -
> -static struct atlas7_grp_mux audio_digmic_grp1_mux = {
> -       .pad_mux_count = ARRAY_SIZE(audio_digmic_grp1_pad_mux),
> -       .pad_mux_list = audio_digmic_grp1_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux audio_digmic_grp2_pad_mux[] = {
> -       MUX(1, 161, 7, 0xa10, 20, 0xa90, 20),
> -};
> -
> -static struct atlas7_grp_mux audio_digmic_grp2_mux = {
> -       .pad_mux_count = ARRAY_SIZE(audio_digmic_grp2_pad_mux),
> -       .pad_mux_list = audio_digmic_grp2_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux audio_func_dbg_grp_pad_mux[] = {
> -       MUX(1, 141, 4, N, N, N, N),
> -       MUX(1, 144, 4, N, N, N, N),
> -       MUX(1, 44, 6, N, N, N, N),
> -       MUX(1, 43, 6, N, N, N, N),
> -       MUX(1, 42, 6, N, N, N, N),
> -       MUX(1, 41, 6, N, N, N, N),
> -       MUX(1, 40, 6, N, N, N, N),
> -       MUX(1, 39, 6, N, N, N, N),
> -       MUX(1, 38, 6, N, N, N, N),
> -       MUX(1, 37, 6, N, N, N, N),
> -       MUX(1, 74, 6, N, N, N, N),
> -       MUX(1, 75, 6, N, N, N, N),
> -       MUX(1, 76, 6, N, N, N, N),
> -       MUX(1, 77, 6, N, N, N, N),
> -       MUX(1, 78, 6, N, N, N, N),
> -       MUX(1, 79, 6, N, N, N, N),
> -       MUX(1, 81, 6, N, N, N, N),
> -       MUX(1, 113, 6, N, N, N, N),
> -       MUX(1, 114, 6, N, N, N, N),
> -       MUX(1, 118, 6, N, N, N, N),
> -       MUX(1, 115, 6, N, N, N, N),
> -       MUX(1, 49, 6, N, N, N, N),
> -       MUX(1, 50, 6, N, N, N, N),
> -       MUX(1, 142, 4, N, N, N, N),
> -       MUX(1, 143, 4, N, N, N, N),
> -       MUX(1, 80, 6, N, N, N, N),
> -};
> -
> -static struct atlas7_grp_mux audio_func_dbg_grp_mux = {
> -       .pad_mux_count = ARRAY_SIZE(audio_func_dbg_grp_pad_mux),
> -       .pad_mux_list = audio_func_dbg_grp_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux audio_i2s_grp_pad_mux[] = {
> -       MUX(1, 118, 1, N, N, N, N),
> -       MUX(1, 115, 1, N, N, N, N),
> -       MUX(1, 116, 1, N, N, N, N),
> -       MUX(1, 117, 1, N, N, N, N),
> -       MUX(1, 112, 1, N, N, N, N),
> -       MUX(1, 113, 1, N, N, N, N),
> -       MUX(1, 114, 1, N, N, N, N),
> -};
> -
> -static struct atlas7_grp_mux audio_i2s_grp_mux = {
> -       .pad_mux_count = ARRAY_SIZE(audio_i2s_grp_pad_mux),
> -       .pad_mux_list = audio_i2s_grp_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux audio_i2s_2ch_grp_pad_mux[] = {
> -       MUX(1, 118, 1, N, N, N, N),
> -       MUX(1, 115, 1, N, N, N, N),
> -       MUX(1, 112, 1, N, N, N, N),
> -       MUX(1, 113, 1, N, N, N, N),
> -       MUX(1, 114, 1, N, N, N, N),
> -};
> -
> -static struct atlas7_grp_mux audio_i2s_2ch_grp_mux = {
> -       .pad_mux_count = ARRAY_SIZE(audio_i2s_2ch_grp_pad_mux),
> -       .pad_mux_list = audio_i2s_2ch_grp_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux audio_i2s_extclk_grp_pad_mux[] = {
> -       MUX(1, 112, 2, N, N, N, N),
> -};
> -
> -static struct atlas7_grp_mux audio_i2s_extclk_grp_mux = {
> -       .pad_mux_count = ARRAY_SIZE(audio_i2s_extclk_grp_pad_mux),
> -       .pad_mux_list = audio_i2s_extclk_grp_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux audio_spdif_out_grp0_pad_mux[] = {
> -       MUX(1, 112, 3, N, N, N, N),
> -};
> -
> -static struct atlas7_grp_mux audio_spdif_out_grp0_mux = {
> -       .pad_mux_count = ARRAY_SIZE(audio_spdif_out_grp0_pad_mux),
> -       .pad_mux_list = audio_spdif_out_grp0_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux audio_spdif_out_grp1_pad_mux[] = {
> -       MUX(1, 116, 3, N, N, N, N),
> -};
> -
> -static struct atlas7_grp_mux audio_spdif_out_grp1_mux = {
> -       .pad_mux_count = ARRAY_SIZE(audio_spdif_out_grp1_pad_mux),
> -       .pad_mux_list = audio_spdif_out_grp1_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux audio_spdif_out_grp2_pad_mux[] = {
> -       MUX(1, 142, 3, N, N, N, N),
> -};
> -
> -static struct atlas7_grp_mux audio_spdif_out_grp2_mux = {
> -       .pad_mux_count = ARRAY_SIZE(audio_spdif_out_grp2_pad_mux),
> -       .pad_mux_list = audio_spdif_out_grp2_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux audio_uart0_basic_grp_pad_mux[] = {
> -       MUX(1, 143, 1, N, N, N, N),
> -       MUX(1, 142, 1, N, N, N, N),
> -       MUX(1, 141, 1, N, N, N, N),
> -       MUX(1, 144, 1, N, N, N, N),
> -};
> -
> -static struct atlas7_grp_mux audio_uart0_basic_grp_mux = {
> -       .pad_mux_count = ARRAY_SIZE(audio_uart0_basic_grp_pad_mux),
> -       .pad_mux_list = audio_uart0_basic_grp_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux audio_uart0_urfs_grp0_pad_mux[] = {
> -       MUX(1, 117, 5, 0xa10, 28, 0xa90, 28),
> -};
> -
> -static struct atlas7_grp_mux audio_uart0_urfs_grp0_mux = {
> -       .pad_mux_count = ARRAY_SIZE(audio_uart0_urfs_grp0_pad_mux),
> -       .pad_mux_list = audio_uart0_urfs_grp0_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux audio_uart0_urfs_grp1_pad_mux[] = {
> -       MUX(1, 139, 3, 0xa10, 28, 0xa90, 28),
> -};
> -
> -static struct atlas7_grp_mux audio_uart0_urfs_grp1_mux = {
> -       .pad_mux_count = ARRAY_SIZE(audio_uart0_urfs_grp1_pad_mux),
> -       .pad_mux_list = audio_uart0_urfs_grp1_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux audio_uart0_urfs_grp2_pad_mux[] = {
> -       MUX(1, 163, 3, 0xa10, 28, 0xa90, 28),
> -};
> -
> -static struct atlas7_grp_mux audio_uart0_urfs_grp2_mux = {
> -       .pad_mux_count = ARRAY_SIZE(audio_uart0_urfs_grp2_pad_mux),
> -       .pad_mux_list = audio_uart0_urfs_grp2_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux audio_uart0_urfs_grp3_pad_mux[] = {
> -       MUX(1, 162, 6, 0xa10, 28, 0xa90, 28),
> -};
> -
> -static struct atlas7_grp_mux audio_uart0_urfs_grp3_mux = {
> -       .pad_mux_count = ARRAY_SIZE(audio_uart0_urfs_grp3_pad_mux),
> -       .pad_mux_list = audio_uart0_urfs_grp3_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux audio_uart1_basic_grp_pad_mux[] = {
> -       MUX(1, 147, 1, 0xa10, 24, 0xa90, 24),
> -       MUX(1, 146, 1, 0xa10, 25, 0xa90, 25),
> -       MUX(1, 145, 1, 0xa10, 23, 0xa90, 23),
> -       MUX(1, 148, 1, 0xa10, 22, 0xa90, 22),
> -};
> -
> -static struct atlas7_grp_mux audio_uart1_basic_grp_mux = {
> -       .pad_mux_count = ARRAY_SIZE(audio_uart1_basic_grp_pad_mux),
> -       .pad_mux_list = audio_uart1_basic_grp_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux audio_uart1_urfs_grp0_pad_mux[] = {
> -       MUX(1, 117, 6, 0xa10, 29, 0xa90, 29),
> -};
> -
> -static struct atlas7_grp_mux audio_uart1_urfs_grp0_mux = {
> -       .pad_mux_count = ARRAY_SIZE(audio_uart1_urfs_grp0_pad_mux),
> -       .pad_mux_list = audio_uart1_urfs_grp0_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux audio_uart1_urfs_grp1_pad_mux[] = {
> -       MUX(1, 140, 3, 0xa10, 29, 0xa90, 29),
> -};
> -
> -static struct atlas7_grp_mux audio_uart1_urfs_grp1_mux = {
> -       .pad_mux_count = ARRAY_SIZE(audio_uart1_urfs_grp1_pad_mux),
> -       .pad_mux_list = audio_uart1_urfs_grp1_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux audio_uart1_urfs_grp2_pad_mux[] = {
> -       MUX(1, 163, 4, 0xa10, 29, 0xa90, 29),
> -};
> -
> -static struct atlas7_grp_mux audio_uart1_urfs_grp2_mux = {
> -       .pad_mux_count = ARRAY_SIZE(audio_uart1_urfs_grp2_pad_mux),
> -       .pad_mux_list = audio_uart1_urfs_grp2_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux audio_uart2_urfs_grp0_pad_mux[] = {
> -       MUX(1, 139, 4, 0xa10, 30, 0xa90, 30),
> -};
> -
> -static struct atlas7_grp_mux audio_uart2_urfs_grp0_mux = {
> -       .pad_mux_count = ARRAY_SIZE(audio_uart2_urfs_grp0_pad_mux),
> -       .pad_mux_list = audio_uart2_urfs_grp0_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux audio_uart2_urfs_grp1_pad_mux[] = {
> -       MUX(1, 163, 6, 0xa10, 30, 0xa90, 30),
> -};
> -
> -static struct atlas7_grp_mux audio_uart2_urfs_grp1_mux = {
> -       .pad_mux_count = ARRAY_SIZE(audio_uart2_urfs_grp1_pad_mux),
> -       .pad_mux_list = audio_uart2_urfs_grp1_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux audio_uart2_urfs_grp2_pad_mux[] = {
> -       MUX(1, 96, 3, 0xa10, 30, 0xa90, 30),
> -};
> -
> -static struct atlas7_grp_mux audio_uart2_urfs_grp2_mux = {
> -       .pad_mux_count = ARRAY_SIZE(audio_uart2_urfs_grp2_pad_mux),
> -       .pad_mux_list = audio_uart2_urfs_grp2_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux audio_uart2_urxd_grp0_pad_mux[] = {
> -       MUX(1, 20, 2, 0xa00, 24, 0xa80, 24),
> -};
> -
> -static struct atlas7_grp_mux audio_uart2_urxd_grp0_mux = {
> -       .pad_mux_count = ARRAY_SIZE(audio_uart2_urxd_grp0_pad_mux),
> -       .pad_mux_list = audio_uart2_urxd_grp0_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux audio_uart2_urxd_grp1_pad_mux[] = {
> -       MUX(1, 109, 2, 0xa00, 24, 0xa80, 24),
> -};
> -
> -static struct atlas7_grp_mux audio_uart2_urxd_grp1_mux = {
> -       .pad_mux_count = ARRAY_SIZE(audio_uart2_urxd_grp1_pad_mux),
> -       .pad_mux_list = audio_uart2_urxd_grp1_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux audio_uart2_urxd_grp2_pad_mux[] = {
> -       MUX(1, 93, 3, 0xa00, 24, 0xa80, 24),
> -};
> -
> -static struct atlas7_grp_mux audio_uart2_urxd_grp2_mux = {
> -       .pad_mux_count = ARRAY_SIZE(audio_uart2_urxd_grp2_pad_mux),
> -       .pad_mux_list = audio_uart2_urxd_grp2_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux audio_uart2_usclk_grp0_pad_mux[] = {
> -       MUX(1, 19, 2, 0xa00, 23, 0xa80, 23),
> -};
> -
> -static struct atlas7_grp_mux audio_uart2_usclk_grp0_mux = {
> -       .pad_mux_count = ARRAY_SIZE(audio_uart2_usclk_grp0_pad_mux),
> -       .pad_mux_list = audio_uart2_usclk_grp0_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux audio_uart2_usclk_grp1_pad_mux[] = {
> -       MUX(1, 101, 2, 0xa00, 23, 0xa80, 23),
> -};
> -
> -static struct atlas7_grp_mux audio_uart2_usclk_grp1_mux = {
> -       .pad_mux_count = ARRAY_SIZE(audio_uart2_usclk_grp1_pad_mux),
> -       .pad_mux_list = audio_uart2_usclk_grp1_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux audio_uart2_usclk_grp2_pad_mux[] = {
> -       MUX(1, 91, 3, 0xa00, 23, 0xa80, 23),
> -};
> -
> -static struct atlas7_grp_mux audio_uart2_usclk_grp2_mux = {
> -       .pad_mux_count = ARRAY_SIZE(audio_uart2_usclk_grp2_pad_mux),
> -       .pad_mux_list = audio_uart2_usclk_grp2_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux audio_uart2_utfs_grp0_pad_mux[] = {
> -       MUX(1, 18, 2, 0xa00, 22, 0xa80, 22),
> -};
> -
> -static struct atlas7_grp_mux audio_uart2_utfs_grp0_mux = {
> -       .pad_mux_count = ARRAY_SIZE(audio_uart2_utfs_grp0_pad_mux),
> -       .pad_mux_list = audio_uart2_utfs_grp0_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux audio_uart2_utfs_grp1_pad_mux[] = {
> -       MUX(1, 111, 2, 0xa00, 22, 0xa80, 22),
> -};
> -
> -static struct atlas7_grp_mux audio_uart2_utfs_grp1_mux = {
> -       .pad_mux_count = ARRAY_SIZE(audio_uart2_utfs_grp1_pad_mux),
> -       .pad_mux_list = audio_uart2_utfs_grp1_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux audio_uart2_utfs_grp2_pad_mux[] = {
> -       MUX(1, 94, 3, 0xa00, 22, 0xa80, 22),
> -};
> -
> -static struct atlas7_grp_mux audio_uart2_utfs_grp2_mux = {
> -       .pad_mux_count = ARRAY_SIZE(audio_uart2_utfs_grp2_pad_mux),
> -       .pad_mux_list = audio_uart2_utfs_grp2_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux audio_uart2_utxd_grp0_pad_mux[] = {
> -       MUX(1, 21, 2, 0xa00, 25, 0xa80, 25),
> -};
> -
> -static struct atlas7_grp_mux audio_uart2_utxd_grp0_mux = {
> -       .pad_mux_count = ARRAY_SIZE(audio_uart2_utxd_grp0_pad_mux),
> -       .pad_mux_list = audio_uart2_utxd_grp0_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux audio_uart2_utxd_grp1_pad_mux[] = {
> -       MUX(1, 110, 2, 0xa00, 25, 0xa80, 25),
> -};
> -
> -static struct atlas7_grp_mux audio_uart2_utxd_grp1_mux = {
> -       .pad_mux_count = ARRAY_SIZE(audio_uart2_utxd_grp1_pad_mux),
> -       .pad_mux_list = audio_uart2_utxd_grp1_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux audio_uart2_utxd_grp2_pad_mux[] = {
> -       MUX(1, 92, 3, 0xa00, 25, 0xa80, 25),
> -};
> -
> -static struct atlas7_grp_mux audio_uart2_utxd_grp2_mux = {
> -       .pad_mux_count = ARRAY_SIZE(audio_uart2_utxd_grp2_pad_mux),
> -       .pad_mux_list = audio_uart2_utxd_grp2_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux c_can_trnsvr_en_grp0_pad_mux[] = {
> -       MUX(0, 2, 6, N, N, N, N),
> -};
> -
> -static struct atlas7_grp_mux c_can_trnsvr_en_grp0_mux = {
> -       .pad_mux_count = ARRAY_SIZE(c_can_trnsvr_en_grp0_pad_mux),
> -       .pad_mux_list = c_can_trnsvr_en_grp0_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux c_can_trnsvr_en_grp1_pad_mux[] = {
> -       MUX(0, 0, 2, N, N, N, N),
> -};
> -
> -static struct atlas7_grp_mux c_can_trnsvr_en_grp1_mux = {
> -       .pad_mux_count = ARRAY_SIZE(c_can_trnsvr_en_grp1_pad_mux),
> -       .pad_mux_list = c_can_trnsvr_en_grp1_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux c_can_trnsvr_intr_grp_pad_mux[] = {
> -       MUX(0, 1, 2, N, N, N, N),
> -};
> -
> -static struct atlas7_grp_mux c_can_trnsvr_intr_grp_mux = {
> -       .pad_mux_count = ARRAY_SIZE(c_can_trnsvr_intr_grp_pad_mux),
> -       .pad_mux_list = c_can_trnsvr_intr_grp_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux c_can_trnsvr_stb_n_grp_pad_mux[] = {
> -       MUX(0, 3, 6, N, N, N, N),
> -};
> -
> -static struct atlas7_grp_mux c_can_trnsvr_stb_n_grp_mux = {
> -       .pad_mux_count = ARRAY_SIZE(c_can_trnsvr_stb_n_grp_pad_mux),
> -       .pad_mux_list = c_can_trnsvr_stb_n_grp_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux c0_can_rxd_trnsv0_grp_pad_mux[] = {
> -       MUX(0, 11, 1, 0xa08, 9, 0xa88, 9),
> -};
> -
> -static struct atlas7_grp_mux c0_can_rxd_trnsv0_grp_mux = {
> -       .pad_mux_count = ARRAY_SIZE(c0_can_rxd_trnsv0_grp_pad_mux),
> -       .pad_mux_list = c0_can_rxd_trnsv0_grp_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux c0_can_rxd_trnsv1_grp_pad_mux[] = {
> -       MUX(0, 2, 5, 0xa10, 9, 0xa90, 9),
> -};
> -
> -static struct atlas7_grp_mux c0_can_rxd_trnsv1_grp_mux = {
> -       .pad_mux_count = ARRAY_SIZE(c0_can_rxd_trnsv1_grp_pad_mux),
> -       .pad_mux_list = c0_can_rxd_trnsv1_grp_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux c0_can_txd_trnsv0_grp_pad_mux[] = {
> -       MUX(0, 10, 1, N, N, N, N),
> -};
> -
> -static struct atlas7_grp_mux c0_can_txd_trnsv0_grp_mux = {
> -       .pad_mux_count = ARRAY_SIZE(c0_can_txd_trnsv0_grp_pad_mux),
> -       .pad_mux_list = c0_can_txd_trnsv0_grp_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux c0_can_txd_trnsv1_grp_pad_mux[] = {
> -       MUX(0, 3, 5, N, N, N, N),
> -};
> -
> -static struct atlas7_grp_mux c0_can_txd_trnsv1_grp_mux = {
> -       .pad_mux_count = ARRAY_SIZE(c0_can_txd_trnsv1_grp_pad_mux),
> -       .pad_mux_list = c0_can_txd_trnsv1_grp_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux c1_can_rxd_grp0_pad_mux[] = {
> -       MUX(1, 138, 2, 0xa00, 4, 0xa80, 4),
> -};
> -
> -static struct atlas7_grp_mux c1_can_rxd_grp0_mux = {
> -       .pad_mux_count = ARRAY_SIZE(c1_can_rxd_grp0_pad_mux),
> -       .pad_mux_list = c1_can_rxd_grp0_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux c1_can_rxd_grp1_pad_mux[] = {
> -       MUX(1, 147, 2, 0xa00, 4, 0xa80, 4),
> -};
> -
> -static struct atlas7_grp_mux c1_can_rxd_grp1_mux = {
> -       .pad_mux_count = ARRAY_SIZE(c1_can_rxd_grp1_pad_mux),
> -       .pad_mux_list = c1_can_rxd_grp1_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux c1_can_rxd_grp2_pad_mux[] = {
> -       MUX(0, 2, 2, 0xa00, 4, 0xa80, 4),
> -};
> -
> -static struct atlas7_grp_mux c1_can_rxd_grp2_mux = {
> -       .pad_mux_count = ARRAY_SIZE(c1_can_rxd_grp2_pad_mux),
> -       .pad_mux_list = c1_can_rxd_grp2_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux c1_can_rxd_grp3_pad_mux[] = {
> -       MUX(1, 162, 4, 0xa00, 4, 0xa80, 4),
> -};
> -
> -static struct atlas7_grp_mux c1_can_rxd_grp3_mux = {
> -       .pad_mux_count = ARRAY_SIZE(c1_can_rxd_grp3_pad_mux),
> -       .pad_mux_list = c1_can_rxd_grp3_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux c1_can_txd_grp0_pad_mux[] = {
> -       MUX(1, 137, 2, N, N, N, N),
> -};
> -
> -static struct atlas7_grp_mux c1_can_txd_grp0_mux = {
> -       .pad_mux_count = ARRAY_SIZE(c1_can_txd_grp0_pad_mux),
> -       .pad_mux_list = c1_can_txd_grp0_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux c1_can_txd_grp1_pad_mux[] = {
> -       MUX(1, 146, 2, N, N, N, N),
> -};
> -
> -static struct atlas7_grp_mux c1_can_txd_grp1_mux = {
> -       .pad_mux_count = ARRAY_SIZE(c1_can_txd_grp1_pad_mux),
> -       .pad_mux_list = c1_can_txd_grp1_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux c1_can_txd_grp2_pad_mux[] = {
> -       MUX(0, 3, 2, N, N, N, N),
> -};
> -
> -static struct atlas7_grp_mux c1_can_txd_grp2_mux = {
> -       .pad_mux_count = ARRAY_SIZE(c1_can_txd_grp2_pad_mux),
> -       .pad_mux_list = c1_can_txd_grp2_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux c1_can_txd_grp3_pad_mux[] = {
> -       MUX(1, 161, 4, N, N, N, N),
> -};
> -
> -static struct atlas7_grp_mux c1_can_txd_grp3_mux = {
> -       .pad_mux_count = ARRAY_SIZE(c1_can_txd_grp3_pad_mux),
> -       .pad_mux_list = c1_can_txd_grp3_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux ca_audio_lpc_grp_pad_mux[] = {
> -       MUX(1, 62, 4, N, N, N, N),
> -       MUX(1, 63, 4, N, N, N, N),
> -       MUX(1, 64, 4, N, N, N, N),
> -       MUX(1, 65, 4, N, N, N, N),
> -       MUX(1, 66, 4, N, N, N, N),
> -       MUX(1, 67, 4, N, N, N, N),
> -       MUX(1, 68, 4, N, N, N, N),
> -       MUX(1, 69, 4, N, N, N, N),
> -       MUX(1, 70, 4, N, N, N, N),
> -       MUX(1, 71, 4, N, N, N, N),
> -};
> -
> -static struct atlas7_grp_mux ca_audio_lpc_grp_mux = {
> -       .pad_mux_count = ARRAY_SIZE(ca_audio_lpc_grp_pad_mux),
> -       .pad_mux_list = ca_audio_lpc_grp_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux ca_bt_lpc_grp_pad_mux[] = {
> -       MUX(1, 85, 5, N, N, N, N),
> -       MUX(1, 86, 5, N, N, N, N),
> -       MUX(1, 87, 5, N, N, N, N),
> -       MUX(1, 88, 5, N, N, N, N),
> -       MUX(1, 89, 5, N, N, N, N),
> -       MUX(1, 90, 5, N, N, N, N),
> -};
> -
> -static struct atlas7_grp_mux ca_bt_lpc_grp_mux = {
> -       .pad_mux_count = ARRAY_SIZE(ca_bt_lpc_grp_pad_mux),
> -       .pad_mux_list = ca_bt_lpc_grp_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux ca_coex_grp_pad_mux[] = {
> -       MUX(1, 129, 1, N, N, N, N),
> -       MUX(1, 130, 1, N, N, N, N),
> -       MUX(1, 131, 1, N, N, N, N),
> -       MUX(1, 132, 1, N, N, N, N),
> -};
> -
> -static struct atlas7_grp_mux ca_coex_grp_mux = {
> -       .pad_mux_count = ARRAY_SIZE(ca_coex_grp_pad_mux),
> -       .pad_mux_list = ca_coex_grp_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux ca_curator_lpc_grp_pad_mux[] = {
> -       MUX(1, 57, 4, N, N, N, N),
> -       MUX(1, 58, 4, N, N, N, N),
> -       MUX(1, 59, 4, N, N, N, N),
> -       MUX(1, 60, 4, N, N, N, N),
> -};
> -
> -static struct atlas7_grp_mux ca_curator_lpc_grp_mux = {
> -       .pad_mux_count = ARRAY_SIZE(ca_curator_lpc_grp_pad_mux),
> -       .pad_mux_list = ca_curator_lpc_grp_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux ca_pcm_debug_grp_pad_mux[] = {
> -       MUX(1, 91, 5, N, N, N, N),
> -       MUX(1, 93, 5, N, N, N, N),
> -       MUX(1, 94, 5, N, N, N, N),
> -       MUX(1, 92, 5, N, N, N, N),
> -};
> -
> -static struct atlas7_grp_mux ca_pcm_debug_grp_mux = {
> -       .pad_mux_count = ARRAY_SIZE(ca_pcm_debug_grp_pad_mux),
> -       .pad_mux_list = ca_pcm_debug_grp_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux ca_pio_grp_pad_mux[] = {
> -       MUX(1, 121, 2, N, N, N, N),
> -       MUX(1, 122, 2, N, N, N, N),
> -       MUX(1, 125, 6, N, N, N, N),
> -       MUX(1, 126, 6, N, N, N, N),
> -       MUX(1, 38, 5, N, N, N, N),
> -       MUX(1, 37, 5, N, N, N, N),
> -       MUX(1, 47, 5, N, N, N, N),
> -       MUX(1, 49, 5, N, N, N, N),
> -       MUX(1, 50, 5, N, N, N, N),
> -       MUX(1, 54, 4, N, N, N, N),
> -       MUX(1, 55, 4, N, N, N, N),
> -       MUX(1, 56, 4, N, N, N, N),
> -};
> -
> -static struct atlas7_grp_mux ca_pio_grp_mux = {
> -       .pad_mux_count = ARRAY_SIZE(ca_pio_grp_pad_mux),
> -       .pad_mux_list = ca_pio_grp_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux ca_sdio_debug_grp_pad_mux[] = {
> -       MUX(1, 40, 5, N, N, N, N),
> -       MUX(1, 39, 5, N, N, N, N),
> -       MUX(1, 44, 5, N, N, N, N),
> -       MUX(1, 43, 5, N, N, N, N),
> -       MUX(1, 42, 5, N, N, N, N),
> -       MUX(1, 41, 5, N, N, N, N),
> -};
> -
> -static struct atlas7_grp_mux ca_sdio_debug_grp_mux = {
> -       .pad_mux_count = ARRAY_SIZE(ca_sdio_debug_grp_pad_mux),
> -       .pad_mux_list = ca_sdio_debug_grp_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux ca_spi_grp_pad_mux[] = {
> -       MUX(1, 82, 5, N, N, N, N),
> -       MUX(1, 79, 5, 0xa08, 6, 0xa88, 6),
> -       MUX(1, 80, 5, N, N, N, N),
> -       MUX(1, 81, 5, N, N, N, N),
> -};
> -
> -static struct atlas7_grp_mux ca_spi_grp_mux = {
> -       .pad_mux_count = ARRAY_SIZE(ca_spi_grp_pad_mux),
> -       .pad_mux_list = ca_spi_grp_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux ca_trb_grp_pad_mux[] = {
> -       MUX(1, 91, 4, N, N, N, N),
> -       MUX(1, 93, 4, N, N, N, N),
> -       MUX(1, 94, 4, N, N, N, N),
> -       MUX(1, 95, 4, N, N, N, N),
> -       MUX(1, 96, 4, N, N, N, N),
> -       MUX(1, 78, 5, N, N, N, N),
> -       MUX(1, 74, 5, N, N, N, N),
> -       MUX(1, 75, 5, N, N, N, N),
> -       MUX(1, 76, 5, N, N, N, N),
> -       MUX(1, 77, 5, N, N, N, N),
> -};
> -
> -static struct atlas7_grp_mux ca_trb_grp_mux = {
> -       .pad_mux_count = ARRAY_SIZE(ca_trb_grp_pad_mux),
> -       .pad_mux_list = ca_trb_grp_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux ca_uart_debug_grp_pad_mux[] = {
> -       MUX(1, 136, 3, N, N, N, N),
> -       MUX(1, 135, 3, N, N, N, N),
> -       MUX(1, 134, 3, N, N, N, N),
> -       MUX(1, 133, 3, N, N, N, N),
> -};
> -
> -static struct atlas7_grp_mux ca_uart_debug_grp_mux = {
> -       .pad_mux_count = ARRAY_SIZE(ca_uart_debug_grp_pad_mux),
> -       .pad_mux_list = ca_uart_debug_grp_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux clkc_grp0_pad_mux[] = {
> -       MUX(1, 30, 2, 0xa08, 14, 0xa88, 14),
> -       MUX(1, 47, 6, N, N, N, N),
> -};
> -
> -static struct atlas7_grp_mux clkc_grp0_mux = {
> -       .pad_mux_count = ARRAY_SIZE(clkc_grp0_pad_mux),
> -       .pad_mux_list = clkc_grp0_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux clkc_grp1_pad_mux[] = {
> -       MUX(1, 78, 3, 0xa08, 14, 0xa88, 14),
> -       MUX(1, 54, 5, N, N, N, N),
> -};
> -
> -static struct atlas7_grp_mux clkc_grp1_mux = {
> -       .pad_mux_count = ARRAY_SIZE(clkc_grp1_pad_mux),
> -       .pad_mux_list = clkc_grp1_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux gn_gnss_i2c_grp_pad_mux[] = {
> -       MUX(1, 128, 2, N, N, N, N),
> -       MUX(1, 127, 2, N, N, N, N),
> -};
> -
> -static struct atlas7_grp_mux gn_gnss_i2c_grp_mux = {
> -       .pad_mux_count = ARRAY_SIZE(gn_gnss_i2c_grp_pad_mux),
> -       .pad_mux_list = gn_gnss_i2c_grp_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux gn_gnss_uart_nopause_grp_pad_mux[] = {
> -       MUX(1, 134, 4, N, N, N, N),
> -       MUX(1, 133, 4, N, N, N, N),
> -};
> -
> -static struct atlas7_grp_mux gn_gnss_uart_nopause_grp_mux = {
> -       .pad_mux_count = ARRAY_SIZE(gn_gnss_uart_nopause_grp_pad_mux),
> -       .pad_mux_list = gn_gnss_uart_nopause_grp_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux gn_gnss_uart_grp_pad_mux[] = {
> -       MUX(1, 134, 4, N, N, N, N),
> -       MUX(1, 133, 4, N, N, N, N),
> -       MUX(1, 136, 4, N, N, N, N),
> -       MUX(1, 135, 4, N, N, N, N),
> -};
> -
> -static struct atlas7_grp_mux gn_gnss_uart_grp_mux = {
> -       .pad_mux_count = ARRAY_SIZE(gn_gnss_uart_grp_pad_mux),
> -       .pad_mux_list = gn_gnss_uart_grp_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux gn_trg_spi_grp0_pad_mux[] = {
> -       MUX(1, 22, 1, N, N, N, N),
> -       MUX(1, 25, 1, N, N, N, N),
> -       MUX(1, 23, 1, 0xa00, 10, 0xa80, 10),
> -       MUX(1, 24, 1, N, N, N, N),
> -};
> -
> -static struct atlas7_grp_mux gn_trg_spi_grp0_mux = {
> -       .pad_mux_count = ARRAY_SIZE(gn_trg_spi_grp0_pad_mux),
> -       .pad_mux_list = gn_trg_spi_grp0_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux gn_trg_spi_grp1_pad_mux[] = {
> -       MUX(1, 82, 3, N, N, N, N),
> -       MUX(1, 79, 3, N, N, N, N),
> -       MUX(1, 80, 3, 0xa00, 10, 0xa80, 10),
> -       MUX(1, 81, 3, N, N, N, N),
> -};
> -
> -static struct atlas7_grp_mux gn_trg_spi_grp1_mux = {
> -       .pad_mux_count = ARRAY_SIZE(gn_trg_spi_grp1_pad_mux),
> -       .pad_mux_list = gn_trg_spi_grp1_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux cvbs_dbg_grp_pad_mux[] = {
> -       MUX(1, 54, 3, N, N, N, N),
> -       MUX(1, 53, 3, N, N, N, N),
> -       MUX(1, 82, 7, N, N, N, N),
> -       MUX(1, 74, 7, N, N, N, N),
> -       MUX(1, 75, 7, N, N, N, N),
> -       MUX(1, 76, 7, N, N, N, N),
> -       MUX(1, 77, 7, N, N, N, N),
> -       MUX(1, 78, 7, N, N, N, N),
> -       MUX(1, 79, 7, N, N, N, N),
> -       MUX(1, 80, 7, N, N, N, N),
> -       MUX(1, 81, 7, N, N, N, N),
> -       MUX(1, 83, 7, N, N, N, N),
> -       MUX(1, 84, 7, N, N, N, N),
> -       MUX(1, 73, 3, N, N, N, N),
> -       MUX(1, 55, 3, N, N, N, N),
> -       MUX(1, 56, 3, N, N, N, N),
> -};
> -
> -static struct atlas7_grp_mux cvbs_dbg_grp_mux = {
> -       .pad_mux_count = ARRAY_SIZE(cvbs_dbg_grp_pad_mux),
> -       .pad_mux_list = cvbs_dbg_grp_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux cvbs_dbg_test_grp0_pad_mux[] = {
> -       MUX(1, 57, 3, N, N, N, N),
> -};
> -
> -static struct atlas7_grp_mux cvbs_dbg_test_grp0_mux = {
> -       .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp0_pad_mux),
> -       .pad_mux_list = cvbs_dbg_test_grp0_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux cvbs_dbg_test_grp1_pad_mux[] = {
> -       MUX(1, 58, 3, N, N, N, N),
> -};
> -
> -static struct atlas7_grp_mux cvbs_dbg_test_grp1_mux = {
> -       .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp1_pad_mux),
> -       .pad_mux_list = cvbs_dbg_test_grp1_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux cvbs_dbg_test_grp2_pad_mux[] = {
> -       MUX(1, 59, 3, N, N, N, N),
> -};
> -
> -static struct atlas7_grp_mux cvbs_dbg_test_grp2_mux = {
> -       .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp2_pad_mux),
> -       .pad_mux_list = cvbs_dbg_test_grp2_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux cvbs_dbg_test_grp3_pad_mux[] = {
> -       MUX(1, 60, 3, N, N, N, N),
> -};
> -
> -static struct atlas7_grp_mux cvbs_dbg_test_grp3_mux = {
> -       .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp3_pad_mux),
> -       .pad_mux_list = cvbs_dbg_test_grp3_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux cvbs_dbg_test_grp4_pad_mux[] = {
> -       MUX(1, 61, 3, N, N, N, N),
> -};
> -
> -static struct atlas7_grp_mux cvbs_dbg_test_grp4_mux = {
> -       .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp4_pad_mux),
> -       .pad_mux_list = cvbs_dbg_test_grp4_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux cvbs_dbg_test_grp5_pad_mux[] = {
> -       MUX(1, 62, 3, N, N, N, N),
> -};
> -
> -static struct atlas7_grp_mux cvbs_dbg_test_grp5_mux = {
> -       .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp5_pad_mux),
> -       .pad_mux_list = cvbs_dbg_test_grp5_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux cvbs_dbg_test_grp6_pad_mux[] = {
> -       MUX(1, 63, 3, N, N, N, N),
> -};
> -
> -static struct atlas7_grp_mux cvbs_dbg_test_grp6_mux = {
> -       .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp6_pad_mux),
> -       .pad_mux_list = cvbs_dbg_test_grp6_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux cvbs_dbg_test_grp7_pad_mux[] = {
> -       MUX(1, 64, 3, N, N, N, N),
> -};
> -
> -static struct atlas7_grp_mux cvbs_dbg_test_grp7_mux = {
> -       .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp7_pad_mux),
> -       .pad_mux_list = cvbs_dbg_test_grp7_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux cvbs_dbg_test_grp8_pad_mux[] = {
> -       MUX(1, 65, 3, N, N, N, N),
> -};
> -
> -static struct atlas7_grp_mux cvbs_dbg_test_grp8_mux = {
> -       .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp8_pad_mux),
> -       .pad_mux_list = cvbs_dbg_test_grp8_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux cvbs_dbg_test_grp9_pad_mux[] = {
> -       MUX(1, 66, 3, N, N, N, N),
> -};
> -
> -static struct atlas7_grp_mux cvbs_dbg_test_grp9_mux = {
> -       .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp9_pad_mux),
> -       .pad_mux_list = cvbs_dbg_test_grp9_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux cvbs_dbg_test_grp10_pad_mux[] = {
> -       MUX(1, 67, 3, N, N, N, N),
> -};
> -
> -static struct atlas7_grp_mux cvbs_dbg_test_grp10_mux = {
> -       .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp10_pad_mux),
> -       .pad_mux_list = cvbs_dbg_test_grp10_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux cvbs_dbg_test_grp11_pad_mux[] = {
> -       MUX(1, 68, 3, N, N, N, N),
> -};
> -
> -static struct atlas7_grp_mux cvbs_dbg_test_grp11_mux = {
> -       .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp11_pad_mux),
> -       .pad_mux_list = cvbs_dbg_test_grp11_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux cvbs_dbg_test_grp12_pad_mux[] = {
> -       MUX(1, 69, 3, N, N, N, N),
> -};
> -
> -static struct atlas7_grp_mux cvbs_dbg_test_grp12_mux = {
> -       .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp12_pad_mux),
> -       .pad_mux_list = cvbs_dbg_test_grp12_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux cvbs_dbg_test_grp13_pad_mux[] = {
> -       MUX(1, 70, 3, N, N, N, N),
> -};
> -
> -static struct atlas7_grp_mux cvbs_dbg_test_grp13_mux = {
> -       .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp13_pad_mux),
> -       .pad_mux_list = cvbs_dbg_test_grp13_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux cvbs_dbg_test_grp14_pad_mux[] = {
> -       MUX(1, 71, 3, N, N, N, N),
> -};
> -
> -static struct atlas7_grp_mux cvbs_dbg_test_grp14_mux = {
> -       .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp14_pad_mux),
> -       .pad_mux_list = cvbs_dbg_test_grp14_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux cvbs_dbg_test_grp15_pad_mux[] = {
> -       MUX(1, 72, 3, N, N, N, N),
> -};
> -
> -static struct atlas7_grp_mux cvbs_dbg_test_grp15_mux = {
> -       .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp15_pad_mux),
> -       .pad_mux_list = cvbs_dbg_test_grp15_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux gn_gnss_power_grp_pad_mux[] = {
> -       MUX(1, 123, 7, N, N, N, N),
> -       MUX(1, 124, 7, N, N, N, N),
> -       MUX(1, 121, 7, N, N, N, N),
> -       MUX(1, 122, 7, N, N, N, N),
> -       MUX(1, 125, 7, N, N, N, N),
> -       MUX(1, 120, 7, N, N, N, N),
> -};
> -
> -static struct atlas7_grp_mux gn_gnss_power_grp_mux = {
> -       .pad_mux_count = ARRAY_SIZE(gn_gnss_power_grp_pad_mux),
> -       .pad_mux_list = gn_gnss_power_grp_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux gn_gnss_sw_status_grp_pad_mux[] = {
> -       MUX(1, 57, 7, N, N, N, N),
> -       MUX(1, 58, 7, N, N, N, N),
> -       MUX(1, 59, 7, N, N, N, N),
> -       MUX(1, 60, 7, N, N, N, N),
> -       MUX(1, 61, 7, N, N, N, N),
> -       MUX(1, 62, 7, N, N, N, N),
> -       MUX(1, 63, 7, N, N, N, N),
> -       MUX(1, 64, 7, N, N, N, N),
> -       MUX(1, 65, 7, N, N, N, N),
> -       MUX(1, 66, 7, N, N, N, N),
> -       MUX(1, 67, 7, N, N, N, N),
> -       MUX(1, 68, 7, N, N, N, N),
> -       MUX(1, 69, 7, N, N, N, N),
> -       MUX(1, 70, 7, N, N, N, N),
> -       MUX(1, 71, 7, N, N, N, N),
> -       MUX(1, 72, 7, N, N, N, N),
> -       MUX(1, 53, 7, N, N, N, N),
> -       MUX(1, 55, 7, N, N, N, N),
> -       MUX(1, 56, 7, 0xa08, 12, 0xa88, 12),
> -       MUX(1, 54, 7, N, N, N, N),
> -};
> -
> -static struct atlas7_grp_mux gn_gnss_sw_status_grp_mux = {
> -       .pad_mux_count = ARRAY_SIZE(gn_gnss_sw_status_grp_pad_mux),
> -       .pad_mux_list = gn_gnss_sw_status_grp_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux gn_gnss_eclk_grp_pad_mux[] = {
> -       MUX(1, 113, 4, N, N, N, N),
> -};
> -
> -static struct atlas7_grp_mux gn_gnss_eclk_grp_mux = {
> -       .pad_mux_count = ARRAY_SIZE(gn_gnss_eclk_grp_pad_mux),
> -       .pad_mux_list = gn_gnss_eclk_grp_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux gn_gnss_irq1_grp0_pad_mux[] = {
> -       MUX(1, 112, 4, 0xa08, 10, 0xa88, 10),
> -};
> -
> -static struct atlas7_grp_mux gn_gnss_irq1_grp0_mux = {
> -       .pad_mux_count = ARRAY_SIZE(gn_gnss_irq1_grp0_pad_mux),
> -       .pad_mux_list = gn_gnss_irq1_grp0_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux gn_gnss_irq2_grp0_pad_mux[] = {
> -       MUX(1, 118, 4, 0xa08, 11, 0xa88, 11),
> -};
> -
> -static struct atlas7_grp_mux gn_gnss_irq2_grp0_mux = {
> -       .pad_mux_count = ARRAY_SIZE(gn_gnss_irq2_grp0_pad_mux),
> -       .pad_mux_list = gn_gnss_irq2_grp0_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux gn_gnss_tm_grp_pad_mux[] = {
> -       MUX(1, 115, 4, N, N, N, N),
> -};
> -
> -static struct atlas7_grp_mux gn_gnss_tm_grp_mux = {
> -       .pad_mux_count = ARRAY_SIZE(gn_gnss_tm_grp_pad_mux),
> -       .pad_mux_list = gn_gnss_tm_grp_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux gn_gnss_tsync_grp_pad_mux[] = {
> -       MUX(1, 114, 4, N, N, N, N),
> -};
> -
> -static struct atlas7_grp_mux gn_gnss_tsync_grp_mux = {
> -       .pad_mux_count = ARRAY_SIZE(gn_gnss_tsync_grp_pad_mux),
> -       .pad_mux_list = gn_gnss_tsync_grp_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux gn_io_gnsssys_sw_cfg_grp_pad_mux[] = {
> -       MUX(1, 44, 7, N, N, N, N),
> -       MUX(1, 43, 7, N, N, N, N),
> -       MUX(1, 42, 7, N, N, N, N),
> -       MUX(1, 41, 7, N, N, N, N),
> -       MUX(1, 40, 7, N, N, N, N),
> -       MUX(1, 39, 7, N, N, N, N),
> -       MUX(1, 38, 7, N, N, N, N),
> -       MUX(1, 37, 7, N, N, N, N),
> -       MUX(1, 49, 7, N, N, N, N),
> -       MUX(1, 50, 7, N, N, N, N),
> -       MUX(1, 91, 7, N, N, N, N),
> -       MUX(1, 92, 7, N, N, N, N),
> -       MUX(1, 93, 7, N, N, N, N),
> -       MUX(1, 94, 7, N, N, N, N),
> -       MUX(1, 95, 7, N, N, N, N),
> -       MUX(1, 96, 7, N, N, N, N),
> -};
> -
> -static struct atlas7_grp_mux gn_io_gnsssys_sw_cfg_grp_mux = {
> -       .pad_mux_count = ARRAY_SIZE(gn_io_gnsssys_sw_cfg_grp_pad_mux),
> -       .pad_mux_list = gn_io_gnsssys_sw_cfg_grp_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux gn_trg_grp0_pad_mux[] = {
> -       MUX(1, 29, 1, 0xa00, 6, 0xa80, 6),
> -       MUX(1, 28, 1, 0xa00, 7, 0xa80, 7),
> -       MUX(1, 26, 1, 0xa00, 8, 0xa80, 8),
> -       MUX(1, 27, 1, 0xa00, 9, 0xa80, 9),
> -};
> -
> -static struct atlas7_grp_mux gn_trg_grp0_mux = {
> -       .pad_mux_count = ARRAY_SIZE(gn_trg_grp0_pad_mux),
> -       .pad_mux_list = gn_trg_grp0_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux gn_trg_grp1_pad_mux[] = {
> -       MUX(1, 77, 3, 0xa00, 6, 0xa80, 6),
> -       MUX(1, 76, 3, 0xa00, 7, 0xa80, 7),
> -       MUX(1, 74, 3, 0xa00, 8, 0xa80, 8),
> -       MUX(1, 75, 3, 0xa00, 9, 0xa80, 9),
> -};
> -
> -static struct atlas7_grp_mux gn_trg_grp1_mux = {
> -       .pad_mux_count = ARRAY_SIZE(gn_trg_grp1_pad_mux),
> -       .pad_mux_list = gn_trg_grp1_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux gn_trg_shutdown_grp0_pad_mux[] = {
> -       MUX(1, 30, 1, N, N, N, N),
> -};
> -
> -static struct atlas7_grp_mux gn_trg_shutdown_grp0_mux = {
> -       .pad_mux_count = ARRAY_SIZE(gn_trg_shutdown_grp0_pad_mux),
> -       .pad_mux_list = gn_trg_shutdown_grp0_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux gn_trg_shutdown_grp1_pad_mux[] = {
> -       MUX(1, 83, 3, N, N, N, N),
> -};
> -
> -static struct atlas7_grp_mux gn_trg_shutdown_grp1_mux = {
> -       .pad_mux_count = ARRAY_SIZE(gn_trg_shutdown_grp1_pad_mux),
> -       .pad_mux_list = gn_trg_shutdown_grp1_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux gn_trg_shutdown_grp2_pad_mux[] = {
> -       MUX(1, 117, 4, N, N, N, N),
> -};
> -
> -static struct atlas7_grp_mux gn_trg_shutdown_grp2_mux = {
> -       .pad_mux_count = ARRAY_SIZE(gn_trg_shutdown_grp2_pad_mux),
> -       .pad_mux_list = gn_trg_shutdown_grp2_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux gn_trg_shutdown_grp3_pad_mux[] = {
> -       MUX(1, 123, 5, N, N, N, N),
> -};
> -
> -static struct atlas7_grp_mux gn_trg_shutdown_grp3_mux = {
> -       .pad_mux_count = ARRAY_SIZE(gn_trg_shutdown_grp3_pad_mux),
> -       .pad_mux_list = gn_trg_shutdown_grp3_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux i2c0_grp_pad_mux[] = {
> -       MUX(1, 128, 1, N, N, N, N),
> -       MUX(1, 127, 1, N, N, N, N),
> -};
> -
> -static struct atlas7_grp_mux i2c0_grp_mux = {
> -       .pad_mux_count = ARRAY_SIZE(i2c0_grp_pad_mux),
> -       .pad_mux_list = i2c0_grp_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux i2c1_grp_pad_mux[] = {
> -       MUX(1, 126, 4, N, N, N, N),
> -       MUX(1, 125, 4, N, N, N, N),
> -};
> -
> -static struct atlas7_grp_mux i2c1_grp_mux = {
> -       .pad_mux_count = ARRAY_SIZE(i2c1_grp_pad_mux),
> -       .pad_mux_list = i2c1_grp_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux i2s0_grp_pad_mux[] = {
> -       MUX(1, 91, 2, 0xa10, 12, 0xa90, 12),
> -       MUX(1, 93, 2, 0xa10, 13, 0xa90, 13),
> -       MUX(1, 94, 2, 0xa10, 14, 0xa90, 14),
> -       MUX(1, 92, 2, 0xa10, 15, 0xa90, 15),
> -};
> -
> -static struct atlas7_grp_mux i2s0_grp_mux = {
> -       .pad_mux_count = ARRAY_SIZE(i2s0_grp_pad_mux),
> -       .pad_mux_list = i2s0_grp_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux i2s1_basic_grp_pad_mux[] = {
> -       MUX(1, 95, 2, 0xa10, 16, 0xa90, 16),
> -       MUX(1, 96, 2, 0xa10, 19, 0xa90, 19),
> -};
> -
> -static struct atlas7_grp_mux i2s1_basic_grp_mux = {
> -       .pad_mux_count = ARRAY_SIZE(i2s1_basic_grp_pad_mux),
> -       .pad_mux_list = i2s1_basic_grp_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux i2s1_rxd0_grp0_pad_mux[] = {
> -       MUX(1, 61, 4, 0xa10, 17, 0xa90, 17),
> -};
> -
> -static struct atlas7_grp_mux i2s1_rxd0_grp0_mux = {
> -       .pad_mux_count = ARRAY_SIZE(i2s1_rxd0_grp0_pad_mux),
> -       .pad_mux_list = i2s1_rxd0_grp0_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux i2s1_rxd0_grp1_pad_mux[] = {
> -       MUX(1, 131, 4, 0xa10, 17, 0xa90, 17),
> -};
> -
> -static struct atlas7_grp_mux i2s1_rxd0_grp1_mux = {
> -       .pad_mux_count = ARRAY_SIZE(i2s1_rxd0_grp1_pad_mux),
> -       .pad_mux_list = i2s1_rxd0_grp1_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux i2s1_rxd0_grp2_pad_mux[] = {
> -       MUX(1, 129, 2, 0xa10, 17, 0xa90, 17),
> -};
> -
> -static struct atlas7_grp_mux i2s1_rxd0_grp2_mux = {
> -       .pad_mux_count = ARRAY_SIZE(i2s1_rxd0_grp2_pad_mux),
> -       .pad_mux_list = i2s1_rxd0_grp2_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux i2s1_rxd0_grp3_pad_mux[] = {
> -       MUX(1, 117, 7, 0xa10, 17, 0xa90, 17),
> -};
> -
> -static struct atlas7_grp_mux i2s1_rxd0_grp3_mux = {
> -       .pad_mux_count = ARRAY_SIZE(i2s1_rxd0_grp3_pad_mux),
> -       .pad_mux_list = i2s1_rxd0_grp3_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux i2s1_rxd0_grp4_pad_mux[] = {
> -       MUX(1, 83, 4, 0xa10, 17, 0xa90, 17),
> -};
> -
> -static struct atlas7_grp_mux i2s1_rxd0_grp4_mux = {
> -       .pad_mux_count = ARRAY_SIZE(i2s1_rxd0_grp4_pad_mux),
> -       .pad_mux_list = i2s1_rxd0_grp4_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux i2s1_rxd1_grp0_pad_mux[] = {
> -       MUX(1, 72, 4, 0xa10, 18, 0xa90, 18),
> -};
> -
> -static struct atlas7_grp_mux i2s1_rxd1_grp0_mux = {
> -       .pad_mux_count = ARRAY_SIZE(i2s1_rxd1_grp0_pad_mux),
> -       .pad_mux_list = i2s1_rxd1_grp0_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux i2s1_rxd1_grp1_pad_mux[] = {
> -       MUX(1, 132, 4, 0xa10, 18, 0xa90, 18),
> -};
> -
> -static struct atlas7_grp_mux i2s1_rxd1_grp1_mux = {
> -       .pad_mux_count = ARRAY_SIZE(i2s1_rxd1_grp1_pad_mux),
> -       .pad_mux_list = i2s1_rxd1_grp1_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux i2s1_rxd1_grp2_pad_mux[] = {
> -       MUX(1, 130, 2, 0xa10, 18, 0xa90, 18),
> -};
> -
> -static struct atlas7_grp_mux i2s1_rxd1_grp2_mux = {
> -       .pad_mux_count = ARRAY_SIZE(i2s1_rxd1_grp2_pad_mux),
> -       .pad_mux_list = i2s1_rxd1_grp2_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux i2s1_rxd1_grp3_pad_mux[] = {
> -       MUX(1, 118, 7, 0xa10, 18, 0xa90, 18),
> -};
> -
> -static struct atlas7_grp_mux i2s1_rxd1_grp3_mux = {
> -       .pad_mux_count = ARRAY_SIZE(i2s1_rxd1_grp3_pad_mux),
> -       .pad_mux_list = i2s1_rxd1_grp3_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux i2s1_rxd1_grp4_pad_mux[] = {
> -       MUX(1, 84, 4, 0xa10, 18, 0xa90, 18),
> -};
> -
> -static struct atlas7_grp_mux i2s1_rxd1_grp4_mux = {
> -       .pad_mux_count = ARRAY_SIZE(i2s1_rxd1_grp4_pad_mux),
> -       .pad_mux_list = i2s1_rxd1_grp4_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux jtag_jt_dbg_nsrst_grp_pad_mux[] = {
> -       MUX(1, 125, 5, 0xa08, 2, 0xa88, 2),
> -};
> -
> -static struct atlas7_grp_mux jtag_jt_dbg_nsrst_grp_mux = {
> -       .pad_mux_count = ARRAY_SIZE(jtag_jt_dbg_nsrst_grp_pad_mux),
> -       .pad_mux_list = jtag_jt_dbg_nsrst_grp_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux jtag_ntrst_grp0_pad_mux[] = {
> -       MUX(0, 4, 3, 0xa08, 3, 0xa88, 3),
> -};
> -
> -static struct atlas7_grp_mux jtag_ntrst_grp0_mux = {
> -       .pad_mux_count = ARRAY_SIZE(jtag_ntrst_grp0_pad_mux),
> -       .pad_mux_list = jtag_ntrst_grp0_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux jtag_ntrst_grp1_pad_mux[] = {
> -       MUX(1, 163, 1, 0xa08, 3, 0xa88, 3),
> -};
> -
> -static struct atlas7_grp_mux jtag_ntrst_grp1_mux = {
> -       .pad_mux_count = ARRAY_SIZE(jtag_ntrst_grp1_pad_mux),
> -       .pad_mux_list = jtag_ntrst_grp1_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux jtag_swdiotms_grp0_pad_mux[] = {
> -       MUX(0, 2, 3, 0xa10, 10, 0xa90, 10),
> -};
> -
> -static struct atlas7_grp_mux jtag_swdiotms_grp0_mux = {
> -       .pad_mux_count = ARRAY_SIZE(jtag_swdiotms_grp0_pad_mux),
> -       .pad_mux_list = jtag_swdiotms_grp0_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux jtag_swdiotms_grp1_pad_mux[] = {
> -       MUX(1, 160, 1, 0xa10, 10, 0xa90, 10),
> -};
> -
> -static struct atlas7_grp_mux jtag_swdiotms_grp1_mux = {
> -       .pad_mux_count = ARRAY_SIZE(jtag_swdiotms_grp1_pad_mux),
> -       .pad_mux_list = jtag_swdiotms_grp1_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux jtag_tck_grp0_pad_mux[] = {
> -       MUX(0, 0, 3, 0xa10, 11, 0xa90, 11),
> -};
> -
> -static struct atlas7_grp_mux jtag_tck_grp0_mux = {
> -       .pad_mux_count = ARRAY_SIZE(jtag_tck_grp0_pad_mux),
> -       .pad_mux_list = jtag_tck_grp0_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux jtag_tck_grp1_pad_mux[] = {
> -       MUX(1, 161, 1, 0xa10, 11, 0xa90, 11),
> -};
> -
> -static struct atlas7_grp_mux jtag_tck_grp1_mux = {
> -       .pad_mux_count = ARRAY_SIZE(jtag_tck_grp1_pad_mux),
> -       .pad_mux_list = jtag_tck_grp1_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux jtag_tdi_grp0_pad_mux[] = {
> -       MUX(0, 1, 3, 0xa10, 31, 0xa90, 31),
> -};
> -
> -static struct atlas7_grp_mux jtag_tdi_grp0_mux = {
> -       .pad_mux_count = ARRAY_SIZE(jtag_tdi_grp0_pad_mux),
> -       .pad_mux_list = jtag_tdi_grp0_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux jtag_tdi_grp1_pad_mux[] = {
> -       MUX(1, 162, 1, 0xa10, 31, 0xa90, 31),
> -};
> -
> -static struct atlas7_grp_mux jtag_tdi_grp1_mux = {
> -       .pad_mux_count = ARRAY_SIZE(jtag_tdi_grp1_pad_mux),
> -       .pad_mux_list = jtag_tdi_grp1_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux jtag_tdo_grp0_pad_mux[] = {
> -       MUX(0, 3, 3, N, N, N, N),
> -};
> -
> -static struct atlas7_grp_mux jtag_tdo_grp0_mux = {
> -       .pad_mux_count = ARRAY_SIZE(jtag_tdo_grp0_pad_mux),
> -       .pad_mux_list = jtag_tdo_grp0_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux jtag_tdo_grp1_pad_mux[] = {
> -       MUX(1, 159, 1, N, N, N, N),
> -};
> -
> -static struct atlas7_grp_mux jtag_tdo_grp1_mux = {
> -       .pad_mux_count = ARRAY_SIZE(jtag_tdo_grp1_pad_mux),
> -       .pad_mux_list = jtag_tdo_grp1_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux ks_kas_spi_grp0_pad_mux[] = {
> -       MUX(1, 141, 2, N, N, N, N),
> -       MUX(1, 144, 2, 0xa08, 8, 0xa88, 8),
> -       MUX(1, 143, 2, N, N, N, N),
> -       MUX(1, 142, 2, N, N, N, N),
> -};
> -
> -static struct atlas7_grp_mux ks_kas_spi_grp0_mux = {
> -       .pad_mux_count = ARRAY_SIZE(ks_kas_spi_grp0_pad_mux),
> -       .pad_mux_list = ks_kas_spi_grp0_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux ld_ldd_grp_pad_mux[] = {
> -       MUX(1, 57, 1, N, N, N, N),
> -       MUX(1, 58, 1, N, N, N, N),
> -       MUX(1, 59, 1, N, N, N, N),
> -       MUX(1, 60, 1, N, N, N, N),
> -       MUX(1, 61, 1, N, N, N, N),
> -       MUX(1, 62, 1, N, N, N, N),
> -       MUX(1, 63, 1, N, N, N, N),
> -       MUX(1, 64, 1, N, N, N, N),
> -       MUX(1, 65, 1, N, N, N, N),
> -       MUX(1, 66, 1, N, N, N, N),
> -       MUX(1, 67, 1, N, N, N, N),
> -       MUX(1, 68, 1, N, N, N, N),
> -       MUX(1, 69, 1, N, N, N, N),
> -       MUX(1, 70, 1, N, N, N, N),
> -       MUX(1, 71, 1, N, N, N, N),
> -       MUX(1, 72, 1, N, N, N, N),
> -       MUX(1, 74, 2, N, N, N, N),
> -       MUX(1, 75, 2, N, N, N, N),
> -       MUX(1, 76, 2, N, N, N, N),
> -       MUX(1, 77, 2, N, N, N, N),
> -       MUX(1, 78, 2, N, N, N, N),
> -       MUX(1, 79, 2, N, N, N, N),
> -       MUX(1, 80, 2, N, N, N, N),
> -       MUX(1, 81, 2, N, N, N, N),
> -       MUX(1, 56, 1, N, N, N, N),
> -       MUX(1, 53, 1, N, N, N, N),
> -};
> -
> -static struct atlas7_grp_mux ld_ldd_grp_mux = {
> -       .pad_mux_count = ARRAY_SIZE(ld_ldd_grp_pad_mux),
> -       .pad_mux_list = ld_ldd_grp_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux ld_ldd_16bit_grp_pad_mux[] = {
> -       MUX(1, 57, 1, N, N, N, N),
> -       MUX(1, 58, 1, N, N, N, N),
> -       MUX(1, 59, 1, N, N, N, N),
> -       MUX(1, 60, 1, N, N, N, N),
> -       MUX(1, 61, 1, N, N, N, N),
> -       MUX(1, 62, 1, N, N, N, N),
> -       MUX(1, 63, 1, N, N, N, N),
> -       MUX(1, 64, 1, N, N, N, N),
> -       MUX(1, 65, 1, N, N, N, N),
> -       MUX(1, 66, 1, N, N, N, N),
> -       MUX(1, 67, 1, N, N, N, N),
> -       MUX(1, 68, 1, N, N, N, N),
> -       MUX(1, 69, 1, N, N, N, N),
> -       MUX(1, 70, 1, N, N, N, N),
> -       MUX(1, 71, 1, N, N, N, N),
> -       MUX(1, 72, 1, N, N, N, N),
> -       MUX(1, 56, 1, N, N, N, N),
> -       MUX(1, 53, 1, N, N, N, N),
> -};
> -
> -static struct atlas7_grp_mux ld_ldd_16bit_grp_mux = {
> -       .pad_mux_count = ARRAY_SIZE(ld_ldd_16bit_grp_pad_mux),
> -       .pad_mux_list = ld_ldd_16bit_grp_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux ld_ldd_fck_grp_pad_mux[] = {
> -       MUX(1, 55, 1, N, N, N, N),
> -};
> -
> -static struct atlas7_grp_mux ld_ldd_fck_grp_mux = {
> -       .pad_mux_count = ARRAY_SIZE(ld_ldd_fck_grp_pad_mux),
> -       .pad_mux_list = ld_ldd_fck_grp_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux ld_ldd_lck_grp_pad_mux[] = {
> -       MUX(1, 54, 1, N, N, N, N),
> -};
> -
> -static struct atlas7_grp_mux ld_ldd_lck_grp_mux = {
> -       .pad_mux_count = ARRAY_SIZE(ld_ldd_lck_grp_pad_mux),
> -       .pad_mux_list = ld_ldd_lck_grp_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux lr_lcdrom_grp_pad_mux[] = {
> -       MUX(1, 73, 2, N, N, N, N),
> -       MUX(1, 54, 2, N, N, N, N),
> -       MUX(1, 57, 2, N, N, N, N),
> -       MUX(1, 58, 2, N, N, N, N),
> -       MUX(1, 59, 2, N, N, N, N),
> -       MUX(1, 60, 2, N, N, N, N),
> -       MUX(1, 61, 2, N, N, N, N),
> -       MUX(1, 62, 2, N, N, N, N),
> -       MUX(1, 63, 2, N, N, N, N),
> -       MUX(1, 64, 2, N, N, N, N),
> -       MUX(1, 65, 2, N, N, N, N),
> -       MUX(1, 66, 2, N, N, N, N),
> -       MUX(1, 67, 2, N, N, N, N),
> -       MUX(1, 68, 2, N, N, N, N),
> -       MUX(1, 69, 2, N, N, N, N),
> -       MUX(1, 70, 2, N, N, N, N),
> -       MUX(1, 71, 2, N, N, N, N),
> -       MUX(1, 72, 2, N, N, N, N),
> -       MUX(1, 56, 2, N, N, N, N),
> -       MUX(1, 53, 2, N, N, N, N),
> -       MUX(1, 55, 2, N, N, N, N),
> -};
> -
> -static struct atlas7_grp_mux lr_lcdrom_grp_mux = {
> -       .pad_mux_count = ARRAY_SIZE(lr_lcdrom_grp_pad_mux),
> -       .pad_mux_list = lr_lcdrom_grp_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux lvds_analog_grp_pad_mux[] = {
> -       MUX(1, 149, 8, N, N, N, N),
> -       MUX(1, 150, 8, N, N, N, N),
> -       MUX(1, 151, 8, N, N, N, N),
> -       MUX(1, 152, 8, N, N, N, N),
> -       MUX(1, 153, 8, N, N, N, N),
> -       MUX(1, 154, 8, N, N, N, N),
> -       MUX(1, 155, 8, N, N, N, N),
> -       MUX(1, 156, 8, N, N, N, N),
> -       MUX(1, 157, 8, N, N, N, N),
> -       MUX(1, 158, 8, N, N, N, N),
> -};
> -
> -static struct atlas7_grp_mux lvds_analog_grp_mux = {
> -       .pad_mux_count = ARRAY_SIZE(lvds_analog_grp_pad_mux),
> -       .pad_mux_list = lvds_analog_grp_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux nd_df_basic_grp_pad_mux[] = {
> -       MUX(1, 44, 1, N, N, N, N),
> -       MUX(1, 43, 1, N, N, N, N),
> -       MUX(1, 42, 1, N, N, N, N),
> -       MUX(1, 41, 1, N, N, N, N),
> -       MUX(1, 40, 1, N, N, N, N),
> -       MUX(1, 39, 1, N, N, N, N),
> -       MUX(1, 38, 1, N, N, N, N),
> -       MUX(1, 37, 1, N, N, N, N),
> -       MUX(1, 47, 1, N, N, N, N),
> -       MUX(1, 46, 1, N, N, N, N),
> -       MUX(1, 52, 1, N, N, N, N),
> -       MUX(1, 45, 1, N, N, N, N),
> -       MUX(1, 49, 1, N, N, N, N),
> -       MUX(1, 50, 1, N, N, N, N),
> -       MUX(1, 48, 1, N, N, N, N),
> -};
> -
> -static struct atlas7_grp_mux nd_df_basic_grp_mux = {
> -       .pad_mux_count = ARRAY_SIZE(nd_df_basic_grp_pad_mux),
> -       .pad_mux_list = nd_df_basic_grp_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux nd_df_wp_grp_pad_mux[] = {
> -       MUX(1, 124, 4, N, N, N, N),
> -};
> -
> -static struct atlas7_grp_mux nd_df_wp_grp_mux = {
> -       .pad_mux_count = ARRAY_SIZE(nd_df_wp_grp_pad_mux),
> -       .pad_mux_list = nd_df_wp_grp_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux nd_df_cs_grp_pad_mux[] = {
> -       MUX(1, 51, 1, N, N, N, N),
> -};
> -
> -static struct atlas7_grp_mux nd_df_cs_grp_mux = {
> -       .pad_mux_count = ARRAY_SIZE(nd_df_cs_grp_pad_mux),
> -       .pad_mux_list = nd_df_cs_grp_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux ps_grp_pad_mux[] = {
> -       MUX(1, 120, 2, N, N, N, N),
> -       MUX(1, 119, 2, N, N, N, N),
> -       MUX(1, 121, 5, N, N, N, N),
> -};
> -
> -static struct atlas7_grp_mux ps_grp_mux = {
> -       .pad_mux_count = ARRAY_SIZE(ps_grp_pad_mux),
> -       .pad_mux_list = ps_grp_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux ps_no_dir_grp_pad_mux[] = {
> -       MUX(1, 119, 2, N, N, N, N),
> -};
> -
> -static struct atlas7_grp_mux ps_no_dir_grp_mux = {
> -       .pad_mux_count = ARRAY_SIZE(ps_no_dir_grp_pad_mux),
> -       .pad_mux_list = ps_no_dir_grp_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux pwc_core_on_grp_pad_mux[] = {
> -       MUX(0, 8, 1, N, N, N, N),
> -};
> -
> -static struct atlas7_grp_mux pwc_core_on_grp_mux = {
> -       .pad_mux_count = ARRAY_SIZE(pwc_core_on_grp_pad_mux),
> -       .pad_mux_list = pwc_core_on_grp_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux pwc_ext_on_grp_pad_mux[] = {
> -       MUX(0, 6, 1, N, N, N, N),
> -};
> -
> -static struct atlas7_grp_mux pwc_ext_on_grp_mux = {
> -       .pad_mux_count = ARRAY_SIZE(pwc_ext_on_grp_pad_mux),
> -       .pad_mux_list = pwc_ext_on_grp_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux pwc_gpio3_clk_grp_pad_mux[] = {
> -       MUX(0, 3, 4, N, N, N, N),
> -};
> -
> -static struct atlas7_grp_mux pwc_gpio3_clk_grp_mux = {
> -       .pad_mux_count = ARRAY_SIZE(pwc_gpio3_clk_grp_pad_mux),
> -       .pad_mux_list = pwc_gpio3_clk_grp_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux pwc_io_on_grp_pad_mux[] = {
> -       MUX(0, 9, 1, N, N, N, N),
> -};
> -
> -static struct atlas7_grp_mux pwc_io_on_grp_mux = {
> -       .pad_mux_count = ARRAY_SIZE(pwc_io_on_grp_pad_mux),
> -       .pad_mux_list = pwc_io_on_grp_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux pwc_lowbatt_b_grp0_pad_mux[] = {
> -       MUX(0, 4, 1, 0xa08, 4, 0xa88, 4),
> -};
> -
> -static struct atlas7_grp_mux pwc_lowbatt_b_grp0_mux = {
> -       .pad_mux_count = ARRAY_SIZE(pwc_lowbatt_b_grp0_pad_mux),
> -       .pad_mux_list = pwc_lowbatt_b_grp0_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux pwc_mem_on_grp_pad_mux[] = {
> -       MUX(0, 7, 1, N, N, N, N),
> -};
> -
> -static struct atlas7_grp_mux pwc_mem_on_grp_mux = {
> -       .pad_mux_count = ARRAY_SIZE(pwc_mem_on_grp_pad_mux),
> -       .pad_mux_list = pwc_mem_on_grp_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux pwc_on_key_b_grp0_pad_mux[] = {
> -       MUX(0, 5, 1, 0xa08, 5, 0xa88, 5),
> -};
> -
> -static struct atlas7_grp_mux pwc_on_key_b_grp0_mux = {
> -       .pad_mux_count = ARRAY_SIZE(pwc_on_key_b_grp0_pad_mux),
> -       .pad_mux_list = pwc_on_key_b_grp0_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux pwc_wakeup_src0_grp_pad_mux[] = {
> -       MUX(0, 0, 1, N, N, N, N),
> -};
> -
> -static struct atlas7_grp_mux pwc_wakeup_src0_grp_mux = {
> -       .pad_mux_count = ARRAY_SIZE(pwc_wakeup_src0_grp_pad_mux),
> -       .pad_mux_list = pwc_wakeup_src0_grp_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux pwc_wakeup_src1_grp_pad_mux[] = {
> -       MUX(0, 1, 1, N, N, N, N),
> -};
> -
> -static struct atlas7_grp_mux pwc_wakeup_src1_grp_mux = {
> -       .pad_mux_count = ARRAY_SIZE(pwc_wakeup_src1_grp_pad_mux),
> -       .pad_mux_list = pwc_wakeup_src1_grp_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux pwc_wakeup_src2_grp_pad_mux[] = {
> -       MUX(0, 2, 1, N, N, N, N),
> -};
> -
> -static struct atlas7_grp_mux pwc_wakeup_src2_grp_mux = {
> -       .pad_mux_count = ARRAY_SIZE(pwc_wakeup_src2_grp_pad_mux),
> -       .pad_mux_list = pwc_wakeup_src2_grp_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux pwc_wakeup_src3_grp_pad_mux[] = {
> -       MUX(0, 3, 1, N, N, N, N),
> -};
> -
> -static struct atlas7_grp_mux pwc_wakeup_src3_grp_mux = {
> -       .pad_mux_count = ARRAY_SIZE(pwc_wakeup_src3_grp_pad_mux),
> -       .pad_mux_list = pwc_wakeup_src3_grp_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux pw_cko0_grp0_pad_mux[] = {
> -       MUX(1, 123, 3, N, N, N, N),
> -};
> -
> -static struct atlas7_grp_mux pw_cko0_grp0_mux = {
> -       .pad_mux_count = ARRAY_SIZE(pw_cko0_grp0_pad_mux),
> -       .pad_mux_list = pw_cko0_grp0_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux pw_cko0_grp1_pad_mux[] = {
> -       MUX(1, 101, 4, N, N, N, N),
> -};
> -
> -static struct atlas7_grp_mux pw_cko0_grp1_mux = {
> -       .pad_mux_count = ARRAY_SIZE(pw_cko0_grp1_pad_mux),
> -       .pad_mux_list = pw_cko0_grp1_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux pw_cko0_grp2_pad_mux[] = {
> -       MUX(1, 82, 2, N, N, N, N),
> -};
> -
> -static struct atlas7_grp_mux pw_cko0_grp2_mux = {
> -       .pad_mux_count = ARRAY_SIZE(pw_cko0_grp2_pad_mux),
> -       .pad_mux_list = pw_cko0_grp2_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux pw_cko0_grp3_pad_mux[] = {
> -       MUX(1, 162, 5, N, N, N, N),
> -};
> -
> -static struct atlas7_grp_mux pw_cko0_grp3_mux = {
> -       .pad_mux_count = ARRAY_SIZE(pw_cko0_grp3_pad_mux),
> -       .pad_mux_list = pw_cko0_grp3_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux pw_cko1_grp0_pad_mux[] = {
> -       MUX(1, 124, 3, N, N, N, N),
> -};
> -
> -static struct atlas7_grp_mux pw_cko1_grp0_mux = {
> -       .pad_mux_count = ARRAY_SIZE(pw_cko1_grp0_pad_mux),
> -       .pad_mux_list = pw_cko1_grp0_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux pw_cko1_grp1_pad_mux[] = {
> -       MUX(1, 110, 4, N, N, N, N),
> -};
> -
> -static struct atlas7_grp_mux pw_cko1_grp1_mux = {
> -       .pad_mux_count = ARRAY_SIZE(pw_cko1_grp1_pad_mux),
> -       .pad_mux_list = pw_cko1_grp1_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux pw_cko1_grp2_pad_mux[] = {
> -       MUX(1, 163, 5, N, N, N, N),
> -};
> -
> -static struct atlas7_grp_mux pw_cko1_grp2_mux = {
> -       .pad_mux_count = ARRAY_SIZE(pw_cko1_grp2_pad_mux),
> -       .pad_mux_list = pw_cko1_grp2_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux pw_i2s01_clk_grp0_pad_mux[] = {
> -       MUX(1, 125, 3, N, N, N, N),
> -};
> -
> -static struct atlas7_grp_mux pw_i2s01_clk_grp0_mux = {
> -       .pad_mux_count = ARRAY_SIZE(pw_i2s01_clk_grp0_pad_mux),
> -       .pad_mux_list = pw_i2s01_clk_grp0_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux pw_i2s01_clk_grp1_pad_mux[] = {
> -       MUX(1, 117, 3, N, N, N, N),
> -};
> -
> -static struct atlas7_grp_mux pw_i2s01_clk_grp1_mux = {
> -       .pad_mux_count = ARRAY_SIZE(pw_i2s01_clk_grp1_pad_mux),
> -       .pad_mux_list = pw_i2s01_clk_grp1_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux pw_i2s01_clk_grp2_pad_mux[] = {
> -       MUX(1, 132, 2, N, N, N, N),
> -};
> -
> -static struct atlas7_grp_mux pw_i2s01_clk_grp2_mux = {
> -       .pad_mux_count = ARRAY_SIZE(pw_i2s01_clk_grp2_pad_mux),
> -       .pad_mux_list = pw_i2s01_clk_grp2_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux pw_pwm0_grp0_pad_mux[] = {
> -       MUX(1, 119, 3, N, N, N, N),
> -};
> -
> -static struct atlas7_grp_mux pw_pwm0_grp0_mux = {
> -       .pad_mux_count = ARRAY_SIZE(pw_pwm0_grp0_pad_mux),
> -       .pad_mux_list = pw_pwm0_grp0_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux pw_pwm0_grp1_pad_mux[] = {
> -       MUX(1, 159, 5, N, N, N, N),
> -};
> -
> -static struct atlas7_grp_mux pw_pwm0_grp1_mux = {
> -       .pad_mux_count = ARRAY_SIZE(pw_pwm0_grp1_pad_mux),
> -       .pad_mux_list = pw_pwm0_grp1_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux pw_pwm1_grp0_pad_mux[] = {
> -       MUX(1, 120, 3, N, N, N, N),
> -};
> -
> -static struct atlas7_grp_mux pw_pwm1_grp0_mux = {
> -       .pad_mux_count = ARRAY_SIZE(pw_pwm1_grp0_pad_mux),
> -       .pad_mux_list = pw_pwm1_grp0_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux pw_pwm1_grp1_pad_mux[] = {
> -       MUX(1, 160, 5, N, N, N, N),
> -};
> -
> -static struct atlas7_grp_mux pw_pwm1_grp1_mux = {
> -       .pad_mux_count = ARRAY_SIZE(pw_pwm1_grp1_pad_mux),
> -       .pad_mux_list = pw_pwm1_grp1_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux pw_pwm1_grp2_pad_mux[] = {
> -       MUX(1, 131, 2, N, N, N, N),
> -};
> -
> -static struct atlas7_grp_mux pw_pwm1_grp2_mux = {
> -       .pad_mux_count = ARRAY_SIZE(pw_pwm1_grp2_pad_mux),
> -       .pad_mux_list = pw_pwm1_grp2_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux pw_pwm2_grp0_pad_mux[] = {
> -       MUX(1, 121, 3, N, N, N, N),
> -};
> -
> -static struct atlas7_grp_mux pw_pwm2_grp0_mux = {
> -       .pad_mux_count = ARRAY_SIZE(pw_pwm2_grp0_pad_mux),
> -       .pad_mux_list = pw_pwm2_grp0_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux pw_pwm2_grp1_pad_mux[] = {
> -       MUX(1, 98, 3, N, N, N, N),
> -};
> -
> -static struct atlas7_grp_mux pw_pwm2_grp1_mux = {
> -       .pad_mux_count = ARRAY_SIZE(pw_pwm2_grp1_pad_mux),
> -       .pad_mux_list = pw_pwm2_grp1_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux pw_pwm2_grp2_pad_mux[] = {
> -       MUX(1, 161, 5, N, N, N, N),
> -};
> -
> -static struct atlas7_grp_mux pw_pwm2_grp2_mux = {
> -       .pad_mux_count = ARRAY_SIZE(pw_pwm2_grp2_pad_mux),
> -       .pad_mux_list = pw_pwm2_grp2_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux pw_pwm3_grp0_pad_mux[] = {
> -       MUX(1, 122, 3, N, N, N, N),
> -};
> -
> -static struct atlas7_grp_mux pw_pwm3_grp0_mux = {
> -       .pad_mux_count = ARRAY_SIZE(pw_pwm3_grp0_pad_mux),
> -       .pad_mux_list = pw_pwm3_grp0_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux pw_pwm3_grp1_pad_mux[] = {
> -       MUX(1, 73, 4, N, N, N, N),
> -};
> -
> -static struct atlas7_grp_mux pw_pwm3_grp1_mux = {
> -       .pad_mux_count = ARRAY_SIZE(pw_pwm3_grp1_pad_mux),
> -       .pad_mux_list = pw_pwm3_grp1_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux pw_pwm_cpu_vol_grp0_pad_mux[] = {
> -       MUX(1, 121, 3, N, N, N, N),
> -};
> -
> -static struct atlas7_grp_mux pw_pwm_cpu_vol_grp0_mux = {
> -       .pad_mux_count = ARRAY_SIZE(pw_pwm_cpu_vol_grp0_pad_mux),
> -       .pad_mux_list = pw_pwm_cpu_vol_grp0_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux pw_pwm_cpu_vol_grp1_pad_mux[] = {
> -       MUX(1, 98, 3, N, N, N, N),
> -};
> -
> -static struct atlas7_grp_mux pw_pwm_cpu_vol_grp1_mux = {
> -       .pad_mux_count = ARRAY_SIZE(pw_pwm_cpu_vol_grp1_pad_mux),
> -       .pad_mux_list = pw_pwm_cpu_vol_grp1_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux pw_pwm_cpu_vol_grp2_pad_mux[] = {
> -       MUX(1, 161, 5, N, N, N, N),
> -};
> -
> -static struct atlas7_grp_mux pw_pwm_cpu_vol_grp2_mux = {
> -       .pad_mux_count = ARRAY_SIZE(pw_pwm_cpu_vol_grp2_pad_mux),
> -       .pad_mux_list = pw_pwm_cpu_vol_grp2_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux pw_backlight_grp0_pad_mux[] = {
> -       MUX(1, 122, 3, N, N, N, N),
> -};
> -
> -static struct atlas7_grp_mux pw_backlight_grp0_mux = {
> -       .pad_mux_count = ARRAY_SIZE(pw_backlight_grp0_pad_mux),
> -       .pad_mux_list = pw_backlight_grp0_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux pw_backlight_grp1_pad_mux[] = {
> -       MUX(1, 73, 4, N, N, N, N),
> -};
> -
> -static struct atlas7_grp_mux pw_backlight_grp1_mux = {
> -       .pad_mux_count = ARRAY_SIZE(pw_backlight_grp1_pad_mux),
> -       .pad_mux_list = pw_backlight_grp1_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux rg_eth_mac_grp_pad_mux[] = {
> -       MUX(1, 108, 1, N, N, N, N),
> -       MUX(1, 103, 1, N, N, N, N),
> -       MUX(1, 104, 1, N, N, N, N),
> -       MUX(1, 105, 1, N, N, N, N),
> -       MUX(1, 106, 1, N, N, N, N),
> -       MUX(1, 107, 1, N, N, N, N),
> -       MUX(1, 102, 1, N, N, N, N),
> -       MUX(1, 97, 1, N, N, N, N),
> -       MUX(1, 98, 1, N, N, N, N),
> -       MUX(1, 99, 1, N, N, N, N),
> -       MUX(1, 100, 1, N, N, N, N),
> -       MUX(1, 101, 1, N, N, N, N),
> -};
> -
> -static struct atlas7_grp_mux rg_eth_mac_grp_mux = {
> -       .pad_mux_count = ARRAY_SIZE(rg_eth_mac_grp_pad_mux),
> -       .pad_mux_list = rg_eth_mac_grp_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux rg_gmac_phy_intr_n_grp_pad_mux[] = {
> -       MUX(1, 111, 1, 0xa08, 13, 0xa88, 13),
> -};
> -
> -static struct atlas7_grp_mux rg_gmac_phy_intr_n_grp_mux = {
> -       .pad_mux_count = ARRAY_SIZE(rg_gmac_phy_intr_n_grp_pad_mux),
> -       .pad_mux_list = rg_gmac_phy_intr_n_grp_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux rg_rgmii_mac_grp_pad_mux[] = {
> -       MUX(1, 109, 1, N, N, N, N),
> -       MUX(1, 110, 1, N, N, N, N),
> -};
> -
> -static struct atlas7_grp_mux rg_rgmii_mac_grp_mux = {
> -       .pad_mux_count = ARRAY_SIZE(rg_rgmii_mac_grp_pad_mux),
> -       .pad_mux_list = rg_rgmii_mac_grp_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux rg_rgmii_phy_ref_clk_grp0_pad_mux[] = {
> -       MUX(1, 111, 5, N, N, N, N),
> -};
> -
> -static struct atlas7_grp_mux rg_rgmii_phy_ref_clk_grp0_mux = {
> -       .pad_mux_count = ARRAY_SIZE(rg_rgmii_phy_ref_clk_grp0_pad_mux),
> -       .pad_mux_list = rg_rgmii_phy_ref_clk_grp0_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux rg_rgmii_phy_ref_clk_grp1_pad_mux[] = {
> -       MUX(1, 53, 4, N, N, N, N),
> -};
> -
> -static struct atlas7_grp_mux rg_rgmii_phy_ref_clk_grp1_mux = {
> -       .pad_mux_count = ARRAY_SIZE(rg_rgmii_phy_ref_clk_grp1_pad_mux),
> -       .pad_mux_list = rg_rgmii_phy_ref_clk_grp1_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux sd0_grp_pad_mux[] = {
> -       MUX(1, 46, 2, N, N, N, N),
> -       MUX(1, 47, 2, N, N, N, N),
> -       MUX(1, 44, 2, N, N, N, N),
> -       MUX(1, 43, 2, N, N, N, N),
> -       MUX(1, 42, 2, N, N, N, N),
> -       MUX(1, 41, 2, N, N, N, N),
> -       MUX(1, 40, 2, N, N, N, N),
> -       MUX(1, 39, 2, N, N, N, N),
> -       MUX(1, 38, 2, N, N, N, N),
> -       MUX(1, 37, 2, N, N, N, N),
> -};
> -
> -static struct atlas7_grp_mux sd0_grp_mux = {
> -       .pad_mux_count = ARRAY_SIZE(sd0_grp_pad_mux),
> -       .pad_mux_list = sd0_grp_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux sd0_4bit_grp_pad_mux[] = {
> -       MUX(1, 46, 2, N, N, N, N),
> -       MUX(1, 47, 2, N, N, N, N),
> -       MUX(1, 44, 2, N, N, N, N),
> -       MUX(1, 43, 2, N, N, N, N),
> -       MUX(1, 42, 2, N, N, N, N),
> -       MUX(1, 41, 2, N, N, N, N),
> -};
> -
> -static struct atlas7_grp_mux sd0_4bit_grp_mux = {
> -       .pad_mux_count = ARRAY_SIZE(sd0_4bit_grp_pad_mux),
> -       .pad_mux_list = sd0_4bit_grp_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux sd1_grp_pad_mux[] = {
> -       MUX(1, 48, 3, N, N, N, N),
> -       MUX(1, 49, 3, N, N, N, N),
> -       MUX(1, 44, 3, 0xa00, 0, 0xa80, 0),
> -       MUX(1, 43, 3, 0xa00, 1, 0xa80, 1),
> -       MUX(1, 42, 3, 0xa00, 2, 0xa80, 2),
> -       MUX(1, 41, 3, 0xa00, 3, 0xa80, 3),
> -       MUX(1, 40, 3, N, N, N, N),
> -       MUX(1, 39, 3, N, N, N, N),
> -       MUX(1, 38, 3, N, N, N, N),
> -       MUX(1, 37, 3, N, N, N, N),
> -};
> -
> -static struct atlas7_grp_mux sd1_grp_mux = {
> -       .pad_mux_count = ARRAY_SIZE(sd1_grp_pad_mux),
> -       .pad_mux_list = sd1_grp_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux sd1_4bit_grp0_pad_mux[] = {
> -       MUX(1, 48, 3, N, N, N, N),
> -       MUX(1, 49, 3, N, N, N, N),
> -       MUX(1, 44, 3, 0xa00, 0, 0xa80, 0),
> -       MUX(1, 43, 3, 0xa00, 1, 0xa80, 1),
> -       MUX(1, 42, 3, 0xa00, 2, 0xa80, 2),
> -       MUX(1, 41, 3, 0xa00, 3, 0xa80, 3),
> -};
> -
> -static struct atlas7_grp_mux sd1_4bit_grp0_mux = {
> -       .pad_mux_count = ARRAY_SIZE(sd1_4bit_grp0_pad_mux),
> -       .pad_mux_list = sd1_4bit_grp0_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux sd1_4bit_grp1_pad_mux[] = {
> -       MUX(1, 48, 3, N, N, N, N),
> -       MUX(1, 49, 3, N, N, N, N),
> -       MUX(1, 40, 4, 0xa00, 0, 0xa80, 0),
> -       MUX(1, 39, 4, 0xa00, 1, 0xa80, 1),
> -       MUX(1, 38, 4, 0xa00, 2, 0xa80, 2),
> -       MUX(1, 37, 4, 0xa00, 3, 0xa80, 3),
> -};
> -
> -static struct atlas7_grp_mux sd1_4bit_grp1_mux = {
> -       .pad_mux_count = ARRAY_SIZE(sd1_4bit_grp1_pad_mux),
> -       .pad_mux_list = sd1_4bit_grp1_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux sd2_basic_grp_pad_mux[] = {
> -       MUX(1, 31, 1, N, N, N, N),
> -       MUX(1, 32, 1, N, N, N, N),
> -       MUX(1, 33, 1, N, N, N, N),
> -       MUX(1, 34, 1, N, N, N, N),
> -       MUX(1, 35, 1, N, N, N, N),
> -       MUX(1, 36, 1, N, N, N, N),
> -};
> -
> -static struct atlas7_grp_mux sd2_basic_grp_mux = {
> -       .pad_mux_count = ARRAY_SIZE(sd2_basic_grp_pad_mux),
> -       .pad_mux_list = sd2_basic_grp_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux sd2_cdb_grp0_pad_mux[] = {
> -       MUX(1, 124, 2, 0xa08, 7, 0xa88, 7),
> -};
> -
> -static struct atlas7_grp_mux sd2_cdb_grp0_mux = {
> -       .pad_mux_count = ARRAY_SIZE(sd2_cdb_grp0_pad_mux),
> -       .pad_mux_list = sd2_cdb_grp0_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux sd2_cdb_grp1_pad_mux[] = {
> -       MUX(1, 161, 6, 0xa08, 7, 0xa88, 7),
> -};
> -
> -static struct atlas7_grp_mux sd2_cdb_grp1_mux = {
> -       .pad_mux_count = ARRAY_SIZE(sd2_cdb_grp1_pad_mux),
> -       .pad_mux_list = sd2_cdb_grp1_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux sd2_wpb_grp0_pad_mux[] = {
> -       MUX(1, 123, 2, 0xa10, 6, 0xa90, 6),
> -};
> -
> -static struct atlas7_grp_mux sd2_wpb_grp0_mux = {
> -       .pad_mux_count = ARRAY_SIZE(sd2_wpb_grp0_pad_mux),
> -       .pad_mux_list = sd2_wpb_grp0_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux sd2_wpb_grp1_pad_mux[] = {
> -       MUX(1, 163, 7, 0xa10, 6, 0xa90, 6),
> -};
> -
> -static struct atlas7_grp_mux sd2_wpb_grp1_mux = {
> -       .pad_mux_count = ARRAY_SIZE(sd2_wpb_grp1_pad_mux),
> -       .pad_mux_list = sd2_wpb_grp1_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux sd3_9_grp_pad_mux[] = {
> -       MUX(1, 85, 1, N, N, N, N),
> -       MUX(1, 86, 1, N, N, N, N),
> -       MUX(1, 87, 1, N, N, N, N),
> -       MUX(1, 88, 1, N, N, N, N),
> -       MUX(1, 89, 1, N, N, N, N),
> -       MUX(1, 90, 1, N, N, N, N),
> -};
> -
> -static struct atlas7_grp_mux sd3_9_grp_mux = {
> -       .pad_mux_count = ARRAY_SIZE(sd3_9_grp_pad_mux),
> -       .pad_mux_list = sd3_9_grp_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux sd5_grp_pad_mux[] = {
> -       MUX(1, 91, 1, N, N, N, N),
> -       MUX(1, 92, 1, N, N, N, N),
> -       MUX(1, 93, 1, N, N, N, N),
> -       MUX(1, 94, 1, N, N, N, N),
> -       MUX(1, 95, 1, N, N, N, N),
> -       MUX(1, 96, 1, N, N, N, N),
> -};
> -
> -static struct atlas7_grp_mux sd5_grp_mux = {
> -       .pad_mux_count = ARRAY_SIZE(sd5_grp_pad_mux),
> -       .pad_mux_list = sd5_grp_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux sd6_grp0_pad_mux[] = {
> -       MUX(1, 79, 4, 0xa00, 27, 0xa80, 27),
> -       MUX(1, 78, 4, 0xa00, 26, 0xa80, 26),
> -       MUX(1, 74, 4, 0xa00, 28, 0xa80, 28),
> -       MUX(1, 75, 4, 0xa00, 29, 0xa80, 29),
> -       MUX(1, 76, 4, 0xa00, 30, 0xa80, 30),
> -       MUX(1, 77, 4, 0xa00, 31, 0xa80, 31),
> -};
> -
> -static struct atlas7_grp_mux sd6_grp0_mux = {
> -       .pad_mux_count = ARRAY_SIZE(sd6_grp0_pad_mux),
> -       .pad_mux_list = sd6_grp0_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux sd6_grp1_pad_mux[] = {
> -       MUX(1, 101, 3, 0xa00, 27, 0xa80, 27),
> -       MUX(1, 99, 3, 0xa00, 26, 0xa80, 26),
> -       MUX(1, 100, 3, 0xa00, 28, 0xa80, 28),
> -       MUX(1, 110, 3, 0xa00, 29, 0xa80, 29),
> -       MUX(1, 109, 3, 0xa00, 30, 0xa80, 30),
> -       MUX(1, 111, 3, 0xa00, 31, 0xa80, 31),
> -};
> -
> -static struct atlas7_grp_mux sd6_grp1_mux = {
> -       .pad_mux_count = ARRAY_SIZE(sd6_grp1_pad_mux),
> -       .pad_mux_list = sd6_grp1_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux sp0_ext_ldo_on_grp_pad_mux[] = {
> -       MUX(0, 4, 2, N, N, N, N),
> -};
> -
> -static struct atlas7_grp_mux sp0_ext_ldo_on_grp_mux = {
> -       .pad_mux_count = ARRAY_SIZE(sp0_ext_ldo_on_grp_pad_mux),
> -       .pad_mux_list = sp0_ext_ldo_on_grp_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux sp0_qspi_grp_pad_mux[] = {
> -       MUX(0, 12, 1, N, N, N, N),
> -       MUX(0, 13, 1, N, N, N, N),
> -       MUX(0, 14, 1, N, N, N, N),
> -       MUX(0, 15, 1, N, N, N, N),
> -       MUX(0, 16, 1, N, N, N, N),
> -       MUX(0, 17, 1, N, N, N, N),
> -};
> -
> -static struct atlas7_grp_mux sp0_qspi_grp_mux = {
> -       .pad_mux_count = ARRAY_SIZE(sp0_qspi_grp_pad_mux),
> -       .pad_mux_list = sp0_qspi_grp_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux sp1_spi_grp_pad_mux[] = {
> -       MUX(1, 19, 1, N, N, N, N),
> -       MUX(1, 20, 1, N, N, N, N),
> -       MUX(1, 21, 1, N, N, N, N),
> -       MUX(1, 18, 1, N, N, N, N),
> -};
> -
> -static struct atlas7_grp_mux sp1_spi_grp_mux = {
> -       .pad_mux_count = ARRAY_SIZE(sp1_spi_grp_pad_mux),
> -       .pad_mux_list = sp1_spi_grp_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux tpiu_trace_grp_pad_mux[] = {
> -       MUX(1, 53, 5, N, N, N, N),
> -       MUX(1, 56, 5, N, N, N, N),
> -       MUX(1, 57, 5, N, N, N, N),
> -       MUX(1, 58, 5, N, N, N, N),
> -       MUX(1, 59, 5, N, N, N, N),
> -       MUX(1, 60, 5, N, N, N, N),
> -       MUX(1, 61, 5, N, N, N, N),
> -       MUX(1, 62, 5, N, N, N, N),
> -       MUX(1, 63, 5, N, N, N, N),
> -       MUX(1, 64, 5, N, N, N, N),
> -       MUX(1, 65, 5, N, N, N, N),
> -       MUX(1, 66, 5, N, N, N, N),
> -       MUX(1, 67, 5, N, N, N, N),
> -       MUX(1, 68, 5, N, N, N, N),
> -       MUX(1, 69, 5, N, N, N, N),
> -       MUX(1, 70, 5, N, N, N, N),
> -       MUX(1, 71, 5, N, N, N, N),
> -       MUX(1, 72, 5, N, N, N, N),
> -};
> -
> -static struct atlas7_grp_mux tpiu_trace_grp_mux = {
> -       .pad_mux_count = ARRAY_SIZE(tpiu_trace_grp_pad_mux),
> -       .pad_mux_list = tpiu_trace_grp_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux uart0_grp_pad_mux[] = {
> -       MUX(1, 121, 4, N, N, N, N),
> -       MUX(1, 120, 4, N, N, N, N),
> -       MUX(1, 134, 1, N, N, N, N),
> -       MUX(1, 133, 1, N, N, N, N),
> -};
> -
> -static struct atlas7_grp_mux uart0_grp_mux = {
> -       .pad_mux_count = ARRAY_SIZE(uart0_grp_pad_mux),
> -       .pad_mux_list = uart0_grp_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux uart0_nopause_grp_pad_mux[] = {
> -       MUX(1, 134, 1, N, N, N, N),
> -       MUX(1, 133, 1, N, N, N, N),
> -};
> -
> -static struct atlas7_grp_mux uart0_nopause_grp_mux = {
> -       .pad_mux_count = ARRAY_SIZE(uart0_nopause_grp_pad_mux),
> -       .pad_mux_list = uart0_nopause_grp_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux uart1_grp_pad_mux[] = {
> -       MUX(1, 136, 1, N, N, N, N),
> -       MUX(1, 135, 1, N, N, N, N),
> -};
> -
> -static struct atlas7_grp_mux uart1_grp_mux = {
> -       .pad_mux_count = ARRAY_SIZE(uart1_grp_pad_mux),
> -       .pad_mux_list = uart1_grp_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux uart2_cts_grp0_pad_mux[] = {
> -       MUX(1, 132, 3, 0xa10, 2, 0xa90, 2),
> -};
> -
> -static struct atlas7_grp_mux uart2_cts_grp0_mux = {
> -       .pad_mux_count = ARRAY_SIZE(uart2_cts_grp0_pad_mux),
> -       .pad_mux_list = uart2_cts_grp0_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux uart2_cts_grp1_pad_mux[] = {
> -       MUX(1, 162, 2, 0xa10, 2, 0xa90, 2),
> -};
> -
> -static struct atlas7_grp_mux uart2_cts_grp1_mux = {
> -       .pad_mux_count = ARRAY_SIZE(uart2_cts_grp1_pad_mux),
> -       .pad_mux_list = uart2_cts_grp1_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux uart2_rts_grp0_pad_mux[] = {
> -       MUX(1, 131, 3, N, N, N, N),
> -};
> -
> -static struct atlas7_grp_mux uart2_rts_grp0_mux = {
> -       .pad_mux_count = ARRAY_SIZE(uart2_rts_grp0_pad_mux),
> -       .pad_mux_list = uart2_rts_grp0_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux uart2_rts_grp1_pad_mux[] = {
> -       MUX(1, 161, 2, N, N, N, N),
> -};
> -
> -static struct atlas7_grp_mux uart2_rts_grp1_mux = {
> -       .pad_mux_count = ARRAY_SIZE(uart2_rts_grp1_pad_mux),
> -       .pad_mux_list = uart2_rts_grp1_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux uart2_rxd_grp0_pad_mux[] = {
> -       MUX(0, 11, 2, 0xa10, 5, 0xa90, 5),
> -};
> -
> -static struct atlas7_grp_mux uart2_rxd_grp0_mux = {
> -       .pad_mux_count = ARRAY_SIZE(uart2_rxd_grp0_pad_mux),
> -       .pad_mux_list = uart2_rxd_grp0_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux uart2_rxd_grp1_pad_mux[] = {
> -       MUX(1, 160, 2, 0xa10, 5, 0xa90, 5),
> -};
> -
> -static struct atlas7_grp_mux uart2_rxd_grp1_mux = {
> -       .pad_mux_count = ARRAY_SIZE(uart2_rxd_grp1_pad_mux),
> -       .pad_mux_list = uart2_rxd_grp1_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux uart2_rxd_grp2_pad_mux[] = {
> -       MUX(1, 130, 3, 0xa10, 5, 0xa90, 5),
> -};
> -
> -static struct atlas7_grp_mux uart2_rxd_grp2_mux = {
> -       .pad_mux_count = ARRAY_SIZE(uart2_rxd_grp2_pad_mux),
> -       .pad_mux_list = uart2_rxd_grp2_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux uart2_txd_grp0_pad_mux[] = {
> -       MUX(0, 10, 2, N, N, N, N),
> -};
> -
> -static struct atlas7_grp_mux uart2_txd_grp0_mux = {
> -       .pad_mux_count = ARRAY_SIZE(uart2_txd_grp0_pad_mux),
> -       .pad_mux_list = uart2_txd_grp0_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux uart2_txd_grp1_pad_mux[] = {
> -       MUX(1, 159, 2, N, N, N, N),
> -};
> -
> -static struct atlas7_grp_mux uart2_txd_grp1_mux = {
> -       .pad_mux_count = ARRAY_SIZE(uart2_txd_grp1_pad_mux),
> -       .pad_mux_list = uart2_txd_grp1_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux uart2_txd_grp2_pad_mux[] = {
> -       MUX(1, 129, 3, N, N, N, N),
> -};
> -
> -static struct atlas7_grp_mux uart2_txd_grp2_mux = {
> -       .pad_mux_count = ARRAY_SIZE(uart2_txd_grp2_pad_mux),
> -       .pad_mux_list = uart2_txd_grp2_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux uart3_cts_grp0_pad_mux[] = {
> -       MUX(1, 125, 2, 0xa08, 0, 0xa88, 0),
> -};
> -
> -static struct atlas7_grp_mux uart3_cts_grp0_mux = {
> -       .pad_mux_count = ARRAY_SIZE(uart3_cts_grp0_pad_mux),
> -       .pad_mux_list = uart3_cts_grp0_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux uart3_cts_grp1_pad_mux[] = {
> -       MUX(1, 111, 4, 0xa08, 0, 0xa88, 0),
> -};
> -
> -static struct atlas7_grp_mux uart3_cts_grp1_mux = {
> -       .pad_mux_count = ARRAY_SIZE(uart3_cts_grp1_pad_mux),
> -       .pad_mux_list = uart3_cts_grp1_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux uart3_cts_grp2_pad_mux[] = {
> -       MUX(1, 140, 2, 0xa08, 0, 0xa88, 0),
> -};
> -
> -static struct atlas7_grp_mux uart3_cts_grp2_mux = {
> -       .pad_mux_count = ARRAY_SIZE(uart3_cts_grp2_pad_mux),
> -       .pad_mux_list = uart3_cts_grp2_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux uart3_rts_grp0_pad_mux[] = {
> -       MUX(1, 126, 2, N, N, N, N),
> -};
> -
> -static struct atlas7_grp_mux uart3_rts_grp0_mux = {
> -       .pad_mux_count = ARRAY_SIZE(uart3_rts_grp0_pad_mux),
> -       .pad_mux_list = uart3_rts_grp0_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux uart3_rts_grp1_pad_mux[] = {
> -       MUX(1, 109, 4, N, N, N, N),
> -};
> -
> -static struct atlas7_grp_mux uart3_rts_grp1_mux = {
> -       .pad_mux_count = ARRAY_SIZE(uart3_rts_grp1_pad_mux),
> -       .pad_mux_list = uart3_rts_grp1_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux uart3_rts_grp2_pad_mux[] = {
> -       MUX(1, 139, 2, N, N, N, N),
> -};
> -
> -static struct atlas7_grp_mux uart3_rts_grp2_mux = {
> -       .pad_mux_count = ARRAY_SIZE(uart3_rts_grp2_pad_mux),
> -       .pad_mux_list = uart3_rts_grp2_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux uart3_rxd_grp0_pad_mux[] = {
> -       MUX(1, 138, 1, 0xa00, 5, 0xa80, 5),
> -};
> -
> -static struct atlas7_grp_mux uart3_rxd_grp0_mux = {
> -       .pad_mux_count = ARRAY_SIZE(uart3_rxd_grp0_pad_mux),
> -       .pad_mux_list = uart3_rxd_grp0_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux uart3_rxd_grp1_pad_mux[] = {
> -       MUX(1, 84, 2, 0xa00, 5, 0xa80, 5),
> -};
> -
> -static struct atlas7_grp_mux uart3_rxd_grp1_mux = {
> -       .pad_mux_count = ARRAY_SIZE(uart3_rxd_grp1_pad_mux),
> -       .pad_mux_list = uart3_rxd_grp1_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux uart3_rxd_grp2_pad_mux[] = {
> -       MUX(1, 162, 3, 0xa00, 5, 0xa80, 5),
> -};
> -
> -static struct atlas7_grp_mux uart3_rxd_grp2_mux = {
> -       .pad_mux_count = ARRAY_SIZE(uart3_rxd_grp2_pad_mux),
> -       .pad_mux_list = uart3_rxd_grp2_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux uart3_txd_grp0_pad_mux[] = {
> -       MUX(1, 137, 1, N, N, N, N),
> -};
> -
> -static struct atlas7_grp_mux uart3_txd_grp0_mux = {
> -       .pad_mux_count = ARRAY_SIZE(uart3_txd_grp0_pad_mux),
> -       .pad_mux_list = uart3_txd_grp0_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux uart3_txd_grp1_pad_mux[] = {
> -       MUX(1, 83, 2, N, N, N, N),
> -};
> -
> -static struct atlas7_grp_mux uart3_txd_grp1_mux = {
> -       .pad_mux_count = ARRAY_SIZE(uart3_txd_grp1_pad_mux),
> -       .pad_mux_list = uart3_txd_grp1_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux uart3_txd_grp2_pad_mux[] = {
> -       MUX(1, 161, 3, N, N, N, N),
> -};
> -
> -static struct atlas7_grp_mux uart3_txd_grp2_mux = {
> -       .pad_mux_count = ARRAY_SIZE(uart3_txd_grp2_pad_mux),
> -       .pad_mux_list = uart3_txd_grp2_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux uart4_basic_grp_pad_mux[] = {
> -       MUX(1, 140, 1, N, N, N, N),
> -       MUX(1, 139, 1, N, N, N, N),
> -};
> -
> -static struct atlas7_grp_mux uart4_basic_grp_mux = {
> -       .pad_mux_count = ARRAY_SIZE(uart4_basic_grp_pad_mux),
> -       .pad_mux_list = uart4_basic_grp_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux uart4_cts_grp0_pad_mux[] = {
> -       MUX(1, 122, 4, 0xa08, 1, 0xa88, 1),
> -};
> -
> -static struct atlas7_grp_mux uart4_cts_grp0_mux = {
> -       .pad_mux_count = ARRAY_SIZE(uart4_cts_grp0_pad_mux),
> -       .pad_mux_list = uart4_cts_grp0_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux uart4_cts_grp1_pad_mux[] = {
> -       MUX(1, 100, 4, 0xa08, 1, 0xa88, 1),
> -};
> -
> -static struct atlas7_grp_mux uart4_cts_grp1_mux = {
> -       .pad_mux_count = ARRAY_SIZE(uart4_cts_grp1_pad_mux),
> -       .pad_mux_list = uart4_cts_grp1_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux uart4_cts_grp2_pad_mux[] = {
> -       MUX(1, 117, 2, 0xa08, 1, 0xa88, 1),
> -};
> -
> -static struct atlas7_grp_mux uart4_cts_grp2_mux = {
> -       .pad_mux_count = ARRAY_SIZE(uart4_cts_grp2_pad_mux),
> -       .pad_mux_list = uart4_cts_grp2_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux uart4_rts_grp0_pad_mux[] = {
> -       MUX(1, 123, 4, N, N, N, N),
> -};
> -
> -static struct atlas7_grp_mux uart4_rts_grp0_mux = {
> -       .pad_mux_count = ARRAY_SIZE(uart4_rts_grp0_pad_mux),
> -       .pad_mux_list = uart4_rts_grp0_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux uart4_rts_grp1_pad_mux[] = {
> -       MUX(1, 99, 4, N, N, N, N),
> -};
> -
> -static struct atlas7_grp_mux uart4_rts_grp1_mux = {
> -       .pad_mux_count = ARRAY_SIZE(uart4_rts_grp1_pad_mux),
> -       .pad_mux_list = uart4_rts_grp1_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux uart4_rts_grp2_pad_mux[] = {
> -       MUX(1, 116, 2, N, N, N, N),
> -};
> -
> -static struct atlas7_grp_mux uart4_rts_grp2_mux = {
> -       .pad_mux_count = ARRAY_SIZE(uart4_rts_grp2_pad_mux),
> -       .pad_mux_list = uart4_rts_grp2_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux usb0_drvvbus_grp0_pad_mux[] = {
> -       MUX(1, 51, 2, N, N, N, N),
> -};
> -
> -static struct atlas7_grp_mux usb0_drvvbus_grp0_mux = {
> -       .pad_mux_count = ARRAY_SIZE(usb0_drvvbus_grp0_pad_mux),
> -       .pad_mux_list = usb0_drvvbus_grp0_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux usb0_drvvbus_grp1_pad_mux[] = {
> -       MUX(1, 162, 7, N, N, N, N),
> -};
> -
> -static struct atlas7_grp_mux usb0_drvvbus_grp1_mux = {
> -       .pad_mux_count = ARRAY_SIZE(usb0_drvvbus_grp1_pad_mux),
> -       .pad_mux_list = usb0_drvvbus_grp1_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux usb1_drvvbus_grp0_pad_mux[] = {
> -       MUX(1, 134, 2, N, N, N, N),
> -};
> -
> -static struct atlas7_grp_mux usb1_drvvbus_grp0_mux = {
> -       .pad_mux_count = ARRAY_SIZE(usb1_drvvbus_grp0_pad_mux),
> -       .pad_mux_list = usb1_drvvbus_grp0_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux usb1_drvvbus_grp1_pad_mux[] = {
> -       MUX(1, 163, 2, N, N, N, N),
> -};
> -
> -static struct atlas7_grp_mux usb1_drvvbus_grp1_mux = {
> -       .pad_mux_count = ARRAY_SIZE(usb1_drvvbus_grp1_pad_mux),
> -       .pad_mux_list = usb1_drvvbus_grp1_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux visbus_dout_grp_pad_mux[] = {
> -       MUX(1, 57, 6, N, N, N, N),
> -       MUX(1, 58, 6, N, N, N, N),
> -       MUX(1, 59, 6, N, N, N, N),
> -       MUX(1, 60, 6, N, N, N, N),
> -       MUX(1, 61, 6, N, N, N, N),
> -       MUX(1, 62, 6, N, N, N, N),
> -       MUX(1, 63, 6, N, N, N, N),
> -       MUX(1, 64, 6, N, N, N, N),
> -       MUX(1, 65, 6, N, N, N, N),
> -       MUX(1, 66, 6, N, N, N, N),
> -       MUX(1, 67, 6, N, N, N, N),
> -       MUX(1, 68, 6, N, N, N, N),
> -       MUX(1, 69, 6, N, N, N, N),
> -       MUX(1, 70, 6, N, N, N, N),
> -       MUX(1, 71, 6, N, N, N, N),
> -       MUX(1, 72, 6, N, N, N, N),
> -       MUX(1, 53, 6, N, N, N, N),
> -       MUX(1, 54, 6, N, N, N, N),
> -       MUX(1, 55, 6, N, N, N, N),
> -       MUX(1, 56, 6, N, N, N, N),
> -       MUX(1, 85, 6, N, N, N, N),
> -       MUX(1, 86, 6, N, N, N, N),
> -       MUX(1, 87, 6, N, N, N, N),
> -       MUX(1, 88, 6, N, N, N, N),
> -       MUX(1, 89, 6, N, N, N, N),
> -       MUX(1, 90, 6, N, N, N, N),
> -       MUX(1, 91, 6, N, N, N, N),
> -       MUX(1, 92, 6, N, N, N, N),
> -       MUX(1, 93, 6, N, N, N, N),
> -       MUX(1, 94, 6, N, N, N, N),
> -       MUX(1, 95, 6, N, N, N, N),
> -       MUX(1, 96, 6, N, N, N, N),
> -};
> -
> -static struct atlas7_grp_mux visbus_dout_grp_mux = {
> -       .pad_mux_count = ARRAY_SIZE(visbus_dout_grp_pad_mux),
> -       .pad_mux_list = visbus_dout_grp_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux vi_vip1_grp_pad_mux[] = {
> -       MUX(1, 74, 1, N, N, N, N),
> -       MUX(1, 75, 1, N, N, N, N),
> -       MUX(1, 76, 1, N, N, N, N),
> -       MUX(1, 77, 1, N, N, N, N),
> -       MUX(1, 78, 1, N, N, N, N),
> -       MUX(1, 79, 1, N, N, N, N),
> -       MUX(1, 80, 1, N, N, N, N),
> -       MUX(1, 81, 1, N, N, N, N),
> -       MUX(1, 82, 1, N, N, N, N),
> -       MUX(1, 83, 1, N, N, N, N),
> -       MUX(1, 84, 1, N, N, N, N),
> -       MUX(1, 103, 2, N, N, N, N),
> -       MUX(1, 104, 2, N, N, N, N),
> -       MUX(1, 105, 2, N, N, N, N),
> -       MUX(1, 106, 2, N, N, N, N),
> -       MUX(1, 107, 2, N, N, N, N),
> -       MUX(1, 102, 2, N, N, N, N),
> -       MUX(1, 97, 2, N, N, N, N),
> -       MUX(1, 98, 2, N, N, N, N),
> -};
> -
> -static struct atlas7_grp_mux vi_vip1_grp_mux = {
> -       .pad_mux_count = ARRAY_SIZE(vi_vip1_grp_pad_mux),
> -       .pad_mux_list = vi_vip1_grp_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux vi_vip1_ext_grp_pad_mux[] = {
> -       MUX(1, 74, 1, N, N, N, N),
> -       MUX(1, 75, 1, N, N, N, N),
> -       MUX(1, 76, 1, N, N, N, N),
> -       MUX(1, 77, 1, N, N, N, N),
> -       MUX(1, 78, 1, N, N, N, N),
> -       MUX(1, 79, 1, N, N, N, N),
> -       MUX(1, 80, 1, N, N, N, N),
> -       MUX(1, 81, 1, N, N, N, N),
> -       MUX(1, 82, 1, N, N, N, N),
> -       MUX(1, 83, 1, N, N, N, N),
> -       MUX(1, 84, 1, N, N, N, N),
> -       MUX(1, 108, 2, N, N, N, N),
> -       MUX(1, 103, 2, N, N, N, N),
> -       MUX(1, 104, 2, N, N, N, N),
> -       MUX(1, 105, 2, N, N, N, N),
> -       MUX(1, 106, 2, N, N, N, N),
> -       MUX(1, 107, 2, N, N, N, N),
> -       MUX(1, 102, 2, N, N, N, N),
> -       MUX(1, 97, 2, N, N, N, N),
> -       MUX(1, 98, 2, N, N, N, N),
> -       MUX(1, 99, 2, N, N, N, N),
> -       MUX(1, 100, 2, N, N, N, N),
> -};
> -
> -static struct atlas7_grp_mux vi_vip1_ext_grp_mux = {
> -       .pad_mux_count = ARRAY_SIZE(vi_vip1_ext_grp_pad_mux),
> -       .pad_mux_list = vi_vip1_ext_grp_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux vi_vip1_low8bit_grp_pad_mux[] = {
> -       MUX(1, 74, 1, N, N, N, N),
> -       MUX(1, 75, 1, N, N, N, N),
> -       MUX(1, 76, 1, N, N, N, N),
> -       MUX(1, 77, 1, N, N, N, N),
> -       MUX(1, 78, 1, N, N, N, N),
> -       MUX(1, 79, 1, N, N, N, N),
> -       MUX(1, 80, 1, N, N, N, N),
> -       MUX(1, 81, 1, N, N, N, N),
> -       MUX(1, 82, 1, N, N, N, N),
> -       MUX(1, 83, 1, N, N, N, N),
> -       MUX(1, 84, 1, N, N, N, N),
> -};
> -
> -static struct atlas7_grp_mux vi_vip1_low8bit_grp_mux = {
> -       .pad_mux_count = ARRAY_SIZE(vi_vip1_low8bit_grp_pad_mux),
> -       .pad_mux_list = vi_vip1_low8bit_grp_pad_mux,
> -};
> -
> -static struct atlas7_pad_mux vi_vip1_high8bit_grp_pad_mux[] = {
> -       MUX(1, 82, 1, N, N, N, N),
> -       MUX(1, 83, 1, N, N, N, N),
> -       MUX(1, 84, 1, N, N, N, N),
> -       MUX(1, 103, 2, N, N, N, N),
> -       MUX(1, 104, 2, N, N, N, N),
> -       MUX(1, 105, 2, N, N, N, N),
> -       MUX(1, 106, 2, N, N, N, N),
> -       MUX(1, 107, 2, N, N, N, N),
> -       MUX(1, 102, 2, N, N, N, N),
> -       MUX(1, 97, 2, N, N, N, N),
> -       MUX(1, 98, 2, N, N, N, N),
> -};
> -
> -static struct atlas7_grp_mux vi_vip1_high8bit_grp_mux = {
> -       .pad_mux_count = ARRAY_SIZE(vi_vip1_high8bit_grp_pad_mux),
> -       .pad_mux_list = vi_vip1_high8bit_grp_pad_mux,
> -};
> -
> -static struct atlas7_pmx_func atlas7_pmx_functions[] = {
> -       FUNCTION("gnss_gpio", gnss_gpio_grp, &gnss_gpio_grp_mux),
> -       FUNCTION("lcd_vip_gpio", lcd_vip_gpio_grp, &lcd_vip_gpio_grp_mux),
> -       FUNCTION("sdio_i2s_gpio", sdio_i2s_gpio_grp, &sdio_i2s_gpio_grp_mux),
> -       FUNCTION("sp_rgmii_gpio", sp_rgmii_gpio_grp, &sp_rgmii_gpio_grp_mux),
> -       FUNCTION("lvds_gpio", lvds_gpio_grp, &lvds_gpio_grp_mux),
> -       FUNCTION("jtag_uart_nand_gpio",
> -                       jtag_uart_nand_gpio_grp,
> -                       &jtag_uart_nand_gpio_grp_mux),
> -       FUNCTION("rtc_gpio", rtc_gpio_grp, &rtc_gpio_grp_mux),
> -       FUNCTION("audio_ac97", audio_ac97_grp, &audio_ac97_grp_mux),
> -       FUNCTION("audio_digmic_m0",
> -                       audio_digmic_grp0,
> -                       &audio_digmic_grp0_mux),
> -       FUNCTION("audio_digmic_m1",
> -                       audio_digmic_grp1,
> -                       &audio_digmic_grp1_mux),
> -       FUNCTION("audio_digmic_m2",
> -                       audio_digmic_grp2,
> -                       &audio_digmic_grp2_mux),
> -       FUNCTION("audio_func_dbg",
> -                       audio_func_dbg_grp,
> -                       &audio_func_dbg_grp_mux),
> -       FUNCTION("audio_i2s", audio_i2s_grp, &audio_i2s_grp_mux),
> -       FUNCTION("audio_i2s_2ch", audio_i2s_2ch_grp, &audio_i2s_2ch_grp_mux),
> -       FUNCTION("audio_i2s_extclk",
> -                       audio_i2s_extclk_grp,
> -                       &audio_i2s_extclk_grp_mux),
> -       FUNCTION("audio_spdif_out_m0",
> -                       audio_spdif_out_grp0,
> -                       &audio_spdif_out_grp0_mux),
> -       FUNCTION("audio_spdif_out_m1",
> -                       audio_spdif_out_grp1,
> -                       &audio_spdif_out_grp1_mux),
> -       FUNCTION("audio_spdif_out_m2",
> -                       audio_spdif_out_grp2,
> -                       &audio_spdif_out_grp2_mux),
> -       FUNCTION("audio_uart0_basic",
> -                       audio_uart0_basic_grp,
> -                       &audio_uart0_basic_grp_mux),
> -       FUNCTION("audio_uart0_urfs_m0",
> -                       audio_uart0_urfs_grp0,
> -                       &audio_uart0_urfs_grp0_mux),
> -       FUNCTION("audio_uart0_urfs_m1",
> -                       audio_uart0_urfs_grp1,
> -                       &audio_uart0_urfs_grp1_mux),
> -       FUNCTION("audio_uart0_urfs_m2",
> -                       audio_uart0_urfs_grp2,
> -                       &audio_uart0_urfs_grp2_mux),
> -       FUNCTION("audio_uart0_urfs_m3",
> -                       audio_uart0_urfs_grp3,
> -                       &audio_uart0_urfs_grp3_mux),
> -       FUNCTION("audio_uart1_basic",
> -                       audio_uart1_basic_grp,
> -                       &audio_uart1_basic_grp_mux),
> -       FUNCTION("audio_uart1_urfs_m0",
> -                       audio_uart1_urfs_grp0,
> -                       &audio_uart1_urfs_grp0_mux),
> -       FUNCTION("audio_uart1_urfs_m1",
> -                       audio_uart1_urfs_grp1,
> -                       &audio_uart1_urfs_grp1_mux),
> -       FUNCTION("audio_uart1_urfs_m2",
> -                       audio_uart1_urfs_grp2,
> -                       &audio_uart1_urfs_grp2_mux),
> -       FUNCTION("audio_uart2_urfs_m0",
> -                       audio_uart2_urfs_grp0,
> -                       &audio_uart2_urfs_grp0_mux),
> -       FUNCTION("audio_uart2_urfs_m1",
> -                       audio_uart2_urfs_grp1,
> -                       &audio_uart2_urfs_grp1_mux),
> -       FUNCTION("audio_uart2_urfs_m2",
> -                       audio_uart2_urfs_grp2,
> -                       &audio_uart2_urfs_grp2_mux),
> -       FUNCTION("audio_uart2_urxd_m0",
> -                       audio_uart2_urxd_grp0,
> -                       &audio_uart2_urxd_grp0_mux),
> -       FUNCTION("audio_uart2_urxd_m1",
> -                       audio_uart2_urxd_grp1,
> -                       &audio_uart2_urxd_grp1_mux),
> -       FUNCTION("audio_uart2_urxd_m2",
> -                       audio_uart2_urxd_grp2,
> -                       &audio_uart2_urxd_grp2_mux),
> -       FUNCTION("audio_uart2_usclk_m0",
> -                       audio_uart2_usclk_grp0,
> -                       &audio_uart2_usclk_grp0_mux),
> -       FUNCTION("audio_uart2_usclk_m1",
> -                       audio_uart2_usclk_grp1,
> -                       &audio_uart2_usclk_grp1_mux),
> -       FUNCTION("audio_uart2_usclk_m2",
> -                       audio_uart2_usclk_grp2,
> -                       &audio_uart2_usclk_grp2_mux),
> -       FUNCTION("audio_uart2_utfs_m0",
> -                       audio_uart2_utfs_grp0,
> -                       &audio_uart2_utfs_grp0_mux),
> -       FUNCTION("audio_uart2_utfs_m1",
> -                       audio_uart2_utfs_grp1,
> -                       &audio_uart2_utfs_grp1_mux),
> -       FUNCTION("audio_uart2_utfs_m2",
> -                       audio_uart2_utfs_grp2,
> -                       &audio_uart2_utfs_grp2_mux),
> -       FUNCTION("audio_uart2_utxd_m0",
> -                       audio_uart2_utxd_grp0,
> -                       &audio_uart2_utxd_grp0_mux),
> -       FUNCTION("audio_uart2_utxd_m1",
> -                       audio_uart2_utxd_grp1,
> -                       &audio_uart2_utxd_grp1_mux),
> -       FUNCTION("audio_uart2_utxd_m2",
> -                       audio_uart2_utxd_grp2,
> -                       &audio_uart2_utxd_grp2_mux),
> -       FUNCTION("c_can_trnsvr_en_m0",
> -                       c_can_trnsvr_en_grp0,
> -                       &c_can_trnsvr_en_grp0_mux),
> -       FUNCTION("c_can_trnsvr_en_m1",
> -                       c_can_trnsvr_en_grp1,
> -                       &c_can_trnsvr_en_grp1_mux),
> -       FUNCTION("c_can_trnsvr_intr",
> -                       c_can_trnsvr_intr_grp,
> -                       &c_can_trnsvr_intr_grp_mux),
> -       FUNCTION("c_can_trnsvr_stb_n",
> -                       c_can_trnsvr_stb_n_grp,
> -                       &c_can_trnsvr_stb_n_grp_mux),
> -       FUNCTION("c0_can_rxd_trnsv0",
> -                       c0_can_rxd_trnsv0_grp,
> -                       &c0_can_rxd_trnsv0_grp_mux),
> -       FUNCTION("c0_can_rxd_trnsv1",
> -                       c0_can_rxd_trnsv1_grp,
> -                       &c0_can_rxd_trnsv1_grp_mux),
> -       FUNCTION("c0_can_txd_trnsv0",
> -                       c0_can_txd_trnsv0_grp,
> -                       &c0_can_txd_trnsv0_grp_mux),
> -       FUNCTION("c0_can_txd_trnsv1",
> -                       c0_can_txd_trnsv1_grp,
> -                       &c0_can_txd_trnsv1_grp_mux),
> -       FUNCTION("c1_can_rxd_m0", c1_can_rxd_grp0, &c1_can_rxd_grp0_mux),
> -       FUNCTION("c1_can_rxd_m1", c1_can_rxd_grp1, &c1_can_rxd_grp1_mux),
> -       FUNCTION("c1_can_rxd_m2", c1_can_rxd_grp2, &c1_can_rxd_grp2_mux),
> -       FUNCTION("c1_can_rxd_m3", c1_can_rxd_grp3, &c1_can_rxd_grp3_mux),
> -       FUNCTION("c1_can_txd_m0", c1_can_txd_grp0, &c1_can_txd_grp0_mux),
> -       FUNCTION("c1_can_txd_m1", c1_can_txd_grp1, &c1_can_txd_grp1_mux),
> -       FUNCTION("c1_can_txd_m2", c1_can_txd_grp2, &c1_can_txd_grp2_mux),
> -       FUNCTION("c1_can_txd_m3", c1_can_txd_grp3, &c1_can_txd_grp3_mux),
> -       FUNCTION("ca_audio_lpc", ca_audio_lpc_grp, &ca_audio_lpc_grp_mux),
> -       FUNCTION("ca_bt_lpc", ca_bt_lpc_grp, &ca_bt_lpc_grp_mux),
> -       FUNCTION("ca_coex", ca_coex_grp, &ca_coex_grp_mux),
> -       FUNCTION("ca_curator_lpc",
> -                       ca_curator_lpc_grp,
> -                       &ca_curator_lpc_grp_mux),
> -       FUNCTION("ca_pcm_debug", ca_pcm_debug_grp, &ca_pcm_debug_grp_mux),
> -       FUNCTION("ca_pio", ca_pio_grp, &ca_pio_grp_mux),
> -       FUNCTION("ca_sdio_debug", ca_sdio_debug_grp, &ca_sdio_debug_grp_mux),
> -       FUNCTION("ca_spi", ca_spi_grp, &ca_spi_grp_mux),
> -       FUNCTION("ca_trb", ca_trb_grp, &ca_trb_grp_mux),
> -       FUNCTION("ca_uart_debug", ca_uart_debug_grp, &ca_uart_debug_grp_mux),
> -       FUNCTION("clkc_m0", clkc_grp0, &clkc_grp0_mux),
> -       FUNCTION("clkc_m1", clkc_grp1, &clkc_grp1_mux),
> -       FUNCTION("gn_gnss_i2c", gn_gnss_i2c_grp, &gn_gnss_i2c_grp_mux),
> -       FUNCTION("gn_gnss_uart_nopause",
> -                       gn_gnss_uart_nopause_grp,
> -                       &gn_gnss_uart_nopause_grp_mux),
> -       FUNCTION("gn_gnss_uart", gn_gnss_uart_grp, &gn_gnss_uart_grp_mux),
> -       FUNCTION("gn_trg_spi_m0", gn_trg_spi_grp0, &gn_trg_spi_grp0_mux),
> -       FUNCTION("gn_trg_spi_m1", gn_trg_spi_grp1, &gn_trg_spi_grp1_mux),
> -       FUNCTION("cvbs_dbg", cvbs_dbg_grp, &cvbs_dbg_grp_mux),
> -       FUNCTION("cvbs_dbg_test_m0",
> -                       cvbs_dbg_test_grp0,
> -                       &cvbs_dbg_test_grp0_mux),
> -       FUNCTION("cvbs_dbg_test_m1",
> -                       cvbs_dbg_test_grp1,
> -                       &cvbs_dbg_test_grp1_mux),
> -       FUNCTION("cvbs_dbg_test_m2",
> -                       cvbs_dbg_test_grp2,
> -                       &cvbs_dbg_test_grp2_mux),
> -       FUNCTION("cvbs_dbg_test_m3",
> -                       cvbs_dbg_test_grp3,
> -                       &cvbs_dbg_test_grp3_mux),
> -       FUNCTION("cvbs_dbg_test_m4",
> -                       cvbs_dbg_test_grp4,
> -                       &cvbs_dbg_test_grp4_mux),
> -       FUNCTION("cvbs_dbg_test_m5",
> -                       cvbs_dbg_test_grp5,
> -                       &cvbs_dbg_test_grp5_mux),
> -       FUNCTION("cvbs_dbg_test_m6",
> -                       cvbs_dbg_test_grp6,
> -                       &cvbs_dbg_test_grp6_mux),
> -       FUNCTION("cvbs_dbg_test_m7",
> -                       cvbs_dbg_test_grp7,
> -                       &cvbs_dbg_test_grp7_mux),
> -       FUNCTION("cvbs_dbg_test_m8",
> -                       cvbs_dbg_test_grp8,
> -                       &cvbs_dbg_test_grp8_mux),
> -       FUNCTION("cvbs_dbg_test_m9",
> -                       cvbs_dbg_test_grp9,
> -                       &cvbs_dbg_test_grp9_mux),
> -       FUNCTION("cvbs_dbg_test_m10",
> -                       cvbs_dbg_test_grp10,
> -                       &cvbs_dbg_test_grp10_mux),
> -       FUNCTION("cvbs_dbg_test_m11",
> -                       cvbs_dbg_test_grp11,
> -                       &cvbs_dbg_test_grp11_mux),
> -       FUNCTION("cvbs_dbg_test_m12",
> -                       cvbs_dbg_test_grp12,
> -                       &cvbs_dbg_test_grp12_mux),
> -       FUNCTION("cvbs_dbg_test_m13",
> -                       cvbs_dbg_test_grp13,
> -                       &cvbs_dbg_test_grp13_mux),
> -       FUNCTION("cvbs_dbg_test_m14",
> -                       cvbs_dbg_test_grp14,
> -                       &cvbs_dbg_test_grp14_mux),
> -       FUNCTION("cvbs_dbg_test_m15",
> -                       cvbs_dbg_test_grp15,
> -                       &cvbs_dbg_test_grp15_mux),
> -       FUNCTION("gn_gnss_power", gn_gnss_power_grp, &gn_gnss_power_grp_mux),
> -       FUNCTION("gn_gnss_sw_status",
> -                       gn_gnss_sw_status_grp,
> -                       &gn_gnss_sw_status_grp_mux),
> -       FUNCTION("gn_gnss_eclk", gn_gnss_eclk_grp, &gn_gnss_eclk_grp_mux),
> -       FUNCTION("gn_gnss_irq1_m0",
> -                       gn_gnss_irq1_grp0,
> -                       &gn_gnss_irq1_grp0_mux),
> -       FUNCTION("gn_gnss_irq2_m0",
> -                       gn_gnss_irq2_grp0,
> -                       &gn_gnss_irq2_grp0_mux),
> -       FUNCTION("gn_gnss_tm", gn_gnss_tm_grp, &gn_gnss_tm_grp_mux),
> -       FUNCTION("gn_gnss_tsync", gn_gnss_tsync_grp, &gn_gnss_tsync_grp_mux),
> -       FUNCTION("gn_io_gnsssys_sw_cfg",
> -                       gn_io_gnsssys_sw_cfg_grp,
> -                       &gn_io_gnsssys_sw_cfg_grp_mux),
> -       FUNCTION("gn_trg_m0", gn_trg_grp0, &gn_trg_grp0_mux),
> -       FUNCTION("gn_trg_m1", gn_trg_grp1, &gn_trg_grp1_mux),
> -       FUNCTION("gn_trg_shutdown_m0",
> -                       gn_trg_shutdown_grp0,
> -                       &gn_trg_shutdown_grp0_mux),
> -       FUNCTION("gn_trg_shutdown_m1",
> -                       gn_trg_shutdown_grp1,
> -                       &gn_trg_shutdown_grp1_mux),
> -       FUNCTION("gn_trg_shutdown_m2",
> -                       gn_trg_shutdown_grp2,
> -                       &gn_trg_shutdown_grp2_mux),
> -       FUNCTION("gn_trg_shutdown_m3",
> -                       gn_trg_shutdown_grp3,
> -                       &gn_trg_shutdown_grp3_mux),
> -       FUNCTION("i2c0", i2c0_grp, &i2c0_grp_mux),
> -       FUNCTION("i2c1", i2c1_grp, &i2c1_grp_mux),
> -       FUNCTION("i2s0", i2s0_grp, &i2s0_grp_mux),
> -       FUNCTION("i2s1_basic", i2s1_basic_grp, &i2s1_basic_grp_mux),
> -       FUNCTION("i2s1_rxd0_m0", i2s1_rxd0_grp0, &i2s1_rxd0_grp0_mux),
> -       FUNCTION("i2s1_rxd0_m1", i2s1_rxd0_grp1, &i2s1_rxd0_grp1_mux),
> -       FUNCTION("i2s1_rxd0_m2", i2s1_rxd0_grp2, &i2s1_rxd0_grp2_mux),
> -       FUNCTION("i2s1_rxd0_m3", i2s1_rxd0_grp3, &i2s1_rxd0_grp3_mux),
> -       FUNCTION("i2s1_rxd0_m4", i2s1_rxd0_grp4, &i2s1_rxd0_grp4_mux),
> -       FUNCTION("i2s1_rxd1_m0", i2s1_rxd1_grp0, &i2s1_rxd1_grp0_mux),
> -       FUNCTION("i2s1_rxd1_m1", i2s1_rxd1_grp1, &i2s1_rxd1_grp1_mux),
> -       FUNCTION("i2s1_rxd1_m2", i2s1_rxd1_grp2, &i2s1_rxd1_grp2_mux),
> -       FUNCTION("i2s1_rxd1_m3", i2s1_rxd1_grp3, &i2s1_rxd1_grp3_mux),
> -       FUNCTION("i2s1_rxd1_m4", i2s1_rxd1_grp4, &i2s1_rxd1_grp4_mux),
> -       FUNCTION("jtag_jt_dbg_nsrst",
> -                       jtag_jt_dbg_nsrst_grp,
> -                       &jtag_jt_dbg_nsrst_grp_mux),
> -       FUNCTION("jtag_ntrst_m0", jtag_ntrst_grp0, &jtag_ntrst_grp0_mux),
> -       FUNCTION("jtag_ntrst_m1", jtag_ntrst_grp1, &jtag_ntrst_grp1_mux),
> -       FUNCTION("jtag_swdiotms_m0",
> -                       jtag_swdiotms_grp0,
> -                       &jtag_swdiotms_grp0_mux),
> -       FUNCTION("jtag_swdiotms_m1",
> -                       jtag_swdiotms_grp1,
> -                       &jtag_swdiotms_grp1_mux),
> -       FUNCTION("jtag_tck_m0", jtag_tck_grp0, &jtag_tck_grp0_mux),
> -       FUNCTION("jtag_tck_m1", jtag_tck_grp1, &jtag_tck_grp1_mux),
> -       FUNCTION("jtag_tdi_m0", jtag_tdi_grp0, &jtag_tdi_grp0_mux),
> -       FUNCTION("jtag_tdi_m1", jtag_tdi_grp1, &jtag_tdi_grp1_mux),
> -       FUNCTION("jtag_tdo_m0", jtag_tdo_grp0, &jtag_tdo_grp0_mux),
> -       FUNCTION("jtag_tdo_m1", jtag_tdo_grp1, &jtag_tdo_grp1_mux),
> -       FUNCTION("ks_kas_spi_m0", ks_kas_spi_grp0, &ks_kas_spi_grp0_mux),
> -       FUNCTION("ld_ldd", ld_ldd_grp, &ld_ldd_grp_mux),
> -       FUNCTION("ld_ldd_16bit", ld_ldd_16bit_grp, &ld_ldd_16bit_grp_mux),
> -       FUNCTION("ld_ldd_fck", ld_ldd_fck_grp, &ld_ldd_fck_grp_mux),
> -       FUNCTION("ld_ldd_lck", ld_ldd_lck_grp, &ld_ldd_lck_grp_mux),
> -       FUNCTION("lr_lcdrom", lr_lcdrom_grp, &lr_lcdrom_grp_mux),
> -       FUNCTION("lvds_analog", lvds_analog_grp, &lvds_analog_grp_mux),
> -       FUNCTION("nd_df_basic", nd_df_basic_grp, &nd_df_basic_grp_mux),
> -       FUNCTION("nd_df_wp", nd_df_wp_grp, &nd_df_wp_grp_mux),
> -       FUNCTION("nd_df_cs", nd_df_cs_grp, &nd_df_cs_grp_mux),
> -       FUNCTION("ps", ps_grp, &ps_grp_mux),
> -       FUNCTION("ps_no_dir", ps_no_dir_grp, &ps_no_dir_grp_mux),
> -       FUNCTION("pwc_core_on", pwc_core_on_grp, &pwc_core_on_grp_mux),
> -       FUNCTION("pwc_ext_on", pwc_ext_on_grp, &pwc_ext_on_grp_mux),
> -       FUNCTION("pwc_gpio3_clk", pwc_gpio3_clk_grp, &pwc_gpio3_clk_grp_mux),
> -       FUNCTION("pwc_io_on", pwc_io_on_grp, &pwc_io_on_grp_mux),
> -       FUNCTION("pwc_lowbatt_b_m0",
> -                       pwc_lowbatt_b_grp0,
> -                       &pwc_lowbatt_b_grp0_mux),
> -       FUNCTION("pwc_mem_on", pwc_mem_on_grp, &pwc_mem_on_grp_mux),
> -       FUNCTION("pwc_on_key_b_m0",
> -                       pwc_on_key_b_grp0,
> -                       &pwc_on_key_b_grp0_mux),
> -       FUNCTION("pwc_wakeup_src0",
> -                       pwc_wakeup_src0_grp,
> -                       &pwc_wakeup_src0_grp_mux),
> -       FUNCTION("pwc_wakeup_src1",
> -                       pwc_wakeup_src1_grp,
> -                       &pwc_wakeup_src1_grp_mux),
> -       FUNCTION("pwc_wakeup_src2",
> -                       pwc_wakeup_src2_grp,
> -                       &pwc_wakeup_src2_grp_mux),
> -       FUNCTION("pwc_wakeup_src3",
> -                       pwc_wakeup_src3_grp,
> -                       &pwc_wakeup_src3_grp_mux),
> -       FUNCTION("pw_cko0_m0", pw_cko0_grp0, &pw_cko0_grp0_mux),
> -       FUNCTION("pw_cko0_m1", pw_cko0_grp1, &pw_cko0_grp1_mux),
> -       FUNCTION("pw_cko0_m2", pw_cko0_grp2, &pw_cko0_grp2_mux),
> -       FUNCTION("pw_cko0_m3", pw_cko0_grp3, &pw_cko0_grp3_mux),
> -       FUNCTION("pw_cko1_m0", pw_cko1_grp0, &pw_cko1_grp0_mux),
> -       FUNCTION("pw_cko1_m1", pw_cko1_grp1, &pw_cko1_grp1_mux),
> -       FUNCTION("pw_cko1_m2", pw_cko1_grp2, &pw_cko1_grp2_mux),
> -       FUNCTION("pw_i2s01_clk_m0",
> -                       pw_i2s01_clk_grp0,
> -                       &pw_i2s01_clk_grp0_mux),
> -       FUNCTION("pw_i2s01_clk_m1",
> -                       pw_i2s01_clk_grp1,
> -                       &pw_i2s01_clk_grp1_mux),
> -       FUNCTION("pw_i2s01_clk_m2",
> -                       pw_i2s01_clk_grp2,
> -                       &pw_i2s01_clk_grp2_mux),
> -       FUNCTION("pw_pwm0_m0", pw_pwm0_grp0, &pw_pwm0_grp0_mux),
> -       FUNCTION("pw_pwm0_m1", pw_pwm0_grp1, &pw_pwm0_grp1_mux),
> -       FUNCTION("pw_pwm1_m0", pw_pwm1_grp0, &pw_pwm1_grp0_mux),
> -       FUNCTION("pw_pwm1_m1", pw_pwm1_grp1, &pw_pwm1_grp1_mux),
> -       FUNCTION("pw_pwm1_m2", pw_pwm1_grp2, &pw_pwm1_grp2_mux),
> -       FUNCTION("pw_pwm2_m0", pw_pwm2_grp0, &pw_pwm2_grp0_mux),
> -       FUNCTION("pw_pwm2_m1", pw_pwm2_grp1, &pw_pwm2_grp1_mux),
> -       FUNCTION("pw_pwm2_m2", pw_pwm2_grp2, &pw_pwm2_grp2_mux),
> -       FUNCTION("pw_pwm3_m0", pw_pwm3_grp0, &pw_pwm3_grp0_mux),
> -       FUNCTION("pw_pwm3_m1", pw_pwm3_grp1, &pw_pwm3_grp1_mux),
> -       FUNCTION("pw_pwm_cpu_vol_m0",
> -                       pw_pwm_cpu_vol_grp0,
> -                       &pw_pwm_cpu_vol_grp0_mux),
> -       FUNCTION("pw_pwm_cpu_vol_m1",
> -                       pw_pwm_cpu_vol_grp1,
> -                       &pw_pwm_cpu_vol_grp1_mux),
> -       FUNCTION("pw_pwm_cpu_vol_m2",
> -                       pw_pwm_cpu_vol_grp2,
> -                       &pw_pwm_cpu_vol_grp2_mux),
> -       FUNCTION("pw_backlight_m0",
> -                       pw_backlight_grp0,
> -                       &pw_backlight_grp0_mux),
> -       FUNCTION("pw_backlight_m1",
> -                       pw_backlight_grp1,
> -                       &pw_backlight_grp1_mux),
> -       FUNCTION("rg_eth_mac", rg_eth_mac_grp, &rg_eth_mac_grp_mux),
> -       FUNCTION("rg_gmac_phy_intr_n",
> -                       rg_gmac_phy_intr_n_grp,
> -                       &rg_gmac_phy_intr_n_grp_mux),
> -       FUNCTION("rg_rgmii_mac", rg_rgmii_mac_grp, &rg_rgmii_mac_grp_mux),
> -       FUNCTION("rg_rgmii_phy_ref_clk_m0",
> -                       rg_rgmii_phy_ref_clk_grp0,
> -                       &rg_rgmii_phy_ref_clk_grp0_mux),
> -       FUNCTION("rg_rgmii_phy_ref_clk_m1",
> -                       rg_rgmii_phy_ref_clk_grp1,
> -                       &rg_rgmii_phy_ref_clk_grp1_mux),
> -       FUNCTION("sd0", sd0_grp, &sd0_grp_mux),
> -       FUNCTION("sd0_4bit", sd0_4bit_grp, &sd0_4bit_grp_mux),
> -       FUNCTION("sd1", sd1_grp, &sd1_grp_mux),
> -       FUNCTION("sd1_4bit_m0", sd1_4bit_grp0, &sd1_4bit_grp0_mux),
> -       FUNCTION("sd1_4bit_m1", sd1_4bit_grp1, &sd1_4bit_grp1_mux),
> -       FUNCTION("sd2_basic", sd2_basic_grp, &sd2_basic_grp_mux),
> -       FUNCTION("sd2_cdb_m0", sd2_cdb_grp0, &sd2_cdb_grp0_mux),
> -       FUNCTION("sd2_cdb_m1", sd2_cdb_grp1, &sd2_cdb_grp1_mux),
> -       FUNCTION("sd2_wpb_m0", sd2_wpb_grp0, &sd2_wpb_grp0_mux),
> -       FUNCTION("sd2_wpb_m1", sd2_wpb_grp1, &sd2_wpb_grp1_mux),
> -       FUNCTION("sd3", sd3_9_grp, &sd3_9_grp_mux),
> -       FUNCTION("sd5", sd5_grp, &sd5_grp_mux),
> -       FUNCTION("sd6_m0", sd6_grp0, &sd6_grp0_mux),
> -       FUNCTION("sd6_m1", sd6_grp1, &sd6_grp1_mux),
> -       FUNCTION("sd9", sd3_9_grp, &sd3_9_grp_mux),
> -       FUNCTION("sp0_ext_ldo_on",
> -                       sp0_ext_ldo_on_grp,
> -                       &sp0_ext_ldo_on_grp_mux),
> -       FUNCTION("sp0_qspi", sp0_qspi_grp, &sp0_qspi_grp_mux),
> -       FUNCTION("sp1_spi", sp1_spi_grp, &sp1_spi_grp_mux),
> -       FUNCTION("tpiu_trace", tpiu_trace_grp, &tpiu_trace_grp_mux),
> -       FUNCTION("uart0", uart0_grp, &uart0_grp_mux),
> -       FUNCTION("uart0_nopause", uart0_nopause_grp, &uart0_nopause_grp_mux),
> -       FUNCTION("uart1", uart1_grp, &uart1_grp_mux),
> -       FUNCTION("uart2_cts_m0", uart2_cts_grp0, &uart2_cts_grp0_mux),
> -       FUNCTION("uart2_cts_m1", uart2_cts_grp1, &uart2_cts_grp1_mux),
> -       FUNCTION("uart2_rts_m0", uart2_rts_grp0, &uart2_rts_grp0_mux),
> -       FUNCTION("uart2_rts_m1", uart2_rts_grp1, &uart2_rts_grp1_mux),
> -       FUNCTION("uart2_rxd_m0", uart2_rxd_grp0, &uart2_rxd_grp0_mux),
> -       FUNCTION("uart2_rxd_m1", uart2_rxd_grp1, &uart2_rxd_grp1_mux),
> -       FUNCTION("uart2_rxd_m2", uart2_rxd_grp2, &uart2_rxd_grp2_mux),
> -       FUNCTION("uart2_txd_m0", uart2_txd_grp0, &uart2_txd_grp0_mux),
> -       FUNCTION("uart2_txd_m1", uart2_txd_grp1, &uart2_txd_grp1_mux),
> -       FUNCTION("uart2_txd_m2", uart2_txd_grp2, &uart2_txd_grp2_mux),
> -       FUNCTION("uart3_cts_m0", uart3_cts_grp0, &uart3_cts_grp0_mux),
> -       FUNCTION("uart3_cts_m1", uart3_cts_grp1, &uart3_cts_grp1_mux),
> -       FUNCTION("uart3_cts_m2", uart3_cts_grp2, &uart3_cts_grp2_mux),
> -       FUNCTION("uart3_rts_m0", uart3_rts_grp0, &uart3_rts_grp0_mux),
> -       FUNCTION("uart3_rts_m1", uart3_rts_grp1, &uart3_rts_grp1_mux),
> -       FUNCTION("uart3_rts_m2", uart3_rts_grp2, &uart3_rts_grp2_mux),
> -       FUNCTION("uart3_rxd_m0", uart3_rxd_grp0, &uart3_rxd_grp0_mux),
> -       FUNCTION("uart3_rxd_m1", uart3_rxd_grp1, &uart3_rxd_grp1_mux),
> -       FUNCTION("uart3_rxd_m2", uart3_rxd_grp2, &uart3_rxd_grp2_mux),
> -       FUNCTION("uart3_txd_m0", uart3_txd_grp0, &uart3_txd_grp0_mux),
> -       FUNCTION("uart3_txd_m1", uart3_txd_grp1, &uart3_txd_grp1_mux),
> -       FUNCTION("uart3_txd_m2", uart3_txd_grp2, &uart3_txd_grp2_mux),
> -       FUNCTION("uart4_basic", uart4_basic_grp, &uart4_basic_grp_mux),
> -       FUNCTION("uart4_cts_m0", uart4_cts_grp0, &uart4_cts_grp0_mux),
> -       FUNCTION("uart4_cts_m1", uart4_cts_grp1, &uart4_cts_grp1_mux),
> -       FUNCTION("uart4_cts_m2", uart4_cts_grp2, &uart4_cts_grp2_mux),
> -       FUNCTION("uart4_rts_m0", uart4_rts_grp0, &uart4_rts_grp0_mux),
> -       FUNCTION("uart4_rts_m1", uart4_rts_grp1, &uart4_rts_grp1_mux),
> -       FUNCTION("uart4_rts_m2", uart4_rts_grp2, &uart4_rts_grp2_mux),
> -       FUNCTION("usb0_drvvbus_m0",
> -                       usb0_drvvbus_grp0,
> -                       &usb0_drvvbus_grp0_mux),
> -       FUNCTION("usb0_drvvbus_m1",
> -                       usb0_drvvbus_grp1,
> -                       &usb0_drvvbus_grp1_mux),
> -       FUNCTION("usb1_drvvbus_m0",
> -                       usb1_drvvbus_grp0,
> -                       &usb1_drvvbus_grp0_mux),
> -       FUNCTION("usb1_drvvbus_m1",
> -                       usb1_drvvbus_grp1,
> -                       &usb1_drvvbus_grp1_mux),
> -       FUNCTION("visbus_dout", visbus_dout_grp, &visbus_dout_grp_mux),
> -       FUNCTION("vi_vip1", vi_vip1_grp, &vi_vip1_grp_mux),
> -       FUNCTION("vi_vip1_ext", vi_vip1_ext_grp, &vi_vip1_ext_grp_mux),
> -       FUNCTION("vi_vip1_low8bit",
> -                       vi_vip1_low8bit_grp,
> -                       &vi_vip1_low8bit_grp_mux),
> -       FUNCTION("vi_vip1_high8bit",
> -                       vi_vip1_high8bit_grp,
> -                       &vi_vip1_high8bit_grp_mux),
> -};
> -
> -static struct atlas7_pinctrl_data atlas7_ioc_data = {
> -       .pads = (struct pinctrl_pin_desc *)atlas7_ioc_pads,
> -       .pads_cnt = ARRAY_SIZE(atlas7_ioc_pads),
> -       .grps = (struct atlas7_pin_group *)altas7_pin_groups,
> -       .grps_cnt = ARRAY_SIZE(altas7_pin_groups),
> -       .funcs = (struct atlas7_pmx_func *)atlas7_pmx_functions,
> -       .funcs_cnt = ARRAY_SIZE(atlas7_pmx_functions),
> -       .confs = (struct atlas7_pad_config *)atlas7_ioc_pad_confs,
> -       .confs_cnt = ARRAY_SIZE(atlas7_ioc_pad_confs),
> -};
> -
> -/* Simple map data structure */
> -struct map_data {
> -       u8 idx;
> -       u8 data;
> -};
> -
> -/**
> - * struct atlas7_pull_info - Atlas7 Pad pull info
> - * @pad_type:  The type of this Pad.
> - * @mask:      The mas value of this pin's pull bits.
> - * @v2s:       The map of pull register value to pull status.
> - * @s2v:       The map of pull status to pull register value.
> - */
> -struct atlas7_pull_info {
> -       u8 pad_type;
> -       u8 mask;
> -       const struct map_data *v2s;
> -       const struct map_data *s2v;
> -};
> -
> -/* Pull Register value map to status */
> -static const struct map_data p4we_pull_v2s[] = {
> -       { P4WE_PULL_UP, PULL_UP },
> -       { P4WE_HIGH_HYSTERESIS, HIGH_HYSTERESIS },
> -       { P4WE_HIGH_Z, HIGH_Z },
> -       { P4WE_PULL_DOWN, PULL_DOWN },
> -};
> -
> -static const struct map_data p16st_pull_v2s[] = {
> -       { P16ST_PULL_UP, PULL_UP },
> -       { PD, PULL_UNKNOWN },
> -       { P16ST_HIGH_Z, HIGH_Z },
> -       { P16ST_PULL_DOWN, PULL_DOWN },
> -};
> -
> -static const struct map_data pm31_pull_v2s[] = {
> -       { PM31_PULL_DISABLED, PULL_DOWN },
> -       { PM31_PULL_ENABLED, PULL_UP },
> -};
> -
> -static const struct map_data pangd_pull_v2s[] = {
> -       { PANGD_PULL_UP, PULL_UP },
> -       { PD, PULL_UNKNOWN },
> -       { PANGD_HIGH_Z, HIGH_Z },
> -       { PANGD_PULL_DOWN, PULL_DOWN },
> -};
> -
> -/* Pull status map to register value */
> -static const struct map_data p4we_pull_s2v[] = {
> -       { PULL_UP, P4WE_PULL_UP },
> -       { HIGH_HYSTERESIS, P4WE_HIGH_HYSTERESIS },
> -       { HIGH_Z, P4WE_HIGH_Z },
> -       { PULL_DOWN, P4WE_PULL_DOWN },
> -       { PULL_DISABLE, -1 },
> -       { PULL_ENABLE, -1 },
> -};
> -
> -static const struct map_data p16st_pull_s2v[] = {
> -       { PULL_UP, P16ST_PULL_UP },
> -       { HIGH_HYSTERESIS, -1 },
> -       { HIGH_Z, P16ST_HIGH_Z },
> -       { PULL_DOWN, P16ST_PULL_DOWN },
> -       { PULL_DISABLE, -1 },
> -       { PULL_ENABLE, -1 },
> -};
> -
> -static const struct map_data pm31_pull_s2v[] = {
> -       { PULL_UP, PM31_PULL_ENABLED },
> -       { HIGH_HYSTERESIS, -1 },
> -       { HIGH_Z, -1 },
> -       { PULL_DOWN, PM31_PULL_DISABLED },
> -       { PULL_DISABLE, -1 },
> -       { PULL_ENABLE, -1 },
> -};
> -
> -static const struct map_data pangd_pull_s2v[] = {
> -       { PULL_UP, PANGD_PULL_UP },
> -       { HIGH_HYSTERESIS, -1 },
> -       { HIGH_Z, PANGD_HIGH_Z },
> -       { PULL_DOWN, PANGD_PULL_DOWN },
> -       { PULL_DISABLE, -1 },
> -       { PULL_ENABLE, -1 },
> -};
> -
> -static const struct atlas7_pull_info atlas7_pull_map[] = {
> -       { PAD_T_4WE_PD, P4WE_PULL_MASK, p4we_pull_v2s, p4we_pull_s2v },
> -       { PAD_T_4WE_PU, P4WE_PULL_MASK, p4we_pull_v2s, p4we_pull_s2v },
> -       { PAD_T_16ST, P16ST_PULL_MASK, p16st_pull_v2s, p16st_pull_s2v },
> -       { PAD_T_M31_0204_PD, PM31_PULL_MASK, pm31_pull_v2s, pm31_pull_s2v },
> -       { PAD_T_M31_0204_PU, PM31_PULL_MASK, pm31_pull_v2s, pm31_pull_s2v },
> -       { PAD_T_M31_0610_PD, PM31_PULL_MASK, pm31_pull_v2s, pm31_pull_s2v },
> -       { PAD_T_M31_0610_PU, PM31_PULL_MASK, pm31_pull_v2s, pm31_pull_s2v },
> -       { PAD_T_AD, PANGD_PULL_MASK, pangd_pull_v2s, pangd_pull_s2v },
> -};
> -
> -/**
> - * struct atlas7_ds_ma_info - Atlas7 Pad DriveStrength & currents info
> - * @ma:                The Drive Strength in current value .
> - * @ds_16st:   The correspond raw value of 16st pad.
> - * @ds_4we:    The correspond raw value of 4we pad.
> - * @ds_0204m31:        The correspond raw value of 0204m31 pad.
> - * @ds_0610m31:        The correspond raw value of 0610m31 pad.
> - */
> -struct atlas7_ds_ma_info {
> -       u32 ma;
> -       u32 ds_16st;
> -       u32 ds_4we;
> -       u32 ds_0204m31;
> -       u32 ds_0610m31;
> -};
> -
> -static const struct atlas7_ds_ma_info atlas7_ma2ds_map[] = {
> -       { 2, DS_16ST_0, DS_4WE_0, DS_M31_0, DS_NULL },
> -       { 4, DS_16ST_1, DS_NULL, DS_M31_1, DS_NULL },
> -       { 6, DS_16ST_2, DS_NULL, DS_NULL, DS_M31_0 },
> -       { 8, DS_16ST_3, DS_4WE_1, DS_NULL, DS_NULL },
> -       { 10, DS_16ST_4, DS_NULL, DS_NULL, DS_M31_1 },
> -       { 12, DS_16ST_5, DS_NULL, DS_NULL, DS_NULL },
> -       { 14, DS_16ST_6, DS_NULL, DS_NULL, DS_NULL },
> -       { 16, DS_16ST_7, DS_4WE_2, DS_NULL, DS_NULL },
> -       { 18, DS_16ST_8, DS_NULL, DS_NULL, DS_NULL },
> -       { 20, DS_16ST_9, DS_NULL, DS_NULL, DS_NULL },
> -       { 22, DS_16ST_10, DS_NULL, DS_NULL, DS_NULL },
> -       { 24, DS_16ST_11, DS_NULL, DS_NULL, DS_NULL },
> -       { 26, DS_16ST_12, DS_NULL, DS_NULL, DS_NULL },
> -       { 28, DS_16ST_13, DS_4WE_3, DS_NULL, DS_NULL },
> -       { 30, DS_16ST_14, DS_NULL, DS_NULL, DS_NULL },
> -       { 32, DS_16ST_15, DS_NULL, DS_NULL, DS_NULL },
> -};
> -
> -/**
> - * struct atlas7_ds_info - Atlas7 Pad DriveStrength info
> - * @type:              The type of this Pad.
> - * @mask:              The mask value of this pin's pull bits.
> - * @imval:             The immediate value of drives trength register.
> - * @reserved:          Reserved space
> - */
> -struct atlas7_ds_info {
> -       u8 type;
> -       u8 mask;
> -       u8 imval;
> -       u8 reserved;
> -};
> -
> -static const struct atlas7_ds_info atlas7_ds_map[] = {
> -       { PAD_T_4WE_PD, DS_2BIT_MASK, DS_2BIT_IM_VAL },
> -       { PAD_T_4WE_PU, DS_2BIT_MASK, DS_2BIT_IM_VAL },
> -       { PAD_T_16ST, DS_4BIT_MASK, DS_4BIT_IM_VAL },
> -       { PAD_T_M31_0204_PD, DS_1BIT_MASK, DS_1BIT_IM_VAL },
> -       { PAD_T_M31_0204_PU, DS_1BIT_MASK, DS_1BIT_IM_VAL },
> -       { PAD_T_M31_0610_PD, DS_1BIT_MASK, DS_1BIT_IM_VAL },
> -       { PAD_T_M31_0610_PU, DS_1BIT_MASK, DS_1BIT_IM_VAL },
> -       { PAD_T_AD, DS_NULL, DS_NULL },
> -};
> -
> -static inline u32 atlas7_pin_to_bank(u32 pin)
> -{
> -       return (pin >= ATLAS7_PINCTRL_BANK_0_PINS) ? 1 : 0;
> -}
> -
> -static int atlas7_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
> -{
> -       struct atlas7_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
> -
> -       return pmx->pctl_data->funcs_cnt;
> -}
> -
> -static const char *atlas7_pmx_get_func_name(struct pinctrl_dev *pctldev,
> -                                       u32 selector)
> -{
> -       struct atlas7_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
> -
> -       return pmx->pctl_data->funcs[selector].name;
> -}
> -
> -static int atlas7_pmx_get_func_groups(struct pinctrl_dev *pctldev,
> -               u32 selector, const char * const **groups,
> -               u32 * const num_groups)
> -{
> -       struct atlas7_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
> -
> -       *groups = pmx->pctl_data->funcs[selector].groups;
> -       *num_groups = pmx->pctl_data->funcs[selector].num_groups;
> -
> -       return 0;
> -}
> -
> -static void __atlas7_pmx_pin_input_disable_set(struct atlas7_pmx *pmx,
> -                               const struct atlas7_pad_mux *mux)
> -{
> -       /* Set Input Disable to avoid input glitches
> -        *
> -        * All Input-Disable Control registers are located on IOCRTC.
> -        * So the regs bank is always 0.
> -        *
> -        */
> -       if (mux->dinput_reg && mux->dinput_val_reg) {
> -               writel(DI_MASK << mux->dinput_bit,
> -                       pmx->regs[BANK_DS] + CLR_REG(mux->dinput_reg));
> -               writel(DI_DISABLE << mux->dinput_bit,
> -                       pmx->regs[BANK_DS] + mux->dinput_reg);
> -
> -
> -               writel(DIV_MASK << mux->dinput_val_bit,
> -                       pmx->regs[BANK_DS] + CLR_REG(mux->dinput_val_reg));
> -               writel(DIV_DISABLE << mux->dinput_val_bit,
> -                       pmx->regs[BANK_DS] + mux->dinput_val_reg);
> -       }
> -}
> -
> -static void __atlas7_pmx_pin_input_disable_clr(struct atlas7_pmx *pmx,
> -                               const struct atlas7_pad_mux *mux)
> -{
> -       /* Clear Input Disable to avoid input glitches */
> -       if (mux->dinput_reg && mux->dinput_val_reg) {
> -               writel(DI_MASK << mux->dinput_bit,
> -                       pmx->regs[BANK_DS] + CLR_REG(mux->dinput_reg));
> -               writel(DI_ENABLE << mux->dinput_bit,
> -                       pmx->regs[BANK_DS] + mux->dinput_reg);
> -
> -               writel(DIV_MASK << mux->dinput_val_bit,
> -                       pmx->regs[BANK_DS] + CLR_REG(mux->dinput_val_reg));
> -               writel(DIV_ENABLE << mux->dinput_val_bit,
> -                       pmx->regs[BANK_DS] + mux->dinput_val_reg);
> -       }
> -}
> -
> -static int __atlas7_pmx_pin_ad_sel(struct atlas7_pmx *pmx,
> -                       struct atlas7_pad_config *conf,
> -                       u32 bank, u32 ad_sel)
> -{
> -       unsigned long regv;
> -
> -       /* Write to clear register to clear A/D selector */
> -       writel(ANA_CLEAR_MASK << conf->ad_ctrl_bit,
> -               pmx->regs[bank] + CLR_REG(conf->ad_ctrl_reg));
> -
> -       /* Set target pad A/D selector */
> -       regv = readl(pmx->regs[bank] + conf->ad_ctrl_reg);
> -       regv &= ~(ANA_CLEAR_MASK << conf->ad_ctrl_bit);
> -       writel(regv | (ad_sel << conf->ad_ctrl_bit),
> -                       pmx->regs[bank] + conf->ad_ctrl_reg);
> -
> -       regv = readl(pmx->regs[bank] + conf->ad_ctrl_reg);
> -       pr_debug("bank:%d reg:0x%04x val:0x%08lx\n",
> -                       bank, conf->ad_ctrl_reg, regv);
> -       return 0;
> -}
> -
> -static int  __atlas7_pmx_pin_analog_enable(struct atlas7_pmx *pmx,
> -                       struct atlas7_pad_config *conf, u32 bank)
> -{
> -       /* Only PAD_T_AD pins can change between Analogue&Digital */
> -       if (conf->type != PAD_T_AD)
> -               return -EINVAL;
> -
> -       return __atlas7_pmx_pin_ad_sel(pmx, conf, bank, 0);
> -}
> -
> -static int __atlas7_pmx_pin_digital_enable(struct atlas7_pmx *pmx,
> -                       struct atlas7_pad_config *conf, u32 bank)
> -{
> -       /* Other type pads are always digital */
> -       if (conf->type != PAD_T_AD)
> -               return 0;
> -
> -       return __atlas7_pmx_pin_ad_sel(pmx, conf, bank, 1);
> -}
> -
> -static int __atlas7_pmx_pin_enable(struct atlas7_pmx *pmx,
> -                               u32 pin, u32 func)
> -{
> -       struct atlas7_pad_config *conf;
> -       u32 bank;
> -       int ret;
> -       unsigned long regv;
> -
> -       pr_debug("PMX DUMP ### pin#%d func:%d #### START >>>\n",
> -                       pin, func);
> -
> -       /* Get this Pad's descriptor from PINCTRL */
> -       conf = &pmx->pctl_data->confs[pin];
> -       bank = atlas7_pin_to_bank(pin);
> -
> -       /* Just enable the analog function of this pad */
> -       if (FUNC_ANALOGUE == func) {
> -               ret = __atlas7_pmx_pin_analog_enable(pmx, conf, bank);
> -               if (ret)
> -                       dev_err(pmx->dev,
> -                               "Convert pad#%d to analog failed, ret=%d\n",
> -                               pin, ret);
> -               return ret;
> -       }
> -
> -       /* Set Pads from analog to digital */
> -       ret = __atlas7_pmx_pin_digital_enable(pmx, conf, bank);
> -       if (ret) {
> -               dev_err(pmx->dev,
> -                       "Convert pad#%d to digital failed, ret=%d\n",
> -                       pin, ret);
> -               return ret;
> -       }
> -
> -       /* Write to clear register to clear current function */
> -       writel(FUNC_CLEAR_MASK << conf->mux_bit,
> -               pmx->regs[bank] + CLR_REG(conf->mux_reg));
> -
> -       /* Set target pad mux function */
> -       regv = readl(pmx->regs[bank] + conf->mux_reg);
> -       regv &= ~(FUNC_CLEAR_MASK << conf->mux_bit);
> -       writel(regv | (func << conf->mux_bit),
> -                       pmx->regs[bank] + conf->mux_reg);
> -
> -       regv = readl(pmx->regs[bank] + conf->mux_reg);
> -       pr_debug("bank:%d reg:0x%04x val:0x%08lx\n",
> -               bank, conf->mux_reg, regv);
> -
> -       return 0;
> -}
> -
> -static int atlas7_pmx_set_mux(struct pinctrl_dev *pctldev,
> -                       u32 func_selector, u32 group_selector)
> -{
> -       int idx, ret;
> -       struct atlas7_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
> -       struct atlas7_pmx_func *pmx_func;
> -       struct atlas7_pin_group *pin_grp;
> -       const struct atlas7_grp_mux *grp_mux;
> -       const struct atlas7_pad_mux *mux;
> -
> -       pmx_func = &pmx->pctl_data->funcs[func_selector];
> -       pin_grp = &pmx->pctl_data->grps[group_selector];
> -
> -       pr_debug("PMX DUMP ### Function:[%s] Group:[%s] #### START >>>\n",
> -                       pmx_func->name, pin_grp->name);
> -
> -       /* the sd3 and sd9 pin select by SYS2PCI_SDIO9SEL register */
> -       if (pin_grp->pins == (unsigned int *)&sd3_9_pins) {
> -               if (!strcmp(pmx_func->name, "sd9"))
> -                       writel(1, pmx->sys2pci_base + SYS2PCI_SDIO9SEL);
> -               else
> -                       writel(0, pmx->sys2pci_base + SYS2PCI_SDIO9SEL);
> -       }
> -
> -       grp_mux = pmx_func->grpmux;
> -
> -       for (idx = 0; idx < grp_mux->pad_mux_count; idx++) {
> -               mux = &grp_mux->pad_mux_list[idx];
> -               __atlas7_pmx_pin_input_disable_set(pmx, mux);
> -               ret = __atlas7_pmx_pin_enable(pmx, mux->pin, mux->func);
> -               if (ret) {
> -                       dev_err(pmx->dev,
> -                               "FUNC:%s GRP:%s PIN#%d.%d failed, ret=%d\n",
> -                               pmx_func->name, pin_grp->name,
> -                               mux->pin, mux->func, ret);
> -                       BUG_ON(1);
> -               }
> -               __atlas7_pmx_pin_input_disable_clr(pmx, mux);
> -       }
> -       pr_debug("PMX DUMP ### Function:[%s] Group:[%s] #### END <<<\n",
> -                       pmx_func->name, pin_grp->name);
> -
> -       return 0;
> -}
> -
> -static u32 convert_current_to_drive_strength(u32 type, u32 ma)
> -{
> -       int idx;
> -
> -       for (idx = 0; idx < ARRAY_SIZE(atlas7_ma2ds_map); idx++) {
> -               if (atlas7_ma2ds_map[idx].ma != ma)
> -                       continue;
> -
> -               if (type == PAD_T_4WE_PD || type == PAD_T_4WE_PU)
> -                       return atlas7_ma2ds_map[idx].ds_4we;
> -               else if (type == PAD_T_16ST)
> -                       return atlas7_ma2ds_map[idx].ds_16st;
> -               else if (type == PAD_T_M31_0204_PD || type == PAD_T_M31_0204_PU)
> -                       return atlas7_ma2ds_map[idx].ds_0204m31;
> -               else if (type == PAD_T_M31_0610_PD || type == PAD_T_M31_0610_PU)
> -                       return atlas7_ma2ds_map[idx].ds_0610m31;
> -       }
> -
> -       return DS_NULL;
> -}
> -
> -static int altas7_pinctrl_set_pull_sel(struct pinctrl_dev *pctldev,
> -                                       u32 pin, u32 sel)
> -{
> -       struct atlas7_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
> -       struct atlas7_pad_config *conf = &pmx->pctl_data->confs[pin];
> -       const struct atlas7_pull_info *pull_info;
> -       u32 bank;
> -       unsigned long regv;
> -       void __iomem *pull_sel_reg;
> -
> -       bank = atlas7_pin_to_bank(pin);
> -       pull_info = &atlas7_pull_map[conf->type];
> -       pull_sel_reg = pmx->regs[bank] + conf->pupd_reg;
> -
> -       /* Retrieve correspond register value from table by sel */
> -       regv = pull_info->s2v[sel].data & pull_info->mask;
> -
> -       /* Clear & Set new value to pull register */
> -       writel(pull_info->mask << conf->pupd_bit, CLR_REG(pull_sel_reg));
> -       writel(regv << conf->pupd_bit, pull_sel_reg);
> -
> -       pr_debug("PIN_CFG ### SET PIN#%d PULL SELECTOR:%d == OK ####\n",
> -               pin, sel);
> -       return 0;
> -}
> -
> -static int __altas7_pinctrl_set_drive_strength_sel(struct pinctrl_dev *pctldev,
> -                                               u32 pin, u32 sel)
> -{
> -       struct atlas7_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
> -       struct atlas7_pad_config *conf = &pmx->pctl_data->confs[pin];
> -       const struct atlas7_ds_info *ds_info;
> -       u32 bank;
> -       void __iomem *ds_sel_reg;
> -
> -       ds_info = &atlas7_ds_map[conf->type];
> -       if (sel & (~(ds_info->mask)))
> -               goto unsupport;
> -
> -       bank = atlas7_pin_to_bank(pin);
> -       ds_sel_reg = pmx->regs[bank] + conf->drvstr_reg;
> -
> -       writel(ds_info->imval << conf->drvstr_bit, CLR_REG(ds_sel_reg));
> -       writel(sel << conf->drvstr_bit, ds_sel_reg);
> -
> -       return 0;
> -
> -unsupport:
> -       pr_err("Pad#%d type[%d] doesn't support ds code[%d]!\n",
> -               pin, conf->type, sel);
> -       return -ENOTSUPP;
> -}
> -
> -static int altas7_pinctrl_set_drive_strength_sel(struct pinctrl_dev *pctldev,
> -                                               u32 pin, u32 ma)
> -{
> -       struct atlas7_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
> -       struct atlas7_pad_config *conf = &pmx->pctl_data->confs[pin];
> -       u32 type = conf->type;
> -       u32 sel;
> -       int ret;
> -
> -       sel = convert_current_to_drive_strength(conf->type, ma);
> -       if (DS_NULL == sel) {
> -               pr_err("Pad#%d type[%d] doesn't support ds current[%d]!\n",
> -               pin, type, ma);
> -               return -ENOTSUPP;
> -       }
> -
> -       ret =  __altas7_pinctrl_set_drive_strength_sel(pctldev,
> -                                               pin, sel);
> -       pr_debug("PIN_CFG ### SET PIN#%d DS:%d MA:%d == %s ####\n",
> -               pin, sel, ma, ret?"FAILED":"OK");
> -       return ret;
> -}
> -
> -static int atlas7_pmx_gpio_request_enable(struct pinctrl_dev *pctldev,
> -               struct pinctrl_gpio_range *range, u32 pin)
> -{
> -       struct atlas7_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
> -       u32 idx;
> -
> -       dev_dbg(pmx->dev,
> -               "atlas7_pmx_gpio_request_enable: pin=%d\n", pin);
> -       for (idx = 0; idx < range->npins; idx++) {
> -               if (pin == range->pins[idx])
> -                       break;
> -       }
> -
> -       if (idx >= range->npins) {
> -               dev_err(pmx->dev,
> -                       "The pin#%d could not be requested as GPIO!!\n",
> -                       pin);
> -               return -EPERM;
> -       }
> -
> -       __atlas7_pmx_pin_enable(pmx, pin, FUNC_GPIO);
> -
> -       return 0;
> -}
> -
> -static const struct pinmux_ops atlas7_pinmux_ops = {
> -       .get_functions_count = atlas7_pmx_get_funcs_count,
> -       .get_function_name = atlas7_pmx_get_func_name,
> -       .get_function_groups = atlas7_pmx_get_func_groups,
> -       .set_mux = atlas7_pmx_set_mux,
> -       .gpio_request_enable = atlas7_pmx_gpio_request_enable,
> -};
> -
> -static int atlas7_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
> -{
> -       struct atlas7_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
> -
> -       return pmx->pctl_data->grps_cnt;
> -}
> -
> -static const char *atlas7_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
> -                                               u32 group)
> -{
> -       struct atlas7_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
> -
> -       return pmx->pctl_data->grps[group].name;
> -}
> -
> -static int atlas7_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
> -               u32 group, const u32 **pins, u32 *num_pins)
> -{
> -       struct atlas7_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
> -
> -       *num_pins = pmx->pctl_data->grps[group].num_pins;
> -       *pins = pmx->pctl_data->grps[group].pins;
> -
> -       return 0;
> -}
> -
> -static int atlas7_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
> -                                       struct device_node *np_config,
> -                                       struct pinctrl_map **map,
> -                                       u32 *num_maps)
> -{
> -       return pinconf_generic_dt_node_to_map(pctldev, np_config, map,
> -                               num_maps, PIN_MAP_TYPE_INVALID);
> -}
> -
> -static void atlas7_pinctrl_dt_free_map(struct pinctrl_dev *pctldev,
> -               struct pinctrl_map *map, u32 num_maps)
> -{
> -       kfree(map);
> -}
> -
> -static const struct pinctrl_ops atlas7_pinctrl_ops = {
> -       .get_groups_count = atlas7_pinctrl_get_groups_count,
> -       .get_group_name = atlas7_pinctrl_get_group_name,
> -       .get_group_pins = atlas7_pinctrl_get_group_pins,
> -       .dt_node_to_map = atlas7_pinctrl_dt_node_to_map,
> -       .dt_free_map = atlas7_pinctrl_dt_free_map,
> -};
> -
> -static int atlas7_pin_config_set(struct pinctrl_dev *pctldev,
> -                               unsigned pin, unsigned long *configs,
> -                               unsigned num_configs)
> -{
> -       u16 param;
> -       u32 arg;
> -       int idx, err;
> -
> -       for (idx = 0; idx < num_configs; idx++) {
> -               param = pinconf_to_config_param(configs[idx]);
> -               arg = pinconf_to_config_argument(configs[idx]);
> -
> -               pr_debug("PMX CFG###### ATLAS7 PIN#%d [%s] CONFIG PARAM:%d ARG:%d >>>>>\n",
> -                       pin, atlas7_ioc_pads[pin].name, param, arg);
> -               switch (param) {
> -               case PIN_CONFIG_BIAS_PULL_UP:
> -                       err = altas7_pinctrl_set_pull_sel(pctldev,
> -                                                       pin, PULL_UP);
> -                       if (err)
> -                               return err;
> -                       break;
> -
> -               case PIN_CONFIG_BIAS_PULL_DOWN:
> -                       err = altas7_pinctrl_set_pull_sel(pctldev,
> -                                                       pin, PULL_DOWN);
> -                       if (err)
> -                               return err;
> -                       break;
> -
> -               case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
> -                       err = altas7_pinctrl_set_pull_sel(pctldev,
> -                                                       pin, HIGH_HYSTERESIS);
> -                       if (err)
> -                               return err;
> -                       break;
> -               case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
> -                       err = altas7_pinctrl_set_pull_sel(pctldev,
> -                                                       pin, HIGH_Z);
> -                       if (err)
> -                               return err;
> -                       break;
> -
> -               case PIN_CONFIG_DRIVE_STRENGTH:
> -                       err = altas7_pinctrl_set_drive_strength_sel(pctldev,
> -                                                       pin, arg);
> -                       if (err)
> -                               return err;
> -                       break;
> -               default:
> -                       return -ENOTSUPP;
> -               }
> -               pr_debug("PMX CFG###### ATLAS7 PIN#%d [%s] CONFIG PARAM:%d ARG:%d <<<<\n",
> -                       pin, atlas7_ioc_pads[pin].name, param, arg);
> -       }
> -
> -       return 0;
> -}
> -
> -static int atlas7_pin_config_group_set(struct pinctrl_dev *pctldev,
> -                               unsigned group, unsigned long *configs,
> -                               unsigned num_configs)
> -{
> -       const unsigned *pins;
> -       unsigned npins;
> -       int i, ret;
> -
> -       ret = atlas7_pinctrl_get_group_pins(pctldev, group, &pins, &npins);
> -       if (ret)
> -               return ret;
> -       for (i = 0; i < npins; i++) {
> -               if (atlas7_pin_config_set(pctldev, pins[i],
> -                                         configs, num_configs))
> -                       return -ENOTSUPP;
> -       }
> -       return 0;
> -}
> -
> -static const struct pinconf_ops atlas7_pinconf_ops = {
> -       .pin_config_set = atlas7_pin_config_set,
> -       .pin_config_group_set = atlas7_pin_config_group_set,
> -       .is_generic = true,
> -};
> -
> -static int atlas7_pinmux_probe(struct platform_device *pdev)
> -{
> -       int ret, idx;
> -       struct atlas7_pmx *pmx;
> -       struct device_node *np = pdev->dev.of_node;
> -       u32 banks = ATLAS7_PINCTRL_REG_BANKS;
> -       struct device_node *sys2pci_np;
> -       struct resource res;
> -
> -       /* Create state holders etc for this driver */
> -       pmx = devm_kzalloc(&pdev->dev, sizeof(*pmx), GFP_KERNEL);
> -       if (!pmx)
> -               return -ENOMEM;
> -
> -       /* The sd3 and sd9 shared all pins, and the function select by
> -        * SYS2PCI_SDIO9SEL register
> -        */
> -       sys2pci_np = of_find_node_by_name(NULL, "sys2pci");
> -       if (!sys2pci_np)
> -               return -EINVAL;
> -
> -       ret = of_address_to_resource(sys2pci_np, 0, &res);
> -       of_node_put(sys2pci_np);
> -       if (ret)
> -               return ret;
> -
> -       pmx->sys2pci_base = devm_ioremap_resource(&pdev->dev, &res);
> -       if (IS_ERR(pmx->sys2pci_base))
> -               return -ENOMEM;
> -
> -       pmx->dev = &pdev->dev;
> -
> -       pmx->pctl_data = &atlas7_ioc_data;
> -       pmx->pctl_desc.name = "pinctrl-atlas7";
> -       pmx->pctl_desc.pins = pmx->pctl_data->pads;
> -       pmx->pctl_desc.npins = pmx->pctl_data->pads_cnt;
> -       pmx->pctl_desc.pctlops = &atlas7_pinctrl_ops;
> -       pmx->pctl_desc.pmxops = &atlas7_pinmux_ops;
> -       pmx->pctl_desc.confops = &atlas7_pinconf_ops;
> -
> -       for (idx = 0; idx < banks; idx++) {
> -               pmx->regs[idx] = of_iomap(np, idx);
> -               if (!pmx->regs[idx]) {
> -                       dev_err(&pdev->dev,
> -                               "can't map ioc bank#%d registers\n", idx);
> -                       ret = -ENOMEM;
> -                       goto unmap_io;
> -               }
> -       }
> -
> -       /* Now register the pin controller and all pins it handles */
> -       pmx->pctl = pinctrl_register(&pmx->pctl_desc, &pdev->dev, pmx);
> -       if (IS_ERR(pmx->pctl)) {
> -               dev_err(&pdev->dev, "could not register atlas7 pinmux driver\n");
> -               ret = PTR_ERR(pmx->pctl);
> -               goto unmap_io;
> -       }
> -
> -       platform_set_drvdata(pdev, pmx);
> -
> -       dev_info(&pdev->dev, "initialized atlas7 pinmux driver\n");
> -
> -       return 0;
> -
> -unmap_io:
> -       for (idx = 0; idx < banks; idx++) {
> -               if (!pmx->regs[idx])
> -                       break;
> -               iounmap(pmx->regs[idx]);
> -       }
> -
> -       return ret;
> -}
> -
> -#ifdef CONFIG_PM_SLEEP
> -static int atlas7_pinmux_suspend_noirq(struct device *dev)
> -{
> -       struct atlas7_pmx *pmx = dev_get_drvdata(dev);
> -       struct atlas7_pad_status *status;
> -       struct atlas7_pad_config *conf;
> -       const struct atlas7_ds_info *ds_info;
> -       const struct atlas7_pull_info *pull_info;
> -       int idx;
> -       u32 bank;
> -       unsigned long regv;
> -
> -       for (idx = 0; idx < pmx->pctl_desc.npins; idx++) {
> -               /* Get this Pad's descriptor from PINCTRL */
> -               conf = &pmx->pctl_data->confs[idx];
> -               bank = atlas7_pin_to_bank(idx);
> -               status = &pmx->sleep_data[idx];
> -
> -               /* Save Function selector */
> -               regv = readl(pmx->regs[bank] + conf->mux_reg);
> -               status->func = (regv >> conf->mux_bit) & FUNC_CLEAR_MASK;
> -
> -               /* Check if Pad is in Analogue selector */
> -               if (conf->ad_ctrl_reg == -1)
> -                       goto save_ds_sel;
> -
> -               regv = readl(pmx->regs[bank] + conf->ad_ctrl_reg);
> -               if (!(regv & (conf->ad_ctrl_bit << ANA_CLEAR_MASK)))
> -                       status->func = FUNC_ANALOGUE;
> -
> -save_ds_sel:
> -               if (conf->drvstr_reg == -1)
> -                       goto save_pull_sel;
> -
> -               /* Save Drive Strength selector */
> -               ds_info = &atlas7_ds_map[conf->type];
> -               regv = readl(pmx->regs[bank] + conf->drvstr_reg);
> -               status->dstr = (regv >> conf->drvstr_bit) & ds_info->mask;
> -
> -save_pull_sel:
> -               /* Save Pull selector */
> -               pull_info = &atlas7_pull_map[conf->type];
> -               regv = readl(pmx->regs[bank] + conf->pupd_reg);
> -               regv = (regv >> conf->pupd_bit) & pull_info->mask;
> -               status->pull = pull_info->v2s[regv].data;
> -       }
> -
> -       /*
> -        * Save disable input selector, this selector is not for Pin,
> -        * but for Mux function.
> -        */
> -       for (idx = 0; idx < NUM_OF_IN_DISABLE_REG; idx++) {
> -               pmx->status_ds[idx] = readl(pmx->regs[BANK_DS] +
> -                                       IN_DISABLE_0_REG_SET + 0x8 * idx);
> -               pmx->status_dsv[idx] = readl(pmx->regs[BANK_DS] +
> -                                       IN_DISABLE_VAL_0_REG_SET + 0x8 * idx);
> -       }
> -
> -       return 0;
> -}
> -
> -static int atlas7_pinmux_resume_noirq(struct device *dev)
> -{
> -       struct atlas7_pmx *pmx = dev_get_drvdata(dev);
> -       struct atlas7_pad_status *status;
> -       int idx;
> -
> -       for (idx = 0; idx < pmx->pctl_desc.npins; idx++) {
> -               /* Get this Pad's descriptor from PINCTRL */
> -               status = &pmx->sleep_data[idx];
> -
> -               /* Restore Function selector */
> -               __atlas7_pmx_pin_enable(pmx, idx, (u32)status->func & 0xff);
> -
> -               if (FUNC_ANALOGUE == status->func)
> -                       goto restore_pull_sel;
> -
> -               /* Restore Drive Strength selector */
> -               __altas7_pinctrl_set_drive_strength_sel(pmx->pctl, idx,
> -                                               (u32)status->dstr & 0xff);
> -
> -restore_pull_sel:
> -               /* Restore Pull selector */
> -               altas7_pinctrl_set_pull_sel(pmx->pctl, idx,
> -                                               (u32)status->pull & 0xff);
> -       }
> -
> -       /*
> -        * Restore disable input selector, this selector is not for Pin,
> -        * but for Mux function
> -        */
> -       for (idx = 0; idx < NUM_OF_IN_DISABLE_REG; idx++) {
> -               writel(~0, pmx->regs[BANK_DS] +
> -                                       IN_DISABLE_0_REG_CLR + 0x8 * idx);
> -               writel(pmx->status_ds[idx], pmx->regs[BANK_DS] +
> -                                       IN_DISABLE_0_REG_SET + 0x8 * idx);
> -               writel(~0, pmx->regs[BANK_DS] +
> -                                       IN_DISABLE_VAL_0_REG_CLR + 0x8 * idx);
> -               writel(pmx->status_dsv[idx], pmx->regs[BANK_DS] +
> -                                       IN_DISABLE_VAL_0_REG_SET + 0x8 * idx);
> -       }
> -
> -       return 0;
> -}
> -
> -static const struct dev_pm_ops atlas7_pinmux_pm_ops = {
> -       .suspend_noirq = atlas7_pinmux_suspend_noirq,
> -       .resume_noirq = atlas7_pinmux_resume_noirq,
> -       .freeze_noirq = atlas7_pinmux_suspend_noirq,
> -       .restore_noirq = atlas7_pinmux_resume_noirq,
> -};
> -#endif
> -
> -static const struct of_device_id atlas7_pinmux_ids[] = {
> -       { .compatible = "sirf,atlas7-ioc",},
> -       {},
> -};
> -
> -static struct platform_driver atlas7_pinmux_driver = {
> -       .driver = {
> -               .name = "atlas7-ioc",
> -               .of_match_table = atlas7_pinmux_ids,
> -#ifdef CONFIG_PM_SLEEP
> -               .pm = &atlas7_pinmux_pm_ops,
> -#endif
> -       },
> -       .probe = atlas7_pinmux_probe,
> -};
> -
> -static int __init atlas7_pinmux_init(void)
> -{
> -       return platform_driver_register(&atlas7_pinmux_driver);
> -}
> -arch_initcall(atlas7_pinmux_init);
> -
> -
> -/*
> - * The Following is GPIO Code
> - */
> -static inline struct
> -atlas7_gpio_bank *atlas7_gpio_to_bank(struct atlas7_gpio_chip *a7gc, u32 gpio)
> -{
> -       return &a7gc->banks[GPIO_TO_BANK(gpio)];
> -}
> -
> -static int __atlas7_gpio_to_pin(struct atlas7_gpio_chip *a7gc, u32 gpio)
> -{
> -       struct atlas7_gpio_bank *bank;
> -       u32 ofs;
> -
> -       bank = atlas7_gpio_to_bank(a7gc, gpio);
> -       ofs = gpio - bank->gpio_offset;
> -       if (ofs >= bank->ngpio)
> -               return -ENODEV;
> -
> -       return bank->gpio_pins[ofs];
> -}
> -
> -static void atlas7_gpio_irq_ack(struct irq_data *d)
> -{
> -       struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
> -       struct atlas7_gpio_chip *a7gc = gpiochip_get_data(gc);
> -       struct atlas7_gpio_bank *bank;
> -       void __iomem *ctrl_reg;
> -       u32 val, pin_in_bank;
> -       unsigned long flags;
> -
> -       bank = atlas7_gpio_to_bank(a7gc, d->hwirq);
> -       pin_in_bank = d->hwirq - bank->gpio_offset;
> -       ctrl_reg = ATLAS7_GPIO_CTRL(bank, pin_in_bank);
> -
> -       raw_spin_lock_irqsave(&a7gc->lock, flags);
> -
> -       val = readl(ctrl_reg);
> -       /* clear interrupt status */
> -       writel(val, ctrl_reg);
> -
> -       raw_spin_unlock_irqrestore(&a7gc->lock, flags);
> -}
> -
> -static void __atlas7_gpio_irq_mask(struct atlas7_gpio_chip *a7gc, int idx)
> -{
> -       struct atlas7_gpio_bank *bank;
> -       void __iomem *ctrl_reg;
> -       u32 val, pin_in_bank;
> -
> -       bank = atlas7_gpio_to_bank(a7gc, idx);
> -       pin_in_bank = idx - bank->gpio_offset;
> -       ctrl_reg = ATLAS7_GPIO_CTRL(bank, pin_in_bank);
> -
> -       val = readl(ctrl_reg);
> -       val &= ~(ATLAS7_GPIO_CTL_INTR_EN_MASK |
> -               ATLAS7_GPIO_CTL_INTR_STATUS_MASK);
> -       writel(val, ctrl_reg);
> -}
> -
> -static void atlas7_gpio_irq_mask(struct irq_data *d)
> -{
> -       struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
> -       struct atlas7_gpio_chip *a7gc = gpiochip_get_data(gc);
> -       unsigned long flags;
> -
> -       raw_spin_lock_irqsave(&a7gc->lock, flags);
> -
> -       __atlas7_gpio_irq_mask(a7gc, d->hwirq);
> -
> -       raw_spin_unlock_irqrestore(&a7gc->lock, flags);
> -}
> -
> -static void atlas7_gpio_irq_unmask(struct irq_data *d)
> -{
> -       struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
> -       struct atlas7_gpio_chip *a7gc = gpiochip_get_data(gc);
> -       struct atlas7_gpio_bank *bank;
> -       void __iomem *ctrl_reg;
> -       u32 val, pin_in_bank;
> -       unsigned long flags;
> -
> -       bank = atlas7_gpio_to_bank(a7gc, d->hwirq);
> -       pin_in_bank = d->hwirq - bank->gpio_offset;
> -       ctrl_reg = ATLAS7_GPIO_CTRL(bank, pin_in_bank);
> -
> -       raw_spin_lock_irqsave(&a7gc->lock, flags);
> -
> -       val = readl(ctrl_reg);
> -       val &= ~ATLAS7_GPIO_CTL_INTR_STATUS_MASK;
> -       val |= ATLAS7_GPIO_CTL_INTR_EN_MASK;
> -       writel(val, ctrl_reg);
> -
> -       raw_spin_unlock_irqrestore(&a7gc->lock, flags);
> -}
> -
> -static int atlas7_gpio_irq_type(struct irq_data *d,
> -                               unsigned int type)
> -{
> -       struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
> -       struct atlas7_gpio_chip *a7gc = gpiochip_get_data(gc);
> -       struct atlas7_gpio_bank *bank;
> -       void __iomem *ctrl_reg;
> -       u32 val, pin_in_bank;
> -       unsigned long flags;
> -
> -       bank = atlas7_gpio_to_bank(a7gc, d->hwirq);
> -       pin_in_bank = d->hwirq - bank->gpio_offset;
> -       ctrl_reg = ATLAS7_GPIO_CTRL(bank, pin_in_bank);
> -
> -       raw_spin_lock_irqsave(&a7gc->lock, flags);
> -
> -       val = readl(ctrl_reg);
> -       val &= ~(ATLAS7_GPIO_CTL_INTR_STATUS_MASK |
> -               ATLAS7_GPIO_CTL_INTR_EN_MASK);
> -
> -       switch (type) {
> -       case IRQ_TYPE_NONE:
> -               break;
> -
> -       case IRQ_TYPE_EDGE_RISING:
> -               val |= ATLAS7_GPIO_CTL_INTR_HIGH_MASK |
> -                       ATLAS7_GPIO_CTL_INTR_TYPE_MASK;
> -               val &= ~ATLAS7_GPIO_CTL_INTR_LOW_MASK;
> -               break;
> -
> -       case IRQ_TYPE_EDGE_FALLING:
> -               val &= ~ATLAS7_GPIO_CTL_INTR_HIGH_MASK;
> -               val |= ATLAS7_GPIO_CTL_INTR_LOW_MASK |
> -                       ATLAS7_GPIO_CTL_INTR_TYPE_MASK;
> -               break;
> -
> -       case IRQ_TYPE_EDGE_BOTH:
> -               val |= ATLAS7_GPIO_CTL_INTR_HIGH_MASK |
> -                       ATLAS7_GPIO_CTL_INTR_LOW_MASK |
> -                       ATLAS7_GPIO_CTL_INTR_TYPE_MASK;
> -               break;
> -
> -       case IRQ_TYPE_LEVEL_LOW:
> -               val &= ~(ATLAS7_GPIO_CTL_INTR_HIGH_MASK |
> -                       ATLAS7_GPIO_CTL_INTR_TYPE_MASK);
> -               val |= ATLAS7_GPIO_CTL_INTR_LOW_MASK;
> -               break;
> -
> -       case IRQ_TYPE_LEVEL_HIGH:
> -               val |= ATLAS7_GPIO_CTL_INTR_HIGH_MASK;
> -               val &= ~(ATLAS7_GPIO_CTL_INTR_LOW_MASK |
> -                       ATLAS7_GPIO_CTL_INTR_TYPE_MASK);
> -               break;
> -       }
> -
> -       writel(val, ctrl_reg);
> -
> -       raw_spin_unlock_irqrestore(&a7gc->lock, flags);
> -
> -       return 0;
> -}
> -
> -static struct irq_chip atlas7_gpio_irq_chip = {
> -       .name = "atlas7-gpio-irq",
> -       .irq_ack = atlas7_gpio_irq_ack,
> -       .irq_mask = atlas7_gpio_irq_mask,
> -       .irq_unmask = atlas7_gpio_irq_unmask,
> -       .irq_set_type = atlas7_gpio_irq_type,
> -};
> -
> -static void atlas7_gpio_handle_irq(struct irq_desc *desc)
> -{
> -       struct gpio_chip *gc = irq_desc_get_handler_data(desc);
> -       struct atlas7_gpio_chip *a7gc = gpiochip_get_data(gc);
> -       struct atlas7_gpio_bank *bank = NULL;
> -       u32 status, ctrl;
> -       int pin_in_bank = 0, idx;
> -       struct irq_chip *chip = irq_desc_get_chip(desc);
> -       unsigned int irq = irq_desc_get_irq(desc);
> -
> -       for (idx = 0; idx < a7gc->nbank; idx++) {
> -               bank = &a7gc->banks[idx];
> -               if (bank->irq == irq)
> -                       break;
> -       }
> -       BUG_ON(idx == a7gc->nbank);
> -
> -       chained_irq_enter(chip, desc);
> -
> -       status = readl(ATLAS7_GPIO_INT_STATUS(bank));
> -       if (!status) {
> -               pr_warn("%s: gpio [%s] status %#x no interrupt is flagged\n",
> -                       __func__, gc->label, status);
> -               handle_bad_irq(desc);
> -               return;
> -       }
> -
> -       while (status) {
> -               ctrl = readl(ATLAS7_GPIO_CTRL(bank, pin_in_bank));
> -
> -               /*
> -                * Here we must check whether the corresponding GPIO's
> -                * interrupt has been enabled, otherwise just skip it
> -                */
> -               if ((status & 0x1) && (ctrl & ATLAS7_GPIO_CTL_INTR_EN_MASK)) {
> -                       pr_debug("%s: chip[%s] gpio:%d happens\n",
> -                               __func__, gc->label,
> -                               bank->gpio_offset + pin_in_bank);
> -                       generic_handle_irq(
> -                               irq_find_mapping(gc->irq.domain,
> -                                       bank->gpio_offset + pin_in_bank));
> -               }
> -
> -               if (++pin_in_bank >= bank->ngpio)
> -                       break;
> -
> -               status = status >> 1;
> -       }
> -
> -       chained_irq_exit(chip, desc);
> -}
> -
> -static void __atlas7_gpio_set_input(struct atlas7_gpio_chip *a7gc,
> -                               unsigned int gpio)
> -{
> -       struct atlas7_gpio_bank *bank;
> -       void __iomem *ctrl_reg;
> -       u32 val, pin_in_bank;
> -
> -       bank = atlas7_gpio_to_bank(a7gc, gpio);
> -       pin_in_bank = gpio - bank->gpio_offset;
> -       ctrl_reg = ATLAS7_GPIO_CTRL(bank, pin_in_bank);
> -
> -       val = readl(ctrl_reg);
> -       val &= ~ATLAS7_GPIO_CTL_OUT_EN_MASK;
> -       writel(val, ctrl_reg);
> -}
> -
> -static int atlas7_gpio_request(struct gpio_chip *chip,
> -                               unsigned int gpio)
> -{
> -       struct atlas7_gpio_chip *a7gc = gpiochip_get_data(chip);
> -       int ret;
> -       unsigned long flags;
> -
> -       ret = __atlas7_gpio_to_pin(a7gc, gpio);
> -       if (ret < 0)
> -               return ret;
> -
> -       if (pinctrl_gpio_request(chip->base + gpio))
> -               return -ENODEV;
> -
> -       raw_spin_lock_irqsave(&a7gc->lock, flags);
> -
> -       /*
> -        * default status:
> -        * set direction as input and mask irq
> -        */
> -       __atlas7_gpio_set_input(a7gc, gpio);
> -       __atlas7_gpio_irq_mask(a7gc, gpio);
> -
> -       raw_spin_unlock_irqrestore(&a7gc->lock, flags);
> -
> -       return 0;
> -}
> -
> -static void atlas7_gpio_free(struct gpio_chip *chip,
> -                               unsigned int gpio)
> -{
> -       struct atlas7_gpio_chip *a7gc = gpiochip_get_data(chip);
> -       unsigned long flags;
> -
> -       raw_spin_lock_irqsave(&a7gc->lock, flags);
> -
> -       __atlas7_gpio_irq_mask(a7gc, gpio);
> -       __atlas7_gpio_set_input(a7gc, gpio);
> -
> -       raw_spin_unlock_irqrestore(&a7gc->lock, flags);
> -
> -       pinctrl_gpio_free(chip->base + gpio);
> -}
> -
> -static int atlas7_gpio_direction_input(struct gpio_chip *chip,
> -                                       unsigned int gpio)
> -{
> -       struct atlas7_gpio_chip *a7gc = gpiochip_get_data(chip);
> -       unsigned long flags;
> -
> -       raw_spin_lock_irqsave(&a7gc->lock, flags);
> -
> -       __atlas7_gpio_set_input(a7gc, gpio);
> -
> -       raw_spin_unlock_irqrestore(&a7gc->lock, flags);
> -
> -       return 0;
> -}
> -
> -static void __atlas7_gpio_set_output(struct atlas7_gpio_chip *a7gc,
> -                          unsigned int gpio, int value)
> -{
> -       struct atlas7_gpio_bank *bank;
> -       void __iomem *ctrl_reg;
> -       u32 out_ctrl, pin_in_bank;
> -
> -       bank = atlas7_gpio_to_bank(a7gc, gpio);
> -       pin_in_bank = gpio - bank->gpio_offset;
> -       ctrl_reg = ATLAS7_GPIO_CTRL(bank, pin_in_bank);
> -
> -       out_ctrl = readl(ctrl_reg);
> -       if (value)
> -               out_ctrl |= ATLAS7_GPIO_CTL_DATAOUT_MASK;
> -       else
> -               out_ctrl &= ~ATLAS7_GPIO_CTL_DATAOUT_MASK;
> -
> -       out_ctrl &= ~ATLAS7_GPIO_CTL_INTR_EN_MASK;
> -       out_ctrl |= ATLAS7_GPIO_CTL_OUT_EN_MASK;
> -       writel(out_ctrl, ctrl_reg);
> -}
> -
> -static int atlas7_gpio_direction_output(struct gpio_chip *chip,
> -                               unsigned int gpio, int value)
> -{
> -       struct atlas7_gpio_chip *a7gc = gpiochip_get_data(chip);
> -       unsigned long flags;
> -
> -       raw_spin_lock_irqsave(&a7gc->lock, flags);
> -
> -       __atlas7_gpio_set_output(a7gc, gpio, value);
> -
> -       raw_spin_unlock_irqrestore(&a7gc->lock, flags);
> -
> -       return 0;
> -}
> -
> -static int atlas7_gpio_get_value(struct gpio_chip *chip,
> -                                       unsigned int gpio)
> -{
> -       struct atlas7_gpio_chip *a7gc = gpiochip_get_data(chip);
> -       struct atlas7_gpio_bank *bank;
> -       u32 val, pin_in_bank;
> -       unsigned long flags;
> -
> -       bank = atlas7_gpio_to_bank(a7gc, gpio);
> -       pin_in_bank = gpio - bank->gpio_offset;
> -
> -       raw_spin_lock_irqsave(&a7gc->lock, flags);
> -
> -       val = readl(ATLAS7_GPIO_CTRL(bank, pin_in_bank));
> -
> -       raw_spin_unlock_irqrestore(&a7gc->lock, flags);
> -
> -       return !!(val & ATLAS7_GPIO_CTL_DATAIN_MASK);
> -}
> -
> -static void atlas7_gpio_set_value(struct gpio_chip *chip,
> -                               unsigned int gpio, int value)
> -{
> -       struct atlas7_gpio_chip *a7gc = gpiochip_get_data(chip);
> -       struct atlas7_gpio_bank *bank;
> -       void __iomem *ctrl_reg;
> -       u32 ctrl, pin_in_bank;
> -       unsigned long flags;
> -
> -       bank = atlas7_gpio_to_bank(a7gc, gpio);
> -       pin_in_bank = gpio - bank->gpio_offset;
> -       ctrl_reg = ATLAS7_GPIO_CTRL(bank, pin_in_bank);
> -
> -       raw_spin_lock_irqsave(&a7gc->lock, flags);
> -
> -       ctrl = readl(ctrl_reg);
> -       if (value)
> -               ctrl |= ATLAS7_GPIO_CTL_DATAOUT_MASK;
> -       else
> -               ctrl &= ~ATLAS7_GPIO_CTL_DATAOUT_MASK;
> -       writel(ctrl, ctrl_reg);
> -
> -       raw_spin_unlock_irqrestore(&a7gc->lock, flags);
> -}
> -
> -static const struct of_device_id atlas7_gpio_ids[] = {
> -       { .compatible = "sirf,atlas7-gpio", },
> -       {},
> -};
> -
> -static int atlas7_gpio_probe(struct platform_device *pdev)
> -{
> -       struct device_node *np = pdev->dev.of_node;
> -       struct atlas7_gpio_chip *a7gc;
> -       struct gpio_chip *chip;
> -       u32 nbank;
> -       int ret, idx;
> -       struct gpio_irq_chip *girq;
> -
> -       ret = of_property_read_u32(np, "gpio-banks", &nbank);
> -       if (ret) {
> -               dev_err(&pdev->dev,
> -                       "Could not find GPIO bank info,ret=%d!\n",
> -                       ret);
> -               return ret;
> -       }
> -
> -       /* retrieve gpio descriptor data */
> -       a7gc = devm_kzalloc(&pdev->dev, struct_size(a7gc, banks, nbank),
> -                           GFP_KERNEL);
> -       if (!a7gc)
> -               return -ENOMEM;
> -
> -       /* Get Gpio clk */
> -       a7gc->clk = of_clk_get(np, 0);
> -       if (!IS_ERR(a7gc->clk)) {
> -               ret = clk_prepare_enable(a7gc->clk);
> -               if (ret) {
> -                       dev_err(&pdev->dev,
> -                               "Could not enable clock!\n");
> -                       return ret;
> -               }
> -       }
> -
> -       /* Get Gpio Registers */
> -       a7gc->reg = of_iomap(np, 0);
> -       if (!a7gc->reg) {
> -               dev_err(&pdev->dev, "Could not map GPIO Registers!\n");
> -               return -ENOMEM;
> -       }
> -
> -       a7gc->nbank = nbank;
> -       raw_spin_lock_init(&a7gc->lock);
> -
> -       /* Setup GPIO Chip */
> -       chip = &a7gc->chip;
> -       chip->request = atlas7_gpio_request;
> -       chip->free = atlas7_gpio_free;
> -       chip->direction_input = atlas7_gpio_direction_input;
> -       chip->get = atlas7_gpio_get_value;
> -       chip->direction_output = atlas7_gpio_direction_output;
> -       chip->set = atlas7_gpio_set_value;
> -       chip->base = -1;
> -       /* Each chip can support 32 pins at one bank */
> -       chip->ngpio = NGPIO_OF_BANK * nbank;
> -       chip->label = kstrdup(np->name, GFP_KERNEL);
> -       chip->of_node = np;
> -       chip->of_gpio_n_cells = 2;
> -       chip->parent = &pdev->dev;
> -
> -       girq = &chip->irq;
> -       girq->chip = &atlas7_gpio_irq_chip;
> -       girq->parent_handler = atlas7_gpio_handle_irq;
> -       girq->num_parents = nbank;
> -       girq->parents = devm_kcalloc(&pdev->dev, nbank,
> -                                    sizeof(*girq->parents),
> -                                    GFP_KERNEL);
> -       if (!girq->parents)
> -               return -ENOMEM;
> -       for (idx = 0; idx < nbank; idx++) {
> -               struct atlas7_gpio_bank *bank;
> -
> -               bank = &a7gc->banks[idx];
> -               /* Set ctrl registers' base of this bank */
> -               bank->base = ATLAS7_GPIO_BASE(a7gc, idx);
> -               bank->gpio_offset = idx * NGPIO_OF_BANK;
> -
> -               /* Get interrupt number from DTS */
> -               ret = of_irq_get(np, idx);
> -               if (ret <= 0) {
> -                       dev_err(&pdev->dev,
> -                               "Unable to find IRQ number. ret=%d\n", ret);
> -                       if (!ret)
> -                               ret = -ENXIO;
> -                       goto failed;
> -               }
> -               bank->irq = ret;
> -               girq->parents[idx] = ret;
> -       }
> -       girq->default_type = IRQ_TYPE_NONE;
> -       girq->handler = handle_level_irq;
> -
> -       /* Add gpio chip to system */
> -       ret = gpiochip_add_data(chip, a7gc);
> -       if (ret) {
> -               dev_err(&pdev->dev,
> -                       "%pOF: error in probe function with status %d\n",
> -                       np, ret);
> -               goto failed;
> -       }
> -
> -       platform_set_drvdata(pdev, a7gc);
> -       dev_info(&pdev->dev, "add to system.\n");
> -       return 0;
> -failed:
> -       return ret;
> -}
> -
> -#ifdef CONFIG_PM_SLEEP
> -static int atlas7_gpio_suspend_noirq(struct device *dev)
> -{
> -       struct atlas7_gpio_chip *a7gc = dev_get_drvdata(dev);
> -       struct atlas7_gpio_bank *bank;
> -       void __iomem *ctrl_reg;
> -       u32 idx, pin;
> -
> -       for (idx = 0; idx < a7gc->nbank; idx++) {
> -               bank = &a7gc->banks[idx];
> -               for (pin = 0; pin < bank->ngpio; pin++) {
> -                       ctrl_reg = ATLAS7_GPIO_CTRL(bank, pin);
> -                       bank->sleep_data[pin] = readl(ctrl_reg);
> -               }
> -       }
> -
> -       return 0;
> -}
> -
> -static int atlas7_gpio_resume_noirq(struct device *dev)
> -{
> -       struct atlas7_gpio_chip *a7gc = dev_get_drvdata(dev);
> -       struct atlas7_gpio_bank *bank;
> -       void __iomem *ctrl_reg;
> -       u32 idx, pin;
> -
> -       for (idx = 0; idx < a7gc->nbank; idx++) {
> -               bank = &a7gc->banks[idx];
> -               for (pin = 0; pin < bank->ngpio; pin++) {
> -                       ctrl_reg = ATLAS7_GPIO_CTRL(bank, pin);
> -                       writel(bank->sleep_data[pin], ctrl_reg);
> -               }
> -       }
> -
> -       return 0;
> -}
> -
> -static const struct dev_pm_ops atlas7_gpio_pm_ops = {
> -       .suspend_noirq = atlas7_gpio_suspend_noirq,
> -       .resume_noirq = atlas7_gpio_resume_noirq,
> -       .freeze_noirq = atlas7_gpio_suspend_noirq,
> -       .restore_noirq = atlas7_gpio_resume_noirq,
> -};
> -#endif
> -
> -static struct platform_driver atlas7_gpio_driver = {
> -       .driver = {
> -               .name = "atlas7-gpio",
> -               .of_match_table = atlas7_gpio_ids,
> -#ifdef CONFIG_PM_SLEEP
> -               .pm = &atlas7_gpio_pm_ops,
> -#endif
> -       },
> -       .probe = atlas7_gpio_probe,
> -};
> -
> -static int __init atlas7_gpio_init(void)
> -{
> -       return platform_driver_register(&atlas7_gpio_driver);
> -}
> -subsys_initcall(atlas7_gpio_init);
> diff --git a/drivers/pinctrl/sirf/pinctrl-prima2.c b/drivers/pinctrl/sirf/pinctrl-prima2.c
> deleted file mode 100644
> index 49da2a7eba1f..000000000000
> --- a/drivers/pinctrl/sirf/pinctrl-prima2.c
> +++ /dev/null
> @@ -1,1131 +0,0 @@
> -// SPDX-License-Identifier: GPL-2.0-or-later
> -/*
> - * pinctrl pads, groups, functions for CSR SiRFprimaII
> - *
> - * Copyright (c) 2011 - 2014 Cambridge Silicon Radio Limited, a CSR plc group
> - * company.
> - */
> -
> -#include <linux/pinctrl/pinctrl.h>
> -#include <linux/bitops.h>
> -
> -#include "pinctrl-sirf.h"
> -
> -/*
> - * pad list for the pinmux subsystem
> - * refer to CS-131858-DC-6A.xls
> - */
> -static const struct pinctrl_pin_desc sirfsoc_pads[] = {
> -       PINCTRL_PIN(0, "gpio0-0"),
> -       PINCTRL_PIN(1, "gpio0-1"),
> -       PINCTRL_PIN(2, "gpio0-2"),
> -       PINCTRL_PIN(3, "gpio0-3"),
> -       PINCTRL_PIN(4, "pwm0"),
> -       PINCTRL_PIN(5, "pwm1"),
> -       PINCTRL_PIN(6, "pwm2"),
> -       PINCTRL_PIN(7, "pwm3"),
> -       PINCTRL_PIN(8, "warm_rst_b"),
> -       PINCTRL_PIN(9, "odo_0"),
> -       PINCTRL_PIN(10, "odo_1"),
> -       PINCTRL_PIN(11, "dr_dir"),
> -       PINCTRL_PIN(12, "viprom_fa"),
> -       PINCTRL_PIN(13, "scl_1"),
> -       PINCTRL_PIN(14, "ntrst"),
> -       PINCTRL_PIN(15, "sda_1"),
> -       PINCTRL_PIN(16, "x_ldd[16]"),
> -       PINCTRL_PIN(17, "x_ldd[17]"),
> -       PINCTRL_PIN(18, "x_ldd[18]"),
> -       PINCTRL_PIN(19, "x_ldd[19]"),
> -       PINCTRL_PIN(20, "x_ldd[20]"),
> -       PINCTRL_PIN(21, "x_ldd[21]"),
> -       PINCTRL_PIN(22, "x_ldd[22]"),
> -       PINCTRL_PIN(23, "x_ldd[23], lcdrom_frdy"),
> -       PINCTRL_PIN(24, "gps_sgn"),
> -       PINCTRL_PIN(25, "gps_mag"),
> -       PINCTRL_PIN(26, "gps_clk"),
> -       PINCTRL_PIN(27, "sd_cd_b_1"),
> -       PINCTRL_PIN(28, "sd_vcc_on_1"),
> -       PINCTRL_PIN(29, "sd_wp_b_1"),
> -       PINCTRL_PIN(30, "sd_clk_3"),
> -       PINCTRL_PIN(31, "sd_cmd_3"),
> -
> -       PINCTRL_PIN(32, "x_sd_dat_3[0]"),
> -       PINCTRL_PIN(33, "x_sd_dat_3[1]"),
> -       PINCTRL_PIN(34, "x_sd_dat_3[2]"),
> -       PINCTRL_PIN(35, "x_sd_dat_3[3]"),
> -       PINCTRL_PIN(36, "x_sd_clk_4"),
> -       PINCTRL_PIN(37, "x_sd_cmd_4"),
> -       PINCTRL_PIN(38, "x_sd_dat_4[0]"),
> -       PINCTRL_PIN(39, "x_sd_dat_4[1]"),
> -       PINCTRL_PIN(40, "x_sd_dat_4[2]"),
> -       PINCTRL_PIN(41, "x_sd_dat_4[3]"),
> -       PINCTRL_PIN(42, "x_cko_1"),
> -       PINCTRL_PIN(43, "x_ac97_bit_clk"),
> -       PINCTRL_PIN(44, "x_ac97_dout"),
> -       PINCTRL_PIN(45, "x_ac97_din"),
> -       PINCTRL_PIN(46, "x_ac97_sync"),
> -       PINCTRL_PIN(47, "x_txd_1"),
> -       PINCTRL_PIN(48, "x_txd_2"),
> -       PINCTRL_PIN(49, "x_rxd_1"),
> -       PINCTRL_PIN(50, "x_rxd_2"),
> -       PINCTRL_PIN(51, "x_usclk_0"),
> -       PINCTRL_PIN(52, "x_utxd_0"),
> -       PINCTRL_PIN(53, "x_urxd_0"),
> -       PINCTRL_PIN(54, "x_utfs_0"),
> -       PINCTRL_PIN(55, "x_urfs_0"),
> -       PINCTRL_PIN(56, "x_usclk_1"),
> -       PINCTRL_PIN(57, "x_utxd_1"),
> -       PINCTRL_PIN(58, "x_urxd_1"),
> -       PINCTRL_PIN(59, "x_utfs_1"),
> -       PINCTRL_PIN(60, "x_urfs_1"),
> -       PINCTRL_PIN(61, "x_usclk_2"),
> -       PINCTRL_PIN(62, "x_utxd_2"),
> -       PINCTRL_PIN(63, "x_urxd_2"),
> -
> -       PINCTRL_PIN(64, "x_utfs_2"),
> -       PINCTRL_PIN(65, "x_urfs_2"),
> -       PINCTRL_PIN(66, "x_df_we_b"),
> -       PINCTRL_PIN(67, "x_df_re_b"),
> -       PINCTRL_PIN(68, "x_txd_0"),
> -       PINCTRL_PIN(69, "x_rxd_0"),
> -       PINCTRL_PIN(78, "x_cko_0"),
> -       PINCTRL_PIN(79, "x_vip_pxd[7]"),
> -       PINCTRL_PIN(80, "x_vip_pxd[6]"),
> -       PINCTRL_PIN(81, "x_vip_pxd[5]"),
> -       PINCTRL_PIN(82, "x_vip_pxd[4]"),
> -       PINCTRL_PIN(83, "x_vip_pxd[3]"),
> -       PINCTRL_PIN(84, "x_vip_pxd[2]"),
> -       PINCTRL_PIN(85, "x_vip_pxd[1]"),
> -       PINCTRL_PIN(86, "x_vip_pxd[0]"),
> -       PINCTRL_PIN(87, "x_vip_vsync"),
> -       PINCTRL_PIN(88, "x_vip_hsync"),
> -       PINCTRL_PIN(89, "x_vip_pxclk"),
> -       PINCTRL_PIN(90, "x_sda_0"),
> -       PINCTRL_PIN(91, "x_scl_0"),
> -       PINCTRL_PIN(92, "x_df_ry_by"),
> -       PINCTRL_PIN(93, "x_df_cs_b[1]"),
> -       PINCTRL_PIN(94, "x_df_cs_b[0]"),
> -       PINCTRL_PIN(95, "x_l_pclk"),
> -
> -       PINCTRL_PIN(96, "x_l_lck"),
> -       PINCTRL_PIN(97, "x_l_fck"),
> -       PINCTRL_PIN(98, "x_l_de"),
> -       PINCTRL_PIN(99, "x_ldd[0]"),
> -       PINCTRL_PIN(100, "x_ldd[1]"),
> -       PINCTRL_PIN(101, "x_ldd[2]"),
> -       PINCTRL_PIN(102, "x_ldd[3]"),
> -       PINCTRL_PIN(103, "x_ldd[4]"),
> -       PINCTRL_PIN(104, "x_ldd[5]"),
> -       PINCTRL_PIN(105, "x_ldd[6]"),
> -       PINCTRL_PIN(106, "x_ldd[7]"),
> -       PINCTRL_PIN(107, "x_ldd[8]"),
> -       PINCTRL_PIN(108, "x_ldd[9]"),
> -       PINCTRL_PIN(109, "x_ldd[10]"),
> -       PINCTRL_PIN(110, "x_ldd[11]"),
> -       PINCTRL_PIN(111, "x_ldd[12]"),
> -       PINCTRL_PIN(112, "x_ldd[13]"),
> -       PINCTRL_PIN(113, "x_ldd[14]"),
> -       PINCTRL_PIN(114, "x_ldd[15]"),
> -
> -       PINCTRL_PIN(115, "x_usb1_dp"),
> -       PINCTRL_PIN(116, "x_usb1_dn"),
> -};
> -
> -static const struct sirfsoc_muxmask lcd_16bits_sirfsoc_muxmask[] = {
> -       {
> -               .group = 3,
> -               .mask = BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) |
> -                       BIT(6) | BIT(7) | BIT(8) | BIT(9) | BIT(10) | BIT(11) |
> -                       BIT(12) | BIT(13) | BIT(14) | BIT(15) | BIT(16) |
> -                       BIT(17) | BIT(18),
> -       }, {
> -               .group = 2,
> -               .mask = BIT(31),
> -       },
> -};
> -
> -static const struct sirfsoc_padmux lcd_16bits_padmux = {
> -       .muxmask_counts = ARRAY_SIZE(lcd_16bits_sirfsoc_muxmask),
> -       .muxmask = lcd_16bits_sirfsoc_muxmask,
> -       .ctrlreg = SIRFSOC_RSC_PIN_MUX,
> -       .funcmask = BIT(4),
> -       .funcval = 0,
> -};
> -
> -static const unsigned lcd_16bits_pins[] = { 95, 96, 97, 98, 99, 100, 101, 102,
> -       103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113, 114 };
> -
> -static const struct sirfsoc_muxmask lcd_18bits_muxmask[] = {
> -       {
> -               .group = 3,
> -               .mask = BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) |
> -                       BIT(6) | BIT(7) | BIT(8) | BIT(9) | BIT(10) | BIT(11) |
> -                       BIT(12) | BIT(13) | BIT(14) | BIT(15) | BIT(16) |
> -                       BIT(17) | BIT(18),
> -       }, {
> -               .group = 2,
> -               .mask = BIT(31),
> -       }, {
> -               .group = 0,
> -               .mask = BIT(16) | BIT(17),
> -       },
> -};
> -
> -static const struct sirfsoc_padmux lcd_18bits_padmux = {
> -       .muxmask_counts = ARRAY_SIZE(lcd_18bits_muxmask),
> -       .muxmask = lcd_18bits_muxmask,
> -       .ctrlreg = SIRFSOC_RSC_PIN_MUX,
> -       .funcmask = BIT(4),
> -       .funcval = 0,
> -};
> -
> -static const unsigned lcd_18bits_pins[] = { 16, 17, 95, 96, 97, 98, 99, 100,
> -       101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113, 114};
> -
> -static const struct sirfsoc_muxmask lcd_24bits_muxmask[] = {
> -       {
> -               .group = 3,
> -               .mask = BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) |
> -                       BIT(6) | BIT(7) | BIT(8) | BIT(9) | BIT(10) | BIT(11) |
> -                       BIT(12) | BIT(13) | BIT(14) | BIT(15) | BIT(16) |
> -                       BIT(17) | BIT(18),
> -       }, {
> -               .group = 2,
> -               .mask = BIT(31),
> -       }, {
> -               .group = 0,
> -               .mask = BIT(16) | BIT(17) | BIT(18) | BIT(19) | BIT(20) |
> -                       BIT(21) | BIT(22) | BIT(23),
> -       },
> -};
> -
> -static const struct sirfsoc_padmux lcd_24bits_padmux = {
> -       .muxmask_counts = ARRAY_SIZE(lcd_24bits_muxmask),
> -       .muxmask = lcd_24bits_muxmask,
> -       .ctrlreg = SIRFSOC_RSC_PIN_MUX,
> -       .funcmask = BIT(4),
> -       .funcval = 0,
> -};
> -
> -static const unsigned lcd_24bits_pins[] = { 16, 17, 18, 19, 20, 21, 22, 23,
> -       95, 96, 97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 108, 109,
> -       110, 111, 112, 113, 114 };
> -
> -static const struct sirfsoc_muxmask lcdrom_muxmask[] = {
> -       {
> -               .group = 3,
> -               .mask = BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) |
> -                       BIT(6) | BIT(7) | BIT(8) | BIT(9) | BIT(10) | BIT(11) |
> -                       BIT(12) | BIT(13) | BIT(14) | BIT(15) | BIT(16) |
> -                       BIT(17) | BIT(18),
> -       }, {
> -               .group = 2,
> -               .mask = BIT(31),
> -       }, {
> -               .group = 0,
> -               .mask = BIT(23),
> -       },
> -};
> -
> -static const struct sirfsoc_padmux lcdrom_padmux = {
> -       .muxmask_counts = ARRAY_SIZE(lcdrom_muxmask),
> -       .muxmask = lcdrom_muxmask,
> -       .ctrlreg = SIRFSOC_RSC_PIN_MUX,
> -       .funcmask = BIT(4),
> -       .funcval = BIT(4),
> -};
> -
> -static const unsigned lcdrom_pins[] = { 23, 95, 96, 97, 98, 99, 100, 101, 102,
> -       103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113, 114 };
> -
> -static const struct sirfsoc_muxmask uart0_muxmask[] = {
> -       {
> -               .group = 2,
> -               .mask = BIT(4) | BIT(5),
> -       }, {
> -               .group = 1,
> -               .mask = BIT(23) | BIT(28),
> -       },
> -};
> -
> -static const struct sirfsoc_padmux uart0_padmux = {
> -       .muxmask_counts = ARRAY_SIZE(uart0_muxmask),
> -       .muxmask = uart0_muxmask,
> -       .ctrlreg = SIRFSOC_RSC_PIN_MUX,
> -       .funcmask = BIT(9),
> -       .funcval = BIT(9),
> -};
> -
> -static const unsigned uart0_pins[] = { 55, 60, 68, 69 };
> -
> -static const struct sirfsoc_muxmask uart0_nostreamctrl_muxmask[] = {
> -       {
> -               .group = 2,
> -               .mask = BIT(4) | BIT(5),
> -       },
> -};
> -
> -static const struct sirfsoc_padmux uart0_nostreamctrl_padmux = {
> -       .muxmask_counts = ARRAY_SIZE(uart0_nostreamctrl_muxmask),
> -       .muxmask = uart0_nostreamctrl_muxmask,
> -};
> -
> -static const unsigned uart0_nostreamctrl_pins[] = { 68, 69 };
> -
> -static const struct sirfsoc_muxmask uart1_muxmask[] = {
> -       {
> -               .group = 1,
> -               .mask = BIT(15) | BIT(17),
> -       },
> -};
> -
> -static const struct sirfsoc_padmux uart1_padmux = {
> -       .muxmask_counts = ARRAY_SIZE(uart1_muxmask),
> -       .muxmask = uart1_muxmask,
> -};
> -
> -static const unsigned uart1_pins[] = { 47, 49 };
> -
> -static const struct sirfsoc_muxmask uart2_muxmask[] = {
> -       {
> -               .group = 1,
> -               .mask = BIT(16) | BIT(18) | BIT(24) | BIT(27),
> -       },
> -};
> -
> -static const struct sirfsoc_padmux uart2_padmux = {
> -       .muxmask_counts = ARRAY_SIZE(uart2_muxmask),
> -       .muxmask = uart2_muxmask,
> -       .ctrlreg = SIRFSOC_RSC_PIN_MUX,
> -       .funcmask = BIT(10),
> -       .funcval = BIT(10),
> -};
> -
> -static const unsigned uart2_pins[] = { 48, 50, 56, 59 };
> -
> -static const struct sirfsoc_muxmask uart2_nostreamctrl_muxmask[] = {
> -       {
> -               .group = 1,
> -               .mask = BIT(16) | BIT(18),
> -       },
> -};
> -
> -static const struct sirfsoc_padmux uart2_nostreamctrl_padmux = {
> -       .muxmask_counts = ARRAY_SIZE(uart2_nostreamctrl_muxmask),
> -       .muxmask = uart2_nostreamctrl_muxmask,
> -};
> -
> -static const unsigned uart2_nostreamctrl_pins[] = { 48, 50 };
> -
> -static const struct sirfsoc_muxmask sdmmc3_muxmask[] = {
> -       {
> -               .group = 0,
> -               .mask = BIT(30) | BIT(31),
> -       }, {
> -               .group = 1,
> -               .mask = BIT(0) | BIT(1) | BIT(2) | BIT(3),
> -       },
> -};
> -
> -static const struct sirfsoc_padmux sdmmc3_padmux = {
> -       .muxmask_counts = ARRAY_SIZE(sdmmc3_muxmask),
> -       .muxmask = sdmmc3_muxmask,
> -       .ctrlreg = SIRFSOC_RSC_PIN_MUX,
> -       .funcmask = BIT(7),
> -       .funcval = 0,
> -};
> -
> -static const unsigned sdmmc3_pins[] = { 30, 31, 32, 33, 34, 35 };
> -
> -static const struct sirfsoc_muxmask spi0_muxmask[] = {
> -       {
> -               .group = 1,
> -               .mask = BIT(0) | BIT(1) | BIT(2) | BIT(3),
> -       },
> -};
> -
> -static const struct sirfsoc_padmux spi0_padmux = {
> -       .muxmask_counts = ARRAY_SIZE(spi0_muxmask),
> -       .muxmask = spi0_muxmask,
> -       .ctrlreg = SIRFSOC_RSC_PIN_MUX,
> -       .funcmask = BIT(7),
> -       .funcval = BIT(7),
> -};
> -
> -static const unsigned spi0_pins[] = { 32, 33, 34, 35 };
> -
> -static const struct sirfsoc_muxmask sdmmc4_muxmask[] = {
> -       {
> -               .group = 1,
> -               .mask = BIT(4) | BIT(5) | BIT(6) | BIT(7) | BIT(8) | BIT(9),
> -       },
> -};
> -
> -static const struct sirfsoc_padmux sdmmc4_padmux = {
> -       .muxmask_counts = ARRAY_SIZE(sdmmc4_muxmask),
> -       .muxmask = sdmmc4_muxmask,
> -};
> -
> -static const unsigned sdmmc4_pins[] = { 36, 37, 38, 39, 40, 41 };
> -
> -static const struct sirfsoc_muxmask cko1_muxmask[] = {
> -       {
> -               .group = 1,
> -               .mask = BIT(10),
> -       },
> -};
> -
> -static const struct sirfsoc_padmux cko1_padmux = {
> -       .muxmask_counts = ARRAY_SIZE(cko1_muxmask),
> -       .muxmask = cko1_muxmask,
> -       .ctrlreg = SIRFSOC_RSC_PIN_MUX,
> -       .funcmask = BIT(3),
> -       .funcval = 0,
> -};
> -
> -static const unsigned cko1_pins[] = { 42 };
> -
> -static const struct sirfsoc_muxmask i2s_mclk_muxmask[] = {
> -       {
> -               .group = 1,
> -               .mask = BIT(10),
> -       },
> -};
> -
> -static const struct sirfsoc_padmux i2s_mclk_padmux = {
> -       .muxmask_counts = ARRAY_SIZE(i2s_mclk_muxmask),
> -       .muxmask = i2s_mclk_muxmask,
> -       .ctrlreg = SIRFSOC_RSC_PIN_MUX,
> -       .funcmask = BIT(3),
> -       .funcval = BIT(3),
> -};
> -
> -static const unsigned i2s_mclk_pins[] = { 42 };
> -
> -static const struct sirfsoc_muxmask i2s_ext_clk_input_muxmask[] = {
> -       {
> -               .group = 1,
> -               .mask = BIT(19),
> -       },
> -};
> -
> -static const struct sirfsoc_padmux i2s_ext_clk_input_padmux = {
> -       .muxmask_counts = ARRAY_SIZE(i2s_ext_clk_input_muxmask),
> -       .muxmask = i2s_ext_clk_input_muxmask,
> -       .ctrlreg = SIRFSOC_RSC_PIN_MUX,
> -       .funcmask = BIT(2),
> -       .funcval = BIT(2),
> -};
> -
> -static const unsigned i2s_ext_clk_input_pins[] = { 51 };
> -
> -static const struct sirfsoc_muxmask i2s_muxmask[] = {
> -       {
> -               .group = 1,
> -               .mask = BIT(11) | BIT(12) | BIT(13) | BIT(14),
> -       },
> -};
> -
> -static const struct sirfsoc_padmux i2s_padmux = {
> -       .muxmask_counts = ARRAY_SIZE(i2s_muxmask),
> -       .muxmask = i2s_muxmask,
> -       .ctrlreg = SIRFSOC_RSC_PIN_MUX,
> -};
> -
> -static const unsigned i2s_pins[] = { 43, 44, 45, 46 };
> -
> -static const struct sirfsoc_muxmask i2s_no_din_muxmask[] = {
> -       {
> -               .group = 1,
> -               .mask = BIT(11) | BIT(12) | BIT(14),
> -       },
> -};
> -
> -static const struct sirfsoc_padmux i2s_no_din_padmux = {
> -       .muxmask_counts = ARRAY_SIZE(i2s_no_din_muxmask),
> -       .muxmask = i2s_no_din_muxmask,
> -       .ctrlreg = SIRFSOC_RSC_PIN_MUX,
> -};
> -
> -static const unsigned i2s_no_din_pins[] = { 43, 44, 46 };
> -
> -static const struct sirfsoc_muxmask i2s_6chn_muxmask[] = {
> -       {
> -               .group = 1,
> -               .mask = BIT(11) | BIT(12) | BIT(13) | BIT(14)
> -                       | BIT(23) | BIT(28),
> -       },
> -};
> -
> -static const struct sirfsoc_padmux i2s_6chn_padmux = {
> -       .muxmask_counts = ARRAY_SIZE(i2s_6chn_muxmask),
> -       .muxmask = i2s_6chn_muxmask,
> -       .ctrlreg = SIRFSOC_RSC_PIN_MUX,
> -       .funcmask = BIT(1) | BIT(9),
> -       .funcval = BIT(1) | BIT(9),
> -};
> -
> -static const unsigned i2s_6chn_pins[] = { 43, 44, 45, 46, 55, 60  };
> -
> -static const struct sirfsoc_muxmask ac97_muxmask[] = {
> -       {
> -               .group = 1,
> -               .mask = BIT(11) | BIT(12) | BIT(13) | BIT(14),
> -       },
> -};
> -
> -static const struct sirfsoc_padmux ac97_padmux = {
> -       .muxmask_counts = ARRAY_SIZE(ac97_muxmask),
> -       .muxmask = ac97_muxmask,
> -       .ctrlreg = SIRFSOC_RSC_PIN_MUX,
> -       .funcmask = BIT(8),
> -       .funcval = 0,
> -};
> -
> -static const unsigned ac97_pins[] = { 43, 44, 45, 46 };
> -
> -static const struct sirfsoc_muxmask spi1_muxmask[] = {
> -       {
> -               .group = 1,
> -               .mask = BIT(11) | BIT(12) | BIT(13) | BIT(14),
> -       },
> -};
> -
> -static const struct sirfsoc_padmux spi1_padmux = {
> -       .muxmask_counts = ARRAY_SIZE(spi1_muxmask),
> -       .muxmask = spi1_muxmask,
> -       .ctrlreg = SIRFSOC_RSC_PIN_MUX,
> -       .funcmask = BIT(8),
> -       .funcval = BIT(8),
> -};
> -
> -static const unsigned spi1_pins[] = { 43, 44, 45, 46 };
> -
> -static const struct sirfsoc_muxmask sdmmc1_muxmask[] = {
> -       {
> -               .group = 0,
> -               .mask = BIT(27) | BIT(28) | BIT(29),
> -       },
> -};
> -
> -static const struct sirfsoc_padmux sdmmc1_padmux = {
> -       .muxmask_counts = ARRAY_SIZE(sdmmc1_muxmask),
> -       .muxmask = sdmmc1_muxmask,
> -};
> -
> -static const unsigned sdmmc1_pins[] = { 27, 28, 29 };
> -
> -static const struct sirfsoc_muxmask gps_muxmask[] = {
> -       {
> -               .group = 0,
> -               .mask = BIT(24) | BIT(25) | BIT(26),
> -       },
> -};
> -
> -static const struct sirfsoc_padmux gps_padmux = {
> -       .muxmask_counts = ARRAY_SIZE(gps_muxmask),
> -       .muxmask = gps_muxmask,
> -       .ctrlreg = SIRFSOC_RSC_PIN_MUX,
> -       .funcmask = BIT(12) | BIT(13) | BIT(14),
> -       .funcval = BIT(12),
> -};
> -
> -static const unsigned gps_pins[] = { 24, 25, 26 };
> -
> -static const struct sirfsoc_muxmask sdmmc5_muxmask[] = {
> -       {
> -               .group = 0,
> -               .mask = BIT(24) | BIT(25) | BIT(26),
> -       },
> -};
> -
> -static const struct sirfsoc_padmux sdmmc5_padmux = {
> -       .muxmask_counts = ARRAY_SIZE(sdmmc5_muxmask),
> -       .muxmask = sdmmc5_muxmask,
> -       .ctrlreg = SIRFSOC_RSC_PIN_MUX,
> -       .funcmask = BIT(13) | BIT(14),
> -       .funcval = BIT(13) | BIT(14),
> -};
> -
> -static const unsigned sdmmc5_pins[] = { 24, 25, 26 };
> -
> -static const struct sirfsoc_muxmask usp0_muxmask[] = {
> -       {
> -               .group = 1,
> -               .mask = BIT(19) | BIT(20) | BIT(21) | BIT(22) | BIT(23),
> -       },
> -};
> -
> -static const struct sirfsoc_padmux usp0_padmux = {
> -       .muxmask_counts = ARRAY_SIZE(usp0_muxmask),
> -       .muxmask = usp0_muxmask,
> -       .ctrlreg = SIRFSOC_RSC_PIN_MUX,
> -       .funcmask = BIT(1) | BIT(2) | BIT(6) | BIT(9),
> -       .funcval = 0,
> -};
> -
> -static const unsigned usp0_pins[] = { 51, 52, 53, 54, 55 };
> -
> -static const struct sirfsoc_muxmask usp0_only_utfs_muxmask[] = {
> -       {
> -               .group = 1,
> -               .mask = BIT(19) | BIT(20) | BIT(21) | BIT(22),
> -       },
> -};
> -
> -static const struct sirfsoc_padmux usp0_only_utfs_padmux = {
> -       .muxmask_counts = ARRAY_SIZE(usp0_only_utfs_muxmask),
> -       .muxmask = usp0_only_utfs_muxmask,
> -       .ctrlreg = SIRFSOC_RSC_PIN_MUX,
> -       .funcmask = BIT(1) | BIT(2) | BIT(6),
> -       .funcval = 0,
> -};
> -
> -static const unsigned usp0_only_utfs_pins[] = { 51, 52, 53, 54 };
> -
> -static const struct sirfsoc_muxmask usp0_only_urfs_muxmask[] = {
> -       {
> -               .group = 1,
> -               .mask = BIT(19) | BIT(20) | BIT(21) | BIT(23),
> -       },
> -};
> -
> -static const struct sirfsoc_padmux usp0_only_urfs_padmux = {
> -       .muxmask_counts = ARRAY_SIZE(usp0_only_urfs_muxmask),
> -       .muxmask = usp0_only_urfs_muxmask,
> -       .ctrlreg = SIRFSOC_RSC_PIN_MUX,
> -       .funcmask = BIT(1) | BIT(2) | BIT(9),
> -       .funcval = 0,
> -};
> -
> -static const unsigned usp0_only_urfs_pins[] = { 51, 52, 53, 55 };
> -
> -static const struct sirfsoc_muxmask usp0_uart_nostreamctrl_muxmask[] = {
> -       {
> -               .group = 1,
> -               .mask = BIT(20) | BIT(21),
> -       },
> -};
> -
> -static const struct sirfsoc_padmux usp0_uart_nostreamctrl_padmux = {
> -       .muxmask_counts = ARRAY_SIZE(usp0_uart_nostreamctrl_muxmask),
> -       .muxmask = usp0_uart_nostreamctrl_muxmask,
> -};
> -
> -static const unsigned usp0_uart_nostreamctrl_pins[] = { 52, 53 };
> -
> -static const struct sirfsoc_muxmask usp1_muxmask[] = {
> -       {
> -               .group = 1,
> -               .mask = BIT(24) | BIT(25) | BIT(26) | BIT(27) | BIT(28),
> -       },
> -};
> -
> -static const struct sirfsoc_padmux usp1_padmux = {
> -       .muxmask_counts = ARRAY_SIZE(usp1_muxmask),
> -       .muxmask = usp1_muxmask,
> -       .ctrlreg = SIRFSOC_RSC_PIN_MUX,
> -       .funcmask = BIT(1) | BIT(9) | BIT(10) | BIT(11),
> -       .funcval = 0,
> -};
> -
> -static const unsigned usp1_pins[] = { 56, 57, 58, 59, 60 };
> -
> -static const struct sirfsoc_muxmask usp1_uart_nostreamctrl_muxmask[] = {
> -       {
> -               .group = 1,
> -               .mask = BIT(25) | BIT(26),
> -       },
> -};
> -
> -static const struct sirfsoc_padmux usp1_uart_nostreamctrl_padmux = {
> -       .muxmask_counts = ARRAY_SIZE(usp1_uart_nostreamctrl_muxmask),
> -       .muxmask = usp1_uart_nostreamctrl_muxmask,
> -};
> -
> -static const unsigned usp1_uart_nostreamctrl_pins[] = { 57, 58 };
> -
> -static const struct sirfsoc_muxmask usp2_muxmask[] = {
> -       {
> -               .group = 1,
> -               .mask = BIT(29) | BIT(30) | BIT(31),
> -       }, {
> -               .group = 2,
> -               .mask = BIT(0) | BIT(1),
> -       },
> -};
> -
> -static const struct sirfsoc_padmux usp2_padmux = {
> -       .muxmask_counts = ARRAY_SIZE(usp2_muxmask),
> -       .muxmask = usp2_muxmask,
> -       .ctrlreg = SIRFSOC_RSC_PIN_MUX,
> -       .funcmask = BIT(13) | BIT(14),
> -       .funcval = 0,
> -};
> -
> -static const unsigned usp2_pins[] = { 61, 62, 63, 64, 65 };
> -
> -static const struct sirfsoc_muxmask usp2_uart_nostreamctrl_muxmask[] = {
> -       {
> -               .group = 1,
> -               .mask = BIT(30) | BIT(31),
> -       },
> -};
> -
> -static const struct sirfsoc_padmux usp2_uart_nostreamctrl_padmux = {
> -       .muxmask_counts = ARRAY_SIZE(usp2_uart_nostreamctrl_muxmask),
> -       .muxmask = usp2_uart_nostreamctrl_muxmask,
> -};
> -
> -static const unsigned usp2_uart_nostreamctrl_pins[] = { 62, 63 };
> -
> -static const struct sirfsoc_muxmask nand_muxmask[] = {
> -       {
> -               .group = 2,
> -               .mask = BIT(2) | BIT(3) | BIT(28) | BIT(29) | BIT(30),
> -       },
> -};
> -
> -static const struct sirfsoc_padmux nand_padmux = {
> -       .muxmask_counts = ARRAY_SIZE(nand_muxmask),
> -       .muxmask = nand_muxmask,
> -       .ctrlreg = SIRFSOC_RSC_PIN_MUX,
> -       .funcmask = BIT(5),
> -       .funcval = 0,
> -};
> -
> -static const unsigned nand_pins[] = { 64, 65, 92, 93, 94 };
> -
> -static const struct sirfsoc_padmux sdmmc0_padmux = {
> -       .muxmask_counts = 0,
> -       .ctrlreg = SIRFSOC_RSC_PIN_MUX,
> -       .funcmask = BIT(5),
> -       .funcval = 0,
> -};
> -
> -static const unsigned sdmmc0_pins[] = { };
> -
> -static const struct sirfsoc_muxmask sdmmc2_muxmask[] = {
> -       {
> -               .group = 2,
> -               .mask = BIT(2) | BIT(3),
> -       },
> -};
> -
> -static const struct sirfsoc_padmux sdmmc2_padmux = {
> -       .muxmask_counts = ARRAY_SIZE(sdmmc2_muxmask),
> -       .muxmask = sdmmc2_muxmask,
> -       .ctrlreg = SIRFSOC_RSC_PIN_MUX,
> -       .funcmask = BIT(5),
> -       .funcval = BIT(5),
> -};
> -
> -static const unsigned sdmmc2_pins[] = { 66, 67 };
> -
> -static const struct sirfsoc_muxmask cko0_muxmask[] = {
> -       {
> -               .group = 2,
> -               .mask = BIT(14),
> -       },
> -};
> -
> -static const struct sirfsoc_padmux cko0_padmux = {
> -       .muxmask_counts = ARRAY_SIZE(cko0_muxmask),
> -       .muxmask = cko0_muxmask,
> -};
> -
> -static const unsigned cko0_pins[] = { 78 };
> -
> -static const struct sirfsoc_muxmask vip_muxmask[] = {
> -       {
> -               .group = 2,
> -               .mask = BIT(15) | BIT(16) | BIT(17) | BIT(18) | BIT(19)
> -                       | BIT(20) | BIT(21) | BIT(22) | BIT(23) | BIT(24) |
> -                       BIT(25),
> -       },
> -};
> -
> -static const struct sirfsoc_padmux vip_padmux = {
> -       .muxmask_counts = ARRAY_SIZE(vip_muxmask),
> -       .muxmask = vip_muxmask,
> -       .ctrlreg = SIRFSOC_RSC_PIN_MUX,
> -       .funcmask = BIT(0),
> -       .funcval = 0,
> -};
> -
> -static const unsigned vip_pins[] = { 79, 80, 81, 82, 83, 84, 85, 86, 87,
> -       88, 89 };
> -
> -static const struct sirfsoc_muxmask i2c0_muxmask[] = {
> -       {
> -               .group = 2,
> -               .mask = BIT(26) | BIT(27),
> -       },
> -};
> -
> -static const struct sirfsoc_padmux i2c0_padmux = {
> -       .muxmask_counts = ARRAY_SIZE(i2c0_muxmask),
> -       .muxmask = i2c0_muxmask,
> -};
> -
> -static const unsigned i2c0_pins[] = { 90, 91 };
> -
> -static const struct sirfsoc_muxmask i2c1_muxmask[] = {
> -       {
> -               .group = 0,
> -               .mask = BIT(13) | BIT(15),
> -       },
> -};
> -
> -static const struct sirfsoc_padmux i2c1_padmux = {
> -       .muxmask_counts = ARRAY_SIZE(i2c1_muxmask),
> -       .muxmask = i2c1_muxmask,
> -};
> -
> -static const unsigned i2c1_pins[] = { 13, 15 };
> -
> -static const struct sirfsoc_muxmask viprom_muxmask[] = {
> -       {
> -               .group = 2,
> -               .mask = BIT(15) | BIT(16) | BIT(17) | BIT(18) | BIT(19)
> -                       | BIT(20) | BIT(21) | BIT(22) | BIT(23) | BIT(24) |
> -                       BIT(25),
> -       }, {
> -               .group = 0,
> -               .mask = BIT(12),
> -       },
> -};
> -
> -static const struct sirfsoc_padmux viprom_padmux = {
> -       .muxmask_counts = ARRAY_SIZE(viprom_muxmask),
> -       .muxmask = viprom_muxmask,
> -       .ctrlreg = SIRFSOC_RSC_PIN_MUX,
> -       .funcmask = BIT(0),
> -       .funcval = BIT(0),
> -};
> -
> -static const unsigned viprom_pins[] = { 12, 79, 80, 81, 82, 83, 84, 85, 86,
> -       87, 88, 89 };
> -
> -static const struct sirfsoc_muxmask pwm0_muxmask[] = {
> -       {
> -               .group = 0,
> -               .mask = BIT(4),
> -       },
> -};
> -
> -static const struct sirfsoc_padmux pwm0_padmux = {
> -       .muxmask_counts = ARRAY_SIZE(pwm0_muxmask),
> -       .muxmask = pwm0_muxmask,
> -       .ctrlreg = SIRFSOC_RSC_PIN_MUX,
> -       .funcmask = BIT(12),
> -       .funcval = 0,
> -};
> -
> -static const unsigned pwm0_pins[] = { 4 };
> -
> -static const struct sirfsoc_muxmask pwm1_muxmask[] = {
> -       {
> -               .group = 0,
> -               .mask = BIT(5),
> -       },
> -};
> -
> -static const struct sirfsoc_padmux pwm1_padmux = {
> -       .muxmask_counts = ARRAY_SIZE(pwm1_muxmask),
> -       .muxmask = pwm1_muxmask,
> -};
> -
> -static const unsigned pwm1_pins[] = { 5 };
> -
> -static const struct sirfsoc_muxmask pwm2_muxmask[] = {
> -       {
> -               .group = 0,
> -               .mask = BIT(6),
> -       },
> -};
> -
> -static const struct sirfsoc_padmux pwm2_padmux = {
> -       .muxmask_counts = ARRAY_SIZE(pwm2_muxmask),
> -       .muxmask = pwm2_muxmask,
> -};
> -
> -static const unsigned pwm2_pins[] = { 6 };
> -
> -static const struct sirfsoc_muxmask pwm3_muxmask[] = {
> -       {
> -               .group = 0,
> -               .mask = BIT(7),
> -       },
> -};
> -
> -static const struct sirfsoc_padmux pwm3_padmux = {
> -       .muxmask_counts = ARRAY_SIZE(pwm3_muxmask),
> -       .muxmask = pwm3_muxmask,
> -};
> -
> -static const unsigned pwm3_pins[] = { 7 };
> -
> -static const struct sirfsoc_muxmask warm_rst_muxmask[] = {
> -       {
> -               .group = 0,
> -               .mask = BIT(8),
> -       },
> -};
> -
> -static const struct sirfsoc_padmux warm_rst_padmux = {
> -       .muxmask_counts = ARRAY_SIZE(warm_rst_muxmask),
> -       .muxmask = warm_rst_muxmask,
> -};
> -
> -static const unsigned warm_rst_pins[] = { 8 };
> -
> -static const struct sirfsoc_muxmask usb0_utmi_drvbus_muxmask[] = {
> -       {
> -               .group = 1,
> -               .mask = BIT(22),
> -       },
> -};
> -static const struct sirfsoc_padmux usb0_utmi_drvbus_padmux = {
> -       .muxmask_counts = ARRAY_SIZE(usb0_utmi_drvbus_muxmask),
> -       .muxmask = usb0_utmi_drvbus_muxmask,
> -       .ctrlreg = SIRFSOC_RSC_PIN_MUX,
> -       .funcmask = BIT(6),
> -       .funcval = BIT(6), /* refer to PAD_UTMI_DRVVBUS0_ENABLE */
> -};
> -
> -static const unsigned usb0_utmi_drvbus_pins[] = { 54 };
> -
> -static const struct sirfsoc_muxmask usb1_utmi_drvbus_muxmask[] = {
> -       {
> -               .group = 1,
> -               .mask = BIT(27),
> -       },
> -};
> -
> -static const struct sirfsoc_padmux usb1_utmi_drvbus_padmux = {
> -       .muxmask_counts = ARRAY_SIZE(usb1_utmi_drvbus_muxmask),
> -       .muxmask = usb1_utmi_drvbus_muxmask,
> -       .ctrlreg = SIRFSOC_RSC_PIN_MUX,
> -       .funcmask = BIT(11),
> -       .funcval = BIT(11), /* refer to PAD_UTMI_DRVVBUS1_ENABLE */
> -};
> -
> -static const unsigned usb1_utmi_drvbus_pins[] = { 59 };
> -
> -static const struct sirfsoc_padmux usb1_dp_dn_padmux = {
> -       .muxmask_counts = 0,
> -       .ctrlreg = SIRFSOC_RSC_USB_UART_SHARE,
> -       .funcmask = BIT(2),
> -       .funcval = BIT(2),
> -};
> -
> -static const unsigned usb1_dp_dn_pins[] = { 115, 116 };
> -
> -static const struct sirfsoc_padmux uart1_route_io_usb1_padmux = {
> -       .muxmask_counts = 0,
> -       .ctrlreg = SIRFSOC_RSC_USB_UART_SHARE,
> -       .funcmask = BIT(2),
> -       .funcval = 0,
> -};
> -
> -static const unsigned uart1_route_io_usb1_pins[] = { 115, 116 };
> -
> -static const struct sirfsoc_muxmask pulse_count_muxmask[] = {
> -       {
> -               .group = 0,
> -               .mask = BIT(9) | BIT(10) | BIT(11),
> -       },
> -};
> -
> -static const struct sirfsoc_padmux pulse_count_padmux = {
> -       .muxmask_counts = ARRAY_SIZE(pulse_count_muxmask),
> -       .muxmask = pulse_count_muxmask,
> -};
> -
> -static const unsigned pulse_count_pins[] = { 9, 10, 11 };
> -
> -static const struct sirfsoc_pin_group sirfsoc_pin_groups[] = {
> -       SIRFSOC_PIN_GROUP("lcd_16bitsgrp", lcd_16bits_pins),
> -       SIRFSOC_PIN_GROUP("lcd_18bitsgrp", lcd_18bits_pins),
> -       SIRFSOC_PIN_GROUP("lcd_24bitsgrp", lcd_24bits_pins),
> -       SIRFSOC_PIN_GROUP("lcdrom_grp", lcdrom_pins),
> -       SIRFSOC_PIN_GROUP("uart0grp", uart0_pins),
> -       SIRFSOC_PIN_GROUP("uart0_nostreamctrlgrp", uart0_nostreamctrl_pins),
> -       SIRFSOC_PIN_GROUP("uart1grp", uart1_pins),
> -       SIRFSOC_PIN_GROUP("uart2grp", uart2_pins),
> -       SIRFSOC_PIN_GROUP("uart2_nostreamctrlgrp", uart2_nostreamctrl_pins),
> -       SIRFSOC_PIN_GROUP("usp0grp", usp0_pins),
> -       SIRFSOC_PIN_GROUP("usp0_uart_nostreamctrl_grp",
> -                                       usp0_uart_nostreamctrl_pins),
> -       SIRFSOC_PIN_GROUP("usp0_only_utfs_grp", usp0_only_utfs_pins),
> -       SIRFSOC_PIN_GROUP("usp0_only_urfs_grp", usp0_only_urfs_pins),
> -       SIRFSOC_PIN_GROUP("usp1grp", usp1_pins),
> -       SIRFSOC_PIN_GROUP("usp1_uart_nostreamctrl_grp",
> -                                       usp1_uart_nostreamctrl_pins),
> -       SIRFSOC_PIN_GROUP("usp2grp", usp2_pins),
> -       SIRFSOC_PIN_GROUP("usp2_uart_nostreamctrl_grp",
> -                                       usp2_uart_nostreamctrl_pins),
> -       SIRFSOC_PIN_GROUP("i2c0grp", i2c0_pins),
> -       SIRFSOC_PIN_GROUP("i2c1grp", i2c1_pins),
> -       SIRFSOC_PIN_GROUP("pwm0grp", pwm0_pins),
> -       SIRFSOC_PIN_GROUP("pwm1grp", pwm1_pins),
> -       SIRFSOC_PIN_GROUP("pwm2grp", pwm2_pins),
> -       SIRFSOC_PIN_GROUP("pwm3grp", pwm3_pins),
> -       SIRFSOC_PIN_GROUP("vipgrp", vip_pins),
> -       SIRFSOC_PIN_GROUP("vipromgrp", viprom_pins),
> -       SIRFSOC_PIN_GROUP("warm_rstgrp", warm_rst_pins),
> -       SIRFSOC_PIN_GROUP("cko0grp", cko0_pins),
> -       SIRFSOC_PIN_GROUP("cko1grp", cko1_pins),
> -       SIRFSOC_PIN_GROUP("sdmmc0grp", sdmmc0_pins),
> -       SIRFSOC_PIN_GROUP("sdmmc1grp", sdmmc1_pins),
> -       SIRFSOC_PIN_GROUP("sdmmc2grp", sdmmc2_pins),
> -       SIRFSOC_PIN_GROUP("sdmmc3grp", sdmmc3_pins),
> -       SIRFSOC_PIN_GROUP("sdmmc4grp", sdmmc4_pins),
> -       SIRFSOC_PIN_GROUP("sdmmc5grp", sdmmc5_pins),
> -       SIRFSOC_PIN_GROUP("usb0_utmi_drvbusgrp", usb0_utmi_drvbus_pins),
> -       SIRFSOC_PIN_GROUP("usb1_utmi_drvbusgrp", usb1_utmi_drvbus_pins),
> -       SIRFSOC_PIN_GROUP("usb1_dp_dngrp", usb1_dp_dn_pins),
> -       SIRFSOC_PIN_GROUP("uart1_route_io_usb1grp", uart1_route_io_usb1_pins),
> -       SIRFSOC_PIN_GROUP("pulse_countgrp", pulse_count_pins),
> -       SIRFSOC_PIN_GROUP("i2smclkgrp", i2s_mclk_pins),
> -       SIRFSOC_PIN_GROUP("i2s_ext_clk_inputgrp", i2s_ext_clk_input_pins),
> -       SIRFSOC_PIN_GROUP("i2sgrp", i2s_pins),
> -       SIRFSOC_PIN_GROUP("i2s_no_dingrp", i2s_no_din_pins),
> -       SIRFSOC_PIN_GROUP("i2s_6chngrp", i2s_6chn_pins),
> -       SIRFSOC_PIN_GROUP("ac97grp", ac97_pins),
> -       SIRFSOC_PIN_GROUP("nandgrp", nand_pins),
> -       SIRFSOC_PIN_GROUP("spi0grp", spi0_pins),
> -       SIRFSOC_PIN_GROUP("spi1grp", spi1_pins),
> -       SIRFSOC_PIN_GROUP("gpsgrp", gps_pins),
> -};
> -
> -static const char * const lcd_16bitsgrp[] = { "lcd_16bitsgrp" };
> -static const char * const lcd_18bitsgrp[] = { "lcd_18bitsgrp" };
> -static const char * const lcd_24bitsgrp[] = { "lcd_24bitsgrp" };
> -static const char * const lcdromgrp[] = { "lcdromgrp" };
> -static const char * const uart0grp[] = { "uart0grp" };
> -static const char * const uart0_nostreamctrlgrp[] = { "uart0_nostreamctrlgrp" };
> -static const char * const uart1grp[] = { "uart1grp" };
> -static const char * const uart2grp[] = { "uart2grp" };
> -static const char * const uart2_nostreamctrlgrp[] = { "uart2_nostreamctrlgrp" };
> -static const char * const usp0grp[] = { "usp0grp" };
> -static const char * const usp0_uart_nostreamctrl_grp[] = {
> -       "usp0_uart_nostreamctrl_grp"
> -};
> -static const char * const usp0_only_utfs_grp[] = { "usp0_only_utfs_grp" };
> -static const char * const usp0_only_urfs_grp[] = { "usp0_only_urfs_grp" };
> -static const char * const usp1grp[] = { "usp1grp" };
> -static const char * const usp1_uart_nostreamctrl_grp[] = {
> -       "usp1_uart_nostreamctrl_grp"
> -};
> -static const char * const usp2grp[] = { "usp2grp" };
> -static const char * const usp2_uart_nostreamctrl_grp[] = {
> -       "usp2_uart_nostreamctrl_grp"
> -};
> -static const char * const i2c0grp[] = { "i2c0grp" };
> -static const char * const i2c1grp[] = { "i2c1grp" };
> -static const char * const pwm0grp[] = { "pwm0grp" };
> -static const char * const pwm1grp[] = { "pwm1grp" };
> -static const char * const pwm2grp[] = { "pwm2grp" };
> -static const char * const pwm3grp[] = { "pwm3grp" };
> -static const char * const vipgrp[] = { "vipgrp" };
> -static const char * const vipromgrp[] = { "vipromgrp" };
> -static const char * const warm_rstgrp[] = { "warm_rstgrp" };
> -static const char * const cko0grp[] = { "cko0grp" };
> -static const char * const cko1grp[] = { "cko1grp" };
> -static const char * const sdmmc0grp[] = { "sdmmc0grp" };
> -static const char * const sdmmc1grp[] = { "sdmmc1grp" };
> -static const char * const sdmmc2grp[] = { "sdmmc2grp" };
> -static const char * const sdmmc3grp[] = { "sdmmc3grp" };
> -static const char * const sdmmc4grp[] = { "sdmmc4grp" };
> -static const char * const sdmmc5grp[] = { "sdmmc5grp" };
> -static const char * const usb0_utmi_drvbusgrp[] = { "usb0_utmi_drvbusgrp" };
> -static const char * const usb1_utmi_drvbusgrp[] = { "usb1_utmi_drvbusgrp" };
> -static const char * const usb1_dp_dngrp[] = { "usb1_dp_dngrp" };
> -static const char * const
> -       uart1_route_io_usb1grp[] = { "uart1_route_io_usb1grp" };
> -static const char * const pulse_countgrp[] = { "pulse_countgrp" };
> -static const char * const i2smclkgrp[] = { "i2smclkgrp" };
> -static const char * const i2s_ext_clk_inputgrp[] = { "i2s_ext_clk_inputgrp" };
> -static const char * const i2sgrp[] = { "i2sgrp" };
> -static const char * const i2s_no_dingrp[] = { "i2s_no_dingrp" };
> -static const char * const i2s_6chngrp[] = { "i2s_6chngrp" };
> -static const char * const ac97grp[] = { "ac97grp" };
> -static const char * const nandgrp[] = { "nandgrp" };
> -static const char * const spi0grp[] = { "spi0grp" };
> -static const char * const spi1grp[] = { "spi1grp" };
> -static const char * const gpsgrp[] = { "gpsgrp" };
> -
> -static const struct sirfsoc_pmx_func sirfsoc_pmx_functions[] = {
> -       SIRFSOC_PMX_FUNCTION("lcd_16bits", lcd_16bitsgrp, lcd_16bits_padmux),
> -       SIRFSOC_PMX_FUNCTION("lcd_18bits", lcd_18bitsgrp, lcd_18bits_padmux),
> -       SIRFSOC_PMX_FUNCTION("lcd_24bits", lcd_24bitsgrp, lcd_24bits_padmux),
> -       SIRFSOC_PMX_FUNCTION("lcdrom", lcdromgrp, lcdrom_padmux),
> -       SIRFSOC_PMX_FUNCTION("uart0", uart0grp, uart0_padmux),
> -       SIRFSOC_PMX_FUNCTION("uart0_nostreamctrl",
> -               uart0_nostreamctrlgrp, uart0_nostreamctrl_padmux),
> -       SIRFSOC_PMX_FUNCTION("uart1", uart1grp, uart1_padmux),
> -       SIRFSOC_PMX_FUNCTION("uart2", uart2grp, uart2_padmux),
> -       SIRFSOC_PMX_FUNCTION("uart2_nostreamctrl",
> -               uart2_nostreamctrlgrp, uart2_nostreamctrl_padmux),
> -       SIRFSOC_PMX_FUNCTION("usp0", usp0grp, usp0_padmux),
> -       SIRFSOC_PMX_FUNCTION("usp0_uart_nostreamctrl",
> -               usp0_uart_nostreamctrl_grp, usp0_uart_nostreamctrl_padmux),
> -       SIRFSOC_PMX_FUNCTION("usp0_only_utfs",
> -               usp0_only_utfs_grp, usp0_only_utfs_padmux),
> -       SIRFSOC_PMX_FUNCTION("usp0_only_urfs",
> -               usp0_only_urfs_grp, usp0_only_urfs_padmux),
> -       SIRFSOC_PMX_FUNCTION("usp1", usp1grp, usp1_padmux),
> -       SIRFSOC_PMX_FUNCTION("usp1_uart_nostreamctrl",
> -               usp1_uart_nostreamctrl_grp, usp1_uart_nostreamctrl_padmux),
> -       SIRFSOC_PMX_FUNCTION("usp2", usp2grp, usp2_padmux),
> -       SIRFSOC_PMX_FUNCTION("usp2_uart_nostreamctrl",
> -               usp2_uart_nostreamctrl_grp, usp2_uart_nostreamctrl_padmux),
> -       SIRFSOC_PMX_FUNCTION("i2c0", i2c0grp, i2c0_padmux),
> -       SIRFSOC_PMX_FUNCTION("i2c1", i2c1grp, i2c1_padmux),
> -       SIRFSOC_PMX_FUNCTION("pwm0", pwm0grp, pwm0_padmux),
> -       SIRFSOC_PMX_FUNCTION("pwm1", pwm1grp, pwm1_padmux),
> -       SIRFSOC_PMX_FUNCTION("pwm2", pwm2grp, pwm2_padmux),
> -       SIRFSOC_PMX_FUNCTION("pwm3", pwm3grp, pwm3_padmux),
> -       SIRFSOC_PMX_FUNCTION("vip", vipgrp, vip_padmux),
> -       SIRFSOC_PMX_FUNCTION("viprom", vipromgrp, viprom_padmux),
> -       SIRFSOC_PMX_FUNCTION("warm_rst", warm_rstgrp, warm_rst_padmux),
> -       SIRFSOC_PMX_FUNCTION("cko0", cko0grp, cko0_padmux),
> -       SIRFSOC_PMX_FUNCTION("cko1", cko1grp, cko1_padmux),
> -       SIRFSOC_PMX_FUNCTION("sdmmc0", sdmmc0grp, sdmmc0_padmux),
> -       SIRFSOC_PMX_FUNCTION("sdmmc1", sdmmc1grp, sdmmc1_padmux),
> -       SIRFSOC_PMX_FUNCTION("sdmmc2", sdmmc2grp, sdmmc2_padmux),
> -       SIRFSOC_PMX_FUNCTION("sdmmc3", sdmmc3grp, sdmmc3_padmux),
> -       SIRFSOC_PMX_FUNCTION("sdmmc4", sdmmc4grp, sdmmc4_padmux),
> -       SIRFSOC_PMX_FUNCTION("sdmmc5", sdmmc5grp, sdmmc5_padmux),
> -       SIRFSOC_PMX_FUNCTION("usb0_utmi_drvbus",
> -               usb0_utmi_drvbusgrp, usb0_utmi_drvbus_padmux),
> -       SIRFSOC_PMX_FUNCTION("usb1_utmi_drvbus",
> -               usb1_utmi_drvbusgrp, usb1_utmi_drvbus_padmux),
> -       SIRFSOC_PMX_FUNCTION("usb1_dp_dn", usb1_dp_dngrp, usb1_dp_dn_padmux),
> -       SIRFSOC_PMX_FUNCTION("uart1_route_io_usb1",
> -               uart1_route_io_usb1grp, uart1_route_io_usb1_padmux),
> -       SIRFSOC_PMX_FUNCTION("pulse_count", pulse_countgrp, pulse_count_padmux),
> -       SIRFSOC_PMX_FUNCTION("i2s_mclk", i2smclkgrp, i2s_mclk_padmux),
> -       SIRFSOC_PMX_FUNCTION("i2s_ext_clk_input", i2s_ext_clk_inputgrp,
> -                                               i2s_ext_clk_input_padmux),
> -       SIRFSOC_PMX_FUNCTION("i2s", i2sgrp, i2s_padmux),
> -       SIRFSOC_PMX_FUNCTION("i2s_no_din", i2s_no_dingrp, i2s_no_din_padmux),
> -       SIRFSOC_PMX_FUNCTION("i2s_6chn", i2s_6chngrp, i2s_6chn_padmux),
> -       SIRFSOC_PMX_FUNCTION("ac97", ac97grp, ac97_padmux),
> -       SIRFSOC_PMX_FUNCTION("nand", nandgrp, nand_padmux),
> -       SIRFSOC_PMX_FUNCTION("spi0", spi0grp, spi0_padmux),
> -       SIRFSOC_PMX_FUNCTION("spi1", spi1grp, spi1_padmux),
> -       SIRFSOC_PMX_FUNCTION("gps", gpsgrp, gps_padmux),
> -};
> -
> -struct sirfsoc_pinctrl_data prima2_pinctrl_data = {
> -       (struct pinctrl_pin_desc *)sirfsoc_pads,
> -       ARRAY_SIZE(sirfsoc_pads),
> -       (struct sirfsoc_pin_group *)sirfsoc_pin_groups,
> -       ARRAY_SIZE(sirfsoc_pin_groups),
> -       (struct sirfsoc_pmx_func *)sirfsoc_pmx_functions,
> -       ARRAY_SIZE(sirfsoc_pmx_functions),
> -};
> -
> diff --git a/drivers/pinctrl/sirf/pinctrl-sirf.c b/drivers/pinctrl/sirf/pinctrl-sirf.c
> deleted file mode 100644
> index 63a287d5795f..000000000000
> --- a/drivers/pinctrl/sirf/pinctrl-sirf.c
> +++ /dev/null
> @@ -1,894 +0,0 @@
> -// SPDX-License-Identifier: GPL-2.0-or-later
> -/*
> - * pinmux driver for CSR SiRFprimaII
> - *
> - * Authors:
> - *     Rongjun Ying <rongjun.ying@csr.com>
> - *     Yuping Luo <yuping.luo@csr.com>
> - *     Barry Song <baohua.song@csr.com>
> - *
> - * Copyright (c) 2011 - 2014 Cambridge Silicon Radio Limited, a CSR plc group
> - * company.
> - */
> -
> -#include <linux/init.h>
> -#include <linux/irq.h>
> -#include <linux/platform_device.h>
> -#include <linux/io.h>
> -#include <linux/slab.h>
> -#include <linux/err.h>
> -#include <linux/pinctrl/pinctrl.h>
> -#include <linux/pinctrl/pinmux.h>
> -#include <linux/pinctrl/consumer.h>
> -#include <linux/pinctrl/machine.h>
> -#include <linux/of.h>
> -#include <linux/of_address.h>
> -#include <linux/of_device.h>
> -#include <linux/of_platform.h>
> -#include <linux/bitops.h>
> -#include <linux/gpio/driver.h>
> -#include <linux/of_gpio.h>
> -
> -#include "pinctrl-sirf.h"
> -
> -#define DRIVER_NAME "pinmux-sirf"
> -
> -struct sirfsoc_gpio_bank {
> -       int id;
> -       int parent_irq;
> -       spinlock_t lock;
> -};
> -
> -struct sirfsoc_gpio_chip {
> -       struct of_mm_gpio_chip chip;
> -       struct sirfsoc_gpio_bank sgpio_bank[SIRFSOC_GPIO_NO_OF_BANKS];
> -       spinlock_t lock;
> -};
> -
> -static struct sirfsoc_pin_group *sirfsoc_pin_groups;
> -static int sirfsoc_pingrp_cnt;
> -
> -static int sirfsoc_get_groups_count(struct pinctrl_dev *pctldev)
> -{
> -       return sirfsoc_pingrp_cnt;
> -}
> -
> -static const char *sirfsoc_get_group_name(struct pinctrl_dev *pctldev,
> -                                      unsigned selector)
> -{
> -       return sirfsoc_pin_groups[selector].name;
> -}
> -
> -static int sirfsoc_get_group_pins(struct pinctrl_dev *pctldev,
> -                               unsigned selector,
> -                               const unsigned **pins,
> -                               unsigned *num_pins)
> -{
> -       *pins = sirfsoc_pin_groups[selector].pins;
> -       *num_pins = sirfsoc_pin_groups[selector].num_pins;
> -       return 0;
> -}
> -
> -static void sirfsoc_pin_dbg_show(struct pinctrl_dev *pctldev,
> -                               struct seq_file *s, unsigned offset)
> -{
> -       seq_printf(s, " " DRIVER_NAME);
> -}
> -
> -static int sirfsoc_dt_node_to_map(struct pinctrl_dev *pctldev,
> -                                struct device_node *np_config,
> -                                struct pinctrl_map **map, unsigned *num_maps)
> -{
> -       struct sirfsoc_pmx *spmx = pinctrl_dev_get_drvdata(pctldev);
> -       struct device_node *np;
> -       struct property *prop;
> -       const char *function, *group;
> -       int ret, index = 0, count = 0;
> -
> -       /* calculate number of maps required */
> -       for_each_child_of_node(np_config, np) {
> -               ret = of_property_read_string(np, "sirf,function", &function);
> -               if (ret < 0) {
> -                       of_node_put(np);
> -                       return ret;
> -               }
> -
> -               ret = of_property_count_strings(np, "sirf,pins");
> -               if (ret < 0) {
> -                       of_node_put(np);
> -                       return ret;
> -               }
> -
> -               count += ret;
> -       }
> -
> -       if (!count) {
> -               dev_err(spmx->dev, "No child nodes passed via DT\n");
> -               return -ENODEV;
> -       }
> -
> -       *map = kcalloc(count, sizeof(**map), GFP_KERNEL);
> -       if (!*map)
> -               return -ENOMEM;
> -
> -       for_each_child_of_node(np_config, np) {
> -               of_property_read_string(np, "sirf,function", &function);
> -               of_property_for_each_string(np, "sirf,pins", prop, group) {
> -                       (*map)[index].type = PIN_MAP_TYPE_MUX_GROUP;
> -                       (*map)[index].data.mux.group = group;
> -                       (*map)[index].data.mux.function = function;
> -                       index++;
> -               }
> -       }
> -
> -       *num_maps = count;
> -
> -       return 0;
> -}
> -
> -static void sirfsoc_dt_free_map(struct pinctrl_dev *pctldev,
> -               struct pinctrl_map *map, unsigned num_maps)
> -{
> -       kfree(map);
> -}
> -
> -static const struct pinctrl_ops sirfsoc_pctrl_ops = {
> -       .get_groups_count = sirfsoc_get_groups_count,
> -       .get_group_name = sirfsoc_get_group_name,
> -       .get_group_pins = sirfsoc_get_group_pins,
> -       .pin_dbg_show = sirfsoc_pin_dbg_show,
> -       .dt_node_to_map = sirfsoc_dt_node_to_map,
> -       .dt_free_map = sirfsoc_dt_free_map,
> -};
> -
> -static struct sirfsoc_pmx_func *sirfsoc_pmx_functions;
> -static int sirfsoc_pmxfunc_cnt;
> -
> -static void sirfsoc_pinmux_endisable(struct sirfsoc_pmx *spmx,
> -                                       unsigned selector, bool enable)
> -{
> -       int i;
> -       const struct sirfsoc_padmux *mux =
> -               sirfsoc_pmx_functions[selector].padmux;
> -       const struct sirfsoc_muxmask *mask = mux->muxmask;
> -
> -       for (i = 0; i < mux->muxmask_counts; i++) {
> -               u32 muxval;
> -               muxval = readl(spmx->gpio_virtbase +
> -                       SIRFSOC_GPIO_PAD_EN(mask[i].group));
> -               if (enable)
> -                       muxval = muxval & ~mask[i].mask;
> -               else
> -                       muxval = muxval | mask[i].mask;
> -               writel(muxval, spmx->gpio_virtbase +
> -                       SIRFSOC_GPIO_PAD_EN(mask[i].group));
> -       }
> -
> -       if (mux->funcmask && enable) {
> -               u32 func_en_val;
> -
> -               func_en_val =
> -                       readl(spmx->rsc_virtbase + mux->ctrlreg);
> -               func_en_val =
> -                       (func_en_val & ~mux->funcmask) | (mux->funcval);
> -               writel(func_en_val, spmx->rsc_virtbase + mux->ctrlreg);
> -       }
> -}
> -
> -static int sirfsoc_pinmux_set_mux(struct pinctrl_dev *pmxdev,
> -                               unsigned selector,
> -                               unsigned group)
> -{
> -       struct sirfsoc_pmx *spmx;
> -
> -       spmx = pinctrl_dev_get_drvdata(pmxdev);
> -       sirfsoc_pinmux_endisable(spmx, selector, true);
> -
> -       return 0;
> -}
> -
> -static int sirfsoc_pinmux_get_funcs_count(struct pinctrl_dev *pmxdev)
> -{
> -       return sirfsoc_pmxfunc_cnt;
> -}
> -
> -static const char *sirfsoc_pinmux_get_func_name(struct pinctrl_dev *pctldev,
> -                                         unsigned selector)
> -{
> -       return sirfsoc_pmx_functions[selector].name;
> -}
> -
> -static int sirfsoc_pinmux_get_groups(struct pinctrl_dev *pctldev,
> -                               unsigned selector,
> -                               const char * const **groups,
> -                               unsigned * const num_groups)
> -{
> -       *groups = sirfsoc_pmx_functions[selector].groups;
> -       *num_groups = sirfsoc_pmx_functions[selector].num_groups;
> -       return 0;
> -}
> -
> -static int sirfsoc_pinmux_request_gpio(struct pinctrl_dev *pmxdev,
> -       struct pinctrl_gpio_range *range, unsigned offset)
> -{
> -       struct sirfsoc_pmx *spmx;
> -
> -       int group = range->id;
> -
> -       u32 muxval;
> -
> -       spmx = pinctrl_dev_get_drvdata(pmxdev);
> -
> -       muxval = readl(spmx->gpio_virtbase +
> -               SIRFSOC_GPIO_PAD_EN(group));
> -       muxval = muxval | (1 << (offset - range->pin_base));
> -       writel(muxval, spmx->gpio_virtbase +
> -               SIRFSOC_GPIO_PAD_EN(group));
> -
> -       return 0;
> -}
> -
> -static const struct pinmux_ops sirfsoc_pinmux_ops = {
> -       .set_mux = sirfsoc_pinmux_set_mux,
> -       .get_functions_count = sirfsoc_pinmux_get_funcs_count,
> -       .get_function_name = sirfsoc_pinmux_get_func_name,
> -       .get_function_groups = sirfsoc_pinmux_get_groups,
> -       .gpio_request_enable = sirfsoc_pinmux_request_gpio,
> -};
> -
> -static struct pinctrl_desc sirfsoc_pinmux_desc = {
> -       .name = DRIVER_NAME,
> -       .pctlops = &sirfsoc_pctrl_ops,
> -       .pmxops = &sirfsoc_pinmux_ops,
> -       .owner = THIS_MODULE,
> -};
> -
> -static void __iomem *sirfsoc_rsc_of_iomap(void)
> -{
> -       const struct of_device_id rsc_ids[]  = {
> -               { .compatible = "sirf,prima2-rsc" },
> -               {}
> -       };
> -       struct device_node *np;
> -
> -