Re: [PATCH] PCI: cadence: respond to received PTM Requests

[Christian Gmeiner <christian.gmeiner@gmail.com>]

Hi

Am Mo., 31. Jan. 2022 um 23:05 Uhr schrieb Bjorn Helgaas <helgaas@kernel.org>:
>
> Update subject line to match previous conventions ("git log --oneline
> drivers/pci/controller/cadence/pcie-cadence-host.c" to see).
>

Sure

> On Mon, Jan 31, 2022 at 01:08:27PM +0100, Christian Gmeiner wrote:
> > This enables the Controller [RP] to automatically respond
> > with Response/ResponseD messages.
>
> Update to imperative mood, e.g., "Enable Controller to ...":
>
>   https://chris.beams.io/posts/git-commit/
>   https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/process/maintainer-tip.rst?id=v5.16#n134
>

Sure


> > Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
> > ---
> >  drivers/pci/controller/cadence/pcie-cadence-host.c | 10 ++++++++++
> >  drivers/pci/controller/cadence/pcie-cadence.h      |  4 ++++
> >  2 files changed, 14 insertions(+)
> >
> > diff --git a/drivers/pci/controller/cadence/pcie-cadence-host.c b/drivers/pci/controller/cadence/pcie-cadence-host.c
> > index fb96d37a135c..940c7dd701d6 100644
> > --- a/drivers/pci/controller/cadence/pcie-cadence-host.c
> > +++ b/drivers/pci/controller/cadence/pcie-cadence-host.c
> > @@ -123,6 +123,14 @@ static int cdns_pcie_retrain(struct cdns_pcie *pcie)
> >       return ret;
> >  }
> >
> > +static void cdns_pcie_host_enable_ptm_response(struct cdns_pcie *pcie)
> > +{
> > +     u32 val;
> > +
> > +     val = cdns_pcie_readl(pcie, CDNS_PCIE_LM_PTM_CTRL);
> > +     cdns_pcie_writel(pcie, CDNS_PCIE_LM_PTM_CTRL, val | CDNS_PCIE_LM_TPM_CTRL_PTMRSEN);
>
> I assume this is some device-specific enable bit that is effectively
> ANDed with PCI_PTM_CTRL_ENABLE in the Precision Time Measurement
> Capability?
>

That is a great question to which I have no answer yet. All I have is
a PCIe based FPGA that wants a working PTM.
My target platform is an TI AM642 and I do not have a full picture of
the pci layering used (cadence, pci-j721e and pci-keystone). All I
have is the AM64x Technical Reference Manual (SPRUIM2C – SEPTEMBER
2021): https://www.ti.com/lit/pdf/SPRUIM2
There I found this register and the meaning of that bit.

I think it is a good idea to get some people with knowledge on board.
So I will add Kishon Vijay Abraham I and Swapnil Jakhade to CC.

> > +}
> > +
> >  static int cdns_pcie_host_start_link(struct cdns_pcie_rc *rc)
> >  {
> >       struct cdns_pcie *pcie = &rc->pcie;
> > @@ -501,6 +509,8 @@ int cdns_pcie_host_setup(struct cdns_pcie_rc *rc)
> >       if (rc->quirk_detect_quiet_flag)
> >               cdns_pcie_detect_quiet_min_delay_set(&rc->pcie);
> >
> > +     cdns_pcie_host_enable_ptm_response(pcie);
> > +
> >       ret = cdns_pcie_start_link(pcie);
> >       if (ret) {
> >               dev_err(dev, "Failed to start link\n");
> > diff --git a/drivers/pci/controller/cadence/pcie-cadence.h b/drivers/pci/controller/cadence/pcie-cadence.h
> > index c8a27b6290ce..9510ea513b8a 100644
> > --- a/drivers/pci/controller/cadence/pcie-cadence.h
> > +++ b/drivers/pci/controller/cadence/pcie-cadence.h
> > @@ -116,6 +116,10 @@
> >  #define LM_RC_BAR_CFG_APERTURE(bar, aperture)                \
> >                                       (((aperture) - 2) << ((bar) * 8))
> >
> > +/* PTM Control Register */
> > +#define CDNS_PCIE_LM_PTM_CTRL        (CDNS_PCIE_LM_BASE + 0x0DA8)
> > +#define CDNS_PCIE_LM_TPM_CTRL_PTMRSEN        BIT(17)
> > +
> >  /*
> >   * Endpoint Function Registers (PCI configuration space for endpoint functions)
> >   */
> > --
> > 2.34.1
> >



--
greets
--
Christian Gmeiner, MSc

https://christian-gmeiner.info/privacypolicy