From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D7F32C433F5 for ; Wed, 23 Feb 2022 07:53:41 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id C4B6083A6A; Wed, 23 Feb 2022 08:53:39 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="S2BUNGok"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 8976583A8D; Wed, 23 Feb 2022 08:53:38 +0100 (CET) Received: from mail-ed1-x529.google.com (mail-ed1-x529.google.com [IPv6:2a00:1450:4864:20::529]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 077C683A48 for ; Wed, 23 Feb 2022 08:53:35 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=christian.gmeiner@gmail.com Received: by mail-ed1-x529.google.com with SMTP id z22so42806042edd.1 for ; Tue, 22 Feb 2022 23:53:35 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=DiJ6cysC7XB4uzy4JmyG1Cf0yMixWVnwPXcEZKQdSEQ=; b=S2BUNGokqHCwz9wsac4a+HuoH/CX0KaGXOuRsRInOhrjzAiqlsz26EeqK4mgavTySK c0vnhKywlEmsv0QSamKLl0yOgGrQCXOBd7YQKDR3muuEJiubCW/GGFAqKGOawJ6+oUb+ hsgzdlIT4D9w0QND14xy4ecv3mLyV5KwvdzYi15vF+UzSUF5PbZJPdW1OgKpzYMx3YM9 NywDwryiYe84wKuasUj+tpYu76fIhVn4WnB8zbgivPGOnUUI7tPqjxfnRKmIDqG+0Oek VvS27EtAOSuHXfriqB+qk6avxs+6hmJrzE9iwgYumckkDXqro6UgZblIGy1BTamzKLZ8 fAqA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=DiJ6cysC7XB4uzy4JmyG1Cf0yMixWVnwPXcEZKQdSEQ=; b=hKNVhbGrcoXtgZ64SG2duygdOFT4MnkdIh7iCYdDvM7TmMxd8pWyV7f5z2AXBm1Sza FdTHGYKxVVveIEjBBRMaAZ2djx/Cb1dc9ByQhYMyleWU697EXQYw/RxtJK4ik+TBQ5WV qr2H1NQRwkBaSLTVrFkxTtG7NUD5a72hl5TZ6jd+SjgQ2sq33be2e6cBo1/zYFKHN0Rr vjIjg6oE0yDdISTDBOAk0xgkMR9DKMLK0K1JtdQpbxK8NxtaohyAmbCZUT8xE/O0ieiG Jw9bHDbhyXsOl+5WmACP4MyH8YUzmkwEGpgJTm1dETW3F3Ug9DNITSWssSjBxdgIRYei 1r9A== X-Gm-Message-State: AOAM531uQLkmb8yDlO1Nrv9vr/jNqBAss2toVvV0oRqS6SosbUvc/RS2 Bej0716XEO83pqa6ud39BQ1lMQmsUfzX8P5J6Js= X-Google-Smtp-Source: ABdhPJz/tR+iA3TaTVYf2SKHeso9RPUvYoQu5nOcYgpy1v+a9F2NZC5gSaTLc2CawS8cEPjWyeW8hKf8uinCAqFJJPU= X-Received: by 2002:a05:6402:358f:b0:410:e245:f665 with SMTP id y15-20020a056402358f00b00410e245f665mr30260927edc.212.1645602814447; Tue, 22 Feb 2022 23:53:34 -0800 (PST) MIME-Version: 1.0 References: <20220202171023.6687-1-hnagalla@ti.com> In-Reply-To: <20220202171023.6687-1-hnagalla@ti.com> From: Christian Gmeiner Date: Wed, 23 Feb 2022 08:53:23 +0100 Message-ID: Subject: Re: [PATCH 0/5] Add ESM driver support for AM64x R5 To: Hari Nagalla Cc: U-Boot Mailing List , Nishanth Menon Content-Type: text/plain; charset="UTF-8" X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.5 at phobos.denx.de X-Virus-Status: Clean Hi Hari Am Mi., 2. Feb. 2022 um 18:50 Uhr schrieb Hari Nagalla : > > AM64x devices have a main ESM and a MCU ESM. The ESM driver enables > routing of the error events from various sources to different processors > or to reset hardware logic. Only the MCU ESM's high output can trigger > reset logic. The main RTI0 WWDT output can be routed to the MCU > highoutput to trigger reset through the main ESM. For this reset to > occur CTRLMMR_MCU_RST_CTRL:MCU_ESM_ERROR_RESET_EN_Z is set to '0'. > > AM64x Technical Reference Manual - https://www.ti.com/lit/pdf/spruim2 Are there any plans to send out a V2 of this patch series? If not I can jump in (as I really want to see in U-Boot sooner than later). -- greets -- Christian Gmeiner, MSc https://christian-gmeiner.info/privacypolicy