From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2955FC4332F for ; Thu, 3 Feb 2022 21:28:40 +0000 (UTC) Received: from localhost ([::1]:37562 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nFjeh-0007Sg-1d for qemu-devel@archiver.kernel.org; Thu, 03 Feb 2022 16:28:39 -0500 Received: from eggs.gnu.org ([209.51.188.92]:41780) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nFitX-0006ZE-6F for qemu-devel@nongnu.org; Thu, 03 Feb 2022 15:39:55 -0500 Received: from [2a00:1450:4864:20::52e] (port=34314 helo=mail-ed1-x52e.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nFitU-0005B4-I9 for qemu-devel@nongnu.org; Thu, 03 Feb 2022 15:39:54 -0500 Received: by mail-ed1-x52e.google.com with SMTP id w20so4633362edc.1 for ; Thu, 03 Feb 2022 12:39:51 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=Cn3JBOPTkmzWDDsQcJOrN9rQ7hIGilL1vixPseHwSKY=; b=tQUCT14j4CoRFoRa7iKEkX4AaZRbqEaRoUAeSEj83hfVYk4QUzfdr7YVcYxm4no8Yi M4ubjNwUbME7O/0guJOgeVk8V6nspwKbm95hjuUtmMCPcqTuvq8kR8nHHToG6p5u9lxf q44Y8LN2Cc/nZBfhm1gtrDifH8seCfSlHTc27mAspyp/irdiiAcKeUSoB8h3e5RWnp7p JmOagO/Sym51xCmLvjB8esKVitpV3HQnfcBu+VmRjJyZ7WS4X8eGQ+gR+KGadkAwryNq MfY/TYlByO1Fl0k1nJw/XOiOFq+icgYKrn0uCaZ9gCzp8yNP2wvm7jcagdQ4HaixqbFq qp+g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=Cn3JBOPTkmzWDDsQcJOrN9rQ7hIGilL1vixPseHwSKY=; b=MMLsJhnobzYQkwfCLvyo/cEvr50PwRY06Rbu7h2EsMWYCMW/aOUlY3W8FRjaq6lP6k AUcovGDAkh2/Ba4gzONzfZ3hiFfVTl/G9c2wDpRS0/nvlk7xNaNAG8e9pkxTXJ/i1mYs 6d74qR+aZvzI8eaGcUbw6jBRifnTA+E21nkB+GM9xTAyn8TSAc5OLgB7Zst1/2a7P2Pl l6PYe5TFdKbbXouS0tlQquUC7X86HvinD5secAeIP/zUPKGQIWVzJ2JpUr9h/Fl+P0XC vBA4Bs4TL+QGyUW39bkCvuxJTU8daPu366fsAFphTEAwdY/qrYGA2dNSOT+Uy/XphvnY pKZQ== X-Gm-Message-State: AOAM5320eaeplcd7D6QrTo46bFtEWJTE2X0bJYXsP1zsnW+bNvnINkDi dSbp5j/4ndCmTHFNHJM4I2z8PK9N47pvVHKXbtUT3g== X-Google-Smtp-Source: ABdhPJwcyNH9cX59BRjdGSW1Z78sJjisPQ0a6DEOX+Pa9C3W83DmdMLzySRlY1ypjsWdHxLs4lPl8RbHv9+8fB/4rBY= X-Received: by 2002:a05:6402:19a9:: with SMTP id o9mr37099905edz.295.1643920790299; Thu, 03 Feb 2022 12:39:50 -0800 (PST) MIME-Version: 1.0 References: <20220120200735.2739543-1-atishp@rivosinc.com> <20220120200735.2739543-5-atishp@rivosinc.com> <2696860.3DGziXre4Q@diego> In-Reply-To: <2696860.3DGziXre4Q@diego> From: Atish Kumar Patra Date: Thu, 3 Feb 2022 12:39:39 -0800 Message-ID: Subject: Re: [RFC 4/5] target/riscv: Add *envcfg* CSRs support To: =?UTF-8?Q?Heiko_St=C3=BCbner?= Content-Type: multipart/alternative; boundary="000000000000beb7f705d7232237" X-Host-Lookup-Failed: Reverse DNS lookup failed for 2a00:1450:4864:20::52e (failed) Received-SPF: pass client-ip=2a00:1450:4864:20::52e; envelope-from=atishp@rivosinc.com; helo=mail-ed1-x52e.google.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, HTML_MESSAGE=0.001, PDS_HP_HELO_NORDNS=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "open list:RISC-V" , Anup Patel , Bin Meng , "qemu-devel@nongnu.org Developers" , Alistair Francis , Palmer Dabbelt Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" --000000000000beb7f705d7232237 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Thu, Feb 3, 2022 at 4:23 AM Heiko St=C3=BCbner wrote: > Hi Atish, > > Am Donnerstag, 20. Januar 2022, 21:07:34 CET schrieb Atish Patra: > > The RISC-V privileged specification v1.12 defines few execution > > environment configuration CSRs that can be used enable/disable > > extensions per privilege levels. > > > > Add the basic support for these CSRs. > > > > Signed-off-by: Atish Patra > > --- > > target/riscv/cpu.h | 8 ++++ > > target/riscv/cpu_bits.h | 31 +++++++++++++++ > > target/riscv/csr.c | 84 +++++++++++++++++++++++++++++++++++++++++ > > target/riscv/machine.c | 26 +++++++++++++ > > 4 files changed, 149 insertions(+) > > > > diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h > > index f6f90b5cbd52..afb237c2313b 100644 > > --- a/target/riscv/cpu_bits.h > > +++ b/target/riscv/cpu_bits.h > > [...] > > > @@ -578,6 +589,26 @@ typedef enum RISCVException { > > #define PM_EXT_CLEAN 0x00000002ULL > > #define PM_EXT_DIRTY 0x00000003ULL > > > > +/* Execution enviornment configuration bits */ > > +#define MENVCFG_FIOM (1 << 0) > > > +#define MENVCFG_CBE 0x30000ULL > > Looking both at the cmo spec as well as the most recent privileged spec > (draft) the field is called CBIE it seems. > > Also the shift looks wrong. Both cmo as well as privileged spec show > it at bits [5:4] and _not_ [17:16]. > > This looks like a typo from my side. These bits are reserved in the spec! Apologies for such a silly mistake. Fixed it in v2. > Also wouldn't doing it like (_UL(3) << 4) be better to catch such things? > > Of course. > > +#define MENVCFG_CBCFE (1 << 6) > > +#define MENVCFG_CBZE (1 << 7) > > +#define MENVCFG_PBMTE (1 << 62) > > +#define MENVCFG_STCE (1 << 63) > > + > > +#define SENVCFG_FIOM MENVCFG_FIOM > > +#define SENVCFG_CBE MENVCFG_CBE > > +#define SENVCFG_CBCFE MENVCFG_CBCFE > > +#define SENVCFG_CBZE MENVCFG_CBZE > > + > > +#define HENVCFG_FIOM MENVCFG_FIOM > > +#define HENVCFG_CBE MENVCFG_CBE > > +#define HENVCFG_CBCFE MENVCFG_CBCFE > > +#define HENVCFG_CBZE MENVCFG_CBZE > > +#define HENVCFG_PBMTE MENVCFG_PBMTE > > +#define HENVCFG_STCE MENVCFG_STCE > > + > > /* Offsets for every pair of control bits per each priv level */ > > #define XS_OFFSET 0ULL > > #define U_OFFSET 2ULL > > > Heiko > > > --000000000000beb7f705d7232237 Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable


=
On Thu, Feb 3, 2022 at 4:23 AM Heiko = St=C3=BCbner <heiko@sntech.de>= wrote:
Hi Atish= ,

Am Donnerstag, 20. Januar 2022, 21:07:34 CET schrieb Atish Patra:
> The RISC-V privileged specification v1.12 defines few execution
> environment configuration CSRs that can be used enable/disable
> extensions per privilege levels.
>
> Add the basic support for these CSRs.
>
> Signed-off-by: Atish Patra <atishp@rivosinc.com>
> ---
>=C2=A0 target/riscv/cpu.h=C2=A0 =C2=A0 =C2=A0 |=C2=A0 8 ++++
>=C2=A0 target/riscv/cpu_bits.h | 31 +++++++++++++++
>=C2=A0 target/riscv/csr.c=C2=A0 =C2=A0 =C2=A0 | 84 ++++++++++++++++++++= +++++++++++++++++++++
>=C2=A0 target/riscv/machine.c=C2=A0 | 26 +++++++++++++
>=C2=A0 4 files changed, 149 insertions(+)
>
> diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
> index f6f90b5cbd52..afb237c2313b 100644
> --- a/target/riscv/cpu_bits.h
> +++ b/target/riscv/cpu_bits.h

[...]

> @@ -578,6 +589,26 @@ typedef enum RISCVException {
>=C2=A0 #define PM_EXT_CLEAN=C2=A0 =C2=A0 0x00000002ULL
>=C2=A0 #define PM_EXT_DIRTY=C2=A0 =C2=A0 0x00000003ULL
>=C2=A0
> +/* Execution enviornment configuration bits */
> +#define MENVCFG_FIOM=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0(1 << 0)

> +#define MENVCFG_CBE=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 0x30000ULL

Looking both at the cmo spec as well as the most recent privileged spec
(draft) the field is called CBIE it seems.

Also the shift looks wrong. Both cmo as well as privileged spec show
it at bits [5:4] and _not_ [17:16].


This looks like a typo from my side. T= hese bits are reserved in the spec!
Apologies for such a silly mi= stake. Fixed it in v2.
=C2=A0
Also wouldn't doing it like (_UL(3) << 4) be better to catch such= things?


Of course.
=C2=A0
> +#define MENVCFG_CBCFE=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 (1 << 6)
> +#define MENVCFG_CBZE=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0(1 << 7)
> +#define MENVCFG_PBMTE=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 (1 << 62)
> +#define MENVCFG_STCE=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0(1 << 63)
> +
> +#define SENVCFG_FIOM=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0MENVCFG_FIOM
> +#define SENVCFG_CBE=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 MENVCFG_CBE
> +#define SENVCFG_CBCFE=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 MENVCFG_CBCFE
> +#define SENVCFG_CBZE=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0MENVCFG_CBZE
> +
> +#define HENVCFG_FIOM=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0MENVCFG_FIOM
> +#define HENVCFG_CBE=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 MENVCFG_CBE
> +#define HENVCFG_CBCFE=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 MENVCFG_CBCFE
> +#define HENVCFG_CBZE=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0MENVCFG_CBZE
> +#define HENVCFG_PBMTE=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 MENVCFG_PBMTE
> +#define HENVCFG_STCE=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0MENVCFG_STCE
> +
>=C2=A0 /* Offsets for every pair of control bits per each priv level */=
>=C2=A0 #define XS_OFFSET=C2=A0 =C2=A0 0ULL
>=C2=A0 #define U_OFFSET=C2=A0 =C2=A0 =C2=A02ULL


Heiko


--000000000000beb7f705d7232237-- From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1nFitZ-0006am-6y for mharc-qemu-riscv@gnu.org; Thu, 03 Feb 2022 15:39:57 -0500 Received: from eggs.gnu.org ([209.51.188.92]:41778) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nFitW-0006XZ-Iw for qemu-riscv@nongnu.org; Thu, 03 Feb 2022 15:39:54 -0500 Received: from [2a00:1450:4864:20::531] (port=39829 helo=mail-ed1-x531.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nFitU-0005B5-HI for qemu-riscv@nongnu.org; Thu, 03 Feb 2022 15:39:54 -0500 Received: by mail-ed1-x531.google.com with SMTP id u18so8479274edt.6 for ; Thu, 03 Feb 2022 12:39:51 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=Cn3JBOPTkmzWDDsQcJOrN9rQ7hIGilL1vixPseHwSKY=; b=tQUCT14j4CoRFoRa7iKEkX4AaZRbqEaRoUAeSEj83hfVYk4QUzfdr7YVcYxm4no8Yi M4ubjNwUbME7O/0guJOgeVk8V6nspwKbm95hjuUtmMCPcqTuvq8kR8nHHToG6p5u9lxf q44Y8LN2Cc/nZBfhm1gtrDifH8seCfSlHTc27mAspyp/irdiiAcKeUSoB8h3e5RWnp7p JmOagO/Sym51xCmLvjB8esKVitpV3HQnfcBu+VmRjJyZ7WS4X8eGQ+gR+KGadkAwryNq MfY/TYlByO1Fl0k1nJw/XOiOFq+icgYKrn0uCaZ9gCzp8yNP2wvm7jcagdQ4HaixqbFq qp+g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=Cn3JBOPTkmzWDDsQcJOrN9rQ7hIGilL1vixPseHwSKY=; b=ahj0wq2eS1Q5xFT6pdSPaIc72I9SKYxBwl8gT84BpaznsylyChZqjvKl4tdMdzqrw4 axW14BdVaF409b/MjPGH6uvhKKVrEnnNMpSb2Sj6b7toGutxAdMrqhsF2iVd2TZi4lee qVZG5l50AeFPjhPs3QqGre3TFod2OaliWKtS661/14lGk+21TBTKICXK+MnYXf7y5211 F3aO5m81dbCP08cOFZ5hqE745AkGMtOl3TXCcNFk6YK+iekjqhjSKWw99RqH1jRg1VSm 7uIGwCsibyoXHyRilIN3853UK+FtofVrLMMQTYjtkha4SFkmZa5VmL3Pi79hi8wK6Kxw nxIg== X-Gm-Message-State: AOAM531Jbg+/L9wmOv0GH4pUdv6DXB/ruVdy59W1+CIj32XowObDpPzb U3hgyEbqHxSa49o84SM4o2uyVK0fI9QU0lW/vT7bwQ== X-Google-Smtp-Source: ABdhPJwcyNH9cX59BRjdGSW1Z78sJjisPQ0a6DEOX+Pa9C3W83DmdMLzySRlY1ypjsWdHxLs4lPl8RbHv9+8fB/4rBY= X-Received: by 2002:a05:6402:19a9:: with SMTP id o9mr37099905edz.295.1643920790299; Thu, 03 Feb 2022 12:39:50 -0800 (PST) MIME-Version: 1.0 References: <20220120200735.2739543-1-atishp@rivosinc.com> <20220120200735.2739543-5-atishp@rivosinc.com> <2696860.3DGziXre4Q@diego> In-Reply-To: <2696860.3DGziXre4Q@diego> From: Atish Kumar Patra Date: Thu, 3 Feb 2022 12:39:39 -0800 Message-ID: Subject: Re: [RFC 4/5] target/riscv: Add *envcfg* CSRs support To: =?UTF-8?Q?Heiko_St=C3=BCbner?= Cc: "qemu-devel@nongnu.org Developers" , "open list:RISC-V" , Anup Patel , Bin Meng , Alistair Francis , Palmer Dabbelt Content-Type: multipart/alternative; boundary="000000000000beb7f705d7232237" X-Host-Lookup-Failed: Reverse DNS lookup failed for 2a00:1450:4864:20::531 (failed) Received-SPF: pass client-ip=2a00:1450:4864:20::531; envelope-from=atishp@rivosinc.com; helo=mail-ed1-x531.google.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, HTML_MESSAGE=0.001, PDS_HP_HELO_NORDNS=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 03 Feb 2022 20:39:55 -0000 --000000000000beb7f705d7232237 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Thu, Feb 3, 2022 at 4:23 AM Heiko St=C3=BCbner wrote: > Hi Atish, > > Am Donnerstag, 20. Januar 2022, 21:07:34 CET schrieb Atish Patra: > > The RISC-V privileged specification v1.12 defines few execution > > environment configuration CSRs that can be used enable/disable > > extensions per privilege levels. > > > > Add the basic support for these CSRs. > > > > Signed-off-by: Atish Patra > > --- > > target/riscv/cpu.h | 8 ++++ > > target/riscv/cpu_bits.h | 31 +++++++++++++++ > > target/riscv/csr.c | 84 +++++++++++++++++++++++++++++++++++++++++ > > target/riscv/machine.c | 26 +++++++++++++ > > 4 files changed, 149 insertions(+) > > > > diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h > > index f6f90b5cbd52..afb237c2313b 100644 > > --- a/target/riscv/cpu_bits.h > > +++ b/target/riscv/cpu_bits.h > > [...] > > > @@ -578,6 +589,26 @@ typedef enum RISCVException { > > #define PM_EXT_CLEAN 0x00000002ULL > > #define PM_EXT_DIRTY 0x00000003ULL > > > > +/* Execution enviornment configuration bits */ > > +#define MENVCFG_FIOM (1 << 0) > > > +#define MENVCFG_CBE 0x30000ULL > > Looking both at the cmo spec as well as the most recent privileged spec > (draft) the field is called CBIE it seems. > > Also the shift looks wrong. Both cmo as well as privileged spec show > it at bits [5:4] and _not_ [17:16]. > > This looks like a typo from my side. These bits are reserved in the spec! Apologies for such a silly mistake. Fixed it in v2. > Also wouldn't doing it like (_UL(3) << 4) be better to catch such things? > > Of course. > > +#define MENVCFG_CBCFE (1 << 6) > > +#define MENVCFG_CBZE (1 << 7) > > +#define MENVCFG_PBMTE (1 << 62) > > +#define MENVCFG_STCE (1 << 63) > > + > > +#define SENVCFG_FIOM MENVCFG_FIOM > > +#define SENVCFG_CBE MENVCFG_CBE > > +#define SENVCFG_CBCFE MENVCFG_CBCFE > > +#define SENVCFG_CBZE MENVCFG_CBZE > > + > > +#define HENVCFG_FIOM MENVCFG_FIOM > > +#define HENVCFG_CBE MENVCFG_CBE > > +#define HENVCFG_CBCFE MENVCFG_CBCFE > > +#define HENVCFG_CBZE MENVCFG_CBZE > > +#define HENVCFG_PBMTE MENVCFG_PBMTE > > +#define HENVCFG_STCE MENVCFG_STCE > > + > > /* Offsets for every pair of control bits per each priv level */ > > #define XS_OFFSET 0ULL > > #define U_OFFSET 2ULL > > > Heiko > > > --000000000000beb7f705d7232237 Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable


=
On Thu, Feb 3, 2022 at 4:23 AM Heiko = St=C3=BCbner <heiko@sntech.de>= wrote:
Hi Atish= ,

Am Donnerstag, 20. Januar 2022, 21:07:34 CET schrieb Atish Patra:
> The RISC-V privileged specification v1.12 defines few execution
> environment configuration CSRs that can be used enable/disable
> extensions per privilege levels.
>
> Add the basic support for these CSRs.
>
> Signed-off-by: Atish Patra <atishp@rivosinc.com>
> ---
>=C2=A0 target/riscv/cpu.h=C2=A0 =C2=A0 =C2=A0 |=C2=A0 8 ++++
>=C2=A0 target/riscv/cpu_bits.h | 31 +++++++++++++++
>=C2=A0 target/riscv/csr.c=C2=A0 =C2=A0 =C2=A0 | 84 ++++++++++++++++++++= +++++++++++++++++++++
>=C2=A0 target/riscv/machine.c=C2=A0 | 26 +++++++++++++
>=C2=A0 4 files changed, 149 insertions(+)
>
> diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
> index f6f90b5cbd52..afb237c2313b 100644
> --- a/target/riscv/cpu_bits.h
> +++ b/target/riscv/cpu_bits.h

[...]

> @@ -578,6 +589,26 @@ typedef enum RISCVException {
>=C2=A0 #define PM_EXT_CLEAN=C2=A0 =C2=A0 0x00000002ULL
>=C2=A0 #define PM_EXT_DIRTY=C2=A0 =C2=A0 0x00000003ULL
>=C2=A0
> +/* Execution enviornment configuration bits */
> +#define MENVCFG_FIOM=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0(1 << 0)

> +#define MENVCFG_CBE=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 0x30000ULL

Looking both at the cmo spec as well as the most recent privileged spec
(draft) the field is called CBIE it seems.

Also the shift looks wrong. Both cmo as well as privileged spec show
it at bits [5:4] and _not_ [17:16].


This looks like a typo from my side. T= hese bits are reserved in the spec!
Apologies for such a silly mi= stake. Fixed it in v2.
=C2=A0
Also wouldn't doing it like (_UL(3) << 4) be better to catch such= things?


Of course.
=C2=A0
> +#define MENVCFG_CBCFE=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 (1 << 6)
> +#define MENVCFG_CBZE=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0(1 << 7)
> +#define MENVCFG_PBMTE=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 (1 << 62)
> +#define MENVCFG_STCE=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0(1 << 63)
> +
> +#define SENVCFG_FIOM=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0MENVCFG_FIOM
> +#define SENVCFG_CBE=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 MENVCFG_CBE
> +#define SENVCFG_CBCFE=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 MENVCFG_CBCFE
> +#define SENVCFG_CBZE=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0MENVCFG_CBZE
> +
> +#define HENVCFG_FIOM=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0MENVCFG_FIOM
> +#define HENVCFG_CBE=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 MENVCFG_CBE
> +#define HENVCFG_CBCFE=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 MENVCFG_CBCFE
> +#define HENVCFG_CBZE=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0MENVCFG_CBZE
> +#define HENVCFG_PBMTE=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 MENVCFG_PBMTE
> +#define HENVCFG_STCE=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0MENVCFG_STCE
> +
>=C2=A0 /* Offsets for every pair of control bits per each priv level */=
>=C2=A0 #define XS_OFFSET=C2=A0 =C2=A0 0ULL
>=C2=A0 #define U_OFFSET=C2=A0 =C2=A0 =C2=A02ULL


Heiko


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