From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 40C79C19F2B for ; Wed, 3 Aug 2022 21:11:04 +0000 (UTC) Received: from localhost ([::1]:58066 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oJLdv-0001BK-23 for qemu-devel@archiver.kernel.org; Wed, 03 Aug 2022 17:11:03 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:49688) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oJLcX-0000J9-P6 for qemu-devel@nongnu.org; Wed, 03 Aug 2022 17:09:37 -0400 Received: from mail-pj1-x1033.google.com ([2607:f8b0:4864:20::1033]:50855) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oJLcS-0002wz-6Y for qemu-devel@nongnu.org; Wed, 03 Aug 2022 17:09:37 -0400 Received: by mail-pj1-x1033.google.com with SMTP id gj1so2688411pjb.0 for ; Wed, 03 Aug 2022 14:09:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc; bh=EnvekbMMffrQdWpRsGlrVRjoL+KVGraVLCP/5qQFtQI=; b=VKwwK67n5+kNir0gKsElfB80051Y/77xmahCzkSbW6ErSzGvoZEMv8zmbFn/t7Zs3g yZYVvi13jnlniA+M7Eem5z9BNFbzpcpJWhoPtXE8qD2Q4VrunYArA0CU53uSo9L9Z9TW 9jsJXnQdi3enT31XKUISrxVFJtvcUfJmYHpSWLWtUHpc+kvjZn03gMFHpymgZe8rxCkG BxJU9P6QN6pnmwIAPRDV4ppKCORrydO6QIE1+2KIGT+1HwX3MBb75T65VQBuN1TWHJTQ udjWyiHprBRa4fK7cLn9aj4d8gNvvy1V5x4R//uQTUJwvKMz/AaXmMTXlN22JYi8fmnD bF1w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc; bh=EnvekbMMffrQdWpRsGlrVRjoL+KVGraVLCP/5qQFtQI=; b=FaNWATHWKOXX2IbJVLGY//B8Mh+Gt3Frmoek2nasHMw9pV2HymaqqhAUo1BS13C3b3 7ZMBJDKGjE/82lb/zu1iPAe7GxErJcVfNApCsdDk/ditr7iLhTe3tQU9zF/Y63M0jcli Sw+f36wnJk//sfSVn0HTEsPNJTArPVXu8My/CFOZ70rYtm+EdfkfnC8/Kfr1PWCOobe5 9ciUi9+20MH4MiT5jzDpnntDN9EJ5p9HopRyk0hlr5RN/PGwsRim73dtx4l0/FGGKU+J 94FXVbZCpDzZIcTr7jWvDxyUTAFw1XZDbWRggqBvTMXJJ+HB5r24+0RlL9mH8Y0+NkBW 9e/g== X-Gm-Message-State: ACgBeo1rIsfHt6h0DaWjjZySSpQVfjypM9syYczypmRyoUFq4xBkrm8c Cf7K42MCF1gpTLX8V9JcyVh3YJPQFSEkF/H/NnTTyg== X-Google-Smtp-Source: AA6agR7pu5QzlJ8sQwzFLh+qqVkbJse1N6AOUimnVS3tJ2SmZQhjK4eWHmEnPl2vKaYkDRaeLPE1Reh3KOG09//AVs8= X-Received: by 2002:a17:90a:9409:b0:1f0:e171:f2bd with SMTP id r9-20020a17090a940900b001f0e171f2bdmr6541780pjo.245.1659560970410; Wed, 03 Aug 2022 14:09:30 -0700 (PDT) MIME-Version: 1.0 References: <20220803082516.2271344-1-atishp@rivosinc.com> <20220803082516.2271344-3-atishp@rivosinc.com> In-Reply-To: From: Atish Kumar Patra Date: Wed, 3 Aug 2022 14:09:19 -0700 Message-ID: Subject: Re: [PATCH v7 2/3] target/riscv: Add stimecmp support To: Weiwei Li Cc: qemu-devel@nongnu.org, Alistair Francis , Bin Meng , Palmer Dabbelt , qemu-riscv@nongnu.org Content-Type: multipart/alternative; boundary="0000000000001ff8b805e55ca6e7" Received-SPF: pass client-ip=2607:f8b0:4864:20::1033; envelope-from=atishp@rivosinc.com; helo=mail-pj1-x1033.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, HTML_MESSAGE=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" --0000000000001ff8b805e55ca6e7 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Wed, Aug 3, 2022 at 1:42 AM Weiwei Li wrote: > > =E5=9C=A8 2022/8/3 =E4=B8=8B=E5=8D=884:25, Atish Patra =E5=86=99=E9=81=93= : > > stimecmp allows the supervisor mode to update stimecmp CSR directly > > to program the next timer interrupt. This CSR is part of the Sstc > > extension which was ratified recently. > > > > Signed-off-by: Atish Patra > > --- > > target/riscv/cpu.c | 12 +++++ > > target/riscv/cpu.h | 5 ++ > > target/riscv/cpu_bits.h | 4 ++ > > target/riscv/csr.c | 81 +++++++++++++++++++++++++++++++ > > target/riscv/machine.c | 1 + > > target/riscv/meson.build | 3 +- > > target/riscv/time_helper.c | 98 +++++++++++++++++++++++++++++++++++++= + > > target/riscv/time_helper.h | 30 ++++++++++++ > > 8 files changed, 233 insertions(+), 1 deletion(-) > > create mode 100644 target/riscv/time_helper.c > > create mode 100644 target/riscv/time_helper.h > > > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > > index d4635c7df46b..e0c3e786849f 100644 > > --- a/target/riscv/cpu.c > > +++ b/target/riscv/cpu.c > > @@ -23,6 +23,7 @@ > > #include "qemu/log.h" > > #include "cpu.h" > > #include "internals.h" > > +#include "time_helper.h" > > #include "exec/exec-all.h" > > #include "qapi/error.h" > > #include "qemu/error-report.h" > > @@ -99,6 +100,7 @@ static const struct isa_ext_data isa_edata_arr[] =3D= { > > ISA_EXT_DATA_ENTRY(zve64f, true, PRIV_VERSION_1_12_0, ext_zve64f)= , > > ISA_EXT_DATA_ENTRY(zhinx, true, PRIV_VERSION_1_12_0, ext_zhinx), > > ISA_EXT_DATA_ENTRY(zhinxmin, true, PRIV_VERSION_1_12_0, > ext_zhinxmin), > > + ISA_EXT_DATA_ENTRY(sstc, true, PRIV_VERSION_1_12_0, ext_sstc), > > ISA_EXT_DATA_ENTRY(svinval, true, PRIV_VERSION_1_12_0, > ext_svinval), > > ISA_EXT_DATA_ENTRY(svnapot, true, PRIV_VERSION_1_12_0, > ext_svnapot), > > ISA_EXT_DATA_ENTRY(svpbmt, true, PRIV_VERSION_1_12_0, ext_svpbmt)= , > > @@ -675,6 +677,13 @@ static void riscv_cpu_realize(DeviceState *dev, > Error **errp) > > > > set_resetvec(env, cpu->cfg.resetvec); > > > > +#ifndef CONFIG_USER_ONLY > > + if (cpu->cfg.ext_sstc) { > > + riscv_timer_init(cpu); > > + } > > +#endif /* CONFIG_USER_ONLY */ > > + > > + > > multi blink line here. > > Fixed it. > Regards, > > Weiwei Li > > > /* Validate that MISA_MXL is set properly. */ > > switch (env->misa_mxl_max) { > > #ifdef TARGET_RISCV64 > > @@ -968,7 +977,9 @@ static void riscv_cpu_init(Object *obj) > > #ifndef CONFIG_USER_ONLY > > qdev_init_gpio_in(DEVICE(cpu), riscv_cpu_set_irq, > > IRQ_LOCAL_MAX + IRQ_LOCAL_GUEST_MAX); > > + > > #endif /* CONFIG_USER_ONLY */ > > + > > } > > > > static Property riscv_cpu_extensions[] =3D { > > @@ -995,6 +1006,7 @@ static Property riscv_cpu_extensions[] =3D { > > DEFINE_PROP_BOOL("Zve64f", RISCVCPU, cfg.ext_zve64f, false), > > DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true), > > DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true), > > + DEFINE_PROP_BOOL("sstc", RISCVCPU, cfg.ext_sstc, true), > > > > DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec), > > DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec), > > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > > index 0fae1569945c..4cda2905661e 100644 > > --- a/target/riscv/cpu.h > > +++ b/target/riscv/cpu.h > > @@ -309,6 +309,9 @@ struct CPUArchState { > > uint64_t mfromhost; > > uint64_t mtohost; > > > > + /* Sstc CSRs */ > > + uint64_t stimecmp; > > + > > /* physical memory protection */ > > pmp_table_t pmp_state; > > target_ulong mseccfg; > > @@ -362,6 +365,7 @@ struct CPUArchState { > > float_status fp_status; > > > > /* Fields from here on are preserved across CPU reset. */ > > + QEMUTimer *stimer; /* Internal timer for S-mode interrupt */ > > > > hwaddr kernel_addr; > > hwaddr fdt_addr; > > @@ -425,6 +429,7 @@ struct RISCVCPUConfig { > > bool ext_ifencei; > > bool ext_icsr; > > bool ext_zihintpause; > > + bool ext_sstc; > > bool ext_svinval; > > bool ext_svnapot; > > bool ext_svpbmt; > > diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h > > index 6be5a9e9f046..ac17cf1515c0 100644 > > --- a/target/riscv/cpu_bits.h > > +++ b/target/riscv/cpu_bits.h > > @@ -206,6 +206,10 @@ > > #define CSR_STVAL 0x143 > > #define CSR_SIP 0x144 > > > > +/* Sstc supervisor CSRs */ > > +#define CSR_STIMECMP 0x14D > > +#define CSR_STIMECMPH 0x15D > > + > > /* Supervisor Protection and Translation */ > > #define CSR_SPTBR 0x180 > > #define CSR_SATP 0x180 > > diff --git a/target/riscv/csr.c b/target/riscv/csr.c > > index 0fb042b2fd0f..b71e2509b64f 100644 > > --- a/target/riscv/csr.c > > +++ b/target/riscv/csr.c > > @@ -22,6 +22,7 @@ > > #include "qemu/timer.h" > > #include "cpu.h" > > #include "pmu.h" > > +#include "time_helper.h" > > #include "qemu/main-loop.h" > > #include "exec/exec-all.h" > > #include "sysemu/cpu-timers.h" > > @@ -803,6 +804,76 @@ static RISCVException read_timeh(CPURISCVState > *env, int csrno, > > return RISCV_EXCP_NONE; > > } > > > > +static RISCVException sstc(CPURISCVState *env, int csrno) > > +{ > > + CPUState *cs =3D env_cpu(env); > > + RISCVCPU *cpu =3D RISCV_CPU(cs); > > + > > + if (!cpu->cfg.ext_sstc || !env->rdtime_fn) { > > + return RISCV_EXCP_ILLEGAL_INST; > > + } > > + > > + if (env->priv =3D=3D PRV_M) { > > + return RISCV_EXCP_NONE; > > + } > > + > > + if (env->priv !=3D PRV_S) { > > + return RISCV_EXCP_ILLEGAL_INST; > > + } > > + > > This check seems unnecessary here. Stimecmp is a S mode csr. So any > priv less than S > > mode will trigger exception in csrrw related check and cannot reach here. > > Yeah. We can remove it. > And maybe we need call smode predicate for it in this function. > > You mean at the end instead of returning RISCV_EXCP_NONE ? We can do that. > > + /* > > + * No need of separate function for rv32 as menvcfg stores both > menvcfg > > + * menvcfgh for RV32. > > + */ > > + if (!(get_field(env->mcounteren, COUNTEREN_TM) && > > + get_field(env->menvcfg, MENVCFG_STCE))) { > > + return RISCV_EXCP_ILLEGAL_INST; > > + } > > + > > + return RISCV_EXCP_NONE; > > +} > > + > > +static RISCVException read_stimecmp(CPURISCVState *env, int csrno, > > + target_ulong *val) > > +{ > > + *val =3D env->stimecmp; > > + return RISCV_EXCP_NONE; > > +} > > + > > +static RISCVException read_stimecmph(CPURISCVState *env, int csrno, > > + target_ulong *val) > > +{ > > + *val =3D env->stimecmp >> 32; > > + return RISCV_EXCP_NONE; > > +} > > + > > +static RISCVException write_stimecmp(CPURISCVState *env, int csrno, > > + target_ulong val) > > +{ > > + RISCVCPU *cpu =3D env_archcpu(env); > > + > > + if (riscv_cpu_mxl(env) =3D=3D MXL_RV32) { > > + env->stimecmp =3D deposit64(env->stimecmp, 0, 32, (uint64_t)va= l); > > + } else { > > + env->stimecmp =3D val; > > + } > > + > > + riscv_timer_write_timecmp(cpu, env->stimer, env->stimecmp, 0, > MIP_STIP); > > + > > + return RISCV_EXCP_NONE; > > +} > > + > > +static RISCVException write_stimecmph(CPURISCVState *env, int csrno, > > + target_ulong val) > > +{ > > + RISCVCPU *cpu =3D env_archcpu(env); > > + > > + env->stimecmp =3D deposit64(env->stimecmp, 32, 32, (uint64_t)val); > > + riscv_timer_write_timecmp(cpu, env->stimer, env->stimecmp, 0, > MIP_STIP); > > + > > + return RISCV_EXCP_NONE; > > +} > > + > > /* Machine constants */ > > > > #define M_MODE_INTERRUPTS ((uint64_t)(MIP_MSIP | MIP_MTIP | MIP_MEIP= )) > > @@ -1719,6 +1790,12 @@ static RISCVException rmw_mip64(CPURISCVState > *env, int csrno, > > new_val |=3D env->external_seip * MIP_SEIP; > > } > > > > + if (cpu->cfg.ext_sstc && (env->priv =3D=3D PRV_M) && > > + get_field(env->menvcfg, MENVCFG_STCE)) { > > + /* sstc extension forbids STIP & VSTIP to be writeable in mip = */ > > + mask =3D mask & ~(MIP_STIP | MIP_VSTIP); > > + } > > + > > if (mask) { > > old_mip =3D riscv_cpu_update_mip(cpu, mask, (new_val & mask))= ; > > } else { > > @@ -3584,6 +3661,10 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D= { > > [CSR_SCAUSE] =3D { "scause", smode, read_scause, write_scau= se > }, > > [CSR_STVAL] =3D { "stval", smode, read_stval, write_stva= l > }, > > [CSR_SIP] =3D { "sip", smode, NULL, NULL, rmw_sip > }, > > + [CSR_STIMECMP] =3D { "stimecmp", sstc, read_stimecmp, write_stimec= mp, > > + .min_priv_ver =3D > PRIV_VERSION_1_12_0 }, > > + [CSR_STIMECMPH] =3D { "stimecmph", sstc, read_stimecmph, > write_stimecmph, > > + .min_priv_ver =3D > PRIV_VERSION_1_12_0 }, > > > > /* Supervisor Protection and Translation */ > > [CSR_SATP] =3D { "satp", smode, read_satp, write_satp > }, > > diff --git a/target/riscv/machine.c b/target/riscv/machine.c > > index b508b042cb73..622fface484e 100644 > > --- a/target/riscv/machine.c > > +++ b/target/riscv/machine.c > > @@ -359,6 +359,7 @@ const VMStateDescription vmstate_riscv_cpu =3D { > > VMSTATE_UINTTL(env.mscratch, RISCVCPU), > > VMSTATE_UINT64(env.mfromhost, RISCVCPU), > > VMSTATE_UINT64(env.mtohost, RISCVCPU), > > + VMSTATE_UINT64(env.stimecmp, RISCVCPU), > > > > VMSTATE_END_OF_LIST() > > }, > > diff --git a/target/riscv/meson.build b/target/riscv/meson.build > > index 2c1975e72c4e..24893c614ee4 100644 > > --- a/target/riscv/meson.build > > +++ b/target/riscv/meson.build > > @@ -31,7 +31,8 @@ riscv_softmmu_ss.add(files( > > 'debug.c', > > 'monitor.c', > > 'machine.c', > > - 'pmu.c' > > + 'pmu.c', > > + 'time_helper.c' > > )) > > > > target_arch +=3D {'riscv': riscv_ss} > > diff --git a/target/riscv/time_helper.c b/target/riscv/time_helper.c > > new file mode 100644 > > index 000000000000..f3fb5eac7b7b > > --- /dev/null > > +++ b/target/riscv/time_helper.c > > @@ -0,0 +1,98 @@ > > +/* > > + * RISC-V timer helper implementation. > > + * > > + * Copyright (c) 2022 Rivos Inc. > > + * > > + * This program is free software; you can redistribute it and/or modif= y > it > > + * under the terms and conditions of the GNU General Public License, > > + * version 2 or later, as published by the Free Software Foundation. > > + * > > + * This program is distributed in the hope it will be useful, but > WITHOUT > > + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY = or > > + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public > License for > > + * more details. > > + * > > + * You should have received a copy of the GNU General Public License > along with > > + * this program. If not, see . > > + */ > > + > > +#include "qemu/osdep.h" > > +#include "qemu/log.h" > > +#include "cpu_bits.h" > > +#include "time_helper.h" > > +#include "hw/intc/riscv_aclint.h" > > + > > +static void riscv_stimer_cb(void *opaque) > > +{ > > + RISCVCPU *cpu =3D opaque; > > + riscv_cpu_update_mip(cpu, MIP_STIP, BOOL_TO_MASK(1)); > > +} > > + > > +/* > > + * Called when timecmp is written to update the QEMU timer or > immediately > > + * trigger timer interrupt if mtimecmp <=3D current timer value. > > + */ > > +void riscv_timer_write_timecmp(RISCVCPU *cpu, QEMUTimer *timer, > > + uint64_t timecmp, uint64_t delta, > > + uint32_t timer_irq) > > +{ > > + uint64_t diff, ns_diff, next; > > + CPURISCVState *env =3D &cpu->env; > > + RISCVAclintMTimerState *mtimer =3D env->rdtime_fn_arg; > > + uint32_t timebase_freq =3D mtimer->timebase_freq; > > + uint64_t rtc_r =3D env->rdtime_fn(env->rdtime_fn_arg) + delta; > > + > > + if (timecmp <=3D rtc_r) { > > + /* > > + * If we're setting an stimecmp value in the "past", > > + * immediately raise the timer interrupt > > + */ > > + riscv_cpu_update_mip(cpu, timer_irq, BOOL_TO_MASK(1)); > > + return; > > + } > > + > > + /* Clear the [V]STIP bit in mip */ > > + riscv_cpu_update_mip(cpu, timer_irq, BOOL_TO_MASK(0)); > > + > > + /* otherwise, set up the future timer interrupt */ > > + diff =3D timecmp - rtc_r; > > + /* back to ns (note args switched in muldiv64) */ > > + ns_diff =3D muldiv64(diff, NANOSECONDS_PER_SECOND, timebase_freq); > > + > > + /* > > + * check if ns_diff overflowed and check if the addition would > potentially > > + * overflow > > + */ > > + if ((NANOSECONDS_PER_SECOND > timebase_freq && ns_diff < diff) || > > + ns_diff > INT64_MAX) { > > + next =3D INT64_MAX; > > + } else { > > + /* > > + * as it is very unlikely qemu_clock_get_ns will return a valu= e > > + * greater than INT64_MAX, no additional check is needed for a= n > > + * unsigned integer overflow. > > + */ > > + next =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + ns_diff; > > + /* > > + * if ns_diff is INT64_MAX next may still be outside the range > > + * of a signed integer. > > + */ > > + next =3D MIN(next, INT64_MAX); > > + } > > + > > + timer_mod(timer, next); > > +} > > + > > +void riscv_timer_init(RISCVCPU *cpu) > > +{ > > + CPURISCVState *env; > > + > > + if (!cpu) { > > + return; > > + } > > + > > + env =3D &cpu->env; > > + env->stimer =3D timer_new_ns(QEMU_CLOCK_VIRTUAL, &riscv_stimer_cb, > cpu); > > + env->stimecmp =3D 0; > > + > > +} > > diff --git a/target/riscv/time_helper.h b/target/riscv/time_helper.h > > new file mode 100644 > > index 000000000000..7b3cdcc35020 > > --- /dev/null > > +++ b/target/riscv/time_helper.h > > @@ -0,0 +1,30 @@ > > +/* > > + * RISC-V timer header file. > > + * > > + * Copyright (c) 2022 Rivos Inc. > > + * > > + * This program is free software; you can redistribute it and/or modif= y > it > > + * under the terms and conditions of the GNU General Public License, > > + * version 2 or later, as published by the Free Software Foundation. > > + * > > + * This program is distributed in the hope it will be useful, but > WITHOUT > > + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY = or > > + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public > License for > > + * more details. > > + * > > + * You should have received a copy of the GNU General Public License > along with > > + * this program. If not, see . > > + */ > > + > > +#ifndef RISCV_TIME_HELPER_H > > +#define RISCV_TIME_HELPER_H > > + > > +#include "cpu.h" > > +#include "qemu/timer.h" > > + > > +void riscv_timer_write_timecmp(RISCVCPU *cpu, QEMUTimer *timer, > > + uint64_t timecmp, uint64_t delta, > > + uint32_t timer_irq); > > +void riscv_timer_init(RISCVCPU *cpu); > > + > > +#endif > > --0000000000001ff8b805e55ca6e7 Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable


=
On Wed, Aug 3, 2022 at 1:42 AM Weiwei= Li <liweiwei@iscas.ac.cn>= ; wrote:

=E5=9C=A8 2022/8/3 =E4=B8=8B=E5=8D=884:25, Atish Patra =E5=86=99=E9=81=93:<= br> > stimecmp allows the supervisor mode to update stimecmp CSR directly > to program the next timer interrupt. This CSR is part of the Sstc
> extension which was ratified recently.
>
> Signed-off-by: Atish Patra <atishp@rivosinc.com>
> ---
>=C2=A0 =C2=A0target/riscv/cpu.c=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0| 12 += ++++
>=C2=A0 =C2=A0target/riscv/cpu.h=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0|=C2= =A0 5 ++
>=C2=A0 =C2=A0target/riscv/cpu_bits.h=C2=A0 =C2=A0 |=C2=A0 4 ++
>=C2=A0 =C2=A0target/riscv/csr.c=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0| 81 += ++++++++++++++++++++++++++++++
>=C2=A0 =C2=A0target/riscv/machine.c=C2=A0 =C2=A0 =C2=A0|=C2=A0 1 +
>=C2=A0 =C2=A0target/riscv/meson.build=C2=A0 =C2=A0|=C2=A0 3 +-
>=C2=A0 =C2=A0target/riscv/time_helper.c | 98 ++++++++++++++++++++++++++= ++++++++++++
>=C2=A0 =C2=A0target/riscv/time_helper.h | 30 ++++++++++++
>=C2=A0 =C2=A08 files changed, 233 insertions(+), 1 deletion(-)
>=C2=A0 =C2=A0create mode 100644 target/riscv/time_helper.c
>=C2=A0 =C2=A0create mode 100644 target/riscv/time_helper.h
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index d4635c7df46b..e0c3e786849f 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -23,6 +23,7 @@
>=C2=A0 =C2=A0#include "qemu/log.h"
>=C2=A0 =C2=A0#include "cpu.h"
>=C2=A0 =C2=A0#include "internals.h"
> +#include "time_helper.h"
>=C2=A0 =C2=A0#include "exec/exec-all.h"
>=C2=A0 =C2=A0#include "qapi/error.h"
>=C2=A0 =C2=A0#include "qemu/error-report.h"
> @@ -99,6 +100,7 @@ static const struct isa_ext_data isa_edata_arr[] = =3D {
>=C2=A0 =C2=A0 =C2=A0 =C2=A0ISA_EXT_DATA_ENTRY(zve64f, true, PRIV_VERSIO= N_1_12_0, ext_zve64f),
>=C2=A0 =C2=A0 =C2=A0 =C2=A0ISA_EXT_DATA_ENTRY(zhinx, true, PRIV_VERSION= _1_12_0, ext_zhinx),
>=C2=A0 =C2=A0 =C2=A0 =C2=A0ISA_EXT_DATA_ENTRY(zhinxmin, true, PRIV_VERS= ION_1_12_0, ext_zhinxmin),
> +=C2=A0 =C2=A0 ISA_EXT_DATA_ENTRY(sstc, true, PRIV_VERSION_1_12_0, ext= _sstc),
>=C2=A0 =C2=A0 =C2=A0 =C2=A0ISA_EXT_DATA_ENTRY(svinval, true, PRIV_VERSI= ON_1_12_0, ext_svinval),
>=C2=A0 =C2=A0 =C2=A0 =C2=A0ISA_EXT_DATA_ENTRY(svnapot, true, PRIV_VERSI= ON_1_12_0, ext_svnapot),
>=C2=A0 =C2=A0 =C2=A0 =C2=A0ISA_EXT_DATA_ENTRY(svpbmt, true, PRIV_VERSIO= N_1_12_0, ext_svpbmt),
> @@ -675,6 +677,13 @@ static void riscv_cpu_realize(DeviceState *dev, E= rror **errp)
>=C2=A0 =C2=A0
>=C2=A0 =C2=A0 =C2=A0 =C2=A0set_resetvec(env, cpu->cfg.resetvec);
>=C2=A0 =C2=A0
> +#ifndef CONFIG_USER_ONLY
> +=C2=A0 =C2=A0 if (cpu->cfg.ext_sstc) {
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 riscv_timer_init(cpu);
> +=C2=A0 =C2=A0 }
> +#endif /* CONFIG_USER_ONLY */
> +
> +

multi blink line here.


Fixed it.
=C2=A0
Regards,

Weiwei Li

>=C2=A0 =C2=A0 =C2=A0 =C2=A0/* Validate that MISA_MXL is set properly. *= /
>=C2=A0 =C2=A0 =C2=A0 =C2=A0switch (env->misa_mxl_max) {
>=C2=A0 =C2=A0#ifdef TARGET_RISCV64
> @@ -968,7 +977,9 @@ static void riscv_cpu_init(Object *obj)
>=C2=A0 =C2=A0#ifndef CONFIG_USER_ONLY
>=C2=A0 =C2=A0 =C2=A0 =C2=A0qdev_init_gpio_in(DEVICE(cpu), riscv_cpu_set= _irq,
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0IRQ_LOCAL_MAX + IRQ_LOCAL_GUEST_MAX);
> +
>=C2=A0 =C2=A0#endif /* CONFIG_USER_ONLY */
> +
>=C2=A0 =C2=A0}
>=C2=A0 =C2=A0
>=C2=A0 =C2=A0static Property riscv_cpu_extensions[] =3D {
> @@ -995,6 +1006,7 @@ static Property riscv_cpu_extensions[] =3D {
>=C2=A0 =C2=A0 =C2=A0 =C2=A0DEFINE_PROP_BOOL("Zve64f", RISCVCP= U, cfg.ext_zve64f, false),
>=C2=A0 =C2=A0 =C2=A0 =C2=A0DEFINE_PROP_BOOL("mmu", RISCVCPU, = cfg.mmu, true),
>=C2=A0 =C2=A0 =C2=A0 =C2=A0DEFINE_PROP_BOOL("pmp", RISCVCPU, = cfg.pmp, true),
> +=C2=A0 =C2=A0 DEFINE_PROP_BOOL("sstc", RISCVCPU, cfg.ext_ss= tc, true),
>=C2=A0 =C2=A0
>=C2=A0 =C2=A0 =C2=A0 =C2=A0DEFINE_PROP_STRING("priv_spec", RI= SCVCPU, cfg.priv_spec),
>=C2=A0 =C2=A0 =C2=A0 =C2=A0DEFINE_PROP_STRING("vext_spec", RI= SCVCPU, cfg.vext_spec),
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 0fae1569945c..4cda2905661e 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -309,6 +309,9 @@ struct CPUArchState {
>=C2=A0 =C2=A0 =C2=A0 =C2=A0uint64_t mfromhost;
>=C2=A0 =C2=A0 =C2=A0 =C2=A0uint64_t mtohost;
>=C2=A0 =C2=A0
> +=C2=A0 =C2=A0 /* Sstc CSRs */
> +=C2=A0 =C2=A0 uint64_t stimecmp;
> +
>=C2=A0 =C2=A0 =C2=A0 =C2=A0/* physical memory protection */
>=C2=A0 =C2=A0 =C2=A0 =C2=A0pmp_table_t pmp_state;
>=C2=A0 =C2=A0 =C2=A0 =C2=A0target_ulong mseccfg;
> @@ -362,6 +365,7 @@ struct CPUArchState {
>=C2=A0 =C2=A0 =C2=A0 =C2=A0float_status fp_status;
>=C2=A0 =C2=A0
>=C2=A0 =C2=A0 =C2=A0 =C2=A0/* Fields from here on are preserved across = CPU reset. */
> +=C2=A0 =C2=A0 QEMUTimer *stimer; /* Internal timer for S-mode interru= pt */
>=C2=A0 =C2=A0
>=C2=A0 =C2=A0 =C2=A0 =C2=A0hwaddr kernel_addr;
>=C2=A0 =C2=A0 =C2=A0 =C2=A0hwaddr fdt_addr;
> @@ -425,6 +429,7 @@ struct RISCVCPUConfig {
>=C2=A0 =C2=A0 =C2=A0 =C2=A0bool ext_ifencei;
>=C2=A0 =C2=A0 =C2=A0 =C2=A0bool ext_icsr;
>=C2=A0 =C2=A0 =C2=A0 =C2=A0bool ext_zihintpause;
> +=C2=A0 =C2=A0 bool ext_sstc;
>=C2=A0 =C2=A0 =C2=A0 =C2=A0bool ext_svinval;
>=C2=A0 =C2=A0 =C2=A0 =C2=A0bool ext_svnapot;
>=C2=A0 =C2=A0 =C2=A0 =C2=A0bool ext_svpbmt;
> diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
> index 6be5a9e9f046..ac17cf1515c0 100644
> --- a/target/riscv/cpu_bits.h
> +++ b/target/riscv/cpu_bits.h
> @@ -206,6 +206,10 @@
>=C2=A0 =C2=A0#define CSR_STVAL=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= 0x143
>=C2=A0 =C2=A0#define CSR_SIP=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A00x144
>=C2=A0 =C2=A0
> +/* Sstc supervisor CSRs */
> +#define CSR_STIMECMP=C2=A0 =C2=A0 =C2=A0 =C2=A0 0x14D
> +#define CSR_STIMECMPH=C2=A0 =C2=A0 =C2=A0 =C2=A00x15D
> +
>=C2=A0 =C2=A0/* Supervisor Protection and Translation */
>=C2=A0 =C2=A0#define CSR_SPTBR=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= 0x180
>=C2=A0 =C2=A0#define CSR_SATP=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = 0x180
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index 0fb042b2fd0f..b71e2509b64f 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -22,6 +22,7 @@
>=C2=A0 =C2=A0#include "qemu/timer.h"
>=C2=A0 =C2=A0#include "cpu.h"
>=C2=A0 =C2=A0#include "pmu.h"
> +#include "time_helper.h"
>=C2=A0 =C2=A0#include "qemu/main-loop.h"
>=C2=A0 =C2=A0#include "exec/exec-all.h"
>=C2=A0 =C2=A0#include "sysemu/cpu-timers.h"
> @@ -803,6 +804,76 @@ static RISCVException read_timeh(CPURISCVState *e= nv, int csrno,
>=C2=A0 =C2=A0 =C2=A0 =C2=A0return RISCV_EXCP_NONE;
>=C2=A0 =C2=A0}
>=C2=A0 =C2=A0
> +static RISCVException sstc(CPURISCVState *env, int csrno)
> +{
> +=C2=A0 =C2=A0 CPUState *cs =3D env_cpu(env);
> +=C2=A0 =C2=A0 RISCVCPU *cpu =3D RISCV_CPU(cs);
> +
> +=C2=A0 =C2=A0 if (!cpu->cfg.ext_sstc || !env->rdtime_fn) {
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 return RISCV_EXCP_ILLEGAL_INST;
> +=C2=A0 =C2=A0 }
> +
> +=C2=A0 =C2=A0 if (env->priv =3D=3D PRV_M) {
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 return RISCV_EXCP_NONE;
> +=C2=A0 =C2=A0 }
> +
> +=C2=A0 =C2=A0 if (env->priv !=3D PRV_S) {
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 return RISCV_EXCP_ILLEGAL_INST;
> +=C2=A0 =C2=A0 }
> +

This check seems unnecessary here. Stimecmp is a S mode=C2=A0 csr. So any <= br> priv less than S

mode will trigger exception in csrrw related check and cannot reach here.

Yeah. We can remove it.=C2=A0
=C2=A0
And maybe we need call smode predicate for it in this function.


You mean at the end instead of returni= ng=C2=A0RISCV_EXCP_NONE ? We can do that.
=C2=A0
> +=C2=A0 =C2=A0 /*
> +=C2=A0 =C2=A0 =C2=A0* No need of separate function for rv32 as menvcf= g stores both menvcfg
> +=C2=A0 =C2=A0 =C2=A0* menvcfgh for RV32.
> +=C2=A0 =C2=A0 =C2=A0*/
> +=C2=A0 =C2=A0 if (!(get_field(env->mcounteren, COUNTEREN_TM) &= &
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 get_field(env->menvcfg, MENVCFG= _STCE))) {
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 return RISCV_EXCP_ILLEGAL_INST;
> +=C2=A0 =C2=A0 }
> +
> +=C2=A0 =C2=A0 return RISCV_EXCP_NONE;
> +}
> +
> +static RISCVException read_stimecmp(CPURISCVState *env, int csrno, > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 target_ulong *val)=
> +{
> +=C2=A0 =C2=A0 *val =3D env->stimecmp;
> +=C2=A0 =C2=A0 return RISCV_EXCP_NONE;
> +}
> +
> +static RISCVException read_stimecmph(CPURISCVState *env, int csrno, > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 target_ulong *val)=
> +{
> +=C2=A0 =C2=A0 *val =3D env->stimecmp >> 32;
> +=C2=A0 =C2=A0 return RISCV_EXCP_NONE;
> +}
> +
> +static RISCVException write_stimecmp(CPURISCVState *env, int csrno, > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 target_ulong val)<= br> > +{
> +=C2=A0 =C2=A0 RISCVCPU *cpu =3D env_archcpu(env);
> +
> +=C2=A0 =C2=A0 if (riscv_cpu_mxl(env) =3D=3D MXL_RV32) {
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 env->stimecmp =3D deposit64(env->st= imecmp, 0, 32, (uint64_t)val);
> +=C2=A0 =C2=A0 } else {
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 env->stimecmp =3D val;
> +=C2=A0 =C2=A0 }
> +
> +=C2=A0 =C2=A0 riscv_timer_write_timecmp(cpu, env->stimer, env->= stimecmp, 0, MIP_STIP);
> +
> +=C2=A0 =C2=A0 return RISCV_EXCP_NONE;
> +}
> +
> +static RISCVException write_stimecmph(CPURISCVState *env, int csrno,<= br> > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 target_ulong val)<= br> > +{
> +=C2=A0 =C2=A0 RISCVCPU *cpu =3D env_archcpu(env);
> +
> +=C2=A0 =C2=A0 env->stimecmp =3D deposit64(env->stimecmp, 32, 32= , (uint64_t)val);
> +=C2=A0 =C2=A0 riscv_timer_write_timecmp(cpu, env->stimer, env->= stimecmp, 0, MIP_STIP);
> +
> +=C2=A0 =C2=A0 return RISCV_EXCP_NONE;
> +}
> +
>=C2=A0 =C2=A0/* Machine constants */
>=C2=A0 =C2=A0
>=C2=A0 =C2=A0#define M_MODE_INTERRUPTS=C2=A0 ((uint64_t)(MIP_MSIP | MIP= _MTIP | MIP_MEIP))
> @@ -1719,6 +1790,12 @@ static RISCVException rmw_mip64(CPURISCVState *= env, int csrno,
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0new_val |=3D env->external_= seip * MIP_SEIP;
>=C2=A0 =C2=A0 =C2=A0 =C2=A0}
>=C2=A0 =C2=A0
> +=C2=A0 =C2=A0 if (cpu->cfg.ext_sstc && (env->priv =3D= =3D PRV_M) &&
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 get_field(env->menvcfg, MENVCFG_STCE))= {
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 /* sstc extension forbids STIP & VSTI= P to be writeable in mip */
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 mask =3D mask & ~(MIP_STIP | MIP_VSTI= P);
> +=C2=A0 =C2=A0 }
> +
>=C2=A0 =C2=A0 =C2=A0 =C2=A0if (mask) {
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0old_mip =3D riscv_cpu_update_m= ip(cpu, mask, (new_val & mask));
>=C2=A0 =C2=A0 =C2=A0 =C2=A0} else {
> @@ -3584,6 +3661,10 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = =3D {
>=C2=A0 =C2=A0 =C2=A0 =C2=A0[CSR_SCAUSE]=C2=A0 =C2=A0=3D { "scause&= quot;,=C2=A0 =C2=A0smode, read_scause,=C2=A0 =C2=A0write_scause=C2=A0 =C2= =A0},
>=C2=A0 =C2=A0 =C2=A0 =C2=A0[CSR_STVAL]=C2=A0 =C2=A0 =3D { "stval&q= uot;,=C2=A0 =C2=A0 smode, read_stval,=C2=A0 =C2=A0 write_stval=C2=A0 =C2=A0= },
>=C2=A0 =C2=A0 =C2=A0 =C2=A0[CSR_SIP]=C2=A0 =C2=A0 =C2=A0 =3D { "si= p",=C2=A0 =C2=A0 =C2=A0 smode, NULL,=C2=A0 =C2=A0 NULL, rmw_sip=C2=A0 = =C2=A0 =C2=A0 =C2=A0 },
> +=C2=A0 =C2=A0 [CSR_STIMECMP] =3D { "stimecmp", sstc, read_s= timecmp, write_stimecmp,
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 .min_priv_ver =3D PRIV_VERSION_1_12_0 },
> +=C2=A0 =C2=A0 [CSR_STIMECMPH] =3D { "stimecmph", sstc, read= _stimecmph, write_stimecmph,
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 .min_priv_ver =3D PRIV_VERSION_1_12_0 },
>=C2=A0 =C2=A0
>=C2=A0 =C2=A0 =C2=A0 =C2=A0/* Supervisor Protection and Translation */<= br> >=C2=A0 =C2=A0 =C2=A0 =C2=A0[CSR_SATP]=C2=A0 =C2=A0 =C2=A0=3D { "sa= tp",=C2=A0 =C2=A0 =C2=A0smode, read_satp,=C2=A0 =C2=A0 =C2=A0write_sat= p=C2=A0 =C2=A0 =C2=A0},
> diff --git a/target/riscv/machine.c b/target/riscv/machine.c
> index b508b042cb73..622fface484e 100644
> --- a/target/riscv/machine.c
> +++ b/target/riscv/machine.c
> @@ -359,6 +359,7 @@ const VMStateDescription vmstate_riscv_cpu =3D { >=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0VMSTATE_UINTTL(env.mscratch, R= ISCVCPU),
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0VMSTATE_UINT64(env.mfromhost, = RISCVCPU),
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0VMSTATE_UINT64(env.mtohost, RI= SCVCPU),
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 VMSTATE_UINT64(env.stimecmp, RISCVCPU), >=C2=A0 =C2=A0
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0VMSTATE_END_OF_LIST()
>=C2=A0 =C2=A0 =C2=A0 =C2=A0},
> diff --git a/target/riscv/meson.build b/target/riscv/meson.build
> index 2c1975e72c4e..24893c614ee4 100644
> --- a/target/riscv/meson.build
> +++ b/target/riscv/meson.build
> @@ -31,7 +31,8 @@ riscv_softmmu_ss.add(files(
>=C2=A0 =C2=A0 =C2=A0'debug.c',
>=C2=A0 =C2=A0 =C2=A0'monitor.c',
>=C2=A0 =C2=A0 =C2=A0'machine.c',
> -=C2=A0 'pmu.c'
> +=C2=A0 'pmu.c',
> +=C2=A0 'time_helper.c'
>=C2=A0 =C2=A0))
>=C2=A0 =C2=A0
>=C2=A0 =C2=A0target_arch +=3D {'riscv': riscv_ss}
> diff --git a/target/riscv/time_helper.c b/target/riscv/time_helper.c > new file mode 100644
> index 000000000000..f3fb5eac7b7b
> --- /dev/null
> +++ b/target/riscv/time_helper.c
> @@ -0,0 +1,98 @@
> +/*
> + * RISC-V timer helper implementation.
> + *
> + * Copyright (c) 2022 Rivos Inc.
> + *
> + * This program is free software; you can redistribute it and/or modi= fy it
> + * under the terms and conditions of the GNU General Public License,<= br> > + * version 2 or later, as published by the Free Software Foundation.<= br> > + *
> + * This program is distributed in the hope it will be useful, but WIT= HOUT
> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY= or
> + * FITNESS FOR A PARTICULAR PURPOSE.=C2=A0 See the GNU General Public= License for
> + * more details.
> + *
> + * You should have received a copy of the GNU General Public License = along with
> + * this program.=C2=A0 If not, see <http://www.gnu.org/licenses= />.
> + */
> +
> +#include "qemu/osdep.h"
> +#include "qemu/log.h"
> +#include "cpu_bits.h"
> +#include "time_helper.h"
> +#include "hw/intc/riscv_aclint.h"
> +
> +static void riscv_stimer_cb(void *opaque)
> +{
> +=C2=A0 =C2=A0 RISCVCPU *cpu =3D opaque;
> +=C2=A0 =C2=A0 riscv_cpu_update_mip(cpu, MIP_STIP, BOOL_TO_MASK(1)); > +}
> +
> +/*
> + * Called when timecmp is written to update the QEMU timer or immedia= tely
> + * trigger timer interrupt if mtimecmp <=3D current timer value. > + */
> +void riscv_timer_write_timecmp(RISCVCPU *cpu, QEMUTimer *timer,
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0uint64_t timecmp, uint64_t delta,=
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0uint32_t timer_irq)
> +{
> +=C2=A0 =C2=A0 uint64_t diff, ns_diff, next;
> +=C2=A0 =C2=A0 CPURISCVState *env =3D &cpu->env;
> +=C2=A0 =C2=A0 RISCVAclintMTimerState *mtimer =3D env->rdtime_fn_ar= g;
> +=C2=A0 =C2=A0 uint32_t timebase_freq =3D mtimer->timebase_freq; > +=C2=A0 =C2=A0 uint64_t rtc_r =3D env->rdtime_fn(env->rdtime_fn_= arg) + delta;
> +
> +=C2=A0 =C2=A0 if (timecmp <=3D rtc_r) {
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 /*
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0* If we're setting an stimecmp = value in the "past",
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0* immediately raise the timer inter= rupt
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0*/
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 riscv_cpu_update_mip(cpu, timer_irq, BOOL= _TO_MASK(1));
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 return;
> +=C2=A0 =C2=A0 }
> +
> +=C2=A0 =C2=A0 /* Clear the [V]STIP bit in mip */
> +=C2=A0 =C2=A0 riscv_cpu_update_mip(cpu, timer_irq, BOOL_TO_MASK(0));<= br> > +
> +=C2=A0 =C2=A0 /* otherwise, set up the future timer interrupt */
> +=C2=A0 =C2=A0 diff =3D timecmp - rtc_r;
> +=C2=A0 =C2=A0 /* back to ns (note args switched in muldiv64) */
> +=C2=A0 =C2=A0 ns_diff =3D muldiv64(diff, NANOSECONDS_PER_SECOND, time= base_freq);
> +
> +=C2=A0 =C2=A0 /*
> +=C2=A0 =C2=A0 =C2=A0* check if ns_diff overflowed and check if the ad= dition would potentially
> +=C2=A0 =C2=A0 =C2=A0* overflow
> +=C2=A0 =C2=A0 =C2=A0*/
> +=C2=A0 =C2=A0 if ((NANOSECONDS_PER_SECOND > timebase_freq &&am= p; ns_diff < diff) ||
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 ns_diff > INT64_MAX) {
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 next =3D INT64_MAX;
> +=C2=A0 =C2=A0 } else {
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 /*
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0* as it is very unlikely qemu_clock= _get_ns will return a value
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0* greater than INT64_MAX, no additi= onal check is needed for an
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0* unsigned integer overflow.
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0*/
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 next =3D qemu_clock_get_ns(QEMU_CLOCK_VIR= TUAL) + ns_diff;
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 /*
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0* if ns_diff is INT64_MAX next may = still be outside the range
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0* of a signed integer.
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0*/
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 next =3D MIN(next, INT64_MAX);
> +=C2=A0 =C2=A0 }
> +
> +=C2=A0 =C2=A0 timer_mod(timer, next);
> +}
> +
> +void riscv_timer_init(RISCVCPU *cpu)
> +{
> +=C2=A0 =C2=A0 CPURISCVState *env;
> +
> +=C2=A0 =C2=A0 if (!cpu) {
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 return;
> +=C2=A0 =C2=A0 }
> +
> +=C2=A0 =C2=A0 env =3D &cpu->env;
> +=C2=A0 =C2=A0 env->stimer =3D timer_new_ns(QEMU_CLOCK_VIRTUAL, &am= p;riscv_stimer_cb, cpu);
> +=C2=A0 =C2=A0 env->stimecmp =3D 0;
> +
> +}
> diff --git a/target/riscv/time_helper.h b/target/riscv/time_helper.h > new file mode 100644
> index 000000000000..7b3cdcc35020
> --- /dev/null
> +++ b/target/riscv/time_helper.h
> @@ -0,0 +1,30 @@
> +/*
> + * RISC-V timer header file.
> + *
> + * Copyright (c) 2022 Rivos Inc.
> + *
> + * This program is free software; you can redistribute it and/or modi= fy it
> + * under the terms and conditions of the GNU General Public License,<= br> > + * version 2 or later, as published by the Free Software Foundation.<= br> > + *
> + * This program is distributed in the hope it will be useful, but WIT= HOUT
> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY= or
> + * FITNESS FOR A PARTICULAR PURPOSE.=C2=A0 See the GNU General Public= License for
> + * more details.
> + *
> + * You should have received a copy of the GNU General Public License = along with
> + * this program.=C2=A0 If not, see <http://www.gnu.org/licenses= />.
> + */
> +
> +#ifndef RISCV_TIME_HELPER_H
> +#define RISCV_TIME_HELPER_H
> +
> +#include "cpu.h"
> +#include "qemu/timer.h"
> +
> +void riscv_timer_write_timecmp(RISCVCPU *cpu, QEMUTimer *timer,
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0uint64_t timecmp, uint64_t delta,=
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0uint32_t timer_irq);
> +void riscv_timer_init(RISCVCPU *cpu);
> +
> +#endif

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