From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 87A1DC433EF for ; Sat, 30 Apr 2022 15:12:39 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 1C18B83B57; Sat, 30 Apr 2022 17:12:36 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="YEoYZP20"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 4B86A83F27; Sat, 30 Apr 2022 17:12:34 +0200 (CEST) Received: from mail-ej1-x62b.google.com (mail-ej1-x62b.google.com [IPv6:2a00:1450:4864:20::62b]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 2152A83B57 for ; Sat, 30 Apr 2022 17:12:31 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=aford173@gmail.com Received: by mail-ej1-x62b.google.com with SMTP id m20so20426931ejj.10 for ; Sat, 30 Apr 2022 08:12:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=28vNK9NMkcXm8XDYdvvnWBXFBA5YYQYAeTGV0mnbdu0=; b=YEoYZP20sYhgq8iybHv3D0t2plGpfqg+ksfmJbaV0RJw6bz06AGPYtArd8HBkRTMf9 2AKQVHsh7tx6hlSagQvaEgKtGlBx5HhG1HU2t0fZlAcvk1NQNC/ThXkybGA+MSQuAxq+ oboXxPsDFMAqf/ymBmL4SYyCzMAkwA550bk1t/ddeBx7VEmRCsVF/X/1AprET4LbO6FM TCNqo9++oI+DAXKJ08STxS4BLHAaRZKPOVFpwFTeQZ3IJMDsU0w7V2kDzJ0uINP4+8a5 tz3M019wKqI5mad9YWgSzAYyAnNCtM/CL9BhltQUGKzkqjE6FflMkogDONKLIxxuMMvE mfXw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=28vNK9NMkcXm8XDYdvvnWBXFBA5YYQYAeTGV0mnbdu0=; b=kjd594kGox8Q2VL41hxjDcJ53Wi7HNdsTwOkhMv+gv2TQWdGn1ncwkf8+rZ2lQ1Q+L WerI85sijkYtpw7VJI0w0OpCQo9a8htfUhcJzp3i0bSiPn+N1wsL7GN0GCvithDDJgBP 5k0ySRf09dJ6AlOWdm4L2Umk9GRTcS7rzhYRFSUOQtytBGMSv0ylVpMRWGt7452gI7UK DC/wFyISZujFFSTbMbMtYcbUMSkr6nAk/KXGUiMoD2NvQjiaEXOjlcBdQeNWHCSEafM1 LgWanmBJlCV5rvoKLLiyl4/eqfUd9ykjEPwNcjdeeFfO4WcUI03RfeAnc3ZTZiXBlqs4 SDtA== X-Gm-Message-State: AOAM531DofgpI3n6BvquTQZ5Z7hzxOx3AoZEHIs91TMTVEIOCFeSumEJ QkuR6mpmmyPx+ffcDQugbJqgTRdIPmSyE+Xx2lw= X-Google-Smtp-Source: ABdhPJysBUk2luo4Y8/8DfqTapd52Oe1Y/NbHnLFfQBut/OA86WOgWskgo4pR/+sty4UV6CpwPgOE0eqzFHY3W9l1eg= X-Received: by 2002:a17:906:804b:b0:6f3:8d78:ffa8 with SMTP id x11-20020a170906804b00b006f38d78ffa8mr4185672ejw.588.1651331550375; Sat, 30 Apr 2022 08:12:30 -0700 (PDT) MIME-Version: 1.0 References: <20220430124317.17382-1-peng.fan@oss.nxp.com> <20220430124317.17382-5-peng.fan@oss.nxp.com> In-Reply-To: <20220430124317.17382-5-peng.fan@oss.nxp.com> From: Adam Ford Date: Sat, 30 Apr 2022 10:12:19 -0500 Message-ID: Subject: Re: [PATCH 04/15] imx: imx8m[m/n]_beacon: Enable SPL_DM_SERIAL To: "Peng Fan (OSS)" Cc: Stefano Babic , Fabio Estevam , U-Boot Mailing List , Peng Fan Content-Type: text/plain; charset="UTF-8" X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.5 at phobos.denx.de X-Virus-Status: Clean On Sat, Apr 30, 2022 at 7:01 AM Peng Fan (OSS) wrote: > > From: Peng Fan > > Enable CONFIG_SPL_DM_SERIAL. uart2 and its pinmux was already > marked with u-boot,dm-spl. > Move preloader_console_init after spl_init to make sure driver > model work. Thanks for doing this! > Tested-by: Adam Ford #imx8mm_beacon > Signed-off-by: Peng Fan > --- > board/beacon/imx8mm/spl.c | 12 ++---------- > board/beacon/imx8mn/spl.c | 11 ++--------- > configs/imx8mm_beacon_defconfig | 1 - > configs/imx8mn_beacon_2g_defconfig | 1 - > configs/imx8mn_beacon_defconfig | 1 - > include/configs/imx8mm_beacon.h | 2 -- > include/configs/imx8mn_beacon.h | 2 -- > 7 files changed, 4 insertions(+), 26 deletions(-) > > diff --git a/board/beacon/imx8mm/spl.c b/board/beacon/imx8mm/spl.c > index 12266b22a42..f92b4c3ed0a 100644 > --- a/board/beacon/imx8mm/spl.c > +++ b/board/beacon/imx8mm/spl.c > @@ -59,14 +59,8 @@ int board_fit_config_name_match(const char *name) > } > #endif > > -#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1) > #define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE) > > -static iomux_v3_cfg_t const uart_pads[] = { > - IMX8MM_PAD_UART2_RXD_UART2_RX | MUX_PAD_CTRL(UART_PAD_CTRL), > - IMX8MM_PAD_UART2_TXD_UART2_TX | MUX_PAD_CTRL(UART_PAD_CTRL), > -}; > - > static iomux_v3_cfg_t const wdog_pads[] = { > IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL), > }; > @@ -79,8 +73,6 @@ int board_early_init_f(void) > > set_wdog_reset(wdog); > > - imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads)); > - > return 0; > } > > @@ -128,8 +120,6 @@ void board_init_f(ulong dummy) > > timer_init(); > > - preloader_console_init(); > - > /* Clear the BSS. */ > memset(__bss_start, 0, __bss_end - __bss_start); > > @@ -139,6 +129,8 @@ void board_init_f(ulong dummy) > hang(); > } > > + preloader_console_init(); > + > ret = uclass_get_device_by_name(UCLASS_CLK, > "clock-controller@30380000", > &dev); > diff --git a/board/beacon/imx8mn/spl.c b/board/beacon/imx8mn/spl.c > index bb51be01c52..4563446db19 100644 > --- a/board/beacon/imx8mn/spl.c > +++ b/board/beacon/imx8mn/spl.c > @@ -68,7 +68,6 @@ int board_fit_config_name_match(const char *name) > } > #endif > > -#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1) > #define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE) > #define PWM1_PAD_CTRL (PAD_CTL_FSEL2 | PAD_CTL_DSE6) > > @@ -76,11 +75,6 @@ static iomux_v3_cfg_t const pwm_pads[] = { > IMX8MN_PAD_GPIO1_IO01__PWM1_OUT | MUX_PAD_CTRL(PWM1_PAD_CTRL), > }; > > -static iomux_v3_cfg_t const uart_pads[] = { > - IMX8MN_PAD_UART2_RXD__UART2_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), > - IMX8MN_PAD_UART2_TXD__UART2_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), > -}; > - > static iomux_v3_cfg_t const wdog_pads[] = { > IMX8MN_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL), > }; > @@ -95,7 +89,6 @@ int board_early_init_f(void) > imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads)); > set_wdog_reset(wdog); > > - imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads)); > init_uart_clk(1); > > return 0; > @@ -114,14 +107,14 @@ void board_init_f(ulong dummy) > > timer_init(); > > - preloader_console_init(); > - > ret = spl_init(); > if (ret) { > debug("spl_init() failed: %d\n", ret); > hang(); > } > > + preloader_console_init(); > + > enable_tzc380(); > > /* DDR initialization */ > diff --git a/configs/imx8mm_beacon_defconfig b/configs/imx8mm_beacon_defconfig > index 9cd8ac97285..a8981975f66 100644 > --- a/configs/imx8mm_beacon_defconfig > +++ b/configs/imx8mm_beacon_defconfig > @@ -112,7 +112,6 @@ CONFIG_SPL_DM_REGULATOR_FIXED=y > CONFIG_DM_REGULATOR_GPIO=y > CONFIG_CONS_INDEX=2 > CONFIG_DM_SERIAL=y > -# CONFIG_SPL_DM_SERIAL is not set > CONFIG_MXC_UART=y > CONFIG_SPI=y > CONFIG_DM_SPI=y > diff --git a/configs/imx8mn_beacon_2g_defconfig b/configs/imx8mn_beacon_2g_defconfig > index 145f96d491d..cf1720725d0 100644 > --- a/configs/imx8mn_beacon_2g_defconfig > +++ b/configs/imx8mn_beacon_2g_defconfig > @@ -114,7 +114,6 @@ CONFIG_DM_REGULATOR_FIXED=y > CONFIG_DM_REGULATOR_GPIO=y > CONFIG_DM_RESET=y > CONFIG_DM_SERIAL=y > -# CONFIG_SPL_DM_SERIAL is not set > CONFIG_MXC_UART=y > CONFIG_SPI=y > CONFIG_DM_SPI=y > diff --git a/configs/imx8mn_beacon_defconfig b/configs/imx8mn_beacon_defconfig > index 9052e68e967..882a6044989 100644 > --- a/configs/imx8mn_beacon_defconfig > +++ b/configs/imx8mn_beacon_defconfig > @@ -118,7 +118,6 @@ CONFIG_DM_REGULATOR_FIXED=y > CONFIG_DM_REGULATOR_GPIO=y > CONFIG_DM_RESET=y > CONFIG_DM_SERIAL=y > -# CONFIG_SPL_DM_SERIAL is not set > CONFIG_MXC_UART=y > CONFIG_SPI=y > CONFIG_DM_SPI=y > diff --git a/include/configs/imx8mm_beacon.h b/include/configs/imx8mm_beacon.h > index 7c17f14964f..4c9b5491f78 100644 > --- a/include/configs/imx8mm_beacon.h > +++ b/include/configs/imx8mm_beacon.h > @@ -91,8 +91,6 @@ > #define PHYS_SDRAM 0x40000000 > #define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */ > > -#define CONFIG_MXC_UART_BASE UART2_BASE_ADDR > - > /* Monitor Command Prompt */ > #define CONFIG_SYS_CBSIZE 2048 > #define CONFIG_SYS_MAXARGS 64 > diff --git a/include/configs/imx8mn_beacon.h b/include/configs/imx8mn_beacon.h > index 41ce3c1c8ce..c16dda5e22c 100644 > --- a/include/configs/imx8mn_beacon.h > +++ b/include/configs/imx8mn_beacon.h > @@ -107,8 +107,6 @@ > #define PHYS_SDRAM_SIZE 0x40000000 /* 1GB DDR */ > #endif > > -#define CONFIG_MXC_UART_BASE UART2_BASE_ADDR > - > /* Monitor Command Prompt */ > #define CONFIG_SYS_CBSIZE 2048 > #define CONFIG_SYS_MAXARGS 64 > -- > 2.36.0 >