* [PATCH v1 0/7] imx-gpcv2 improvements
@ 2021-04-07 21:21 ` Adrien Grassein
0 siblings, 0 replies; 26+ messages in thread
From: Adrien Grassein @ 2021-04-07 21:21 UTC (permalink / raw)
Cc: robh+dt, shawnguo, s.hauer, kernel, festevam, linux-imx, l.stach,
Anson.Huang, krzk, peng.fan, aisheng.dong, qiangqing.zhang,
alice.guo, aford173, agx, andrew.smirnov, devicetree,
linux-arm-kernel, linux-kernel, Adrien Grassein
Hi,
This patch set aims is to add the support of the i.MX8 MM power domains
on the mainline kernel.
To achieve this, I do several patches
- Check errors when reading or writing registers (concerns i.MX8M base
implementation);
- Fix power up/down sequence. Handshake was not checked and it was
not called at the appropriate time (concerns i.MX8M base
implementaions);
- Allow domains without power sequence control like the HSIOMIX of the
i.MX8MM.
- Add some i.MX8MM domains (HSIO and OTGS);
- Introduce quirks. For example, i.MX8MM OTG domains should not be
powered off (seen n the source code of th i.MX ATF). Quirks are
easily upgrable for other cases.
- Finally I defined power domains into the imx8mm.dtb file.
I know that this kind of patch is rejected by NXP ut the other way
(callin ATF directly) was also rejected.
I also know that NXP is concerned abou adding hundred lines of codes for
each new SOC but it' the way it works on Linux. And the "added code"
mainly consist of adding structures, defines and generic methods for
regmap.
If it's a real problem, maybe we can introduc a new "gpcv3" driver for
i.MX8MM, i.MX8MN and i.MX8MP.
Thanks,
Adrien Grassein (7):
soc: imx: gpcv2: check for errors when r/w registers
soc: imx: gpcv2: Fix power up/down sequence
soc: imx: gpcv2: allow domains without power sequence control
dt-bindings: power: fsl,imx-gpcv2: add definitions for i.MX8MM
soc: imx: gpcv2: add HSIOMIX and USB domains for i.MX8MM
soc: imx: gpcv2: add quirks to domains
arm64: dts: imx8mm: add power-domains
.../bindings/power/fsl,imx-gpcv2.yaml | 7 +-
arch/arm64/boot/dts/freescale/imx8mm.dtsi | 35 ++
drivers/soc/imx/gpcv2.c | 336 ++++++++++++++----
include/dt-bindings/power/imx8mm-power.h | 21 ++
4 files changed, 333 insertions(+), 66 deletions(-)
create mode 100644 include/dt-bindings/power/imx8mm-power.h
--
2.25.1
^ permalink raw reply [flat|nested] 26+ messages in thread
* [PATCH v1 0/7] imx-gpcv2 improvements
@ 2021-04-07 21:21 ` Adrien Grassein
0 siblings, 0 replies; 26+ messages in thread
From: Adrien Grassein @ 2021-04-07 21:21 UTC (permalink / raw)
Cc: robh+dt, shawnguo, s.hauer, kernel, festevam, linux-imx, l.stach,
Anson.Huang, krzk, peng.fan, aisheng.dong, qiangqing.zhang,
alice.guo, aford173, agx, andrew.smirnov, devicetree,
linux-arm-kernel, linux-kernel, Adrien Grassein
Hi,
This patch set aims is to add the support of the i.MX8 MM power domains
on the mainline kernel.
To achieve this, I do several patches
- Check errors when reading or writing registers (concerns i.MX8M base
implementation);
- Fix power up/down sequence. Handshake was not checked and it was
not called at the appropriate time (concerns i.MX8M base
implementaions);
- Allow domains without power sequence control like the HSIOMIX of the
i.MX8MM.
- Add some i.MX8MM domains (HSIO and OTGS);
- Introduce quirks. For example, i.MX8MM OTG domains should not be
powered off (seen n the source code of th i.MX ATF). Quirks are
easily upgrable for other cases.
- Finally I defined power domains into the imx8mm.dtb file.
I know that this kind of patch is rejected by NXP ut the other way
(callin ATF directly) was also rejected.
I also know that NXP is concerned abou adding hundred lines of codes for
each new SOC but it' the way it works on Linux. And the "added code"
mainly consist of adding structures, defines and generic methods for
regmap.
If it's a real problem, maybe we can introduc a new "gpcv3" driver for
i.MX8MM, i.MX8MN and i.MX8MP.
Thanks,
Adrien Grassein (7):
soc: imx: gpcv2: check for errors when r/w registers
soc: imx: gpcv2: Fix power up/down sequence
soc: imx: gpcv2: allow domains without power sequence control
dt-bindings: power: fsl,imx-gpcv2: add definitions for i.MX8MM
soc: imx: gpcv2: add HSIOMIX and USB domains for i.MX8MM
soc: imx: gpcv2: add quirks to domains
arm64: dts: imx8mm: add power-domains
.../bindings/power/fsl,imx-gpcv2.yaml | 7 +-
arch/arm64/boot/dts/freescale/imx8mm.dtsi | 35 ++
drivers/soc/imx/gpcv2.c | 336 ++++++++++++++----
include/dt-bindings/power/imx8mm-power.h | 21 ++
4 files changed, 333 insertions(+), 66 deletions(-)
create mode 100644 include/dt-bindings/power/imx8mm-power.h
--
2.25.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 26+ messages in thread
* [PATCH v1 1/7] soc: imx: gpcv2: check for errors when r/w registers
2021-04-07 21:21 ` Adrien Grassein
@ 2021-04-07 21:21 ` Adrien Grassein
-1 siblings, 0 replies; 26+ messages in thread
From: Adrien Grassein @ 2021-04-07 21:21 UTC (permalink / raw)
Cc: robh+dt, shawnguo, s.hauer, kernel, festevam, linux-imx, l.stach,
Anson.Huang, krzk, peng.fan, aisheng.dong, qiangqing.zhang,
alice.guo, aford173, agx, andrew.smirnov, devicetree,
linux-arm-kernel, linux-kernel, Adrien Grassein
Errors were not checked after each access to registers
and clocks initialisation.
Signed-off-by: Adrien Grassein <adrien.grassein@gmail.com>
---
drivers/soc/imx/gpcv2.c | 62 ++++++++++++++++++++++++++++++-----------
1 file changed, 45 insertions(+), 17 deletions(-)
diff --git a/drivers/soc/imx/gpcv2.c b/drivers/soc/imx/gpcv2.c
index db7e7fc321b1..8ec5b1b817c7 100644
--- a/drivers/soc/imx/gpcv2.c
+++ b/drivers/soc/imx/gpcv2.c
@@ -140,8 +140,12 @@ static int imx_gpc_pu_pgc_sw_pxx_req(struct generic_pm_domain *genpd,
int i, ret = 0;
u32 pxx_req;
- regmap_update_bits(domain->regmap, GPC_PGC_CPU_MAPPING,
- domain->bits.map, domain->bits.map);
+ ret = regmap_update_bits(domain->regmap, GPC_PGC_CPU_MAPPING,
+ domain->bits.map, domain->bits.map);
+ if (ret) {
+ dev_err(domain->dev, "failed to map GPC PGC domain\n");
+ return ret;
+ }
if (has_regulator && on) {
ret = regulator_enable(domain->regulator);
@@ -152,19 +156,39 @@ static int imx_gpc_pu_pgc_sw_pxx_req(struct generic_pm_domain *genpd,
}
/* Enable reset clocks for all devices in the domain */
- for (i = 0; i < domain->num_clks; i++)
- clk_prepare_enable(domain->clk[i]);
+ for (i = 0; i < domain->num_clks; i++) {
+ ret = clk_prepare_enable(domain->clk[i]);
+ if (ret) {
+ dev_err(domain->dev, "failed to enable clocks\n");
+ goto disable_clocks;
+ }
+ }
- if (enable_power_control)
- regmap_update_bits(domain->regmap, GPC_PGC_CTRL(domain->pgc),
- GPC_PGC_CTRL_PCR, GPC_PGC_CTRL_PCR);
+ if (enable_power_control) {
+ ret = regmap_update_bits(domain->regmap, GPC_PGC_CTRL(domain->pgc),
+ GPC_PGC_CTRL_PCR, GPC_PGC_CTRL_PCR);
+ if (ret) {
+ dev_err(domain->dev, "failed to enable power control\n");
+ goto disable_clocks;
+ }
+ }
- if (domain->bits.hsk)
- regmap_update_bits(domain->regmap, GPC_PU_PWRHSK,
- domain->bits.hsk, on ? domain->bits.hsk : 0);
+ if (domain->bits.hsk) {
+ ret = regmap_update_bits(domain->regmap, GPC_PU_PWRHSK,
+ domain->bits.hsk,
+ on ? domain->bits.hsk : 0);
+ if (ret) {
+ dev_err(domain->dev, "Failed to initiate handshake\n");
+ goto disable_power_control;
+ }
+ }
- regmap_update_bits(domain->regmap, offset,
- domain->bits.pxx, domain->bits.pxx);
+ ret = regmap_update_bits(domain->regmap, offset,
+ domain->bits.pxx, domain->bits.pxx);
+ if (ret) {
+ dev_err(domain->dev, "failed to command PGC\n");
+ goto disable_power_control;
+ }
/*
* As per "5.5.9.4 Example Code 4" in IMX7DRM.pdf wait
@@ -173,8 +197,15 @@ static int imx_gpc_pu_pgc_sw_pxx_req(struct generic_pm_domain *genpd,
ret = regmap_read_poll_timeout(domain->regmap, offset, pxx_req,
!(pxx_req & domain->bits.pxx),
0, USEC_PER_MSEC);
- if (ret) {
+ if (ret)
dev_err(domain->dev, "failed to command PGC\n");
+
+disable_power_control:
+ if (enable_power_control)
+ regmap_update_bits(domain->regmap, GPC_PGC_CTRL(domain->pgc),
+ GPC_PGC_CTRL_PCR, 0);
+
+ if (ret) {
/*
* If we were in a process of enabling a
* domain and failed we might as well disable
@@ -185,10 +216,7 @@ static int imx_gpc_pu_pgc_sw_pxx_req(struct generic_pm_domain *genpd,
on = !on;
}
- if (enable_power_control)
- regmap_update_bits(domain->regmap, GPC_PGC_CTRL(domain->pgc),
- GPC_PGC_CTRL_PCR, 0);
-
+disable_clocks:
/* Disable reset clocks for all devices in the domain */
for (i = 0; i < domain->num_clks; i++)
clk_disable_unprepare(domain->clk[i]);
--
2.25.1
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH v1 1/7] soc: imx: gpcv2: check for errors when r/w registers
@ 2021-04-07 21:21 ` Adrien Grassein
0 siblings, 0 replies; 26+ messages in thread
From: Adrien Grassein @ 2021-04-07 21:21 UTC (permalink / raw)
Cc: robh+dt, shawnguo, s.hauer, kernel, festevam, linux-imx, l.stach,
Anson.Huang, krzk, peng.fan, aisheng.dong, qiangqing.zhang,
alice.guo, aford173, agx, andrew.smirnov, devicetree,
linux-arm-kernel, linux-kernel, Adrien Grassein
Errors were not checked after each access to registers
and clocks initialisation.
Signed-off-by: Adrien Grassein <adrien.grassein@gmail.com>
---
drivers/soc/imx/gpcv2.c | 62 ++++++++++++++++++++++++++++++-----------
1 file changed, 45 insertions(+), 17 deletions(-)
diff --git a/drivers/soc/imx/gpcv2.c b/drivers/soc/imx/gpcv2.c
index db7e7fc321b1..8ec5b1b817c7 100644
--- a/drivers/soc/imx/gpcv2.c
+++ b/drivers/soc/imx/gpcv2.c
@@ -140,8 +140,12 @@ static int imx_gpc_pu_pgc_sw_pxx_req(struct generic_pm_domain *genpd,
int i, ret = 0;
u32 pxx_req;
- regmap_update_bits(domain->regmap, GPC_PGC_CPU_MAPPING,
- domain->bits.map, domain->bits.map);
+ ret = regmap_update_bits(domain->regmap, GPC_PGC_CPU_MAPPING,
+ domain->bits.map, domain->bits.map);
+ if (ret) {
+ dev_err(domain->dev, "failed to map GPC PGC domain\n");
+ return ret;
+ }
if (has_regulator && on) {
ret = regulator_enable(domain->regulator);
@@ -152,19 +156,39 @@ static int imx_gpc_pu_pgc_sw_pxx_req(struct generic_pm_domain *genpd,
}
/* Enable reset clocks for all devices in the domain */
- for (i = 0; i < domain->num_clks; i++)
- clk_prepare_enable(domain->clk[i]);
+ for (i = 0; i < domain->num_clks; i++) {
+ ret = clk_prepare_enable(domain->clk[i]);
+ if (ret) {
+ dev_err(domain->dev, "failed to enable clocks\n");
+ goto disable_clocks;
+ }
+ }
- if (enable_power_control)
- regmap_update_bits(domain->regmap, GPC_PGC_CTRL(domain->pgc),
- GPC_PGC_CTRL_PCR, GPC_PGC_CTRL_PCR);
+ if (enable_power_control) {
+ ret = regmap_update_bits(domain->regmap, GPC_PGC_CTRL(domain->pgc),
+ GPC_PGC_CTRL_PCR, GPC_PGC_CTRL_PCR);
+ if (ret) {
+ dev_err(domain->dev, "failed to enable power control\n");
+ goto disable_clocks;
+ }
+ }
- if (domain->bits.hsk)
- regmap_update_bits(domain->regmap, GPC_PU_PWRHSK,
- domain->bits.hsk, on ? domain->bits.hsk : 0);
+ if (domain->bits.hsk) {
+ ret = regmap_update_bits(domain->regmap, GPC_PU_PWRHSK,
+ domain->bits.hsk,
+ on ? domain->bits.hsk : 0);
+ if (ret) {
+ dev_err(domain->dev, "Failed to initiate handshake\n");
+ goto disable_power_control;
+ }
+ }
- regmap_update_bits(domain->regmap, offset,
- domain->bits.pxx, domain->bits.pxx);
+ ret = regmap_update_bits(domain->regmap, offset,
+ domain->bits.pxx, domain->bits.pxx);
+ if (ret) {
+ dev_err(domain->dev, "failed to command PGC\n");
+ goto disable_power_control;
+ }
/*
* As per "5.5.9.4 Example Code 4" in IMX7DRM.pdf wait
@@ -173,8 +197,15 @@ static int imx_gpc_pu_pgc_sw_pxx_req(struct generic_pm_domain *genpd,
ret = regmap_read_poll_timeout(domain->regmap, offset, pxx_req,
!(pxx_req & domain->bits.pxx),
0, USEC_PER_MSEC);
- if (ret) {
+ if (ret)
dev_err(domain->dev, "failed to command PGC\n");
+
+disable_power_control:
+ if (enable_power_control)
+ regmap_update_bits(domain->regmap, GPC_PGC_CTRL(domain->pgc),
+ GPC_PGC_CTRL_PCR, 0);
+
+ if (ret) {
/*
* If we were in a process of enabling a
* domain and failed we might as well disable
@@ -185,10 +216,7 @@ static int imx_gpc_pu_pgc_sw_pxx_req(struct generic_pm_domain *genpd,
on = !on;
}
- if (enable_power_control)
- regmap_update_bits(domain->regmap, GPC_PGC_CTRL(domain->pgc),
- GPC_PGC_CTRL_PCR, 0);
-
+disable_clocks:
/* Disable reset clocks for all devices in the domain */
for (i = 0; i < domain->num_clks; i++)
clk_disable_unprepare(domain->clk[i]);
--
2.25.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH v1 2/7] soc: imx: gpcv2: Fix power up/down sequence
2021-04-07 21:21 ` Adrien Grassein
@ 2021-04-07 21:21 ` Adrien Grassein
-1 siblings, 0 replies; 26+ messages in thread
From: Adrien Grassein @ 2021-04-07 21:21 UTC (permalink / raw)
Cc: robh+dt, shawnguo, s.hauer, kernel, festevam, linux-imx, l.stach,
Anson.Huang, krzk, peng.fan, aisheng.dong, qiangqing.zhang,
alice.guo, aford173, agx, andrew.smirnov, devicetree,
linux-arm-kernel, linux-kernel, Adrien Grassein
Power up/down sequence were wrongly scheduled.
The ADB400 were triggered at the bad time.
The Handshake were not checked.
The solution is to:
- Split power up and power down sequences;
- Add a register holding the bit to check;
Signed-off-by: Adrien Grassein <adrien.grassein@gmail.com>
---
drivers/soc/imx/gpcv2.c | 235 ++++++++++++++++++++++++++++------------
1 file changed, 163 insertions(+), 72 deletions(-)
diff --git a/drivers/soc/imx/gpcv2.c b/drivers/soc/imx/gpcv2.c
index 8ec5b1b817c7..7afb81489f21 100644
--- a/drivers/soc/imx/gpcv2.c
+++ b/drivers/soc/imx/gpcv2.c
@@ -70,8 +70,11 @@
#define GPC_PU_PWRHSK 0x1fc
#define IMX8M_GPU_HSK_PWRDNREQN BIT(6)
+#define IMX8M_GPU_HSK_PWRDNACKN BIT(26)
#define IMX8M_VPU_HSK_PWRDNREQN BIT(5)
+#define IMX8M_VPU_HSK_PWRDNACKN BIT(25)
#define IMX8M_DISP_HSK_PWRDNREQN BIT(4)
+#define IMX8M_DISP_HSK_PWRDNACKN BIT(24)
/*
* The PGC offset values in Reference Manual
@@ -102,6 +105,8 @@
#define GPC_CLK_MAX 6
+static DEFINE_MUTEX(gpc_pd_mutex);
+
struct imx_pgc_domain {
struct generic_pm_domain genpd;
struct regmap *regmap;
@@ -114,7 +119,8 @@ struct imx_pgc_domain {
const struct {
u32 pxx;
u32 map;
- u32 hsk;
+ u32 hsk_req;
+ u32 hsk_ack;
} bits;
const int voltage;
@@ -127,34 +133,25 @@ struct imx_pgc_domain_data {
const struct regmap_access_table *reg_access_table;
};
-static int imx_gpc_pu_pgc_sw_pxx_req(struct generic_pm_domain *genpd,
- bool on)
+static int imx_gpc_pu_pgc_sw_pup_req(struct generic_pm_domain *genpd)
{
struct imx_pgc_domain *domain = container_of(genpd,
struct imx_pgc_domain,
genpd);
- unsigned int offset = on ?
- GPC_PU_PGC_SW_PUP_REQ : GPC_PU_PGC_SW_PDN_REQ;
- const bool enable_power_control = !on;
- const bool has_regulator = !IS_ERR(domain->regulator);
int i, ret = 0;
- u32 pxx_req;
+ u32 value;
- ret = regmap_update_bits(domain->regmap, GPC_PGC_CPU_MAPPING,
- domain->bits.map, domain->bits.map);
- if (ret) {
- dev_err(domain->dev, "failed to map GPC PGC domain\n");
- return ret;
- }
-
- if (has_regulator && on) {
+ /* Enable regulator if needed */
+ if (!IS_ERR(domain->regulator)) {
ret = regulator_enable(domain->regulator);
if (ret) {
dev_err(domain->dev, "failed to enable regulator\n");
- goto unmap;
+ return ret;
}
}
+ mutex_lock(&gpc_pd_mutex);
+
/* Enable reset clocks for all devices in the domain */
for (i = 0; i < domain->num_clks; i++) {
ret = clk_prepare_enable(domain->clk[i]);
@@ -164,87 +161,178 @@ static int imx_gpc_pu_pgc_sw_pxx_req(struct generic_pm_domain *genpd,
}
}
- if (enable_power_control) {
- ret = regmap_update_bits(domain->regmap, GPC_PGC_CTRL(domain->pgc),
- GPC_PGC_CTRL_PCR, GPC_PGC_CTRL_PCR);
+ /* Map the domain to the A53 core */
+ ret = regmap_update_bits(domain->regmap, GPC_PGC_CPU_MAPPING,
+ domain->bits.map, domain->bits.map);
+ if (ret) {
+ dev_err(domain->dev, "failed to map GPC PGC domain\n");
+ goto disable_clocks;
+ }
+
+ /* Request Power Up of the domain */
+ ret = regmap_update_bits(domain->regmap, GPC_PU_PGC_SW_PUP_REQ,
+ domain->bits.pxx, domain->bits.pxx);
+ if (ret) {
+ dev_err(domain->dev, "failed to command PGC\n");
+ goto unmap;
+ }
+
+ /*
+ * As per "5.5.9.4 Example Code 4" in IMX7DRM.pdf wait
+ * for PUP_REQ/PDN_REQ bit to be cleared
+ */
+ ret = regmap_read_poll_timeout(domain->regmap, GPC_PU_PGC_SW_PUP_REQ,
+ value,
+ !(value & domain->bits.pxx),
+ 0, USEC_PER_MSEC);
+ if (ret) {
+ dev_err(domain->dev, "failed to command PGC\n");
+ goto unmap;
+ }
+
+ /* Disable power control */
+ ret = regmap_update_bits(domain->regmap, GPC_PGC_CTRL(domain->pgc),
+ GPC_PGC_CTRL_PCR, 0);
+ if (ret) {
+ dev_err(domain->dev, "Failed to disable power control !\n");
+ goto unmap;
+ }
+
+ /* request the ADB400 to power up */
+ if (domain->bits.hsk_req) {
+ regmap_update_bits(domain->regmap, GPC_PU_PWRHSK,
+ domain->bits.hsk_req, domain->bits.hsk_req);
+
+ ret = regmap_read_poll_timeout(domain->regmap, GPC_PU_PWRHSK,
+ value,
+ (value & domain->bits.hsk_ack),
+ 0, USEC_PER_MSEC);
+ if (ret)
+ dev_err(domain->dev, "Bad ACK while powering on %s\n",
+ genpd->name);
+ }
+
+ regmap_update_bits(domain->regmap, GPC_PGC_CPU_MAPPING,
+ domain->bits.map, 0);
+
+ /* Disable all clocks */
+ for (i = 0; i < domain->num_clks; i++)
+ clk_disable_unprepare(domain->clk[i]);
+
+ mutex_unlock(&gpc_pd_mutex);
+
+ return 0;
+
+unmap:
+ if (domain->bits.map)
+ regmap_update_bits(domain->regmap, GPC_PGC_CPU_MAPPING,
+ domain->bits.map, 0);
+
+disable_clocks:
+ for (i--; i >= 0; i--)
+ clk_disable_unprepare(domain->clk[i]);
+
+ mutex_unlock(&gpc_pd_mutex);
+ return ret;
+}
+
+static int imx_gpc_pu_pgc_sw_pdn_req(struct generic_pm_domain *genpd)
+{
+ struct imx_pgc_domain *domain = container_of(genpd,
+ struct imx_pgc_domain,
+ genpd);
+ int i, ret = 0;
+ u32 value;
+
+ mutex_lock(&gpc_pd_mutex);
+
+ /* Enable reset clocks for all devices in the domain */
+ for (i = 0; i < domain->num_clks; i++) {
+ ret = clk_prepare_enable(domain->clk[i]);
if (ret) {
- dev_err(domain->dev, "failed to enable power control\n");
+ dev_err(domain->dev, "failed to enable clocks\n");
goto disable_clocks;
}
}
- if (domain->bits.hsk) {
- ret = regmap_update_bits(domain->regmap, GPC_PU_PWRHSK,
- domain->bits.hsk,
- on ? domain->bits.hsk : 0);
- if (ret) {
- dev_err(domain->dev, "Failed to initiate handshake\n");
- goto disable_power_control;
- }
+ /* Map the domain to the A53 core */
+ ret = regmap_update_bits(domain->regmap, GPC_PGC_CPU_MAPPING,
+ domain->bits.map, domain->bits.map);
+ if (ret) {
+ dev_err(domain->dev, "failed to map GPC PGC domain\n");
+ goto disable_clocks;
+ }
+
+ /* request the ADB400 to power down */
+ if (domain->bits.hsk_req) {
+ regmap_update_bits(domain->regmap, GPC_PU_PWRHSK,
+ domain->bits.hsk_req, 0);
+
+ ret = regmap_read_poll_timeout(domain->regmap, GPC_PU_PWRHSK,
+ value,
+ !(value & domain->bits.hsk_ack),
+ 0, USEC_PER_MSEC);
+ if (ret)
+ dev_err(domain->dev, "Bad ACK while powering down %s\n",
+ genpd->name);
+
}
- ret = regmap_update_bits(domain->regmap, offset,
+ /* Enable power control */
+ ret = regmap_update_bits(domain->regmap, GPC_PGC_CTRL(domain->pgc),
+ GPC_PGC_CTRL_PCR, GPC_PGC_CTRL_PCR);
+ if (ret) {
+ dev_err(domain->dev, "Failed to enable power control !\n");
+ goto unmap;
+ }
+
+ /* Request Power Down of the domain */
+ ret = regmap_update_bits(domain->regmap, GPC_PU_PGC_SW_PDN_REQ,
domain->bits.pxx, domain->bits.pxx);
if (ret) {
dev_err(domain->dev, "failed to command PGC\n");
- goto disable_power_control;
+ goto unmap;
}
/*
* As per "5.5.9.4 Example Code 4" in IMX7DRM.pdf wait
* for PUP_REQ/PDN_REQ bit to be cleared
*/
- ret = regmap_read_poll_timeout(domain->regmap, offset, pxx_req,
- !(pxx_req & domain->bits.pxx),
+ ret = regmap_read_poll_timeout(domain->regmap, GPC_PU_PGC_SW_PDN_REQ,
+ value,
+ !(value & domain->bits.pxx),
0, USEC_PER_MSEC);
if (ret)
dev_err(domain->dev, "failed to command PGC\n");
-disable_power_control:
- if (enable_power_control)
- regmap_update_bits(domain->regmap, GPC_PGC_CTRL(domain->pgc),
- GPC_PGC_CTRL_PCR, 0);
-
- if (ret) {
- /*
- * If we were in a process of enabling a
- * domain and failed we might as well disable
- * the regulator we just enabled. And if it
- * was the opposite situation and we failed to
- * power down -- keep the regulator on
- */
- on = !on;
+ if (!IS_ERR(domain->regulator)) {
+ ret = regulator_disable(domain->regulator);
+ if (ret)
+ dev_err(domain->dev, "failed to disable regulator\n");
}
-disable_clocks:
- /* Disable reset clocks for all devices in the domain */
+ regmap_update_bits(domain->regmap, GPC_PGC_CPU_MAPPING,
+ domain->bits.map, 0);
+
+ /* Disable all clocks */
for (i = 0; i < domain->num_clks; i++)
clk_disable_unprepare(domain->clk[i]);
- if (has_regulator && !on) {
- int err;
+ mutex_unlock(&gpc_pd_mutex);
+ return 0;
- err = regulator_disable(domain->regulator);
- if (err)
- dev_err(domain->dev,
- "failed to disable regulator: %d\n", err);
- /* Preserve earlier error code */
- ret = ret ?: err;
- }
unmap:
- regmap_update_bits(domain->regmap, GPC_PGC_CPU_MAPPING,
- domain->bits.map, 0);
- return ret;
-}
+ if (domain->bits.map)
+ regmap_update_bits(domain->regmap, GPC_PGC_CPU_MAPPING,
+ domain->bits.map, 0);
-static int imx_gpc_pu_pgc_sw_pup_req(struct generic_pm_domain *genpd)
-{
- return imx_gpc_pu_pgc_sw_pxx_req(genpd, true);
-}
+disable_clocks:
+ for (i--; i >= 0; i--)
+ clk_disable_unprepare(domain->clk[i]);
+
+ mutex_unlock(&gpc_pd_mutex);
+ return ret;
-static int imx_gpc_pu_pgc_sw_pdn_req(struct generic_pm_domain *genpd)
-{
- return imx_gpc_pu_pgc_sw_pxx_req(genpd, false);
}
static const struct imx_pgc_domain imx7_pgc_domains[] = {
@@ -370,7 +458,8 @@ static const struct imx_pgc_domain imx8m_pgc_domains[] = {
.bits = {
.pxx = IMX8M_GPU_SW_Pxx_REQ,
.map = IMX8M_GPU_A53_DOMAIN,
- .hsk = IMX8M_GPU_HSK_PWRDNREQN,
+ .hsk_req = IMX8M_GPU_HSK_PWRDNREQN,
+ .hsk_ack = IMX8M_GPU_HSK_PWRDNACKN
},
.pgc = IMX8M_PGC_GPU,
},
@@ -382,7 +471,8 @@ static const struct imx_pgc_domain imx8m_pgc_domains[] = {
.bits = {
.pxx = IMX8M_VPU_SW_Pxx_REQ,
.map = IMX8M_VPU_A53_DOMAIN,
- .hsk = IMX8M_VPU_HSK_PWRDNREQN,
+ .hsk_req = IMX8M_VPU_HSK_PWRDNREQN,
+ .hsk_ack = IMX8M_VPU_HSK_PWRDNACKN
},
.pgc = IMX8M_PGC_VPU,
},
@@ -394,7 +484,8 @@ static const struct imx_pgc_domain imx8m_pgc_domains[] = {
.bits = {
.pxx = IMX8M_DISP_SW_Pxx_REQ,
.map = IMX8M_DISP_A53_DOMAIN,
- .hsk = IMX8M_DISP_HSK_PWRDNREQN,
+ .hsk_req = IMX8M_DISP_HSK_PWRDNREQN,
+ .hsk_ack = IMX8M_DISP_HSK_PWRDNACKN
},
.pgc = IMX8M_PGC_DISP,
},
--
2.25.1
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH v1 2/7] soc: imx: gpcv2: Fix power up/down sequence
@ 2021-04-07 21:21 ` Adrien Grassein
0 siblings, 0 replies; 26+ messages in thread
From: Adrien Grassein @ 2021-04-07 21:21 UTC (permalink / raw)
Cc: robh+dt, shawnguo, s.hauer, kernel, festevam, linux-imx, l.stach,
Anson.Huang, krzk, peng.fan, aisheng.dong, qiangqing.zhang,
alice.guo, aford173, agx, andrew.smirnov, devicetree,
linux-arm-kernel, linux-kernel, Adrien Grassein
Power up/down sequence were wrongly scheduled.
The ADB400 were triggered at the bad time.
The Handshake were not checked.
The solution is to:
- Split power up and power down sequences;
- Add a register holding the bit to check;
Signed-off-by: Adrien Grassein <adrien.grassein@gmail.com>
---
drivers/soc/imx/gpcv2.c | 235 ++++++++++++++++++++++++++++------------
1 file changed, 163 insertions(+), 72 deletions(-)
diff --git a/drivers/soc/imx/gpcv2.c b/drivers/soc/imx/gpcv2.c
index 8ec5b1b817c7..7afb81489f21 100644
--- a/drivers/soc/imx/gpcv2.c
+++ b/drivers/soc/imx/gpcv2.c
@@ -70,8 +70,11 @@
#define GPC_PU_PWRHSK 0x1fc
#define IMX8M_GPU_HSK_PWRDNREQN BIT(6)
+#define IMX8M_GPU_HSK_PWRDNACKN BIT(26)
#define IMX8M_VPU_HSK_PWRDNREQN BIT(5)
+#define IMX8M_VPU_HSK_PWRDNACKN BIT(25)
#define IMX8M_DISP_HSK_PWRDNREQN BIT(4)
+#define IMX8M_DISP_HSK_PWRDNACKN BIT(24)
/*
* The PGC offset values in Reference Manual
@@ -102,6 +105,8 @@
#define GPC_CLK_MAX 6
+static DEFINE_MUTEX(gpc_pd_mutex);
+
struct imx_pgc_domain {
struct generic_pm_domain genpd;
struct regmap *regmap;
@@ -114,7 +119,8 @@ struct imx_pgc_domain {
const struct {
u32 pxx;
u32 map;
- u32 hsk;
+ u32 hsk_req;
+ u32 hsk_ack;
} bits;
const int voltage;
@@ -127,34 +133,25 @@ struct imx_pgc_domain_data {
const struct regmap_access_table *reg_access_table;
};
-static int imx_gpc_pu_pgc_sw_pxx_req(struct generic_pm_domain *genpd,
- bool on)
+static int imx_gpc_pu_pgc_sw_pup_req(struct generic_pm_domain *genpd)
{
struct imx_pgc_domain *domain = container_of(genpd,
struct imx_pgc_domain,
genpd);
- unsigned int offset = on ?
- GPC_PU_PGC_SW_PUP_REQ : GPC_PU_PGC_SW_PDN_REQ;
- const bool enable_power_control = !on;
- const bool has_regulator = !IS_ERR(domain->regulator);
int i, ret = 0;
- u32 pxx_req;
+ u32 value;
- ret = regmap_update_bits(domain->regmap, GPC_PGC_CPU_MAPPING,
- domain->bits.map, domain->bits.map);
- if (ret) {
- dev_err(domain->dev, "failed to map GPC PGC domain\n");
- return ret;
- }
-
- if (has_regulator && on) {
+ /* Enable regulator if needed */
+ if (!IS_ERR(domain->regulator)) {
ret = regulator_enable(domain->regulator);
if (ret) {
dev_err(domain->dev, "failed to enable regulator\n");
- goto unmap;
+ return ret;
}
}
+ mutex_lock(&gpc_pd_mutex);
+
/* Enable reset clocks for all devices in the domain */
for (i = 0; i < domain->num_clks; i++) {
ret = clk_prepare_enable(domain->clk[i]);
@@ -164,87 +161,178 @@ static int imx_gpc_pu_pgc_sw_pxx_req(struct generic_pm_domain *genpd,
}
}
- if (enable_power_control) {
- ret = regmap_update_bits(domain->regmap, GPC_PGC_CTRL(domain->pgc),
- GPC_PGC_CTRL_PCR, GPC_PGC_CTRL_PCR);
+ /* Map the domain to the A53 core */
+ ret = regmap_update_bits(domain->regmap, GPC_PGC_CPU_MAPPING,
+ domain->bits.map, domain->bits.map);
+ if (ret) {
+ dev_err(domain->dev, "failed to map GPC PGC domain\n");
+ goto disable_clocks;
+ }
+
+ /* Request Power Up of the domain */
+ ret = regmap_update_bits(domain->regmap, GPC_PU_PGC_SW_PUP_REQ,
+ domain->bits.pxx, domain->bits.pxx);
+ if (ret) {
+ dev_err(domain->dev, "failed to command PGC\n");
+ goto unmap;
+ }
+
+ /*
+ * As per "5.5.9.4 Example Code 4" in IMX7DRM.pdf wait
+ * for PUP_REQ/PDN_REQ bit to be cleared
+ */
+ ret = regmap_read_poll_timeout(domain->regmap, GPC_PU_PGC_SW_PUP_REQ,
+ value,
+ !(value & domain->bits.pxx),
+ 0, USEC_PER_MSEC);
+ if (ret) {
+ dev_err(domain->dev, "failed to command PGC\n");
+ goto unmap;
+ }
+
+ /* Disable power control */
+ ret = regmap_update_bits(domain->regmap, GPC_PGC_CTRL(domain->pgc),
+ GPC_PGC_CTRL_PCR, 0);
+ if (ret) {
+ dev_err(domain->dev, "Failed to disable power control !\n");
+ goto unmap;
+ }
+
+ /* request the ADB400 to power up */
+ if (domain->bits.hsk_req) {
+ regmap_update_bits(domain->regmap, GPC_PU_PWRHSK,
+ domain->bits.hsk_req, domain->bits.hsk_req);
+
+ ret = regmap_read_poll_timeout(domain->regmap, GPC_PU_PWRHSK,
+ value,
+ (value & domain->bits.hsk_ack),
+ 0, USEC_PER_MSEC);
+ if (ret)
+ dev_err(domain->dev, "Bad ACK while powering on %s\n",
+ genpd->name);
+ }
+
+ regmap_update_bits(domain->regmap, GPC_PGC_CPU_MAPPING,
+ domain->bits.map, 0);
+
+ /* Disable all clocks */
+ for (i = 0; i < domain->num_clks; i++)
+ clk_disable_unprepare(domain->clk[i]);
+
+ mutex_unlock(&gpc_pd_mutex);
+
+ return 0;
+
+unmap:
+ if (domain->bits.map)
+ regmap_update_bits(domain->regmap, GPC_PGC_CPU_MAPPING,
+ domain->bits.map, 0);
+
+disable_clocks:
+ for (i--; i >= 0; i--)
+ clk_disable_unprepare(domain->clk[i]);
+
+ mutex_unlock(&gpc_pd_mutex);
+ return ret;
+}
+
+static int imx_gpc_pu_pgc_sw_pdn_req(struct generic_pm_domain *genpd)
+{
+ struct imx_pgc_domain *domain = container_of(genpd,
+ struct imx_pgc_domain,
+ genpd);
+ int i, ret = 0;
+ u32 value;
+
+ mutex_lock(&gpc_pd_mutex);
+
+ /* Enable reset clocks for all devices in the domain */
+ for (i = 0; i < domain->num_clks; i++) {
+ ret = clk_prepare_enable(domain->clk[i]);
if (ret) {
- dev_err(domain->dev, "failed to enable power control\n");
+ dev_err(domain->dev, "failed to enable clocks\n");
goto disable_clocks;
}
}
- if (domain->bits.hsk) {
- ret = regmap_update_bits(domain->regmap, GPC_PU_PWRHSK,
- domain->bits.hsk,
- on ? domain->bits.hsk : 0);
- if (ret) {
- dev_err(domain->dev, "Failed to initiate handshake\n");
- goto disable_power_control;
- }
+ /* Map the domain to the A53 core */
+ ret = regmap_update_bits(domain->regmap, GPC_PGC_CPU_MAPPING,
+ domain->bits.map, domain->bits.map);
+ if (ret) {
+ dev_err(domain->dev, "failed to map GPC PGC domain\n");
+ goto disable_clocks;
+ }
+
+ /* request the ADB400 to power down */
+ if (domain->bits.hsk_req) {
+ regmap_update_bits(domain->regmap, GPC_PU_PWRHSK,
+ domain->bits.hsk_req, 0);
+
+ ret = regmap_read_poll_timeout(domain->regmap, GPC_PU_PWRHSK,
+ value,
+ !(value & domain->bits.hsk_ack),
+ 0, USEC_PER_MSEC);
+ if (ret)
+ dev_err(domain->dev, "Bad ACK while powering down %s\n",
+ genpd->name);
+
}
- ret = regmap_update_bits(domain->regmap, offset,
+ /* Enable power control */
+ ret = regmap_update_bits(domain->regmap, GPC_PGC_CTRL(domain->pgc),
+ GPC_PGC_CTRL_PCR, GPC_PGC_CTRL_PCR);
+ if (ret) {
+ dev_err(domain->dev, "Failed to enable power control !\n");
+ goto unmap;
+ }
+
+ /* Request Power Down of the domain */
+ ret = regmap_update_bits(domain->regmap, GPC_PU_PGC_SW_PDN_REQ,
domain->bits.pxx, domain->bits.pxx);
if (ret) {
dev_err(domain->dev, "failed to command PGC\n");
- goto disable_power_control;
+ goto unmap;
}
/*
* As per "5.5.9.4 Example Code 4" in IMX7DRM.pdf wait
* for PUP_REQ/PDN_REQ bit to be cleared
*/
- ret = regmap_read_poll_timeout(domain->regmap, offset, pxx_req,
- !(pxx_req & domain->bits.pxx),
+ ret = regmap_read_poll_timeout(domain->regmap, GPC_PU_PGC_SW_PDN_REQ,
+ value,
+ !(value & domain->bits.pxx),
0, USEC_PER_MSEC);
if (ret)
dev_err(domain->dev, "failed to command PGC\n");
-disable_power_control:
- if (enable_power_control)
- regmap_update_bits(domain->regmap, GPC_PGC_CTRL(domain->pgc),
- GPC_PGC_CTRL_PCR, 0);
-
- if (ret) {
- /*
- * If we were in a process of enabling a
- * domain and failed we might as well disable
- * the regulator we just enabled. And if it
- * was the opposite situation and we failed to
- * power down -- keep the regulator on
- */
- on = !on;
+ if (!IS_ERR(domain->regulator)) {
+ ret = regulator_disable(domain->regulator);
+ if (ret)
+ dev_err(domain->dev, "failed to disable regulator\n");
}
-disable_clocks:
- /* Disable reset clocks for all devices in the domain */
+ regmap_update_bits(domain->regmap, GPC_PGC_CPU_MAPPING,
+ domain->bits.map, 0);
+
+ /* Disable all clocks */
for (i = 0; i < domain->num_clks; i++)
clk_disable_unprepare(domain->clk[i]);
- if (has_regulator && !on) {
- int err;
+ mutex_unlock(&gpc_pd_mutex);
+ return 0;
- err = regulator_disable(domain->regulator);
- if (err)
- dev_err(domain->dev,
- "failed to disable regulator: %d\n", err);
- /* Preserve earlier error code */
- ret = ret ?: err;
- }
unmap:
- regmap_update_bits(domain->regmap, GPC_PGC_CPU_MAPPING,
- domain->bits.map, 0);
- return ret;
-}
+ if (domain->bits.map)
+ regmap_update_bits(domain->regmap, GPC_PGC_CPU_MAPPING,
+ domain->bits.map, 0);
-static int imx_gpc_pu_pgc_sw_pup_req(struct generic_pm_domain *genpd)
-{
- return imx_gpc_pu_pgc_sw_pxx_req(genpd, true);
-}
+disable_clocks:
+ for (i--; i >= 0; i--)
+ clk_disable_unprepare(domain->clk[i]);
+
+ mutex_unlock(&gpc_pd_mutex);
+ return ret;
-static int imx_gpc_pu_pgc_sw_pdn_req(struct generic_pm_domain *genpd)
-{
- return imx_gpc_pu_pgc_sw_pxx_req(genpd, false);
}
static const struct imx_pgc_domain imx7_pgc_domains[] = {
@@ -370,7 +458,8 @@ static const struct imx_pgc_domain imx8m_pgc_domains[] = {
.bits = {
.pxx = IMX8M_GPU_SW_Pxx_REQ,
.map = IMX8M_GPU_A53_DOMAIN,
- .hsk = IMX8M_GPU_HSK_PWRDNREQN,
+ .hsk_req = IMX8M_GPU_HSK_PWRDNREQN,
+ .hsk_ack = IMX8M_GPU_HSK_PWRDNACKN
},
.pgc = IMX8M_PGC_GPU,
},
@@ -382,7 +471,8 @@ static const struct imx_pgc_domain imx8m_pgc_domains[] = {
.bits = {
.pxx = IMX8M_VPU_SW_Pxx_REQ,
.map = IMX8M_VPU_A53_DOMAIN,
- .hsk = IMX8M_VPU_HSK_PWRDNREQN,
+ .hsk_req = IMX8M_VPU_HSK_PWRDNREQN,
+ .hsk_ack = IMX8M_VPU_HSK_PWRDNACKN
},
.pgc = IMX8M_PGC_VPU,
},
@@ -394,7 +484,8 @@ static const struct imx_pgc_domain imx8m_pgc_domains[] = {
.bits = {
.pxx = IMX8M_DISP_SW_Pxx_REQ,
.map = IMX8M_DISP_A53_DOMAIN,
- .hsk = IMX8M_DISP_HSK_PWRDNREQN,
+ .hsk_req = IMX8M_DISP_HSK_PWRDNREQN,
+ .hsk_ack = IMX8M_DISP_HSK_PWRDNACKN
},
.pgc = IMX8M_PGC_DISP,
},
--
2.25.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH v1 3/7] soc: imx: gpcv2: allow domains without power sequence control
2021-04-07 21:21 ` Adrien Grassein
@ 2021-04-07 21:21 ` Adrien Grassein
-1 siblings, 0 replies; 26+ messages in thread
From: Adrien Grassein @ 2021-04-07 21:21 UTC (permalink / raw)
Cc: robh+dt, shawnguo, s.hauer, kernel, festevam, linux-imx, l.stach,
Anson.Huang, krzk, peng.fan, aisheng.dong, qiangqing.zhang,
alice.guo, aford173, agx, andrew.smirnov, devicetree,
linux-arm-kernel, linux-kernel, Adrien Grassein
On new SOCs, some domains does not have power sequence control
registers.
Signed-off-by: Adrien Grassein <adrien.grassein@gmail.com>
---
drivers/soc/imx/gpcv2.c | 134 +++++++++++++++++++++-------------------
1 file changed, 72 insertions(+), 62 deletions(-)
diff --git a/drivers/soc/imx/gpcv2.c b/drivers/soc/imx/gpcv2.c
index 7afb81489f21..d97a53502753 100644
--- a/drivers/soc/imx/gpcv2.c
+++ b/drivers/soc/imx/gpcv2.c
@@ -162,40 +162,44 @@ static int imx_gpc_pu_pgc_sw_pup_req(struct generic_pm_domain *genpd)
}
/* Map the domain to the A53 core */
- ret = regmap_update_bits(domain->regmap, GPC_PGC_CPU_MAPPING,
- domain->bits.map, domain->bits.map);
- if (ret) {
- dev_err(domain->dev, "failed to map GPC PGC domain\n");
- goto disable_clocks;
+ if (domain->bits.map) {
+ ret = regmap_update_bits(domain->regmap, GPC_PGC_CPU_MAPPING,
+ domain->bits.map, domain->bits.map);
+ if (ret) {
+ dev_err(domain->dev, "failed to map GPC PGC domain\n");
+ goto disable_clocks;
+ }
}
/* Request Power Up of the domain */
- ret = regmap_update_bits(domain->regmap, GPC_PU_PGC_SW_PUP_REQ,
- domain->bits.pxx, domain->bits.pxx);
- if (ret) {
- dev_err(domain->dev, "failed to command PGC\n");
- goto unmap;
- }
+ if (domain->bits.pxx) {
+ ret = regmap_update_bits(domain->regmap, GPC_PU_PGC_SW_PUP_REQ,
+ domain->bits.pxx, domain->bits.pxx);
+ if (ret) {
+ dev_err(domain->dev, "failed to command PGC\n");
+ goto unmap;
+ }
- /*
- * As per "5.5.9.4 Example Code 4" in IMX7DRM.pdf wait
- * for PUP_REQ/PDN_REQ bit to be cleared
- */
- ret = regmap_read_poll_timeout(domain->regmap, GPC_PU_PGC_SW_PUP_REQ,
- value,
- !(value & domain->bits.pxx),
- 0, USEC_PER_MSEC);
- if (ret) {
- dev_err(domain->dev, "failed to command PGC\n");
- goto unmap;
- }
+ /*
+ * As per "5.5.9.4 Example Code 4" in IMX7DRM.pdf wait
+ * for PUP_REQ/PDN_REQ bit to be cleared
+ */
+ ret = regmap_read_poll_timeout(domain->regmap, GPC_PU_PGC_SW_PUP_REQ,
+ value,
+ !(value & domain->bits.pxx),
+ 0, USEC_PER_MSEC);
+ if (ret) {
+ dev_err(domain->dev, "failed to command PGC\n");
+ goto unmap;
+ }
- /* Disable power control */
- ret = regmap_update_bits(domain->regmap, GPC_PGC_CTRL(domain->pgc),
- GPC_PGC_CTRL_PCR, 0);
- if (ret) {
- dev_err(domain->dev, "Failed to disable power control !\n");
- goto unmap;
+ /* Disable power control */
+ ret = regmap_update_bits(domain->regmap, GPC_PGC_CTRL(domain->pgc),
+ GPC_PGC_CTRL_PCR, 0);
+ if (ret) {
+ dev_err(domain->dev, "Failed to disable power control !\n");
+ goto unmap;
+ }
}
/* request the ADB400 to power up */
@@ -212,8 +216,9 @@ static int imx_gpc_pu_pgc_sw_pup_req(struct generic_pm_domain *genpd)
genpd->name);
}
- regmap_update_bits(domain->regmap, GPC_PGC_CPU_MAPPING,
- domain->bits.map, 0);
+ if (domain->bits.map)
+ regmap_update_bits(domain->regmap, GPC_PGC_CPU_MAPPING,
+ domain->bits.map, 0);
/* Disable all clocks */
for (i = 0; i < domain->num_clks; i++)
@@ -256,11 +261,13 @@ static int imx_gpc_pu_pgc_sw_pdn_req(struct generic_pm_domain *genpd)
}
/* Map the domain to the A53 core */
- ret = regmap_update_bits(domain->regmap, GPC_PGC_CPU_MAPPING,
- domain->bits.map, domain->bits.map);
- if (ret) {
- dev_err(domain->dev, "failed to map GPC PGC domain\n");
- goto disable_clocks;
+ if (domain->bits.map) {
+ ret = regmap_update_bits(domain->regmap, GPC_PGC_CPU_MAPPING,
+ domain->bits.map, domain->bits.map);
+ if (ret) {
+ dev_err(domain->dev, "failed to map GPC PGC domain\n");
+ goto disable_clocks;
+ }
}
/* request the ADB400 to power down */
@@ -278,32 +285,34 @@ static int imx_gpc_pu_pgc_sw_pdn_req(struct generic_pm_domain *genpd)
}
- /* Enable power control */
- ret = regmap_update_bits(domain->regmap, GPC_PGC_CTRL(domain->pgc),
- GPC_PGC_CTRL_PCR, GPC_PGC_CTRL_PCR);
- if (ret) {
- dev_err(domain->dev, "Failed to enable power control !\n");
- goto unmap;
- }
+ if (domain->bits.pxx) {
+ /* Enable power control */
+ ret = regmap_update_bits(domain->regmap, GPC_PGC_CTRL(domain->pgc),
+ GPC_PGC_CTRL_PCR, GPC_PGC_CTRL_PCR);
+ if (ret) {
+ dev_err(domain->dev, "Failed to enable power control !\n");
+ goto unmap;
+ }
- /* Request Power Down of the domain */
- ret = regmap_update_bits(domain->regmap, GPC_PU_PGC_SW_PDN_REQ,
- domain->bits.pxx, domain->bits.pxx);
- if (ret) {
- dev_err(domain->dev, "failed to command PGC\n");
- goto unmap;
- }
+ /* Request Power Down of the domain */
+ ret = regmap_update_bits(domain->regmap, GPC_PU_PGC_SW_PDN_REQ,
+ domain->bits.pxx, domain->bits.pxx);
+ if (ret) {
+ dev_err(domain->dev, "failed to command PGC\n");
+ goto unmap;
+ }
- /*
- * As per "5.5.9.4 Example Code 4" in IMX7DRM.pdf wait
- * for PUP_REQ/PDN_REQ bit to be cleared
- */
- ret = regmap_read_poll_timeout(domain->regmap, GPC_PU_PGC_SW_PDN_REQ,
- value,
- !(value & domain->bits.pxx),
- 0, USEC_PER_MSEC);
- if (ret)
- dev_err(domain->dev, "failed to command PGC\n");
+ /*
+ * As per "5.5.9.4 Example Code 4" in IMX7DRM.pdf wait
+ * for PUP_REQ/PDN_REQ bit to be cleared
+ */
+ ret = regmap_read_poll_timeout(domain->regmap, GPC_PU_PGC_SW_PDN_REQ,
+ value,
+ !(value & domain->bits.pxx),
+ 0, USEC_PER_MSEC);
+ if (ret)
+ dev_err(domain->dev, "failed to command PGC\n");
+ }
if (!IS_ERR(domain->regulator)) {
ret = regulator_disable(domain->regulator);
@@ -311,8 +320,9 @@ static int imx_gpc_pu_pgc_sw_pdn_req(struct generic_pm_domain *genpd)
dev_err(domain->dev, "failed to disable regulator\n");
}
- regmap_update_bits(domain->regmap, GPC_PGC_CPU_MAPPING,
- domain->bits.map, 0);
+ if (domain->bits.map)
+ regmap_update_bits(domain->regmap, GPC_PGC_CPU_MAPPING,
+ domain->bits.map, 0);
/* Disable all clocks */
for (i = 0; i < domain->num_clks; i++)
--
2.25.1
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH v1 3/7] soc: imx: gpcv2: allow domains without power sequence control
@ 2021-04-07 21:21 ` Adrien Grassein
0 siblings, 0 replies; 26+ messages in thread
From: Adrien Grassein @ 2021-04-07 21:21 UTC (permalink / raw)
Cc: robh+dt, shawnguo, s.hauer, kernel, festevam, linux-imx, l.stach,
Anson.Huang, krzk, peng.fan, aisheng.dong, qiangqing.zhang,
alice.guo, aford173, agx, andrew.smirnov, devicetree,
linux-arm-kernel, linux-kernel, Adrien Grassein
On new SOCs, some domains does not have power sequence control
registers.
Signed-off-by: Adrien Grassein <adrien.grassein@gmail.com>
---
drivers/soc/imx/gpcv2.c | 134 +++++++++++++++++++++-------------------
1 file changed, 72 insertions(+), 62 deletions(-)
diff --git a/drivers/soc/imx/gpcv2.c b/drivers/soc/imx/gpcv2.c
index 7afb81489f21..d97a53502753 100644
--- a/drivers/soc/imx/gpcv2.c
+++ b/drivers/soc/imx/gpcv2.c
@@ -162,40 +162,44 @@ static int imx_gpc_pu_pgc_sw_pup_req(struct generic_pm_domain *genpd)
}
/* Map the domain to the A53 core */
- ret = regmap_update_bits(domain->regmap, GPC_PGC_CPU_MAPPING,
- domain->bits.map, domain->bits.map);
- if (ret) {
- dev_err(domain->dev, "failed to map GPC PGC domain\n");
- goto disable_clocks;
+ if (domain->bits.map) {
+ ret = regmap_update_bits(domain->regmap, GPC_PGC_CPU_MAPPING,
+ domain->bits.map, domain->bits.map);
+ if (ret) {
+ dev_err(domain->dev, "failed to map GPC PGC domain\n");
+ goto disable_clocks;
+ }
}
/* Request Power Up of the domain */
- ret = regmap_update_bits(domain->regmap, GPC_PU_PGC_SW_PUP_REQ,
- domain->bits.pxx, domain->bits.pxx);
- if (ret) {
- dev_err(domain->dev, "failed to command PGC\n");
- goto unmap;
- }
+ if (domain->bits.pxx) {
+ ret = regmap_update_bits(domain->regmap, GPC_PU_PGC_SW_PUP_REQ,
+ domain->bits.pxx, domain->bits.pxx);
+ if (ret) {
+ dev_err(domain->dev, "failed to command PGC\n");
+ goto unmap;
+ }
- /*
- * As per "5.5.9.4 Example Code 4" in IMX7DRM.pdf wait
- * for PUP_REQ/PDN_REQ bit to be cleared
- */
- ret = regmap_read_poll_timeout(domain->regmap, GPC_PU_PGC_SW_PUP_REQ,
- value,
- !(value & domain->bits.pxx),
- 0, USEC_PER_MSEC);
- if (ret) {
- dev_err(domain->dev, "failed to command PGC\n");
- goto unmap;
- }
+ /*
+ * As per "5.5.9.4 Example Code 4" in IMX7DRM.pdf wait
+ * for PUP_REQ/PDN_REQ bit to be cleared
+ */
+ ret = regmap_read_poll_timeout(domain->regmap, GPC_PU_PGC_SW_PUP_REQ,
+ value,
+ !(value & domain->bits.pxx),
+ 0, USEC_PER_MSEC);
+ if (ret) {
+ dev_err(domain->dev, "failed to command PGC\n");
+ goto unmap;
+ }
- /* Disable power control */
- ret = regmap_update_bits(domain->regmap, GPC_PGC_CTRL(domain->pgc),
- GPC_PGC_CTRL_PCR, 0);
- if (ret) {
- dev_err(domain->dev, "Failed to disable power control !\n");
- goto unmap;
+ /* Disable power control */
+ ret = regmap_update_bits(domain->regmap, GPC_PGC_CTRL(domain->pgc),
+ GPC_PGC_CTRL_PCR, 0);
+ if (ret) {
+ dev_err(domain->dev, "Failed to disable power control !\n");
+ goto unmap;
+ }
}
/* request the ADB400 to power up */
@@ -212,8 +216,9 @@ static int imx_gpc_pu_pgc_sw_pup_req(struct generic_pm_domain *genpd)
genpd->name);
}
- regmap_update_bits(domain->regmap, GPC_PGC_CPU_MAPPING,
- domain->bits.map, 0);
+ if (domain->bits.map)
+ regmap_update_bits(domain->regmap, GPC_PGC_CPU_MAPPING,
+ domain->bits.map, 0);
/* Disable all clocks */
for (i = 0; i < domain->num_clks; i++)
@@ -256,11 +261,13 @@ static int imx_gpc_pu_pgc_sw_pdn_req(struct generic_pm_domain *genpd)
}
/* Map the domain to the A53 core */
- ret = regmap_update_bits(domain->regmap, GPC_PGC_CPU_MAPPING,
- domain->bits.map, domain->bits.map);
- if (ret) {
- dev_err(domain->dev, "failed to map GPC PGC domain\n");
- goto disable_clocks;
+ if (domain->bits.map) {
+ ret = regmap_update_bits(domain->regmap, GPC_PGC_CPU_MAPPING,
+ domain->bits.map, domain->bits.map);
+ if (ret) {
+ dev_err(domain->dev, "failed to map GPC PGC domain\n");
+ goto disable_clocks;
+ }
}
/* request the ADB400 to power down */
@@ -278,32 +285,34 @@ static int imx_gpc_pu_pgc_sw_pdn_req(struct generic_pm_domain *genpd)
}
- /* Enable power control */
- ret = regmap_update_bits(domain->regmap, GPC_PGC_CTRL(domain->pgc),
- GPC_PGC_CTRL_PCR, GPC_PGC_CTRL_PCR);
- if (ret) {
- dev_err(domain->dev, "Failed to enable power control !\n");
- goto unmap;
- }
+ if (domain->bits.pxx) {
+ /* Enable power control */
+ ret = regmap_update_bits(domain->regmap, GPC_PGC_CTRL(domain->pgc),
+ GPC_PGC_CTRL_PCR, GPC_PGC_CTRL_PCR);
+ if (ret) {
+ dev_err(domain->dev, "Failed to enable power control !\n");
+ goto unmap;
+ }
- /* Request Power Down of the domain */
- ret = regmap_update_bits(domain->regmap, GPC_PU_PGC_SW_PDN_REQ,
- domain->bits.pxx, domain->bits.pxx);
- if (ret) {
- dev_err(domain->dev, "failed to command PGC\n");
- goto unmap;
- }
+ /* Request Power Down of the domain */
+ ret = regmap_update_bits(domain->regmap, GPC_PU_PGC_SW_PDN_REQ,
+ domain->bits.pxx, domain->bits.pxx);
+ if (ret) {
+ dev_err(domain->dev, "failed to command PGC\n");
+ goto unmap;
+ }
- /*
- * As per "5.5.9.4 Example Code 4" in IMX7DRM.pdf wait
- * for PUP_REQ/PDN_REQ bit to be cleared
- */
- ret = regmap_read_poll_timeout(domain->regmap, GPC_PU_PGC_SW_PDN_REQ,
- value,
- !(value & domain->bits.pxx),
- 0, USEC_PER_MSEC);
- if (ret)
- dev_err(domain->dev, "failed to command PGC\n");
+ /*
+ * As per "5.5.9.4 Example Code 4" in IMX7DRM.pdf wait
+ * for PUP_REQ/PDN_REQ bit to be cleared
+ */
+ ret = regmap_read_poll_timeout(domain->regmap, GPC_PU_PGC_SW_PDN_REQ,
+ value,
+ !(value & domain->bits.pxx),
+ 0, USEC_PER_MSEC);
+ if (ret)
+ dev_err(domain->dev, "failed to command PGC\n");
+ }
if (!IS_ERR(domain->regulator)) {
ret = regulator_disable(domain->regulator);
@@ -311,8 +320,9 @@ static int imx_gpc_pu_pgc_sw_pdn_req(struct generic_pm_domain *genpd)
dev_err(domain->dev, "failed to disable regulator\n");
}
- regmap_update_bits(domain->regmap, GPC_PGC_CPU_MAPPING,
- domain->bits.map, 0);
+ if (domain->bits.map)
+ regmap_update_bits(domain->regmap, GPC_PGC_CPU_MAPPING,
+ domain->bits.map, 0);
/* Disable all clocks */
for (i = 0; i < domain->num_clks; i++)
--
2.25.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH v1 4/7] dt-bindings: power: fsl,imx-gpcv2: add definitions for i.MX8MM
2021-04-07 21:21 ` Adrien Grassein
@ 2021-04-07 21:21 ` Adrien Grassein
-1 siblings, 0 replies; 26+ messages in thread
From: Adrien Grassein @ 2021-04-07 21:21 UTC (permalink / raw)
Cc: robh+dt, shawnguo, s.hauer, kernel, festevam, linux-imx, l.stach,
Anson.Huang, krzk, peng.fan, aisheng.dong, qiangqing.zhang,
alice.guo, aford173, agx, andrew.smirnov, devicetree,
linux-arm-kernel, linux-kernel, Adrien Grassein
Update documentation for i.MX8MM.
Signed-off-by: Adrien Grassein <adrien.grassein@gmail.com>
---
.../bindings/power/fsl,imx-gpcv2.yaml | 7 +++++--
include/dt-bindings/power/imx8mm-power.h | 21 +++++++++++++++++++
2 files changed, 26 insertions(+), 2 deletions(-)
create mode 100644 include/dt-bindings/power/imx8mm-power.h
diff --git a/Documentation/devicetree/bindings/power/fsl,imx-gpcv2.yaml b/Documentation/devicetree/bindings/power/fsl,imx-gpcv2.yaml
index a96e6dbf1858..04928a173698 100644
--- a/Documentation/devicetree/bindings/power/fsl,imx-gpcv2.yaml
+++ b/Documentation/devicetree/bindings/power/fsl,imx-gpcv2.yaml
@@ -26,6 +26,7 @@ properties:
enum:
- fsl,imx7d-gpc
- fsl,imx8mq-gpc
+ - fsl,imx8mm-pgc
reg:
maxItems: 1
@@ -52,8 +53,10 @@ properties:
reg:
description: |
Power domain index. Valid values are defined in
- include/dt-bindings/power/imx7-power.h for fsl,imx7d-gpc and
- include/dt-bindings/power/imx8m-power.h for fsl,imx8mq-gpc
+ include/dt-bindings/power/imx7-power.h for fsl,imx7d-gpc,
+ include/dt-bindings/power/imx8m-power.h for fsl,imx8mq-gpc and
+ include/dt-bindings/power/imx8mm-power.h for fsl,imx8mm-gpc
+
maxItems: 1
clocks:
diff --git a/include/dt-bindings/power/imx8mm-power.h b/include/dt-bindings/power/imx8mm-power.h
new file mode 100644
index 000000000000..bec25fd32394
--- /dev/null
+++ b/include/dt-bindings/power/imx8mm-power.h
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
+/*
+ * Copyright (C) 2021 Adrien Grassein <adrien.grassein@gmail.com>
+ */
+
+#ifndef __DT_BINDINGS_IMX8MM_POWER_H__
+#define __DT_BINDINGS_IMX8MM_POWER_H__
+
+#define IMX8MM_POWER_DOMAIN_HSIOMIX 0
+#define IMX8MM_POWER_DOMAIN_PCIE1 1
+#define IMX8MM_POWER_DOMAIN_USB_OTG1 2
+#define IMX8MM_POWER_DOMAIN_USB_OTG2 3
+#define IMX8MM_POWER_DOMAIN_GPU 4
+#define IMX8MM_POWER_DOMAIN_VPU 5
+#define IMX8MM_POWER_DOMAIN_VPU_G1 6
+#define IMX8MM_POWER_DOMAIN_VPU_G2 7
+#define IMX8MM_POWER_DOMAIN_VPU_H1 8
+#define IMX8MM_POWER_DOMAIN_DISPLAY 9
+#define IMX8MM_POWER_DOMAIN_MIPI 10
+
+#endif
--
2.25.1
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH v1 4/7] dt-bindings: power: fsl, imx-gpcv2: add definitions for i.MX8MM
@ 2021-04-07 21:21 ` Adrien Grassein
0 siblings, 0 replies; 26+ messages in thread
From: Adrien Grassein @ 2021-04-07 21:21 UTC (permalink / raw)
Cc: robh+dt, shawnguo, s.hauer, kernel, festevam, linux-imx, l.stach,
Anson.Huang, krzk, peng.fan, aisheng.dong, qiangqing.zhang,
alice.guo, aford173, agx, andrew.smirnov, devicetree,
linux-arm-kernel, linux-kernel, Adrien Grassein
Update documentation for i.MX8MM.
Signed-off-by: Adrien Grassein <adrien.grassein@gmail.com>
---
.../bindings/power/fsl,imx-gpcv2.yaml | 7 +++++--
include/dt-bindings/power/imx8mm-power.h | 21 +++++++++++++++++++
2 files changed, 26 insertions(+), 2 deletions(-)
create mode 100644 include/dt-bindings/power/imx8mm-power.h
diff --git a/Documentation/devicetree/bindings/power/fsl,imx-gpcv2.yaml b/Documentation/devicetree/bindings/power/fsl,imx-gpcv2.yaml
index a96e6dbf1858..04928a173698 100644
--- a/Documentation/devicetree/bindings/power/fsl,imx-gpcv2.yaml
+++ b/Documentation/devicetree/bindings/power/fsl,imx-gpcv2.yaml
@@ -26,6 +26,7 @@ properties:
enum:
- fsl,imx7d-gpc
- fsl,imx8mq-gpc
+ - fsl,imx8mm-pgc
reg:
maxItems: 1
@@ -52,8 +53,10 @@ properties:
reg:
description: |
Power domain index. Valid values are defined in
- include/dt-bindings/power/imx7-power.h for fsl,imx7d-gpc and
- include/dt-bindings/power/imx8m-power.h for fsl,imx8mq-gpc
+ include/dt-bindings/power/imx7-power.h for fsl,imx7d-gpc,
+ include/dt-bindings/power/imx8m-power.h for fsl,imx8mq-gpc and
+ include/dt-bindings/power/imx8mm-power.h for fsl,imx8mm-gpc
+
maxItems: 1
clocks:
diff --git a/include/dt-bindings/power/imx8mm-power.h b/include/dt-bindings/power/imx8mm-power.h
new file mode 100644
index 000000000000..bec25fd32394
--- /dev/null
+++ b/include/dt-bindings/power/imx8mm-power.h
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
+/*
+ * Copyright (C) 2021 Adrien Grassein <adrien.grassein@gmail.com>
+ */
+
+#ifndef __DT_BINDINGS_IMX8MM_POWER_H__
+#define __DT_BINDINGS_IMX8MM_POWER_H__
+
+#define IMX8MM_POWER_DOMAIN_HSIOMIX 0
+#define IMX8MM_POWER_DOMAIN_PCIE1 1
+#define IMX8MM_POWER_DOMAIN_USB_OTG1 2
+#define IMX8MM_POWER_DOMAIN_USB_OTG2 3
+#define IMX8MM_POWER_DOMAIN_GPU 4
+#define IMX8MM_POWER_DOMAIN_VPU 5
+#define IMX8MM_POWER_DOMAIN_VPU_G1 6
+#define IMX8MM_POWER_DOMAIN_VPU_G2 7
+#define IMX8MM_POWER_DOMAIN_VPU_H1 8
+#define IMX8MM_POWER_DOMAIN_DISPLAY 9
+#define IMX8MM_POWER_DOMAIN_MIPI 10
+
+#endif
--
2.25.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH v1 5/7] soc: imx: gpcv2: add HSIOMIX and USB domains for i.MX8MM
2021-04-07 21:21 ` Adrien Grassein
@ 2021-04-07 21:21 ` Adrien Grassein
-1 siblings, 0 replies; 26+ messages in thread
From: Adrien Grassein @ 2021-04-07 21:21 UTC (permalink / raw)
Cc: robh+dt, shawnguo, s.hauer, kernel, festevam, linux-imx, l.stach,
Anson.Huang, krzk, peng.fan, aisheng.dong, qiangqing.zhang,
alice.guo, aford173, agx, andrew.smirnov, devicetree,
linux-arm-kernel, linux-kernel, Adrien Grassein
Add description for 3 domains of the i.MX8MM:
- HSIO
- USB OTG 1
- USB OTG 2
Signed-off-by: Adrien Grassein <adrien.grassein@gmail.com>
---
drivers/soc/imx/gpcv2.c | 69 +++++++++++++++++++++++++++++++++++++++++
1 file changed, 69 insertions(+)
diff --git a/drivers/soc/imx/gpcv2.c b/drivers/soc/imx/gpcv2.c
index d97a53502753..571d0381dd87 100644
--- a/drivers/soc/imx/gpcv2.c
+++ b/drivers/soc/imx/gpcv2.c
@@ -17,6 +17,8 @@
#include <linux/sizes.h>
#include <dt-bindings/power/imx7-power.h>
#include <dt-bindings/power/imx8mq-power.h>
+#include <dt-bindings/power/imx8mm-power.h>
+
#define GPC_LPCR_A_CORE_BSC 0x000
@@ -42,6 +44,9 @@
#define IMX8M_PCIE1_A53_DOMAIN BIT(3)
#define IMX8M_MIPI_A53_DOMAIN BIT(2)
+#define IMX8MM_OTG2_A53_DOMAIN BIT(5)
+#define IMX8MM_OTG1_A53_DOMAIN BIT(4)
+
#define GPC_PU_PGC_SW_PUP_REQ 0x0f8
#define GPC_PU_PGC_SW_PDN_REQ 0x104
@@ -65,6 +70,9 @@
#define IMX8M_PCIE1_SW_Pxx_REQ BIT(1)
#define IMX8M_MIPI_SW_Pxx_REQ BIT(0)
+#define IMX8MM_OTG1_SW_Pxx_REQ BIT(2)
+#define IMX8MM_OTG2_SW_Pxx_REQ BIT(3)
+
#define GPC_M4_PU_PDN_FLG 0x1bc
#define GPC_PU_PWRHSK 0x1fc
@@ -76,6 +84,9 @@
#define IMX8M_DISP_HSK_PWRDNREQN BIT(4)
#define IMX8M_DISP_HSK_PWRDNACKN BIT(24)
+#define IMX8MM_HSIO_HSK_PWRDNREQN (BIT(5) | BIT(6))
+#define IMX8MM_HSIO_HSK_PWRDNACKN (BIT(23) | BIT(24))
+
/*
* The PGC offset values in Reference Manual
* (Rev. 1, 01/2018 and the older ones) GPC chapter's
@@ -98,6 +109,9 @@
#define IMX8M_PGC_MIPI_CSI2 28
#define IMX8M_PGC_PCIE2 29
+#define IMX8MM_PGC_OTG1 18
+#define IMX8MM_PGC_OTG2 19
+
#define GPC_PGC_CTRL(n) (0x800 + (n) * 0x40)
#define GPC_PGC_SR(n) (GPC_PGC_CTRL(n) + 0xc)
@@ -572,6 +586,60 @@ static const struct imx_pgc_domain_data imx8m_pgc_domain_data = {
.reg_access_table = &imx8m_access_table,
};
+static const struct imx_pgc_domain imx8mm_pgc_domains[] = {
+ [IMX8MM_POWER_DOMAIN_HSIOMIX] = {
+ .genpd = {
+ .name = "hsiomix",
+ },
+ .bits = {
+ .hsk_req = IMX8MM_HSIO_HSK_PWRDNREQN,
+ .hsk_ack = IMX8MM_HSIO_HSK_PWRDNACKN,
+ },
+ },
+
+ [IMX8MM_POWER_DOMAIN_USB_OTG1] = {
+ .genpd = {
+ .name = "usb-otg1",
+ },
+ .bits = {
+ .pxx = IMX8MM_OTG1_SW_Pxx_REQ,
+ .map = IMX8MM_OTG1_A53_DOMAIN,
+ },
+ .pgc = IMX8MM_PGC_OTG1,
+ },
+
+ [IMX8MM_POWER_DOMAIN_USB_OTG2] = {
+ .genpd = {
+ .name = "usb-otg2",
+ },
+ .bits = {
+ .pxx = IMX8MM_OTG2_SW_Pxx_REQ,
+ .map = IMX8MM_OTG2_A53_DOMAIN,
+ },
+ .pgc = IMX8MM_PGC_OTG2,
+ },
+};
+
+static const struct regmap_range imx8mm_yes_ranges[] = {
+ regmap_reg_range(GPC_LPCR_A_CORE_BSC,
+ GPC_PU_PWRHSK),
+ regmap_reg_range(GPC_PGC_CTRL(IMX8MM_PGC_OTG1),
+ GPC_PGC_SR(IMX8MM_PGC_OTG1)),
+ regmap_reg_range(GPC_PGC_CTRL(IMX8MM_PGC_OTG2),
+ GPC_PGC_SR(IMX8MM_PGC_OTG2)),
+};
+
+static const struct regmap_access_table imx8mm_access_table = {
+ .yes_ranges = imx8mm_yes_ranges,
+ .n_yes_ranges = ARRAY_SIZE(imx8mm_yes_ranges),
+};
+
+static const struct imx_pgc_domain_data imx8mm_pgc_domain_data = {
+ .domains = imx8mm_pgc_domains,
+ .domains_num = ARRAY_SIZE(imx8mm_pgc_domains),
+ .reg_access_table = &imx8mm_access_table,
+};
+
static int imx_pgc_get_clocks(struct imx_pgc_domain *domain)
{
int i, ret;
@@ -766,6 +834,7 @@ static int imx_gpcv2_probe(struct platform_device *pdev)
static const struct of_device_id imx_gpcv2_dt_ids[] = {
{ .compatible = "fsl,imx7d-gpc", .data = &imx7_pgc_domain_data, },
{ .compatible = "fsl,imx8mq-gpc", .data = &imx8m_pgc_domain_data, },
+ { .compatible = "fsl,imx8mm-gpc", .data = &imx8mm_pgc_domain_data, },
{ }
};
--
2.25.1
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH v1 5/7] soc: imx: gpcv2: add HSIOMIX and USB domains for i.MX8MM
@ 2021-04-07 21:21 ` Adrien Grassein
0 siblings, 0 replies; 26+ messages in thread
From: Adrien Grassein @ 2021-04-07 21:21 UTC (permalink / raw)
Cc: robh+dt, shawnguo, s.hauer, kernel, festevam, linux-imx, l.stach,
Anson.Huang, krzk, peng.fan, aisheng.dong, qiangqing.zhang,
alice.guo, aford173, agx, andrew.smirnov, devicetree,
linux-arm-kernel, linux-kernel, Adrien Grassein
Add description for 3 domains of the i.MX8MM:
- HSIO
- USB OTG 1
- USB OTG 2
Signed-off-by: Adrien Grassein <adrien.grassein@gmail.com>
---
drivers/soc/imx/gpcv2.c | 69 +++++++++++++++++++++++++++++++++++++++++
1 file changed, 69 insertions(+)
diff --git a/drivers/soc/imx/gpcv2.c b/drivers/soc/imx/gpcv2.c
index d97a53502753..571d0381dd87 100644
--- a/drivers/soc/imx/gpcv2.c
+++ b/drivers/soc/imx/gpcv2.c
@@ -17,6 +17,8 @@
#include <linux/sizes.h>
#include <dt-bindings/power/imx7-power.h>
#include <dt-bindings/power/imx8mq-power.h>
+#include <dt-bindings/power/imx8mm-power.h>
+
#define GPC_LPCR_A_CORE_BSC 0x000
@@ -42,6 +44,9 @@
#define IMX8M_PCIE1_A53_DOMAIN BIT(3)
#define IMX8M_MIPI_A53_DOMAIN BIT(2)
+#define IMX8MM_OTG2_A53_DOMAIN BIT(5)
+#define IMX8MM_OTG1_A53_DOMAIN BIT(4)
+
#define GPC_PU_PGC_SW_PUP_REQ 0x0f8
#define GPC_PU_PGC_SW_PDN_REQ 0x104
@@ -65,6 +70,9 @@
#define IMX8M_PCIE1_SW_Pxx_REQ BIT(1)
#define IMX8M_MIPI_SW_Pxx_REQ BIT(0)
+#define IMX8MM_OTG1_SW_Pxx_REQ BIT(2)
+#define IMX8MM_OTG2_SW_Pxx_REQ BIT(3)
+
#define GPC_M4_PU_PDN_FLG 0x1bc
#define GPC_PU_PWRHSK 0x1fc
@@ -76,6 +84,9 @@
#define IMX8M_DISP_HSK_PWRDNREQN BIT(4)
#define IMX8M_DISP_HSK_PWRDNACKN BIT(24)
+#define IMX8MM_HSIO_HSK_PWRDNREQN (BIT(5) | BIT(6))
+#define IMX8MM_HSIO_HSK_PWRDNACKN (BIT(23) | BIT(24))
+
/*
* The PGC offset values in Reference Manual
* (Rev. 1, 01/2018 and the older ones) GPC chapter's
@@ -98,6 +109,9 @@
#define IMX8M_PGC_MIPI_CSI2 28
#define IMX8M_PGC_PCIE2 29
+#define IMX8MM_PGC_OTG1 18
+#define IMX8MM_PGC_OTG2 19
+
#define GPC_PGC_CTRL(n) (0x800 + (n) * 0x40)
#define GPC_PGC_SR(n) (GPC_PGC_CTRL(n) + 0xc)
@@ -572,6 +586,60 @@ static const struct imx_pgc_domain_data imx8m_pgc_domain_data = {
.reg_access_table = &imx8m_access_table,
};
+static const struct imx_pgc_domain imx8mm_pgc_domains[] = {
+ [IMX8MM_POWER_DOMAIN_HSIOMIX] = {
+ .genpd = {
+ .name = "hsiomix",
+ },
+ .bits = {
+ .hsk_req = IMX8MM_HSIO_HSK_PWRDNREQN,
+ .hsk_ack = IMX8MM_HSIO_HSK_PWRDNACKN,
+ },
+ },
+
+ [IMX8MM_POWER_DOMAIN_USB_OTG1] = {
+ .genpd = {
+ .name = "usb-otg1",
+ },
+ .bits = {
+ .pxx = IMX8MM_OTG1_SW_Pxx_REQ,
+ .map = IMX8MM_OTG1_A53_DOMAIN,
+ },
+ .pgc = IMX8MM_PGC_OTG1,
+ },
+
+ [IMX8MM_POWER_DOMAIN_USB_OTG2] = {
+ .genpd = {
+ .name = "usb-otg2",
+ },
+ .bits = {
+ .pxx = IMX8MM_OTG2_SW_Pxx_REQ,
+ .map = IMX8MM_OTG2_A53_DOMAIN,
+ },
+ .pgc = IMX8MM_PGC_OTG2,
+ },
+};
+
+static const struct regmap_range imx8mm_yes_ranges[] = {
+ regmap_reg_range(GPC_LPCR_A_CORE_BSC,
+ GPC_PU_PWRHSK),
+ regmap_reg_range(GPC_PGC_CTRL(IMX8MM_PGC_OTG1),
+ GPC_PGC_SR(IMX8MM_PGC_OTG1)),
+ regmap_reg_range(GPC_PGC_CTRL(IMX8MM_PGC_OTG2),
+ GPC_PGC_SR(IMX8MM_PGC_OTG2)),
+};
+
+static const struct regmap_access_table imx8mm_access_table = {
+ .yes_ranges = imx8mm_yes_ranges,
+ .n_yes_ranges = ARRAY_SIZE(imx8mm_yes_ranges),
+};
+
+static const struct imx_pgc_domain_data imx8mm_pgc_domain_data = {
+ .domains = imx8mm_pgc_domains,
+ .domains_num = ARRAY_SIZE(imx8mm_pgc_domains),
+ .reg_access_table = &imx8mm_access_table,
+};
+
static int imx_pgc_get_clocks(struct imx_pgc_domain *domain)
{
int i, ret;
@@ -766,6 +834,7 @@ static int imx_gpcv2_probe(struct platform_device *pdev)
static const struct of_device_id imx_gpcv2_dt_ids[] = {
{ .compatible = "fsl,imx7d-gpc", .data = &imx7_pgc_domain_data, },
{ .compatible = "fsl,imx8mq-gpc", .data = &imx8m_pgc_domain_data, },
+ { .compatible = "fsl,imx8mm-gpc", .data = &imx8mm_pgc_domain_data, },
{ }
};
--
2.25.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH v1 6/7] soc: imx: gpcv2: add quirks to domains
2021-04-07 21:21 ` Adrien Grassein
@ 2021-04-07 21:21 ` Adrien Grassein
-1 siblings, 0 replies; 26+ messages in thread
From: Adrien Grassein @ 2021-04-07 21:21 UTC (permalink / raw)
Cc: robh+dt, shawnguo, s.hauer, kernel, festevam, linux-imx, l.stach,
Anson.Huang, krzk, peng.fan, aisheng.dong, qiangqing.zhang,
alice.guo, aford173, agx, andrew.smirnov, devicetree,
linux-arm-kernel, linux-kernel, Adrien Grassein
Some domains need quirks during their operation.
For example, on i.MX8MM, USB domains should not be powered off.
Signed-off-by: Adrien Grassein <adrien.grassein@gmail.com>
---
drivers/soc/imx/gpcv2.c | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/drivers/soc/imx/gpcv2.c b/drivers/soc/imx/gpcv2.c
index 571d0381dd87..592b9808dcd4 100644
--- a/drivers/soc/imx/gpcv2.c
+++ b/drivers/soc/imx/gpcv2.c
@@ -119,6 +119,10 @@
#define GPC_CLK_MAX 6
+/* Quirks */
+//Refuse to poweroff the domain
+#define GPC_QUIRKS_DONT_POWEROFF BIT(0)
+
static DEFINE_MUTEX(gpc_pd_mutex);
struct imx_pgc_domain {
@@ -139,6 +143,7 @@ struct imx_pgc_domain {
const int voltage;
struct device *dev;
+ const unsigned int quirks;
};
struct imx_pgc_domain_data {
@@ -263,6 +268,9 @@ static int imx_gpc_pu_pgc_sw_pdn_req(struct generic_pm_domain *genpd)
int i, ret = 0;
u32 value;
+ if (domain->quirks & GPC_QUIRKS_DONT_POWEROFF)
+ return 0;
+
mutex_lock(&gpc_pd_mutex);
/* Enable reset clocks for all devices in the domain */
@@ -606,6 +614,7 @@ static const struct imx_pgc_domain imx8mm_pgc_domains[] = {
.map = IMX8MM_OTG1_A53_DOMAIN,
},
.pgc = IMX8MM_PGC_OTG1,
+ .quirks = GPC_QUIRKS_DONT_POWEROFF,
},
[IMX8MM_POWER_DOMAIN_USB_OTG2] = {
@@ -617,6 +626,7 @@ static const struct imx_pgc_domain imx8mm_pgc_domains[] = {
.map = IMX8MM_OTG2_A53_DOMAIN,
},
.pgc = IMX8MM_PGC_OTG2,
+ .quirks = GPC_QUIRKS_DONT_POWEROFF,
},
};
--
2.25.1
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH v1 6/7] soc: imx: gpcv2: add quirks to domains
@ 2021-04-07 21:21 ` Adrien Grassein
0 siblings, 0 replies; 26+ messages in thread
From: Adrien Grassein @ 2021-04-07 21:21 UTC (permalink / raw)
Cc: robh+dt, shawnguo, s.hauer, kernel, festevam, linux-imx, l.stach,
Anson.Huang, krzk, peng.fan, aisheng.dong, qiangqing.zhang,
alice.guo, aford173, agx, andrew.smirnov, devicetree,
linux-arm-kernel, linux-kernel, Adrien Grassein
Some domains need quirks during their operation.
For example, on i.MX8MM, USB domains should not be powered off.
Signed-off-by: Adrien Grassein <adrien.grassein@gmail.com>
---
drivers/soc/imx/gpcv2.c | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/drivers/soc/imx/gpcv2.c b/drivers/soc/imx/gpcv2.c
index 571d0381dd87..592b9808dcd4 100644
--- a/drivers/soc/imx/gpcv2.c
+++ b/drivers/soc/imx/gpcv2.c
@@ -119,6 +119,10 @@
#define GPC_CLK_MAX 6
+/* Quirks */
+//Refuse to poweroff the domain
+#define GPC_QUIRKS_DONT_POWEROFF BIT(0)
+
static DEFINE_MUTEX(gpc_pd_mutex);
struct imx_pgc_domain {
@@ -139,6 +143,7 @@ struct imx_pgc_domain {
const int voltage;
struct device *dev;
+ const unsigned int quirks;
};
struct imx_pgc_domain_data {
@@ -263,6 +268,9 @@ static int imx_gpc_pu_pgc_sw_pdn_req(struct generic_pm_domain *genpd)
int i, ret = 0;
u32 value;
+ if (domain->quirks & GPC_QUIRKS_DONT_POWEROFF)
+ return 0;
+
mutex_lock(&gpc_pd_mutex);
/* Enable reset clocks for all devices in the domain */
@@ -606,6 +614,7 @@ static const struct imx_pgc_domain imx8mm_pgc_domains[] = {
.map = IMX8MM_OTG1_A53_DOMAIN,
},
.pgc = IMX8MM_PGC_OTG1,
+ .quirks = GPC_QUIRKS_DONT_POWEROFF,
},
[IMX8MM_POWER_DOMAIN_USB_OTG2] = {
@@ -617,6 +626,7 @@ static const struct imx_pgc_domain imx8mm_pgc_domains[] = {
.map = IMX8MM_OTG2_A53_DOMAIN,
},
.pgc = IMX8MM_PGC_OTG2,
+ .quirks = GPC_QUIRKS_DONT_POWEROFF,
},
};
--
2.25.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH v1 7/7] arm64: dts: imx8mm: add power-domains
2021-04-07 21:21 ` Adrien Grassein
@ 2021-04-07 21:21 ` Adrien Grassein
-1 siblings, 0 replies; 26+ messages in thread
From: Adrien Grassein @ 2021-04-07 21:21 UTC (permalink / raw)
Cc: robh+dt, shawnguo, s.hauer, kernel, festevam, linux-imx, l.stach,
Anson.Huang, krzk, peng.fan, aisheng.dong, qiangqing.zhang,
alice.guo, aford173, agx, andrew.smirnov, devicetree,
linux-arm-kernel, linux-kernel, Adrien Grassein
Add description for HSIO and USB power-domains.
Signed-off-by: Adrien Grassein <adrien.grassein@gmail.com>
---
arch/arm64/boot/dts/freescale/imx8mm.dtsi | 35 +++++++++++++++++++++++
1 file changed, 35 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
index a27e02bee6b4..028b8930db5a 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
@@ -4,6 +4,7 @@
*/
#include <dt-bindings/clock/imx8mm-clock.h>
+#include <dt-bindings/power/imx8mm-power.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
@@ -600,6 +601,38 @@ src: reset-controller@30390000 {
interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
#reset-cells = <1>;
};
+
+ gpc: gpc@303a0000 {
+ compatible = "fsl,imx8mm-gpc";
+ reg = <0x303a0000 0x10000>;
+ interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&gic>;
+ interrupt-controller;
+ #interrupt-cells = <3>;
+
+ pgc {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pgc_hsiomix: power-domain@IMX8MM_POWER_DOMAIN_HSIOMIX {
+ #power-domain-cells = <0>;
+ reg = <IMX8MM_POWER_DOMAIN_HSIOMIX>;
+ clocks = <&clk IMX8MM_CLK_USB_BUS>;
+ };
+
+ pgc_usb_otg1: power-domain@IMX8MM_POWER_DOMAIN_USB_OTG1 {
+ #power-domain-cells = <0>;
+ reg = <IMX8MM_POWER_DOMAIN_USB_OTG1>;
+ power-domains = <&pgc_hsiomix>;
+ };
+
+ pgc_usb_otg2: power-domain@IMX8MM_POWER_DOMAIN_USB_OTG2 {
+ #power-domain-cells = <0>;
+ reg = <IMX8MM_POWER_DOMAIN_USB_OTG2>;
+ power-domains = <&pgc_hsiomix>;
+ };
+ };
+ };
};
aips2: bus@30400000 {
@@ -953,6 +986,7 @@ usbotg1: usb@32e40000 {
assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>;
fsl,usbphy = <&usbphynop1>;
fsl,usbmisc = <&usbmisc1 0>;
+ power-domains = <&pgc_usb_otg1>;
status = "disabled";
};
@@ -972,6 +1006,7 @@ usbotg2: usb@32e50000 {
assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>;
fsl,usbphy = <&usbphynop2>;
fsl,usbmisc = <&usbmisc2 0>;
+ power-domains = <&pgc_usb_otg2>;
status = "disabled";
};
--
2.25.1
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH v1 7/7] arm64: dts: imx8mm: add power-domains
@ 2021-04-07 21:21 ` Adrien Grassein
0 siblings, 0 replies; 26+ messages in thread
From: Adrien Grassein @ 2021-04-07 21:21 UTC (permalink / raw)
Cc: robh+dt, shawnguo, s.hauer, kernel, festevam, linux-imx, l.stach,
Anson.Huang, krzk, peng.fan, aisheng.dong, qiangqing.zhang,
alice.guo, aford173, agx, andrew.smirnov, devicetree,
linux-arm-kernel, linux-kernel, Adrien Grassein
Add description for HSIO and USB power-domains.
Signed-off-by: Adrien Grassein <adrien.grassein@gmail.com>
---
arch/arm64/boot/dts/freescale/imx8mm.dtsi | 35 +++++++++++++++++++++++
1 file changed, 35 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
index a27e02bee6b4..028b8930db5a 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
@@ -4,6 +4,7 @@
*/
#include <dt-bindings/clock/imx8mm-clock.h>
+#include <dt-bindings/power/imx8mm-power.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
@@ -600,6 +601,38 @@ src: reset-controller@30390000 {
interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
#reset-cells = <1>;
};
+
+ gpc: gpc@303a0000 {
+ compatible = "fsl,imx8mm-gpc";
+ reg = <0x303a0000 0x10000>;
+ interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&gic>;
+ interrupt-controller;
+ #interrupt-cells = <3>;
+
+ pgc {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pgc_hsiomix: power-domain@IMX8MM_POWER_DOMAIN_HSIOMIX {
+ #power-domain-cells = <0>;
+ reg = <IMX8MM_POWER_DOMAIN_HSIOMIX>;
+ clocks = <&clk IMX8MM_CLK_USB_BUS>;
+ };
+
+ pgc_usb_otg1: power-domain@IMX8MM_POWER_DOMAIN_USB_OTG1 {
+ #power-domain-cells = <0>;
+ reg = <IMX8MM_POWER_DOMAIN_USB_OTG1>;
+ power-domains = <&pgc_hsiomix>;
+ };
+
+ pgc_usb_otg2: power-domain@IMX8MM_POWER_DOMAIN_USB_OTG2 {
+ #power-domain-cells = <0>;
+ reg = <IMX8MM_POWER_DOMAIN_USB_OTG2>;
+ power-domains = <&pgc_hsiomix>;
+ };
+ };
+ };
};
aips2: bus@30400000 {
@@ -953,6 +986,7 @@ usbotg1: usb@32e40000 {
assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>;
fsl,usbphy = <&usbphynop1>;
fsl,usbmisc = <&usbmisc1 0>;
+ power-domains = <&pgc_usb_otg1>;
status = "disabled";
};
@@ -972,6 +1006,7 @@ usbotg2: usb@32e50000 {
assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>;
fsl,usbphy = <&usbphynop2>;
fsl,usbmisc = <&usbmisc2 0>;
+ power-domains = <&pgc_usb_otg2>;
status = "disabled";
};
--
2.25.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 26+ messages in thread
* Re: [PATCH v1 0/7] imx-gpcv2 improvements
2021-04-07 21:21 ` Adrien Grassein
@ 2021-04-07 22:13 ` Lucas Stach
-1 siblings, 0 replies; 26+ messages in thread
From: Lucas Stach @ 2021-04-07 22:13 UTC (permalink / raw)
To: Adrien Grassein
Cc: robh+dt, shawnguo, s.hauer, kernel, festevam, linux-imx,
Anson.Huang, krzk, peng.fan, aisheng.dong, qiangqing.zhang,
alice.guo, aford173, agx, andrew.smirnov, devicetree,
linux-arm-kernel, linux-kernel
Hi Adrien,
I feel like I already mentioned to you some time ago that there is
already a much more complete patch series to add this functionality on
the list [1].
If you want this functionality to go upstream, please help test and
extend this patch series.
Regards,
Lucas
[1] https://lore.kernel.org/linux-arm-kernel/20201105174434.1817539-1-l.stach@pengutronix.de/
Am Mittwoch, dem 07.04.2021 um 23:21 +0200 schrieb Adrien Grassein:
> Hi,
>
> This patch set aims is to add the support of the i.MX8 MM power domains
> on the mainline kernel.
>
> To achieve this, I do several patches
> - Check errors when reading or writing registers (concerns i.MX8M base
> implementation);
> - Fix power up/down sequence. Handshake was not checked and it was
> not called at the appropriate time (concerns i.MX8M base
> implementaions);
> - Allow domains without power sequence control like the HSIOMIX of the
> i.MX8MM.
> - Add some i.MX8MM domains (HSIO and OTGS);
> - Introduce quirks. For example, i.MX8MM OTG domains should not be
> powered off (seen n the source code of th i.MX ATF). Quirks are
> easily upgrable for other cases.
> - Finally I defined power domains into the imx8mm.dtb file.
>
> I know that this kind of patch is rejected by NXP ut the other way
> (callin ATF directly) was also rejected.
>
> I also know that NXP is concerned abou adding hundred lines of codes for
> each new SOC but it' the way it works on Linux. And the "added code"
> mainly consist of adding structures, defines and generic methods for
> regmap.
>
> If it's a real problem, maybe we can introduc a new "gpcv3" driver for
> i.MX8MM, i.MX8MN and i.MX8MP.
>
> Thanks,
>
> Adrien Grassein (7):
> soc: imx: gpcv2: check for errors when r/w registers
> soc: imx: gpcv2: Fix power up/down sequence
> soc: imx: gpcv2: allow domains without power sequence control
> dt-bindings: power: fsl,imx-gpcv2: add definitions for i.MX8MM
> soc: imx: gpcv2: add HSIOMIX and USB domains for i.MX8MM
> soc: imx: gpcv2: add quirks to domains
> arm64: dts: imx8mm: add power-domains
>
> .../bindings/power/fsl,imx-gpcv2.yaml | 7 +-
> arch/arm64/boot/dts/freescale/imx8mm.dtsi | 35 ++
> drivers/soc/imx/gpcv2.c | 336 ++++++++++++++----
> include/dt-bindings/power/imx8mm-power.h | 21 ++
> 4 files changed, 333 insertions(+), 66 deletions(-)
> create mode 100644 include/dt-bindings/power/imx8mm-power.h
>
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH v1 0/7] imx-gpcv2 improvements
@ 2021-04-07 22:13 ` Lucas Stach
0 siblings, 0 replies; 26+ messages in thread
From: Lucas Stach @ 2021-04-07 22:13 UTC (permalink / raw)
To: Adrien Grassein
Cc: robh+dt, shawnguo, s.hauer, kernel, festevam, linux-imx,
Anson.Huang, krzk, peng.fan, aisheng.dong, qiangqing.zhang,
alice.guo, aford173, agx, andrew.smirnov, devicetree,
linux-arm-kernel, linux-kernel
Hi Adrien,
I feel like I already mentioned to you some time ago that there is
already a much more complete patch series to add this functionality on
the list [1].
If you want this functionality to go upstream, please help test and
extend this patch series.
Regards,
Lucas
[1] https://lore.kernel.org/linux-arm-kernel/20201105174434.1817539-1-l.stach@pengutronix.de/
Am Mittwoch, dem 07.04.2021 um 23:21 +0200 schrieb Adrien Grassein:
> Hi,
>
> This patch set aims is to add the support of the i.MX8 MM power domains
> on the mainline kernel.
>
> To achieve this, I do several patches
> - Check errors when reading or writing registers (concerns i.MX8M base
> implementation);
> - Fix power up/down sequence. Handshake was not checked and it was
> not called at the appropriate time (concerns i.MX8M base
> implementaions);
> - Allow domains without power sequence control like the HSIOMIX of the
> i.MX8MM.
> - Add some i.MX8MM domains (HSIO and OTGS);
> - Introduce quirks. For example, i.MX8MM OTG domains should not be
> powered off (seen n the source code of th i.MX ATF). Quirks are
> easily upgrable for other cases.
> - Finally I defined power domains into the imx8mm.dtb file.
>
> I know that this kind of patch is rejected by NXP ut the other way
> (callin ATF directly) was also rejected.
>
> I also know that NXP is concerned abou adding hundred lines of codes for
> each new SOC but it' the way it works on Linux. And the "added code"
> mainly consist of adding structures, defines and generic methods for
> regmap.
>
> If it's a real problem, maybe we can introduc a new "gpcv3" driver for
> i.MX8MM, i.MX8MN and i.MX8MP.
>
> Thanks,
>
> Adrien Grassein (7):
> soc: imx: gpcv2: check for errors when r/w registers
> soc: imx: gpcv2: Fix power up/down sequence
> soc: imx: gpcv2: allow domains without power sequence control
> dt-bindings: power: fsl,imx-gpcv2: add definitions for i.MX8MM
> soc: imx: gpcv2: add HSIOMIX and USB domains for i.MX8MM
> soc: imx: gpcv2: add quirks to domains
> arm64: dts: imx8mm: add power-domains
>
> .../bindings/power/fsl,imx-gpcv2.yaml | 7 +-
> arch/arm64/boot/dts/freescale/imx8mm.dtsi | 35 ++
> drivers/soc/imx/gpcv2.c | 336 ++++++++++++++----
> include/dt-bindings/power/imx8mm-power.h | 21 ++
> 4 files changed, 333 insertions(+), 66 deletions(-)
> create mode 100644 include/dt-bindings/power/imx8mm-power.h
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH v1 0/7] imx-gpcv2 improvements
2021-04-07 22:13 ` Lucas Stach
@ 2021-04-07 23:03 ` Adam Ford
-1 siblings, 0 replies; 26+ messages in thread
From: Adam Ford @ 2021-04-07 23:03 UTC (permalink / raw)
To: Lucas Stach
Cc: Adrien Grassein, Rob Herring, Shawn Guo, Sascha Hauer,
Sascha Hauer, Fabio Estevam, NXP Linux Team, Anson Huang,
Krzysztof Kozlowski, Peng Fan, Aisheng Dong, qiangqing.zhang,
Alice Guo, Guido Günther, Andrey Smirnov, devicetree,
arm-soc, Linux Kernel Mailing List
On Wed, Apr 7, 2021 at 5:13 PM Lucas Stach <l.stach@pengutronix.de> wrote:
>
> Hi Adrien,
>
> I feel like I already mentioned to you some time ago that there is
> already a much more complete patch series to add this functionality on
> the list [1].
>
> If you want this functionality to go upstream, please help test and
> extend this patch series.
>
> Regards,
> Lucas
>
> [1] https://lore.kernel.org/linux-arm-kernel/20201105174434.1817539-1-l.stach@pengutronix.de/
I took Lucas' code and attempted to build upon it to add Nano support.
At some point, someone from NXP thought it would get really hard to
read if we started filling that file with every supported SoC.
To help with that, I created a patch to split the gpcv2 code into a
gcpv2 core functions with the individual SoC's having separate files
to help keep things a little cleaner, and easier to read:
gpcv2-imx7, gpcv2-imx8mq, gpcv2-imx8mm, and gpcv2-imx8mn, etc.
I was holding off on doing anything with it, because the dt-bindings
appeared to be stalled, and the attempt by Lucas to get the basic
functionality was stalled.
As of right now, it seems like without any changes, I can not get my
Mini or Nano to wake from sleep unless I use a U-Boot and ATF based on
NXP's custom branches. When using the custom branches, I made some
additional patches to the gpcv2 to add a flag which would prevent
disabling USB OTG on Mini and Nano which appeared to help waking from
sleep, and it matched some of what NXP's custom ATF was doing.
I know there has been some concern about using syscon address the
resets and enables, but I took some work Marek did, and added to it by
adding some flags to the structure which could take the syscon and
write different values to the blk-ctl register depending on whether or
not it was a Mini or Nano (and probably Plus). Using some of these,
I was able to get the dispmix to come out of reset and enable the
LCDIF on both Mini and Nano, but for some reason, any attempts to
enable the mipi domain were causing failures in other domains, so I
strilpped them out again. I've withheld posting any of these for the
same reasons I withheld my other patches.
As soon as Lucas' patch [1] above or something similar gets accepted,
can rebase and submit a few of the patches I have.
adam
>
> Am Mittwoch, dem 07.04.2021 um 23:21 +0200 schrieb Adrien Grassein:
> > Hi,
> >
> > This patch set aims is to add the support of the i.MX8 MM power domains
> > on the mainline kernel.
> >
> > To achieve this, I do several patches
> > - Check errors when reading or writing registers (concerns i.MX8M base
> > implementation);
> > - Fix power up/down sequence. Handshake was not checked and it was
> > not called at the appropriate time (concerns i.MX8M base
> > implementaions);
> > - Allow domains without power sequence control like the HSIOMIX of the
> > i.MX8MM.
> > - Add some i.MX8MM domains (HSIO and OTGS);
> > - Introduce quirks. For example, i.MX8MM OTG domains should not be
> > powered off (seen n the source code of th i.MX ATF). Quirks are
> > easily upgrable for other cases.
> > - Finally I defined power domains into the imx8mm.dtb file.
> >
> > I know that this kind of patch is rejected by NXP ut the other way
> > (callin ATF directly) was also rejected.
> >
> > I also know that NXP is concerned abou adding hundred lines of codes for
> > each new SOC but it' the way it works on Linux. And the "added code"
> > mainly consist of adding structures, defines and generic methods for
> > regmap.
> >
> > If it's a real problem, maybe we can introduc a new "gpcv3" driver for
> > i.MX8MM, i.MX8MN and i.MX8MP.
> >
> > Thanks,
> >
> > Adrien Grassein (7):
> > soc: imx: gpcv2: check for errors when r/w registers
> > soc: imx: gpcv2: Fix power up/down sequence
> > soc: imx: gpcv2: allow domains without power sequence control
> > dt-bindings: power: fsl,imx-gpcv2: add definitions for i.MX8MM
> > soc: imx: gpcv2: add HSIOMIX and USB domains for i.MX8MM
> > soc: imx: gpcv2: add quirks to domains
> > arm64: dts: imx8mm: add power-domains
> >
> > .../bindings/power/fsl,imx-gpcv2.yaml | 7 +-
> > arch/arm64/boot/dts/freescale/imx8mm.dtsi | 35 ++
> > drivers/soc/imx/gpcv2.c | 336 ++++++++++++++----
> > include/dt-bindings/power/imx8mm-power.h | 21 ++
> > 4 files changed, 333 insertions(+), 66 deletions(-)
> > create mode 100644 include/dt-bindings/power/imx8mm-power.h
> >
>
>
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH v1 0/7] imx-gpcv2 improvements
@ 2021-04-07 23:03 ` Adam Ford
0 siblings, 0 replies; 26+ messages in thread
From: Adam Ford @ 2021-04-07 23:03 UTC (permalink / raw)
To: Lucas Stach
Cc: Adrien Grassein, Rob Herring, Shawn Guo, Sascha Hauer,
Sascha Hauer, Fabio Estevam, NXP Linux Team, Anson Huang,
Krzysztof Kozlowski, Peng Fan, Aisheng Dong, qiangqing.zhang,
Alice Guo, Guido Günther, Andrey Smirnov, devicetree,
arm-soc, Linux Kernel Mailing List
On Wed, Apr 7, 2021 at 5:13 PM Lucas Stach <l.stach@pengutronix.de> wrote:
>
> Hi Adrien,
>
> I feel like I already mentioned to you some time ago that there is
> already a much more complete patch series to add this functionality on
> the list [1].
>
> If you want this functionality to go upstream, please help test and
> extend this patch series.
>
> Regards,
> Lucas
>
> [1] https://lore.kernel.org/linux-arm-kernel/20201105174434.1817539-1-l.stach@pengutronix.de/
I took Lucas' code and attempted to build upon it to add Nano support.
At some point, someone from NXP thought it would get really hard to
read if we started filling that file with every supported SoC.
To help with that, I created a patch to split the gpcv2 code into a
gcpv2 core functions with the individual SoC's having separate files
to help keep things a little cleaner, and easier to read:
gpcv2-imx7, gpcv2-imx8mq, gpcv2-imx8mm, and gpcv2-imx8mn, etc.
I was holding off on doing anything with it, because the dt-bindings
appeared to be stalled, and the attempt by Lucas to get the basic
functionality was stalled.
As of right now, it seems like without any changes, I can not get my
Mini or Nano to wake from sleep unless I use a U-Boot and ATF based on
NXP's custom branches. When using the custom branches, I made some
additional patches to the gpcv2 to add a flag which would prevent
disabling USB OTG on Mini and Nano which appeared to help waking from
sleep, and it matched some of what NXP's custom ATF was doing.
I know there has been some concern about using syscon address the
resets and enables, but I took some work Marek did, and added to it by
adding some flags to the structure which could take the syscon and
write different values to the blk-ctl register depending on whether or
not it was a Mini or Nano (and probably Plus). Using some of these,
I was able to get the dispmix to come out of reset and enable the
LCDIF on both Mini and Nano, but for some reason, any attempts to
enable the mipi domain were causing failures in other domains, so I
strilpped them out again. I've withheld posting any of these for the
same reasons I withheld my other patches.
As soon as Lucas' patch [1] above or something similar gets accepted,
can rebase and submit a few of the patches I have.
adam
>
> Am Mittwoch, dem 07.04.2021 um 23:21 +0200 schrieb Adrien Grassein:
> > Hi,
> >
> > This patch set aims is to add the support of the i.MX8 MM power domains
> > on the mainline kernel.
> >
> > To achieve this, I do several patches
> > - Check errors when reading or writing registers (concerns i.MX8M base
> > implementation);
> > - Fix power up/down sequence. Handshake was not checked and it was
> > not called at the appropriate time (concerns i.MX8M base
> > implementaions);
> > - Allow domains without power sequence control like the HSIOMIX of the
> > i.MX8MM.
> > - Add some i.MX8MM domains (HSIO and OTGS);
> > - Introduce quirks. For example, i.MX8MM OTG domains should not be
> > powered off (seen n the source code of th i.MX ATF). Quirks are
> > easily upgrable for other cases.
> > - Finally I defined power domains into the imx8mm.dtb file.
> >
> > I know that this kind of patch is rejected by NXP ut the other way
> > (callin ATF directly) was also rejected.
> >
> > I also know that NXP is concerned abou adding hundred lines of codes for
> > each new SOC but it' the way it works on Linux. And the "added code"
> > mainly consist of adding structures, defines and generic methods for
> > regmap.
> >
> > If it's a real problem, maybe we can introduc a new "gpcv3" driver for
> > i.MX8MM, i.MX8MN and i.MX8MP.
> >
> > Thanks,
> >
> > Adrien Grassein (7):
> > soc: imx: gpcv2: check for errors when r/w registers
> > soc: imx: gpcv2: Fix power up/down sequence
> > soc: imx: gpcv2: allow domains without power sequence control
> > dt-bindings: power: fsl,imx-gpcv2: add definitions for i.MX8MM
> > soc: imx: gpcv2: add HSIOMIX and USB domains for i.MX8MM
> > soc: imx: gpcv2: add quirks to domains
> > arm64: dts: imx8mm: add power-domains
> >
> > .../bindings/power/fsl,imx-gpcv2.yaml | 7 +-
> > arch/arm64/boot/dts/freescale/imx8mm.dtsi | 35 ++
> > drivers/soc/imx/gpcv2.c | 336 ++++++++++++++----
> > include/dt-bindings/power/imx8mm-power.h | 21 ++
> > 4 files changed, 333 insertions(+), 66 deletions(-)
> > create mode 100644 include/dt-bindings/power/imx8mm-power.h
> >
>
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH v1 0/7] imx-gpcv2 improvements
2021-04-07 22:13 ` Lucas Stach
@ 2021-04-08 1:27 ` Peng Fan (OSS)
-1 siblings, 0 replies; 26+ messages in thread
From: Peng Fan (OSS) @ 2021-04-08 1:27 UTC (permalink / raw)
To: Lucas Stach, Adrien Grassein
Cc: robh+dt, shawnguo, s.hauer, kernel, festevam, linux-imx,
Anson.Huang, krzk, peng.fan, aisheng.dong, qiangqing.zhang,
alice.guo, aford173, agx, andrew.smirnov, devicetree,
linux-arm-kernel, linux-kernel
Hi Lucas,
On 2021/4/8 6:13, Lucas Stach wrote:
> Hi Adrien,
>
> I feel like I already mentioned to you some time ago that there is
> already a much more complete patch series to add this functionality on
> the list [1].
>
> If you want this functionality to go upstream, please help test and
> extend this patch series.
>
> Regards,
> Lucas
>
> [1] https://lore.kernel.org/linux-arm-kernel/20201105174434.1817539-1-l.stach@pengutronix.de/
Would you share what's the issue that block this going forward?
Thanks,
Peng.
>
> Am Mittwoch, dem 07.04.2021 um 23:21 +0200 schrieb Adrien Grassein:
>> Hi,
>>
>> This patch set aims is to add the support of the i.MX8 MM power domains
>> on the mainline kernel.
>>
>> To achieve this, I do several patches
>> - Check errors when reading or writing registers (concerns i.MX8M base
>> implementation);
>> - Fix power up/down sequence. Handshake was not checked and it was
>> not called at the appropriate time (concerns i.MX8M base
>> implementaions);
>> - Allow domains without power sequence control like the HSIOMIX of the
>> i.MX8MM.
>> - Add some i.MX8MM domains (HSIO and OTGS);
>> - Introduce quirks. For example, i.MX8MM OTG domains should not be
>> powered off (seen n the source code of th i.MX ATF). Quirks are
>> easily upgrable for other cases.
>> - Finally I defined power domains into the imx8mm.dtb file.
>>
>> I know that this kind of patch is rejected by NXP ut the other way
>> (callin ATF directly) was also rejected.
>>
>> I also know that NXP is concerned abou adding hundred lines of codes for
>> each new SOC but it' the way it works on Linux. And the "added code"
>> mainly consist of adding structures, defines and generic methods for
>> regmap.
>>
>> If it's a real problem, maybe we can introduc a new "gpcv3" driver for
>> i.MX8MM, i.MX8MN and i.MX8MP.
>>
>> Thanks,
>>
>> Adrien Grassein (7):
>> soc: imx: gpcv2: check for errors when r/w registers
>> soc: imx: gpcv2: Fix power up/down sequence
>> soc: imx: gpcv2: allow domains without power sequence control
>> dt-bindings: power: fsl,imx-gpcv2: add definitions for i.MX8MM
>> soc: imx: gpcv2: add HSIOMIX and USB domains for i.MX8MM
>> soc: imx: gpcv2: add quirks to domains
>> arm64: dts: imx8mm: add power-domains
>>
>> .../bindings/power/fsl,imx-gpcv2.yaml | 7 +-
>> arch/arm64/boot/dts/freescale/imx8mm.dtsi | 35 ++
>> drivers/soc/imx/gpcv2.c | 336 ++++++++++++++----
>> include/dt-bindings/power/imx8mm-power.h | 21 ++
>> 4 files changed, 333 insertions(+), 66 deletions(-)
>> create mode 100644 include/dt-bindings/power/imx8mm-power.h
>>
>
>
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH v1 0/7] imx-gpcv2 improvements
@ 2021-04-08 1:27 ` Peng Fan (OSS)
0 siblings, 0 replies; 26+ messages in thread
From: Peng Fan (OSS) @ 2021-04-08 1:27 UTC (permalink / raw)
To: Lucas Stach, Adrien Grassein
Cc: robh+dt, shawnguo, s.hauer, kernel, festevam, linux-imx,
Anson.Huang, krzk, peng.fan, aisheng.dong, qiangqing.zhang,
alice.guo, aford173, agx, andrew.smirnov, devicetree,
linux-arm-kernel, linux-kernel
Hi Lucas,
On 2021/4/8 6:13, Lucas Stach wrote:
> Hi Adrien,
>
> I feel like I already mentioned to you some time ago that there is
> already a much more complete patch series to add this functionality on
> the list [1].
>
> If you want this functionality to go upstream, please help test and
> extend this patch series.
>
> Regards,
> Lucas
>
> [1] https://lore.kernel.org/linux-arm-kernel/20201105174434.1817539-1-l.stach@pengutronix.de/
Would you share what's the issue that block this going forward?
Thanks,
Peng.
>
> Am Mittwoch, dem 07.04.2021 um 23:21 +0200 schrieb Adrien Grassein:
>> Hi,
>>
>> This patch set aims is to add the support of the i.MX8 MM power domains
>> on the mainline kernel.
>>
>> To achieve this, I do several patches
>> - Check errors when reading or writing registers (concerns i.MX8M base
>> implementation);
>> - Fix power up/down sequence. Handshake was not checked and it was
>> not called at the appropriate time (concerns i.MX8M base
>> implementaions);
>> - Allow domains without power sequence control like the HSIOMIX of the
>> i.MX8MM.
>> - Add some i.MX8MM domains (HSIO and OTGS);
>> - Introduce quirks. For example, i.MX8MM OTG domains should not be
>> powered off (seen n the source code of th i.MX ATF). Quirks are
>> easily upgrable for other cases.
>> - Finally I defined power domains into the imx8mm.dtb file.
>>
>> I know that this kind of patch is rejected by NXP ut the other way
>> (callin ATF directly) was also rejected.
>>
>> I also know that NXP is concerned abou adding hundred lines of codes for
>> each new SOC but it' the way it works on Linux. And the "added code"
>> mainly consist of adding structures, defines and generic methods for
>> regmap.
>>
>> If it's a real problem, maybe we can introduc a new "gpcv3" driver for
>> i.MX8MM, i.MX8MN and i.MX8MP.
>>
>> Thanks,
>>
>> Adrien Grassein (7):
>> soc: imx: gpcv2: check for errors when r/w registers
>> soc: imx: gpcv2: Fix power up/down sequence
>> soc: imx: gpcv2: allow domains without power sequence control
>> dt-bindings: power: fsl,imx-gpcv2: add definitions for i.MX8MM
>> soc: imx: gpcv2: add HSIOMIX and USB domains for i.MX8MM
>> soc: imx: gpcv2: add quirks to domains
>> arm64: dts: imx8mm: add power-domains
>>
>> .../bindings/power/fsl,imx-gpcv2.yaml | 7 +-
>> arch/arm64/boot/dts/freescale/imx8mm.dtsi | 35 ++
>> drivers/soc/imx/gpcv2.c | 336 ++++++++++++++----
>> include/dt-bindings/power/imx8mm-power.h | 21 ++
>> 4 files changed, 333 insertions(+), 66 deletions(-)
>> create mode 100644 include/dt-bindings/power/imx8mm-power.h
>>
>
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH v1 0/7] imx-gpcv2 improvements
2021-04-08 1:27 ` Peng Fan (OSS)
@ 2021-04-09 13:36 ` Adam Ford
-1 siblings, 0 replies; 26+ messages in thread
From: Adam Ford @ 2021-04-09 13:36 UTC (permalink / raw)
To: Peng Fan (OSS)
Cc: Lucas Stach, Adrien Grassein, Rob Herring, Shawn Guo,
Sascha Hauer, Sascha Hauer, Fabio Estevam, NXP Linux Team,
Anson Huang, Krzysztof Kozlowski, Peng Fan, Aisheng Dong,
qiangqing.zhang, Alice Guo, Guido Günther, Andrey Smirnov,
devicetree, arm-soc, Linux Kernel Mailing List
On Wed, Apr 7, 2021 at 8:27 PM Peng Fan (OSS) <peng.fan@oss.nxp.com> wrote:
>
> Hi Lucas,
>
> On 2021/4/8 6:13, Lucas Stach wrote:
> > Hi Adrien,
> >
> > I feel like I already mentioned to you some time ago that there is
> > already a much more complete patch series to add this functionality on
> > the list [1].
> >
> > If you want this functionality to go upstream, please help test and
> > extend this patch series.
> >
> > Regards,
> > Lucas
> >
> > [1] https://lore.kernel.org/linux-arm-kernel/20201105174434.1817539-1-l.stach@pengutronix.de/
>
> Would you share what's the issue that block this going forward?
Peng,
I know of a few. One of them is mentioned in [1] above. From what I
can tell, the dt-bindings have halted being able to enable the GPU and
USB power domains. See [2] for some of that dialog.
The second part that I am aware is the blk-ctl being dependent on the
power domain and the power domain being dependent on the blk-ctl [3]
There was some discussion of using syscon to let the power-domain
finish coming up and then referencing the the power-domain from the
blk-ctl, but there was some disagreement [4] on that approach
I think Abel tried to create an IRC, but by the time I was able to
join the IRC, there was no activity.
[2] - https://lore.kernel.org/linux-arm-kernel/CAHCN7xLdkEd0G3fa9gAp-xvKZ-bYmvcyn-8OEbgNjBJyCCOs9g@mail.gmail.com/
[3] - https://lkml.org/lkml/2020/11/9/17
[4] - https://www.spinics.net/lists/arm-kernel/msg849032.html
>
> Thanks,
> Peng.
>
> >
> > Am Mittwoch, dem 07.04.2021 um 23:21 +0200 schrieb Adrien Grassein:
> >> Hi,
> >>
> >> This patch set aims is to add the support of the i.MX8 MM power domains
> >> on the mainline kernel.
> >>
> >> To achieve this, I do several patches
> >> - Check errors when reading or writing registers (concerns i.MX8M base
> >> implementation);
> >> - Fix power up/down sequence. Handshake was not checked and it was
> >> not called at the appropriate time (concerns i.MX8M base
> >> implementaions);
> >> - Allow domains without power sequence control like the HSIOMIX of the
> >> i.MX8MM.
> >> - Add some i.MX8MM domains (HSIO and OTGS);
> >> - Introduce quirks. For example, i.MX8MM OTG domains should not be
> >> powered off (seen n the source code of th i.MX ATF). Quirks are
> >> easily upgrable for other cases.
> >> - Finally I defined power domains into the imx8mm.dtb file.
> >>
> >> I know that this kind of patch is rejected by NXP ut the other way
> >> (callin ATF directly) was also rejected.
> >>
> >> I also know that NXP is concerned abou adding hundred lines of codes for
> >> each new SOC but it' the way it works on Linux. And the "added code"
> >> mainly consist of adding structures, defines and generic methods for
> >> regmap.
> >>
> >> If it's a real problem, maybe we can introduc a new "gpcv3" driver for
> >> i.MX8MM, i.MX8MN and i.MX8MP.
> >>
> >> Thanks,
> >>
> >> Adrien Grassein (7):
> >> soc: imx: gpcv2: check for errors when r/w registers
> >> soc: imx: gpcv2: Fix power up/down sequence
> >> soc: imx: gpcv2: allow domains without power sequence control
> >> dt-bindings: power: fsl,imx-gpcv2: add definitions for i.MX8MM
> >> soc: imx: gpcv2: add HSIOMIX and USB domains for i.MX8MM
> >> soc: imx: gpcv2: add quirks to domains
> >> arm64: dts: imx8mm: add power-domains
> >>
> >> .../bindings/power/fsl,imx-gpcv2.yaml | 7 +-
> >> arch/arm64/boot/dts/freescale/imx8mm.dtsi | 35 ++
> >> drivers/soc/imx/gpcv2.c | 336 ++++++++++++++----
> >> include/dt-bindings/power/imx8mm-power.h | 21 ++
> >> 4 files changed, 333 insertions(+), 66 deletions(-)
> >> create mode 100644 include/dt-bindings/power/imx8mm-power.h
> >>
> >
> >
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH v1 0/7] imx-gpcv2 improvements
@ 2021-04-09 13:36 ` Adam Ford
0 siblings, 0 replies; 26+ messages in thread
From: Adam Ford @ 2021-04-09 13:36 UTC (permalink / raw)
To: Peng Fan (OSS)
Cc: Lucas Stach, Adrien Grassein, Rob Herring, Shawn Guo,
Sascha Hauer, Sascha Hauer, Fabio Estevam, NXP Linux Team,
Anson Huang, Krzysztof Kozlowski, Peng Fan, Aisheng Dong,
qiangqing.zhang, Alice Guo, Guido Günther, Andrey Smirnov,
devicetree, arm-soc, Linux Kernel Mailing List
On Wed, Apr 7, 2021 at 8:27 PM Peng Fan (OSS) <peng.fan@oss.nxp.com> wrote:
>
> Hi Lucas,
>
> On 2021/4/8 6:13, Lucas Stach wrote:
> > Hi Adrien,
> >
> > I feel like I already mentioned to you some time ago that there is
> > already a much more complete patch series to add this functionality on
> > the list [1].
> >
> > If you want this functionality to go upstream, please help test and
> > extend this patch series.
> >
> > Regards,
> > Lucas
> >
> > [1] https://lore.kernel.org/linux-arm-kernel/20201105174434.1817539-1-l.stach@pengutronix.de/
>
> Would you share what's the issue that block this going forward?
Peng,
I know of a few. One of them is mentioned in [1] above. From what I
can tell, the dt-bindings have halted being able to enable the GPU and
USB power domains. See [2] for some of that dialog.
The second part that I am aware is the blk-ctl being dependent on the
power domain and the power domain being dependent on the blk-ctl [3]
There was some discussion of using syscon to let the power-domain
finish coming up and then referencing the the power-domain from the
blk-ctl, but there was some disagreement [4] on that approach
I think Abel tried to create an IRC, but by the time I was able to
join the IRC, there was no activity.
[2] - https://lore.kernel.org/linux-arm-kernel/CAHCN7xLdkEd0G3fa9gAp-xvKZ-bYmvcyn-8OEbgNjBJyCCOs9g@mail.gmail.com/
[3] - https://lkml.org/lkml/2020/11/9/17
[4] - https://www.spinics.net/lists/arm-kernel/msg849032.html
>
> Thanks,
> Peng.
>
> >
> > Am Mittwoch, dem 07.04.2021 um 23:21 +0200 schrieb Adrien Grassein:
> >> Hi,
> >>
> >> This patch set aims is to add the support of the i.MX8 MM power domains
> >> on the mainline kernel.
> >>
> >> To achieve this, I do several patches
> >> - Check errors when reading or writing registers (concerns i.MX8M base
> >> implementation);
> >> - Fix power up/down sequence. Handshake was not checked and it was
> >> not called at the appropriate time (concerns i.MX8M base
> >> implementaions);
> >> - Allow domains without power sequence control like the HSIOMIX of the
> >> i.MX8MM.
> >> - Add some i.MX8MM domains (HSIO and OTGS);
> >> - Introduce quirks. For example, i.MX8MM OTG domains should not be
> >> powered off (seen n the source code of th i.MX ATF). Quirks are
> >> easily upgrable for other cases.
> >> - Finally I defined power domains into the imx8mm.dtb file.
> >>
> >> I know that this kind of patch is rejected by NXP ut the other way
> >> (callin ATF directly) was also rejected.
> >>
> >> I also know that NXP is concerned abou adding hundred lines of codes for
> >> each new SOC but it' the way it works on Linux. And the "added code"
> >> mainly consist of adding structures, defines and generic methods for
> >> regmap.
> >>
> >> If it's a real problem, maybe we can introduc a new "gpcv3" driver for
> >> i.MX8MM, i.MX8MN and i.MX8MP.
> >>
> >> Thanks,
> >>
> >> Adrien Grassein (7):
> >> soc: imx: gpcv2: check for errors when r/w registers
> >> soc: imx: gpcv2: Fix power up/down sequence
> >> soc: imx: gpcv2: allow domains without power sequence control
> >> dt-bindings: power: fsl,imx-gpcv2: add definitions for i.MX8MM
> >> soc: imx: gpcv2: add HSIOMIX and USB domains for i.MX8MM
> >> soc: imx: gpcv2: add quirks to domains
> >> arm64: dts: imx8mm: add power-domains
> >>
> >> .../bindings/power/fsl,imx-gpcv2.yaml | 7 +-
> >> arch/arm64/boot/dts/freescale/imx8mm.dtsi | 35 ++
> >> drivers/soc/imx/gpcv2.c | 336 ++++++++++++++----
> >> include/dt-bindings/power/imx8mm-power.h | 21 ++
> >> 4 files changed, 333 insertions(+), 66 deletions(-)
> >> create mode 100644 include/dt-bindings/power/imx8mm-power.h
> >>
> >
> >
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH v1 1/7] soc: imx: gpcv2: check for errors when r/w registers
2021-04-07 21:21 ` Adrien Grassein
@ 2021-04-12 17:16 ` Andrey Smirnov
-1 siblings, 0 replies; 26+ messages in thread
From: Andrey Smirnov @ 2021-04-12 17:16 UTC (permalink / raw)
To: Adrien Grassein
Cc: Rob Herring, Shawn Guo, Sascha Hauer, Sascha Hauer,
Fabio Estevam, dl-linux-imx, Lucas Stach, Anson Huang, krzk,
peng.fan, Dong Aisheng, qiangqing.zhang, alice.guo, aford173,
agx, open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
linux-arm-kernel, linux-kernel
On Wed, Apr 7, 2021 at 2:21 PM Adrien Grassein
<adrien.grassein@gmail.com> wrote:
>
> Errors were not checked after each access to registers
FWIW, I didn't write any error checking code on purpose since all of
those are memory mapped registers and I don't think there's a case for
those to error out. Don't have a strong opinion on this though.
> and clocks initialisation.
>
> Signed-off-by: Adrien Grassein <adrien.grassein@gmail.com>
> ---
> drivers/soc/imx/gpcv2.c | 62 ++++++++++++++++++++++++++++++-----------
> 1 file changed, 45 insertions(+), 17 deletions(-)
>
> diff --git a/drivers/soc/imx/gpcv2.c b/drivers/soc/imx/gpcv2.c
> index db7e7fc321b1..8ec5b1b817c7 100644
> --- a/drivers/soc/imx/gpcv2.c
> +++ b/drivers/soc/imx/gpcv2.c
> @@ -140,8 +140,12 @@ static int imx_gpc_pu_pgc_sw_pxx_req(struct generic_pm_domain *genpd,
> int i, ret = 0;
> u32 pxx_req;
>
> - regmap_update_bits(domain->regmap, GPC_PGC_CPU_MAPPING,
> - domain->bits.map, domain->bits.map);
> + ret = regmap_update_bits(domain->regmap, GPC_PGC_CPU_MAPPING,
> + domain->bits.map, domain->bits.map);
> + if (ret) {
> + dev_err(domain->dev, "failed to map GPC PGC domain\n");
> + return ret;
> + }
>
> if (has_regulator && on) {
> ret = regulator_enable(domain->regulator);
> @@ -152,19 +156,39 @@ static int imx_gpc_pu_pgc_sw_pxx_req(struct generic_pm_domain *genpd,
> }
>
> /* Enable reset clocks for all devices in the domain */
> - for (i = 0; i < domain->num_clks; i++)
> - clk_prepare_enable(domain->clk[i]);
> + for (i = 0; i < domain->num_clks; i++) {
> + ret = clk_prepare_enable(domain->clk[i]);
> + if (ret) {
> + dev_err(domain->dev, "failed to enable clocks\n");
> + goto disable_clocks;
> + }
> + }
>
> - if (enable_power_control)
> - regmap_update_bits(domain->regmap, GPC_PGC_CTRL(domain->pgc),
> - GPC_PGC_CTRL_PCR, GPC_PGC_CTRL_PCR);
> + if (enable_power_control) {
> + ret = regmap_update_bits(domain->regmap, GPC_PGC_CTRL(domain->pgc),
> + GPC_PGC_CTRL_PCR, GPC_PGC_CTRL_PCR);
> + if (ret) {
> + dev_err(domain->dev, "failed to enable power control\n");
> + goto disable_clocks;
> + }
> + }
>
> - if (domain->bits.hsk)
> - regmap_update_bits(domain->regmap, GPC_PU_PWRHSK,
> - domain->bits.hsk, on ? domain->bits.hsk : 0);
> + if (domain->bits.hsk) {
> + ret = regmap_update_bits(domain->regmap, GPC_PU_PWRHSK,
> + domain->bits.hsk,
> + on ? domain->bits.hsk : 0);
> + if (ret) {
> + dev_err(domain->dev, "Failed to initiate handshake\n");
> + goto disable_power_control;
> + }
> + }
>
> - regmap_update_bits(domain->regmap, offset,
> - domain->bits.pxx, domain->bits.pxx);
> + ret = regmap_update_bits(domain->regmap, offset,
> + domain->bits.pxx, domain->bits.pxx);
> + if (ret) {
> + dev_err(domain->dev, "failed to command PGC\n");
> + goto disable_power_control;
> + }
>
> /*
> * As per "5.5.9.4 Example Code 4" in IMX7DRM.pdf wait
> @@ -173,8 +197,15 @@ static int imx_gpc_pu_pgc_sw_pxx_req(struct generic_pm_domain *genpd,
> ret = regmap_read_poll_timeout(domain->regmap, offset, pxx_req,
> !(pxx_req & domain->bits.pxx),
> 0, USEC_PER_MSEC);
> - if (ret) {
> + if (ret)
> dev_err(domain->dev, "failed to command PGC\n");
> +
> +disable_power_control:
> + if (enable_power_control)
> + regmap_update_bits(domain->regmap, GPC_PGC_CTRL(domain->pgc),
> + GPC_PGC_CTRL_PCR, 0);
> +
> + if (ret) {
> /*
> * If we were in a process of enabling a
> * domain and failed we might as well disable
> @@ -185,10 +216,7 @@ static int imx_gpc_pu_pgc_sw_pxx_req(struct generic_pm_domain *genpd,
> on = !on;
> }
>
> - if (enable_power_control)
> - regmap_update_bits(domain->regmap, GPC_PGC_CTRL(domain->pgc),
> - GPC_PGC_CTRL_PCR, 0);
> -
> +disable_clocks:
> /* Disable reset clocks for all devices in the domain */
> for (i = 0; i < domain->num_clks; i++)
> clk_disable_unprepare(domain->clk[i]);
> --
> 2.25.1
>
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH v1 1/7] soc: imx: gpcv2: check for errors when r/w registers
@ 2021-04-12 17:16 ` Andrey Smirnov
0 siblings, 0 replies; 26+ messages in thread
From: Andrey Smirnov @ 2021-04-12 17:16 UTC (permalink / raw)
To: Adrien Grassein
Cc: Rob Herring, Shawn Guo, Sascha Hauer, Sascha Hauer,
Fabio Estevam, dl-linux-imx, Lucas Stach, Anson Huang, krzk,
peng.fan, Dong Aisheng, qiangqing.zhang, alice.guo, aford173,
agx, open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
linux-arm-kernel, linux-kernel
On Wed, Apr 7, 2021 at 2:21 PM Adrien Grassein
<adrien.grassein@gmail.com> wrote:
>
> Errors were not checked after each access to registers
FWIW, I didn't write any error checking code on purpose since all of
those are memory mapped registers and I don't think there's a case for
those to error out. Don't have a strong opinion on this though.
> and clocks initialisation.
>
> Signed-off-by: Adrien Grassein <adrien.grassein@gmail.com>
> ---
> drivers/soc/imx/gpcv2.c | 62 ++++++++++++++++++++++++++++++-----------
> 1 file changed, 45 insertions(+), 17 deletions(-)
>
> diff --git a/drivers/soc/imx/gpcv2.c b/drivers/soc/imx/gpcv2.c
> index db7e7fc321b1..8ec5b1b817c7 100644
> --- a/drivers/soc/imx/gpcv2.c
> +++ b/drivers/soc/imx/gpcv2.c
> @@ -140,8 +140,12 @@ static int imx_gpc_pu_pgc_sw_pxx_req(struct generic_pm_domain *genpd,
> int i, ret = 0;
> u32 pxx_req;
>
> - regmap_update_bits(domain->regmap, GPC_PGC_CPU_MAPPING,
> - domain->bits.map, domain->bits.map);
> + ret = regmap_update_bits(domain->regmap, GPC_PGC_CPU_MAPPING,
> + domain->bits.map, domain->bits.map);
> + if (ret) {
> + dev_err(domain->dev, "failed to map GPC PGC domain\n");
> + return ret;
> + }
>
> if (has_regulator && on) {
> ret = regulator_enable(domain->regulator);
> @@ -152,19 +156,39 @@ static int imx_gpc_pu_pgc_sw_pxx_req(struct generic_pm_domain *genpd,
> }
>
> /* Enable reset clocks for all devices in the domain */
> - for (i = 0; i < domain->num_clks; i++)
> - clk_prepare_enable(domain->clk[i]);
> + for (i = 0; i < domain->num_clks; i++) {
> + ret = clk_prepare_enable(domain->clk[i]);
> + if (ret) {
> + dev_err(domain->dev, "failed to enable clocks\n");
> + goto disable_clocks;
> + }
> + }
>
> - if (enable_power_control)
> - regmap_update_bits(domain->regmap, GPC_PGC_CTRL(domain->pgc),
> - GPC_PGC_CTRL_PCR, GPC_PGC_CTRL_PCR);
> + if (enable_power_control) {
> + ret = regmap_update_bits(domain->regmap, GPC_PGC_CTRL(domain->pgc),
> + GPC_PGC_CTRL_PCR, GPC_PGC_CTRL_PCR);
> + if (ret) {
> + dev_err(domain->dev, "failed to enable power control\n");
> + goto disable_clocks;
> + }
> + }
>
> - if (domain->bits.hsk)
> - regmap_update_bits(domain->regmap, GPC_PU_PWRHSK,
> - domain->bits.hsk, on ? domain->bits.hsk : 0);
> + if (domain->bits.hsk) {
> + ret = regmap_update_bits(domain->regmap, GPC_PU_PWRHSK,
> + domain->bits.hsk,
> + on ? domain->bits.hsk : 0);
> + if (ret) {
> + dev_err(domain->dev, "Failed to initiate handshake\n");
> + goto disable_power_control;
> + }
> + }
>
> - regmap_update_bits(domain->regmap, offset,
> - domain->bits.pxx, domain->bits.pxx);
> + ret = regmap_update_bits(domain->regmap, offset,
> + domain->bits.pxx, domain->bits.pxx);
> + if (ret) {
> + dev_err(domain->dev, "failed to command PGC\n");
> + goto disable_power_control;
> + }
>
> /*
> * As per "5.5.9.4 Example Code 4" in IMX7DRM.pdf wait
> @@ -173,8 +197,15 @@ static int imx_gpc_pu_pgc_sw_pxx_req(struct generic_pm_domain *genpd,
> ret = regmap_read_poll_timeout(domain->regmap, offset, pxx_req,
> !(pxx_req & domain->bits.pxx),
> 0, USEC_PER_MSEC);
> - if (ret) {
> + if (ret)
> dev_err(domain->dev, "failed to command PGC\n");
> +
> +disable_power_control:
> + if (enable_power_control)
> + regmap_update_bits(domain->regmap, GPC_PGC_CTRL(domain->pgc),
> + GPC_PGC_CTRL_PCR, 0);
> +
> + if (ret) {
> /*
> * If we were in a process of enabling a
> * domain and failed we might as well disable
> @@ -185,10 +216,7 @@ static int imx_gpc_pu_pgc_sw_pxx_req(struct generic_pm_domain *genpd,
> on = !on;
> }
>
> - if (enable_power_control)
> - regmap_update_bits(domain->regmap, GPC_PGC_CTRL(domain->pgc),
> - GPC_PGC_CTRL_PCR, 0);
> -
> +disable_clocks:
> /* Disable reset clocks for all devices in the domain */
> for (i = 0; i < domain->num_clks; i++)
> clk_disable_unprepare(domain->clk[i]);
> --
> 2.25.1
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 26+ messages in thread
end of thread, other threads:[~2021-04-12 17:18 UTC | newest]
Thread overview: 26+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-04-07 21:21 [PATCH v1 0/7] imx-gpcv2 improvements Adrien Grassein
2021-04-07 21:21 ` Adrien Grassein
2021-04-07 21:21 ` [PATCH v1 1/7] soc: imx: gpcv2: check for errors when r/w registers Adrien Grassein
2021-04-07 21:21 ` Adrien Grassein
2021-04-12 17:16 ` Andrey Smirnov
2021-04-12 17:16 ` Andrey Smirnov
2021-04-07 21:21 ` [PATCH v1 2/7] soc: imx: gpcv2: Fix power up/down sequence Adrien Grassein
2021-04-07 21:21 ` Adrien Grassein
2021-04-07 21:21 ` [PATCH v1 3/7] soc: imx: gpcv2: allow domains without power sequence control Adrien Grassein
2021-04-07 21:21 ` Adrien Grassein
2021-04-07 21:21 ` [PATCH v1 4/7] dt-bindings: power: fsl,imx-gpcv2: add definitions for i.MX8MM Adrien Grassein
2021-04-07 21:21 ` [PATCH v1 4/7] dt-bindings: power: fsl, imx-gpcv2: " Adrien Grassein
2021-04-07 21:21 ` [PATCH v1 5/7] soc: imx: gpcv2: add HSIOMIX and USB domains " Adrien Grassein
2021-04-07 21:21 ` Adrien Grassein
2021-04-07 21:21 ` [PATCH v1 6/7] soc: imx: gpcv2: add quirks to domains Adrien Grassein
2021-04-07 21:21 ` Adrien Grassein
2021-04-07 21:21 ` [PATCH v1 7/7] arm64: dts: imx8mm: add power-domains Adrien Grassein
2021-04-07 21:21 ` Adrien Grassein
2021-04-07 22:13 ` [PATCH v1 0/7] imx-gpcv2 improvements Lucas Stach
2021-04-07 22:13 ` Lucas Stach
2021-04-07 23:03 ` Adam Ford
2021-04-07 23:03 ` Adam Ford
2021-04-08 1:27 ` Peng Fan (OSS)
2021-04-08 1:27 ` Peng Fan (OSS)
2021-04-09 13:36 ` Adam Ford
2021-04-09 13:36 ` Adam Ford
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