From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C6D90C77B7A for ; Fri, 19 May 2023 22:35:31 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id B5604862B5; Sat, 20 May 2023 00:35:29 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="U/7SGa8X"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id D2E7D862B5; Sat, 20 May 2023 00:35:27 +0200 (CEST) Received: from mail-pj1-x1032.google.com (mail-pj1-x1032.google.com [IPv6:2607:f8b0:4864:20::1032]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id BD5A5847AD for ; Sat, 20 May 2023 00:35:22 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=aford173@gmail.com Received: by mail-pj1-x1032.google.com with SMTP id 98e67ed59e1d1-25332b3915bso3006083a91.2 for ; Fri, 19 May 2023 15:35:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1684535721; x=1687127721; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:from:to:cc:subject:date :message-id:reply-to; bh=BxbNqpBTeIJaPr6sxDNiWOQPp9TE0FJ9lyIBKs+ThwE=; b=U/7SGa8XKXt4NTKuWw3/5MK3fvQowarYOwXTwYDr7FDPfqMVOY10D7FlaFDGfXtptf R6JiHtpetrsrR3C28WjCO0/OwUpahUN7pECwNpBvWyq+Umu6rPxdfSwzGfcb1MBNsxJj Gxd/5Wzf2uDWzftS+YcyrCJM/7lfwAq+18CbiyByGDLBi/IshQNihcMoZnLGopcPwlkt DHRL/kZZVEr+vrs48+MP7fNzWC7cmht0FBnVSS1a/LzezcTw9jk8YXzFqxK0l7wnB2fg +2DkhhXFeirSg0YrjNMIYO1+L11r52XkP1Z8SPig/jR7wkKM+SIL8MsCWE7nlnvNUcSB 2/MQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684535721; x=1687127721; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=BxbNqpBTeIJaPr6sxDNiWOQPp9TE0FJ9lyIBKs+ThwE=; b=Fqh8toq7mvTd67GCMkiwzBGvXCGFpL65DuYgQAWRpDQu0Unr7FO7+CzPdbmY/krl57 nEPuSul6DZuSyhdgwpnHUWJOK5j9zlfWFb8vgQk4u19eNyPyWPllX5a6wuqSbAleVDRk AkqJBWIZtumtxPIkjQ+UDsOR0n5uzlRBW6lCW8JHylQEWFxML0rup251yVab2dKbYA1/ aAwLHxY5yuEWalmPVSx4dInjN6xcuXJV57fhze8GXMICcM11AVWFJIpIIiPj6KTEqaAa v3B2zpBeoaso+yjLctQzMsOO/RtNT1MmM7vTmYdZ4lwPILDIlgzIeMK8afx8S5vkttCo rtEA== X-Gm-Message-State: AC+VfDwKUlZsiCWJKuxApPhMdUATGUDmDkldt3a1hlpSBjILsJVlb2ZN U8q7KudWVmb9iLtg98KEeKj1PKg63HmpZKzhmcy7TouO X-Google-Smtp-Source: ACHHUZ7i2dezV81zHWSaSrYMmQ8EuM1SIOEM57M9zn+3Y/+3Kr4iF8KdeY5A0Ho2gIwmdD6q+9Y+105UCQl3OEYxenA= X-Received: by 2002:a17:90a:cf15:b0:253:572f:79ae with SMTP id h21-20020a17090acf1500b00253572f79aemr3549153pju.46.1684535720934; Fri, 19 May 2023 15:35:20 -0700 (PDT) MIME-Version: 1.0 References: <20230427180845.127439-1-festevam@gmail.com> <20230427180845.127439-3-festevam@gmail.com> In-Reply-To: From: Adam Ford Date: Fri, 19 May 2023 17:35:09 -0500 Message-ID: Subject: Re: [PATCH 3/3] arm: dts: imx8mp: Sync with Linux 6.3 To: Tim Harvey Cc: Fabio Estevam , sbabic@denx.de, u-boot@lists.denx.de, Fabio Estevam Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean On Fri, May 19, 2023 at 5:34=E2=80=AFPM Tim Harvey = wrote: > > On Fri, May 19, 2023 at 3:31=E2=80=AFPM Tim Harvey wrote: > > > > On Fri, May 19, 2023 at 3:27=E2=80=AFPM Adam Ford = wrote: > > > > > > On Fri, May 19, 2023 at 5:19=E2=80=AFPM Tim Harvey wrote: > > > > > > > > On Wed, May 3, 2023 at 9:11=E2=80=AFAM Tim Harvey wrote: > > > > > > > > > > On Thu, Apr 27, 2023 at 11:09=E2=80=AFAM Fabio Estevam wrote: > > > > > > > > > > > > From: Fabio Estevam > > > > > > > > > > > > Sync imx8mp.dtsi and imx8mp-clock.h with Linux 6.3. > > > > > > > > > > > > Signed-off-by: Fabio Estevam > > > > > > --- > > > > > > arch/arm/dts/imx8mp.dtsi | 374 +++++++++++++++= +------- > > > > > > include/dt-bindings/clock/imx8mp-clock.h | 14 +- > > > > > > 2 files changed, 270 insertions(+), 118 deletions(-) > > > > > > > > > > > > diff --git a/arch/arm/dts/imx8mp.dtsi b/arch/arm/dts/imx8mp.dts= i > > > > > > index bb916a0948a8..a237275ee017 100644 > > > > > > --- a/arch/arm/dts/imx8mp.dtsi > > > > > > +++ b/arch/arm/dts/imx8mp.dtsi > > > > > > @@ -123,6 +123,7 @@ > > > > > > > > > > > > A53_L2: l2-cache0 { > > > > > > compatible =3D "cache"; > > > > > > + cache-unified; > > > > > > cache-level =3D <2>; > > > > > > cache-size =3D <0x80000>; > > > > > > cache-line-size =3D <64>; > > > > > > @@ -379,6 +380,8 @@ > > > > > > compatible =3D "fsl,imx8mp-tmu"= ; > > > > > > reg =3D <0x30260000 0x10000>; > > > > > > clocks =3D <&clk IMX8MP_CLK_TSE= NSOR_ROOT>; > > > > > > + nvmem-cells =3D <&tmu_calib>; > > > > > > + nvmem-cell-names =3D "calib"; > > > > > > #thermal-sensor-cells =3D <1>; > > > > > > }; > > > > > > > > > > > > @@ -411,7 +414,7 @@ > > > > > > reg =3D <0x30330000 0x10000>; > > > > > > }; > > > > > > > > > > > > - gpr: iomuxc-gpr@30340000 { > > > > > > + gpr: syscon@30340000 { > > > > > > compatible =3D "fsl,imx8mp-iomu= xc-gpr", "syscon"; > > > > > > reg =3D <0x30340000 0x10000>; > > > > > > }; > > > > > > @@ -424,27 +427,44 @@ > > > > > > #address-cells =3D <1>; > > > > > > #size-cells =3D <1>; > > > > > > > > > > > > - imx8mp_uid: unique-id@420 { > > > > > > + /* > > > > > > + * The register address below m= aps to the MX8M > > > > > > + * Fusemap Description Table en= tries this way. > > > > > > + * Assuming > > > > > > + * reg =3D ; > > > > > > + * then > > > > > > + * Fuse Address =3D (ADDR * 4= ) + 0x400 > > > > > > + * Note that if SIZE is greater= than 4, then > > > > > > + * each subsequent fuse is loca= ted at offset > > > > > > + * +0x10 in Fusemap Description= Table (e.g. > > > > > > + * reg =3D <0x8 0x8> describes = fuses 0x420 and > > > > > > + * 0x430). > > > > > > + */ > > > > > > + imx8mp_uid: unique-id@8 { /* 0x= 420-0x430 */ > > > > > > reg =3D <0x8 0x8>; > > > > > > }; > > > > > > > > > > > > - cpu_speed_grade: speed-grade@10= { > > > > > > + cpu_speed_grade: speed-grade@10= { /* 0x440 */ > > > > > > reg =3D <0x10 4>; > > > > > > }; > > > > > > > > > > > > - eth_mac1: mac-address@90 { > > > > > > + eth_mac1: mac-address@90 { /* 0= x640 */ > > > > > > reg =3D <0x90 6>; > > > > > > }; > > > > > > > > > > > > - eth_mac2: mac-address@96 { > > > > > > + eth_mac2: mac-address@96 { /* 0= x658 */ > > > > > > reg =3D <0x96 6>; > > > > > > }; > > > > > > + > > > > > > + tmu_calib: calib@264 { /* 0xd90= -0xdc0 */ > > > > > > + reg =3D <0x264 0x10>; > > > > > > + }; > > > > > > }; > > > > > > > > > > > > - anatop: anatop@30360000 { > > > > > > - compatible =3D "fsl,imx8mp-anat= op", "fsl,imx8mm-anatop", > > > > > > - "syscon"; > > > > > > + anatop: clock-controller@30360000 { > > > > > > + compatible =3D "fsl,imx8mp-anat= op", "fsl,imx8mm-anatop"; > > > > > > reg =3D <0x30360000 0x10000>; > > > > > > + #clock-cells =3D <1>; > > > > > > }; > > > > > > > > > > > > snvs: snvs@30370000 { > > > > > > @@ -523,6 +543,7 @@ > > > > > > compatible =3D "fsl,imx8mp-gpc"= ; > > > > > > reg =3D <0x303a0000 0x1000>; > > > > > > interrupt-parent =3D <&gic>; > > > > > > + interrupts =3D ; > > > > > > interrupt-controller; > > > > > > #interrupt-cells =3D <3>; > > > > > > > > > > > > @@ -589,7 +610,7 @@ > > > > > > reg =3D ; > > > > > > }; > > > > > > > > > > > > - pgc_hsiomix: power-doma= ins@17 { > > > > > > + pgc_hsiomix: power-doma= in@17 { > > > > > > #power-domain-c= ells =3D <0>; > > > > > > reg =3D ; > > > > > > clocks =3D <&cl= k IMX8MP_CLK_HSIO_AXI>, > > > > > > @@ -631,6 +652,14 @@ > > > > > > reg =3D ; > > > > > > clocks =3D <&cl= k IMX8MP_CLK_VPU_VC8KE_ROOT>; > > > > > > }; > > > > > > + > > > > > > + pgc_mlmix: power-domain= @24 { > > > > > > + #power-domain-c= ells =3D <0>; > > > > > > + reg =3D ; > > > > > > + clocks =3D <&cl= k IMX8MP_CLK_ML_AXI>, > > > > > > + <&clk = IMX8MP_CLK_ML_AHB>, > > > > > > + <&clk = IMX8MP_CLK_NPU_ROOT>; > > > > > > + }; > > > > > > }; > > > > > > }; > > > > > > }; > > > > > > @@ -702,112 +731,129 @@ > > > > > > #size-cells =3D <1>; > > > > > > ranges; > > > > > > > > > > > > - ecspi1: spi@30820000 { > > > > > > + spba-bus@30800000 { > > > > > > + compatible =3D "fsl,spba-bus", = "simple-bus"; > > > > > > + reg =3D <0x30800000 0x100000>; > > > > > > #address-cells =3D <1>; > > > > > > - #size-cells =3D <0>; > > > > > > - compatible =3D "fsl,imx8mp-ecsp= i", "fsl,imx51-ecspi"; > > > > > > - reg =3D <0x30820000 0x10000>; > > > > > > - interrupts =3D ; > > > > > > - clocks =3D <&clk IMX8MP_CLK_ECS= PI1_ROOT>, > > > > > > - <&clk IMX8MP_CLK_ECSPI= 1_ROOT>; > > > > > > - clock-names =3D "ipg", "per"; > > > > > > - dmas =3D <&sdma1 0 7 1>, <&sdma= 1 1 7 2>; > > > > > > - dma-names =3D "rx", "tx"; > > > > > > - status =3D "disabled"; > > > > > > - }; > > > > > > + #size-cells =3D <1>; > > > > > > + ranges; > > > > > > > > > > > > - ecspi2: spi@30830000 { > > > > > > - #address-cells =3D <1>; > > > > > > - #size-cells =3D <0>; > > > > > > - compatible =3D "fsl,imx8mp-ecsp= i", "fsl,imx51-ecspi"; > > > > > > - reg =3D <0x30830000 0x10000>; > > > > > > - interrupts =3D ; > > > > > > - clocks =3D <&clk IMX8MP_CLK_ECS= PI2_ROOT>, > > > > > > - <&clk IMX8MP_CLK_ECSPI= 2_ROOT>; > > > > > > - clock-names =3D "ipg", "per"; > > > > > > - dmas =3D <&sdma1 2 7 1>, <&sdma= 1 3 7 2>; > > > > > > - dma-names =3D "rx", "tx"; > > > > > > - status =3D "disabled"; > > > > > > - }; > > > > > > + ecspi1: spi@30820000 { > > > > > > + #address-cells =3D <1>; > > > > > > + #size-cells =3D <0>; > > > > > > + compatible =3D "fsl,imx= 8mp-ecspi", "fsl,imx6ul-ecspi"; > > > > > > + reg =3D <0x30820000 0x1= 0000>; > > > > > > + interrupts =3D ; > > > > > > + clocks =3D <&clk IMX8MP= _CLK_ECSPI1_ROOT>, > > > > > > + <&clk IMX8MP_C= LK_ECSPI1_ROOT>; > > > > > > + clock-names =3D "ipg", = "per"; > > > > > > + assigned-clock-rates = =3D <80000000>; > > > > > > + assigned-clocks =3D <&c= lk IMX8MP_CLK_ECSPI1>; > > > > > > + assigned-clock-parents = =3D <&clk IMX8MP_SYS_PLL1_800M>; > > > > > > + dmas =3D <&sdma1 0 7 1>= , <&sdma1 1 7 2>; > > > > > > + dma-names =3D "rx", "tx= "; > > > > > > + status =3D "disabled"; > > > > > > + }; > > > > > > > > > > > > - ecspi3: spi@30840000 { > > > > > > - #address-cells =3D <1>; > > > > > > - #size-cells =3D <0>; > > > > > > - compatible =3D "fsl,imx8mp-ecsp= i", "fsl,imx51-ecspi"; > > > > > > - reg =3D <0x30840000 0x10000>; > > > > > > - interrupts =3D ; > > > > > > - clocks =3D <&clk IMX8MP_CLK_ECS= PI3_ROOT>, > > > > > > - <&clk IMX8MP_CLK_ECSPI= 3_ROOT>; > > > > > > - clock-names =3D "ipg", "per"; > > > > > > - dmas =3D <&sdma1 4 7 1>, <&sdma= 1 5 7 2>; > > > > > > - dma-names =3D "rx", "tx"; > > > > > > - status =3D "disabled"; > > > > > > - }; > > > > > > + ecspi2: spi@30830000 { > > > > > > + #address-cells =3D <1>; > > > > > > + #size-cells =3D <0>; > > > > > > + compatible =3D "fsl,imx= 8mp-ecspi", "fsl,imx6ul-ecspi"; > > > > > > + reg =3D <0x30830000 0x1= 0000>; > > > > > > + interrupts =3D ; > > > > > > + clocks =3D <&clk IMX8MP= _CLK_ECSPI2_ROOT>, > > > > > > + <&clk IMX8MP_C= LK_ECSPI2_ROOT>; > > > > > > + clock-names =3D "ipg", = "per"; > > > > > > + assigned-clock-rates = =3D <80000000>; > > > > > > + assigned-clocks =3D <&c= lk IMX8MP_CLK_ECSPI2>; > > > > > > + assigned-clock-parents = =3D <&clk IMX8MP_SYS_PLL1_800M>; > > > > > > + dmas =3D <&sdma1 2 7 1>= , <&sdma1 3 7 2>; > > > > > > + dma-names =3D "rx", "tx= "; > > > > > > + status =3D "disabled"; > > > > > > + }; > > > > > > > > > > > > - uart1: serial@30860000 { > > > > > > - compatible =3D "fsl,imx8mp-uart= ", "fsl,imx6q-uart"; > > > > > > - reg =3D <0x30860000 0x10000>; > > > > > > - interrupts =3D ; > > > > > > - clocks =3D <&clk IMX8MP_CLK_UAR= T1_ROOT>, > > > > > > - <&clk IMX8MP_CLK_UART1= _ROOT>; > > > > > > - clock-names =3D "ipg", "per"; > > > > > > - dmas =3D <&sdma1 22 4 0>, <&sdm= a1 23 4 0>; > > > > > > - dma-names =3D "rx", "tx"; > > > > > > - status =3D "disabled"; > > > > > > - }; > > > > > > + ecspi3: spi@30840000 { > > > > > > + #address-cells =3D <1>; > > > > > > + #size-cells =3D <0>; > > > > > > + compatible =3D "fsl,imx= 8mp-ecspi", "fsl,imx6ul-ecspi"; > > > > > > + reg =3D <0x30840000 0x1= 0000>; > > > > > > + interrupts =3D ; > > > > > > + clocks =3D <&clk IMX8MP= _CLK_ECSPI3_ROOT>, > > > > > > + <&clk IMX8MP_C= LK_ECSPI3_ROOT>; > > > > > > + clock-names =3D "ipg", = "per"; > > > > > > + assigned-clock-rates = =3D <80000000>; > > > > > > + assigned-clocks =3D <&c= lk IMX8MP_CLK_ECSPI3>; > > > > > > + assigned-clock-parents = =3D <&clk IMX8MP_SYS_PLL1_800M>; > > > > > > + dmas =3D <&sdma1 4 7 1>= , <&sdma1 5 7 2>; > > > > > > + dma-names =3D "rx", "tx= "; > > > > > > + status =3D "disabled"; > > > > > > + }; > > > > > > > > > > > > - uart3: serial@30880000 { > > > > > > - compatible =3D "fsl,imx8mp-uart= ", "fsl,imx6q-uart"; > > > > > > - reg =3D <0x30880000 0x10000>; > > > > > > - interrupts =3D ; > > > > > > - clocks =3D <&clk IMX8MP_CLK_UAR= T3_ROOT>, > > > > > > - <&clk IMX8MP_CLK_UART3= _ROOT>; > > > > > > - clock-names =3D "ipg", "per"; > > > > > > - dmas =3D <&sdma1 26 4 0>, <&sdm= a1 27 4 0>; > > > > > > - dma-names =3D "rx", "tx"; > > > > > > - status =3D "disabled"; > > > > > > - }; > > > > > > + uart1: serial@30860000 { > > > > > > + compatible =3D "fsl,imx= 8mp-uart", "fsl,imx6q-uart"; > > > > > > + reg =3D <0x30860000 0x1= 0000>; > > > > > > + interrupts =3D ; > > > > > > + clocks =3D <&clk IMX8MP= _CLK_UART1_ROOT>, > > > > > > + <&clk IMX8MP_C= LK_UART1_ROOT>; > > > > > > + clock-names =3D "ipg", = "per"; > > > > > > + dmas =3D <&sdma1 22 4 0= >, <&sdma1 23 4 0>; > > > > > > + dma-names =3D "rx", "tx= "; > > > > > > + status =3D "disabled"; > > > > > > + }; > > > > > > > > > > > > - uart2: serial@30890000 { > > > > > > - compatible =3D "fsl,imx8mp-uart= ", "fsl,imx6q-uart"; > > > > > > - reg =3D <0x30890000 0x10000>; > > > > > > - interrupts =3D ; > > > > > > - clocks =3D <&clk IMX8MP_CLK_UAR= T2_ROOT>, > > > > > > - <&clk IMX8MP_CLK_UART2= _ROOT>; > > > > > > - clock-names =3D "ipg", "per"; > > > > > > - dmas =3D <&sdma1 24 4 0>, <&sdm= a1 25 4 0>; > > > > > > - dma-names =3D "rx", "tx"; > > > > > > - status =3D "disabled"; > > > > > > - }; > > > > > > + uart3: serial@30880000 { > > > > > > + compatible =3D "fsl,imx= 8mp-uart", "fsl,imx6q-uart"; > > > > > > + reg =3D <0x30880000 0x1= 0000>; > > > > > > + interrupts =3D ; > > > > > > + clocks =3D <&clk IMX8MP= _CLK_UART3_ROOT>, > > > > > > + <&clk IMX8MP_C= LK_UART3_ROOT>; > > > > > > + clock-names =3D "ipg", = "per"; > > > > > > + dmas =3D <&sdma1 26 4 0= >, <&sdma1 27 4 0>; > > > > > > + dma-names =3D "rx", "tx= "; > > > > > > + status =3D "disabled"; > > > > > > + }; > > > > > > > > > > > > - flexcan1: can@308c0000 { > > > > > > - compatible =3D "fsl,imx8mp-flex= can"; > > > > > > - reg =3D <0x308c0000 0x10000>; > > > > > > - interrupts =3D ; > > > > > > - clocks =3D <&clk IMX8MP_CLK_IPG= _ROOT>, > > > > > > - <&clk IMX8MP_CLK_CAN1_= ROOT>; > > > > > > - clock-names =3D "ipg", "per"; > > > > > > - assigned-clocks =3D <&clk IMX8M= P_CLK_CAN1>; > > > > > > - assigned-clock-parents =3D <&cl= k IMX8MP_SYS_PLL1_40M>; > > > > > > - assigned-clock-rates =3D <40000= 000>; > > > > > > - fsl,clk-source =3D /bits/ 8 <0>= ; > > > > > > - fsl,stop-mode =3D <&gpr 0x10 4>= ; > > > > > > - status =3D "disabled"; > > > > > > - }; > > > > > > + uart2: serial@30890000 { > > > > > > + compatible =3D "fsl,imx= 8mp-uart", "fsl,imx6q-uart"; > > > > > > + reg =3D <0x30890000 0x1= 0000>; > > > > > > + interrupts =3D ; > > > > > > + clocks =3D <&clk IMX8MP= _CLK_UART2_ROOT>, > > > > > > + <&clk IMX8MP_C= LK_UART2_ROOT>; > > > > > > + clock-names =3D "ipg", = "per"; > > > > > > + dmas =3D <&sdma1 24 4 0= >, <&sdma1 25 4 0>; > > > > > > + dma-names =3D "rx", "tx= "; > > > > > > + status =3D "disabled"; > > > > > > + }; > > > > > > > > > > > > - flexcan2: can@308d0000 { > > > > > > - compatible =3D "fsl,imx8mp-flex= can"; > > > > > > - reg =3D <0x308d0000 0x10000>; > > > > > > - interrupts =3D ; > > > > > > - clocks =3D <&clk IMX8MP_CLK_IPG= _ROOT>, > > > > > > - <&clk IMX8MP_CLK_CAN2_= ROOT>; > > > > > > - clock-names =3D "ipg", "per"; > > > > > > - assigned-clocks =3D <&clk IMX8M= P_CLK_CAN2>; > > > > > > - assigned-clock-parents =3D <&cl= k IMX8MP_SYS_PLL1_40M>; > > > > > > - assigned-clock-rates =3D <40000= 000>; > > > > > > - fsl,clk-source =3D /bits/ 8 <0>= ; > > > > > > - fsl,stop-mode =3D <&gpr 0x10 5>= ; > > > > > > - status =3D "disabled"; > > > > > > + flexcan1: can@308c0000 { > > > > > > + compatible =3D "fsl,imx= 8mp-flexcan"; > > > > > > + reg =3D <0x308c0000 0x1= 0000>; > > > > > > + interrupts =3D ; > > > > > > + clocks =3D <&clk IMX8MP= _CLK_IPG_ROOT>, > > > > > > + <&clk IMX8MP_C= LK_CAN1_ROOT>; > > > > > > + clock-names =3D "ipg", = "per"; > > > > > > + assigned-clocks =3D <&c= lk IMX8MP_CLK_CAN1>; > > > > > > + assigned-clock-parents = =3D <&clk IMX8MP_SYS_PLL1_40M>; > > > > > > + assigned-clock-rates = =3D <40000000>; > > > > > > + fsl,clk-source =3D /bit= s/ 8 <0>; > > > > > > + fsl,stop-mode =3D <&gpr= 0x10 4>; > > > > > > + status =3D "disabled"; > > > > > > + }; > > > > > > + > > > > > > + flexcan2: can@308d0000 { > > > > > > + compatible =3D "fsl,imx= 8mp-flexcan"; > > > > > > + reg =3D <0x308d0000 0x1= 0000>; > > > > > > + interrupts =3D ; > > > > > > + clocks =3D <&clk IMX8MP= _CLK_IPG_ROOT>, > > > > > > + <&clk IMX8MP_C= LK_CAN2_ROOT>; > > > > > > + clock-names =3D "ipg", = "per"; > > > > > > + assigned-clocks =3D <&c= lk IMX8MP_CLK_CAN2>; > > > > > > + assigned-clock-parents = =3D <&clk IMX8MP_SYS_PLL1_40M>; > > > > > > + assigned-clock-rates = =3D <40000000>; > > > > > > + fsl,clk-source =3D /bit= s/ 8 <0>; > > > > > > + fsl,stop-mode =3D <&gpr= 0x10 5>; > > > > > > + status =3D "disabled"; > > > > > > + }; > > > > > > }; > > > > > > > > > > > > crypto: crypto@30900000 { > > > > > > @@ -1063,11 +1109,11 @@ > > > > > > noc_opp_table: opp-table { > > > > > > compatible =3D "operating-point= s-v2"; > > > > > > > > > > > > - opp-200M { > > > > > > + opp-200000000 { > > > > > > opp-hz =3D /bits/ 64 <2= 00000000>; > > > > > > }; > > > > > > > > > > > > - opp-1000M { > > > > > > + opp-1000000000 { > > > > > > opp-hz =3D /bits/ 64 <1= 000000000>; > > > > > > }; > > > > > > }; > > > > > > @@ -1080,10 +1126,35 @@ > > > > > > #size-cells =3D <1>; > > > > > > ranges; > > > > > > > > > > > > + lcdif2: display-controller@32e90000 { > > > > > > + compatible =3D "fsl,imx8mp-lcdi= f"; > > > > > > + reg =3D <0x32e90000 0x10000>; > > > > > > + interrupts =3D ; > > > > > > + clocks =3D <&clk IMX8MP_CLK_MED= IA_DISP2_PIX_ROOT>, > > > > > > + <&clk IMX8MP_CLK_MEDIA= _APB_ROOT>, > > > > > > + <&clk IMX8MP_CLK_MEDIA= _AXI_ROOT>; > > > > > > + clock-names =3D "pix", "axi", "= disp_axi"; > > > > > > + assigned-clocks =3D <&clk IMX8M= P_CLK_MEDIA_DISP2_PIX>, > > > > > > + <&clk IMX8MP_= VIDEO_PLL1>; > > > > > > + assigned-clock-parents =3D <&cl= k IMX8MP_VIDEO_PLL1_OUT>, > > > > > > + <&clk = IMX8MP_VIDEO_PLL1_REF_SEL>; > > > > > > + assigned-clock-rates =3D <0>, <= 1039500000>; > > > > > > + power-domains =3D <&media_blk_c= trl IMX8MP_MEDIABLK_PD_LCDIF_2>; > > > > > > + status =3D "disabled"; > > > > > > + > > > > > > + port { > > > > > > + lcdif2_to_ldb: endpoint= { > > > > > > + remote-endpoint= =3D <&ldb_from_lcdif2>; > > > > > > + }; > > > > > > + }; > > > > > > + }; > > > > > > + > > > > > > media_blk_ctrl: blk-ctrl@32ec0000 { > > > > > > compatible =3D "fsl,imx8mp-medi= a-blk-ctrl", > > > > > > - "syscon"; > > > > > > + "simple-bus", "sys= con"; > > > > > > reg =3D <0x32ec0000 0x10000>; > > > > > > + #address-cells =3D <1>; > > > > > > + #size-cells =3D <1>; > > > > > > power-domains =3D <&pgc_mediami= x>, > > > > > > <&pgc_mipi_phy1= >, > > > > > > <&pgc_mipi_phy1= >, > > > > > > @@ -1128,6 +1199,44 @@ > > > > > > assigned-clock-rates =3D <50000= 0000>, <200000000>; > > > > > > > > > > > > #power-domain-cells =3D <1>; > > > > > > + > > > > > > + lvds_bridge: bridge@5c { > > > > > > + compatible =3D "fsl,imx= 8mp-ldb"; > > > > > > + clocks =3D <&clk IMX8MP= _CLK_MEDIA_LDB>; > > > > > > + clock-names =3D "ldb"; > > > > > > + reg =3D <0x5c 0x4>, <0x= 128 0x4>; > > > > > > + reg-names =3D "ldb", "l= vds"; > > > > > > + assigned-clocks =3D <&c= lk IMX8MP_CLK_MEDIA_LDB>; > > > > > > + assigned-clock-parents = =3D <&clk IMX8MP_VIDEO_PLL1_OUT>; > > > > > > + status =3D "disabled"; > > > > > > + > > > > > > + ports { > > > > > > + #address-cells = =3D <1>; > > > > > > + #size-cells =3D= <0>; > > > > > > + > > > > > > + port@0 { > > > > > > + reg =3D= <0>; > > > > > > + > > > > > > + ldb_fro= m_lcdif2: endpoint { > > > > > > + = remote-endpoint =3D <&lcdif2_to_ldb>; > > > > > > + }; > > > > > > + }; > > > > > > + > > > > > > + port@1 { > > > > > > + reg =3D= <1>; > > > > > > + > > > > > > + ldb_lvd= s_ch0: endpoint { > > > > > > + }; > > > > > > + }; > > > > > > + > > > > > > + port@2 { > > > > > > + reg =3D= <2>; > > > > > > + > > > > > > + ldb_lvd= s_ch1: endpoint { > > > > > > + }; > > > > > > + }; > > > > > > + }; > > > > > > + }; > > > > > > }; > > > > > > > > > > > > pcie_phy: pcie-phy@32f00000 { > > > > > > @@ -1158,6 +1267,7 @@ > > > > > > <&noc IMX8MP_IC= M_PCIE &noc IMX8MP_ICN_HSIO>; > > > > > > interconnect-names =3D "noc-pci= e", "usb1", "usb2", "pcie"; > > > > > > #power-domain-cells =3D <1>; > > > > > > + #clock-cells =3D <0>; > > > > > > }; > > > > > > }; > > > > > > > > > > > > @@ -1165,6 +1275,13 @@ > > > > > > compatible =3D "fsl,imx8mp-pcie"; > > > > > > reg =3D <0x33800000 0x400000>, <0x1ff00= 000 0x80000>; > > > > > > reg-names =3D "dbi", "config"; > > > > > > + clocks =3D <&clk IMX8MP_CLK_HSIO_ROOT>, > > > > > > + <&clk IMX8MP_CLK_HSIO_AXI>, > > > > > > + <&clk IMX8MP_CLK_PCIE_ROOT>; > > > > > > + clock-names =3D "pcie", "pcie_bus", "pc= ie_aux"; > > > > > > + assigned-clocks =3D <&clk IMX8MP_CLK_PC= IE_AUX>; > > > > > > + assigned-clock-rates =3D <10000000>; > > > > > > + assigned-clock-parents =3D <&clk IMX8MP= _SYS_PLL2_50M>; > > > > > > #address-cells =3D <3>; > > > > > > #size-cells =3D <2>; > > > > > > device_type =3D "pci"; > > > > > > @@ -1223,6 +1340,28 @@ > > > > > > power-domains =3D <&pgc_gpu2d>; > > > > > > }; > > > > > > > > > > > > + vpu_g1: video-codec@38300000 { > > > > > > + compatible =3D "nxp,imx8mm-vpu-g1"; > > > > > > + reg =3D <0x38300000 0x10000>; > > > > > > + interrupts =3D ; > > > > > > + clocks =3D <&clk IMX8MP_CLK_VPU_G1_ROOT= >; > > > > > > + assigned-clocks =3D <&clk IMX8MP_CLK_VP= U_G1>; > > > > > > + assigned-clock-parents =3D <&clk IMX8MP= _VPU_PLL_OUT>; > > > > > > + assigned-clock-rates =3D <600000000>; > > > > > > + power-domains =3D <&vpumix_blk_ctrl IMX= 8MP_VPUBLK_PD_G1>; > > > > > > + }; > > > > > > + > > > > > > + vpu_g2: video-codec@38310000 { > > > > > > + compatible =3D "nxp,imx8mq-vpu-g2"; > > > > > > + reg =3D <0x38310000 0x10000>; > > > > > > + interrupts =3D ; > > > > > > + clocks =3D <&clk IMX8MP_CLK_VPU_G2_ROOT= >; > > > > > > + assigned-clocks =3D <&clk IMX8MP_CLK_VP= U_G2>; > > > > > > + assigned-clock-parents =3D <&clk IMX8MP= _SYS_PLL2_1000M>; > > > > > > + assigned-clock-rates =3D <500000000>; > > > > > > + power-domains =3D <&vpumix_blk_ctrl IMX= 8MP_VPUBLK_PD_G2>; > > > > > > + }; > > > > > > + > > > > > > vpumix_blk_ctrl: blk-ctrl@38330000 { > > > > > > compatible =3D "fsl,imx8mp-vpu-blk-ctrl= ", "syscon"; > > > > > > reg =3D <0x38330000 0x100>; > > > > > > @@ -1234,6 +1373,9 @@ > > > > > > <&clk IMX8MP_CLK_VPU_G2_ROOT>, > > > > > > <&clk IMX8MP_CLK_VPU_VC8KE_ROO= T>; > > > > > > clock-names =3D "g1", "g2", "vc8000e"; > > > > > > + assigned-clocks =3D <&clk IMX8MP_CLK_VP= U_BUS>, <&clk IMX8MP_VPU_PLL>; > > > > > > + assigned-clock-parents =3D <&clk IMX8MP= _VPU_PLL_OUT>; > > > > > > + assigned-clock-rates =3D <600000000>, <= 600000000>; > > > > > > interconnects =3D <&noc IMX8MP_ICM_VPU_= G1 &noc IMX8MP_ICN_VIDEO>, > > > > > > <&noc IMX8MP_ICM_VPU_G2= &noc IMX8MP_ICN_VIDEO>, > > > > > > <&noc IMX8MP_ICM_VPU_H1= &noc IMX8MP_ICN_VIDEO>; > > > > > > @@ -1279,7 +1421,7 @@ > > > > > > reg =3D <0x32f10100 0x8>, > > > > > > <0x381f0000 0x20>; > > > > > > clocks =3D <&clk IMX8MP_CLK_HSIO_ROOT>, > > > > > > - <&clk IMX8MP_CLK_USB_ROOT>; > > > > > > + <&clk IMX8MP_CLK_USB_SUSP>; > > > > > > clock-names =3D "hsio", "suspend"; > > > > > > interrupts =3D ; > > > > > > power-domains =3D <&hsio_blk_ctrl IMX8M= P_HSIOBLK_PD_USB>; > > > > > > @@ -1292,9 +1434,9 @@ > > > > > > usb_dwc3_0: usb@38100000 { > > > > > > compatible =3D "snps,dwc3"; > > > > > > reg =3D <0x38100000 0x10000>; > > > > > > - clocks =3D <&clk IMX8MP_CLK_HSI= O_AXI>, > > > > > > + clocks =3D <&clk IMX8MP_CLK_USB= _ROOT>, > > > > > > <&clk IMX8MP_CLK_USB_C= ORE_REF>, > > > > > > - <&clk IMX8MP_CLK_USB_R= OOT>; > > > > > > + <&clk IMX8MP_CLK_USB_S= USP>; > > > > > > clock-names =3D "bus_early", "r= ef", "suspend"; > > > > > > interrupts =3D ; > > > > > > phys =3D <&usb3_phy0>, <&usb3_p= hy0>; > > > > > > @@ -1321,7 +1463,7 @@ > > > > > > reg =3D <0x32f10108 0x8>, > > > > > > <0x382f0000 0x20>; > > > > > > clocks =3D <&clk IMX8MP_CLK_HSIO_ROOT>, > > > > > > - <&clk IMX8MP_CLK_USB_ROOT>; > > > > > > + <&clk IMX8MP_CLK_USB_SUSP>; > > > > > > clock-names =3D "hsio", "suspend"; > > > > > > interrupts =3D ; > > > > > > power-domains =3D <&hsio_blk_ctrl IMX8M= P_HSIOBLK_PD_USB>; > > > > > > @@ -1334,9 +1476,9 @@ > > > > > > usb_dwc3_1: usb@38200000 { > > > > > > compatible =3D "snps,dwc3"; > > > > > > reg =3D <0x38200000 0x10000>; > > > > > > - clocks =3D <&clk IMX8MP_CLK_HSI= O_AXI>, > > > > > > + clocks =3D <&clk IMX8MP_CLK_USB= _ROOT>, > > > > > > <&clk IMX8MP_CLK_USB_C= ORE_REF>, > > > > > > - <&clk IMX8MP_CLK_USB_R= OOT>; > > > > > > + <&clk IMX8MP_CLK_USB_S= USP>; > > > > > > clock-names =3D "bus_early", "r= ef", "suspend"; > > > > > > interrupts =3D ; > > > > > > phys =3D <&usb3_phy1>, <&usb3_p= hy1>; > > > > > > diff --git a/include/dt-bindings/clock/imx8mp-clock.h b/include= /dt-bindings/clock/imx8mp-clock.h > > > > > > index 9d5cc2ddde89..3f28ce685f41 100644 > > > > > > --- a/include/dt-bindings/clock/imx8mp-clock.h > > > > > > +++ b/include/dt-bindings/clock/imx8mp-clock.h > > > > > > @@ -324,8 +324,18 @@ > > > > > > #define IMX8MP_CLK_CLKOUT2_SEL 317 > > > > > > #define IMX8MP_CLK_CLKOUT2_DIV 318 > > > > > > #define IMX8MP_CLK_CLKOUT2 319 > > > > > > - > > > > > > -#define IMX8MP_CLK_END 320 > > > > > > +#define IMX8MP_CLK_USB_SUSP 320 > > > > > > +#define IMX8MP_CLK_AUDIO_AHB_ROOT IMX8MP_CLK_AUDI= O_ROOT > > > > > > +#define IMX8MP_CLK_AUDIO_AXI_ROOT 321 > > > > > > +#define IMX8MP_CLK_SAI1_ROOT 322 > > > > > > +#define IMX8MP_CLK_SAI2_ROOT 323 > > > > > > +#define IMX8MP_CLK_SAI3_ROOT 324 > > > > > > +#define IMX8MP_CLK_SAI5_ROOT 325 > > > > > > +#define IMX8MP_CLK_SAI6_ROOT 326 > > > > > > +#define IMX8MP_CLK_SAI7_ROOT 327 > > > > > > +#define IMX8MP_CLK_PDM_ROOT 328 > > > > > > +#define IMX8MP_CLK_MEDIA_LDB_ROOT 329 > > > > > > +#define IMX8MP_CLK_END 330 > > > > > > > > > > > > #define IMX8MP_CLK_AUDIOMIX_SAI1_IPG 0 > > > > > > #define IMX8MP_CLK_AUDIOMIX_SAI1_MCLK1 1 > > > > > > -- > > > > > > 2.34.1 > > > > > > > > > > > > > > > > Tested-by: Tim Harvey #imx8mp-venice-gw74= xx > > > > > > > > Fabio, > > > > > > > > Apparently I didn't do a very good job of testing this. This patch = is > > > > causing imx8mp-venice-* and imx8mp-evk boards to no longer boot wit= h > > > > no SPL banner. The specific change that causes breakage is the one > > > > that encapsulates the spi/uart/flexcan children with > > > > spba-bus@30800000. > > > > > > The SPI, UART, and Flexcan are part of the spba-bus. > > > > > > We'll need to add the spba bus to imx8mp-u-boot.dtsi. Since it had no > > > node name, it'll have to fall under aip3. > > > > > > Try this: > > > > > > diff --git a/arch/arm/dts/imx8mp-u-boot.dtsi b/arch/arm/dts/imx8mp-u-= boot.dtsi > > > index 18d1728e1d..0e6811b129 100644 > > > --- a/arch/arm/dts/imx8mp-u-boot.dtsi > > > +++ b/arch/arm/dts/imx8mp-u-boot.dtsi > > > @@ -44,6 +44,10 @@ > > > > > > &aips3 { > > > bootph-pre-ram; > > > + > > > + spba-bus@30800000 { > > > + bootph-pre-ram; > > > + }; > > > }; > > > > > > &iomuxc { > > > > > > > Adam, > > > > Yup... that's it! Thanks. Want to send a patch or want me to do it? > > > > Actually Fabio I think you should re-submit this patch with the > required change to imx8mp-u-boot.dtsi included? I was just about to say the same thing. adam > > Tim