From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 107A6ECAAD4 for ; Mon, 29 Aug 2022 19:42:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229813AbiH2TmT (ORCPT ); Mon, 29 Aug 2022 15:42:19 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39366 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229450AbiH2TmS (ORCPT ); Mon, 29 Aug 2022 15:42:18 -0400 Received: from mail-ej1-x62d.google.com (mail-ej1-x62d.google.com [IPv6:2a00:1450:4864:20::62d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 76FB47332E for ; Mon, 29 Aug 2022 12:42:13 -0700 (PDT) Received: by mail-ej1-x62d.google.com with SMTP id u9so17815815ejy.5 for ; Mon, 29 Aug 2022 12:42:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc; bh=6cTy6keoa6b646vo8Js7s0CIFmnj1Q2o4aqvygA4K3o=; b=DFxjElR5msx7cZgIJRZPd43/YEwRZgLSkWluSuIlAaCJTw3xRblAbfxzDvQ6842Ix7 lJM5BC5VPvtKp9PDOjeXt1Vnmzjfx095NvtvDOLSh1q2LsieFFZt2W6oFuEFqk/MDV1P 9s0c1LvOjVKHDYYmeTs18q9039vwHM10Xbmk2o/kXvKcP2Y7spxlh9mSz7JgxBqRS1m/ mutRWNbZ7eQO6MGyGmXHBTVYPnJ9YHLX6xtlNC7geBZU8Kw2NAHci3irYScaPsiQpzjN Lrh82iQHzutGhmJaFb/BuuC7s54OFTIpiFPEVac8/EJghj/RPSjxFHLjcf3KvHYLs5Yl /GwQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc; bh=6cTy6keoa6b646vo8Js7s0CIFmnj1Q2o4aqvygA4K3o=; b=aS//FGz6KSDrsbiiQQsNuiW82cKkc3XGhVJo4UqCcpEa1wvbb7xRtUM1Nlhj16Ywg+ wNNsJthjA++5bn/DjXzP7qzVXHpI/V5e+ehtMpcBmkYUMPgA8F4fY9bEWZ3W4dM7943d zGL0ZWS/1+NIL66lY6gW6LNrhYevaTl1MPJuoRVDi2m9a3JWXfiMCIthkBKKFx19hTd4 ubJxOofBwc1auzQgY11phh3u+AZ+cfvaWDZ6w+gosKnp8xSyPQ2FFN0venR8H/vnL9G2 g7dz3XAncaJ4l+in3aOtWqIb65KVw8VAKvUAozhVVQTcRNdcv7STGMtavkg2Z0OsQke2 41oA== X-Gm-Message-State: ACgBeo1m7U5IAgbqc3NpJ5iscTyy+csEq4MxtmstbhhzkTBzht1/EgP7 9uzIn+GBc0ETj6we0dBH59CIpIlYzMGVcDtwLuk= X-Google-Smtp-Source: AA6agR7uH/lREQZQwl9H3i0GUO9N6GrUUJHUai+M6A9pycUtOdBDMUR87TRVuoIcQUVD/Y/8XtDbHmmiKYLJtrvlFIg= X-Received: by 2002:a17:907:87b0:b0:731:3dfd:bc8d with SMTP id qv48-20020a17090787b000b007313dfdbc8dmr14315550ejc.607.1661802131774; Mon, 29 Aug 2022 12:42:11 -0700 (PDT) MIME-Version: 1.0 References: <20220829184031.1863663-1-jagan@amarulasolutions.com> <20220829184031.1863663-8-jagan@amarulasolutions.com> In-Reply-To: <20220829184031.1863663-8-jagan@amarulasolutions.com> From: Adam Ford Date: Mon, 29 Aug 2022 14:42:00 -0500 Message-ID: Subject: Re: [PATCH v4 07/12] drm: bridge: samsung-dsim: Fix PLL_P (PMS_P) offset To: Jagan Teki Cc: Andrzej Hajda , Inki Dae , Marek Szyprowski , Joonyoung Shim , Seung-Woo Kim , Kyungmin Park , Frieder Schrempf , Fancy Fang , Tim Harvey , Michael Nazzareno Trimarchi , Neil Armstrong , Robert Foss , Laurent Pinchart , Tommaso Merciai , Marek Vasut , Matteo Lisi , dri-devel , linux-samsung-soc , arm-soc , NXP Linux Team , linux-amarula Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org On Mon, Aug 29, 2022 at 1:41 PM Jagan Teki wrote: > > The i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020 > with 13.7.10.1 Master PLL PMS Value setting Register mentioned PMS_P offset > range from BIT[18-13] and the upstream driver is using the same offset. > > However, offset 13 is not working on i.MX8M Mini platforms but downstream > NXP driver is using 14 [1] and it is working with i.MX8M Mini SoC. >From the line you highlighted in the link, the downstream NXP ones shows 13 if I'm reading it correctly. #define PLLCTRL_SET_P(x) REG_PUT(x, 18, 13) >From what I can tell the PMS calculation here needs to be updated for the Mini because the ranges of the FCO calculator are different. Took your series and tweaked it a bit [2] which changes a few settings, and the PMS calculator appears to more closely match the values I get from the NXP one. I think it could be further tweaked because p min and p_max also have changed. > > Not sure about whether it is reference manual documentation or something > else but this patch trusts the downstream code and fixes the PLL_P offset. > > [1] https://source.codeaurora.org/external/imx/linux-imx/tree/drivers/gpu/drm/bridge/sec-dsim.c?h=imx_5.4.47_2.2.0#n211 > [2] -https://github.com/aford173/linux/commit/a5fa184160ec9ea45a7546eaa0d8b8fc760cf3d9 > v4, v3, v2: > * none > > v1: > * updated commit message > * add downstream driver link > > Signed-off-by: Frieder Schrempf > Signed-off-by: Jagan Teki > --- > drivers/gpu/drm/bridge/samsung-dsim.c | 10 ++++++++-- > include/drm/bridge/samsung-dsim.h | 1 + > 2 files changed, 9 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/bridge/samsung-dsim.c b/drivers/gpu/drm/bridge/samsung-dsim.c > index b6883a6d4681..b6d17c0c9e58 100644 > --- a/drivers/gpu/drm/bridge/samsung-dsim.c > +++ b/drivers/gpu/drm/bridge/samsung-dsim.c > @@ -168,7 +168,7 @@ > /* DSIM_PLLCTRL */ > #define DSIM_FREQ_BAND(x) ((x) << 24) > #define DSIM_PLL_EN (1 << 23) > -#define DSIM_PLL_P(x) ((x) << 13) > +#define DSIM_PLL_P(x, offset) ((x) << (offset)) > #define DSIM_PLL_M(x) ((x) << 4) > #define DSIM_PLL_S(x) ((x) << 1) > > @@ -368,6 +368,7 @@ static const struct samsung_dsim_driver_data exynos3_dsi_driver_data = { > .max_freq = 1000, > .wait_for_reset = 1, > .num_bits_resol = 11, > + .pll_p_offset = 13, > .reg_values = reg_values, > .quirks = DSIM_QUIRK_PLAT_DATA, > }; > @@ -381,6 +382,7 @@ static const struct samsung_dsim_driver_data exynos4_dsi_driver_data = { > .max_freq = 1000, > .wait_for_reset = 1, > .num_bits_resol = 11, > + .pll_p_offset = 13, > .reg_values = reg_values, > .quirks = DSIM_QUIRK_PLAT_DATA, > }; > @@ -392,6 +394,7 @@ static const struct samsung_dsim_driver_data exynos5_dsi_driver_data = { > .max_freq = 1000, > .wait_for_reset = 1, > .num_bits_resol = 11, > + .pll_p_offset = 13, > .reg_values = reg_values, > .quirks = DSIM_QUIRK_PLAT_DATA, > }; > @@ -404,6 +407,7 @@ static const struct samsung_dsim_driver_data exynos5433_dsi_driver_data = { > .max_freq = 1500, > .wait_for_reset = 0, > .num_bits_resol = 12, > + .pll_p_offset = 13, > .reg_values = exynos5433_reg_values, > .quirks = DSIM_QUIRK_PLAT_DATA, > }; > @@ -416,6 +420,7 @@ static const struct samsung_dsim_driver_data exynos5422_dsi_driver_data = { > .max_freq = 1500, > .wait_for_reset = 1, > .num_bits_resol = 12, > + .pll_p_offset = 13, > .reg_values = exynos5422_reg_values, > .quirks = DSIM_QUIRK_PLAT_DATA, > }; > @@ -563,7 +568,8 @@ static unsigned long samsung_dsim_set_pll(struct samsung_dsim *dsi, > writel(driver_data->reg_values[PLL_TIMER], > dsi->reg_base + driver_data->plltmr_reg); > > - reg = DSIM_PLL_EN | DSIM_PLL_P(p) | DSIM_PLL_M(m) | DSIM_PLL_S(s); > + reg = DSIM_PLL_EN | DSIM_PLL_P(p, driver_data->pll_p_offset) | > + DSIM_PLL_M(m) | DSIM_PLL_S(s); > > if (driver_data->has_freqband) { > static const unsigned long freq_bands[] = { > diff --git a/include/drm/bridge/samsung-dsim.h b/include/drm/bridge/samsung-dsim.h > index e15fbfd49efe..95d3f89aec4f 100644 > --- a/include/drm/bridge/samsung-dsim.h > +++ b/include/drm/bridge/samsung-dsim.h > @@ -47,6 +47,7 @@ struct samsung_dsim_driver_data { > unsigned int max_freq; > unsigned int wait_for_reset; > unsigned int num_bits_resol; > + unsigned int pll_p_offset; > const unsigned int *reg_values; > enum samsung_dsim_quirks quirks; > }; > -- > 2.25.1 > From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E0C08ECAAD4 for ; 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charset="UTF-8" X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Marek Vasut , linux-samsung-soc , Laurent Pinchart , Joonyoung Shim , dri-devel , Neil Armstrong , Seung-Woo Kim , Tommaso Merciai , Frieder Schrempf , Kyungmin Park , Matteo Lisi , Robert Foss , Andrzej Hajda , NXP Linux Team , Fancy Fang , Michael Nazzareno Trimarchi , linux-amarula , arm-soc , Marek Szyprowski Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" On Mon, Aug 29, 2022 at 1:41 PM Jagan Teki wrote: > > The i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020 > with 13.7.10.1 Master PLL PMS Value setting Register mentioned PMS_P offset > range from BIT[18-13] and the upstream driver is using the same offset. > > However, offset 13 is not working on i.MX8M Mini platforms but downstream > NXP driver is using 14 [1] and it is working with i.MX8M Mini SoC. >From the line you highlighted in the link, the downstream NXP ones shows 13 if I'm reading it correctly. #define PLLCTRL_SET_P(x) REG_PUT(x, 18, 13) >From what I can tell the PMS calculation here needs to be updated for the Mini because the ranges of the FCO calculator are different. Took your series and tweaked it a bit [2] which changes a few settings, and the PMS calculator appears to more closely match the values I get from the NXP one. I think it could be further tweaked because p min and p_max also have changed. > > Not sure about whether it is reference manual documentation or something > else but this patch trusts the downstream code and fixes the PLL_P offset. > > [1] https://source.codeaurora.org/external/imx/linux-imx/tree/drivers/gpu/drm/bridge/sec-dsim.c?h=imx_5.4.47_2.2.0#n211 > [2] -https://github.com/aford173/linux/commit/a5fa184160ec9ea45a7546eaa0d8b8fc760cf3d9 > v4, v3, v2: > * none > > v1: > * updated commit message > * add downstream driver link > > Signed-off-by: Frieder Schrempf > Signed-off-by: Jagan Teki > --- > drivers/gpu/drm/bridge/samsung-dsim.c | 10 ++++++++-- > include/drm/bridge/samsung-dsim.h | 1 + > 2 files changed, 9 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/bridge/samsung-dsim.c b/drivers/gpu/drm/bridge/samsung-dsim.c > index b6883a6d4681..b6d17c0c9e58 100644 > --- a/drivers/gpu/drm/bridge/samsung-dsim.c > +++ b/drivers/gpu/drm/bridge/samsung-dsim.c > @@ -168,7 +168,7 @@ > /* DSIM_PLLCTRL */ > #define DSIM_FREQ_BAND(x) ((x) << 24) > #define DSIM_PLL_EN (1 << 23) > -#define DSIM_PLL_P(x) ((x) << 13) > +#define DSIM_PLL_P(x, offset) ((x) << (offset)) > #define DSIM_PLL_M(x) ((x) << 4) > #define DSIM_PLL_S(x) ((x) << 1) > > @@ -368,6 +368,7 @@ static const struct samsung_dsim_driver_data exynos3_dsi_driver_data = { > .max_freq = 1000, > .wait_for_reset = 1, > .num_bits_resol = 11, > + .pll_p_offset = 13, > .reg_values = reg_values, > .quirks = DSIM_QUIRK_PLAT_DATA, > }; > @@ -381,6 +382,7 @@ static const struct samsung_dsim_driver_data exynos4_dsi_driver_data = { > .max_freq = 1000, > .wait_for_reset = 1, > .num_bits_resol = 11, > + .pll_p_offset = 13, > .reg_values = reg_values, > .quirks = DSIM_QUIRK_PLAT_DATA, > }; > @@ -392,6 +394,7 @@ static const struct samsung_dsim_driver_data exynos5_dsi_driver_data = { > .max_freq = 1000, > .wait_for_reset = 1, > .num_bits_resol = 11, > + .pll_p_offset = 13, > .reg_values = reg_values, > .quirks = DSIM_QUIRK_PLAT_DATA, > }; > @@ -404,6 +407,7 @@ static const struct samsung_dsim_driver_data exynos5433_dsi_driver_data = { > .max_freq = 1500, > .wait_for_reset = 0, > .num_bits_resol = 12, > + .pll_p_offset = 13, > .reg_values = exynos5433_reg_values, > .quirks = DSIM_QUIRK_PLAT_DATA, > }; > @@ -416,6 +420,7 @@ static const struct samsung_dsim_driver_data exynos5422_dsi_driver_data = { > .max_freq = 1500, > .wait_for_reset = 1, > .num_bits_resol = 12, > + .pll_p_offset = 13, > .reg_values = exynos5422_reg_values, > .quirks = DSIM_QUIRK_PLAT_DATA, > }; > @@ -563,7 +568,8 @@ static unsigned long samsung_dsim_set_pll(struct samsung_dsim *dsi, > writel(driver_data->reg_values[PLL_TIMER], > dsi->reg_base + driver_data->plltmr_reg); > > - reg = DSIM_PLL_EN | DSIM_PLL_P(p) | DSIM_PLL_M(m) | DSIM_PLL_S(s); > + reg = DSIM_PLL_EN | DSIM_PLL_P(p, driver_data->pll_p_offset) | > + DSIM_PLL_M(m) | DSIM_PLL_S(s); > > if (driver_data->has_freqband) { > static const unsigned long freq_bands[] = { > diff --git a/include/drm/bridge/samsung-dsim.h b/include/drm/bridge/samsung-dsim.h > index e15fbfd49efe..95d3f89aec4f 100644 > --- a/include/drm/bridge/samsung-dsim.h > +++ b/include/drm/bridge/samsung-dsim.h > @@ -47,6 +47,7 @@ struct samsung_dsim_driver_data { > unsigned int max_freq; > unsigned int wait_for_reset; > unsigned int num_bits_resol; > + unsigned int pll_p_offset; > const unsigned int *reg_values; > enum samsung_dsim_quirks quirks; > }; > -- > 2.25.1 > From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B1558ECAAD4 for ; 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d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc; bh=6cTy6keoa6b646vo8Js7s0CIFmnj1Q2o4aqvygA4K3o=; b=yGDl+Hli9sMsdfgr5WitbWvDa4GfjcpfNyldr2MD1NrxOHFXYXun/TceykvSkMWofV VQiFyHGWHYuuKmHr/d0+CvkDbY5XnxeG3kc1AkBAh1D1e/mJcuPlSimIuZyaeW1pi5n9 sYTqjawSR1qjC3BrPmO8U2jvp9QJbyMkQYrABfJ1/VntiKFLTkemddjbKASujLbmWbkF Kb4fJkOiygYBAzPA6/f2LAEPDXoA39MAjWkd//GKZN4UyHeyhQXoGRIhCo7xPpT7+Nlw IBEu2zpAdyNqOh7RthddE90nikArz5oN3a4ohYhWmkG5OZlfEb/Ub2AjI8Rczx0fWeai TWzw== X-Gm-Message-State: ACgBeo1Ls8cC2L3SqCXsSAIvc658lEGaZy7Jiiy8MTylT+Va067m5ZKR jvovg8GC+ho3PWBQxSwC+g4ZFoyBVCOK+oUDLf4= X-Google-Smtp-Source: AA6agR7uH/lREQZQwl9H3i0GUO9N6GrUUJHUai+M6A9pycUtOdBDMUR87TRVuoIcQUVD/Y/8XtDbHmmiKYLJtrvlFIg= X-Received: by 2002:a17:907:87b0:b0:731:3dfd:bc8d with SMTP id qv48-20020a17090787b000b007313dfdbc8dmr14315550ejc.607.1661802131774; Mon, 29 Aug 2022 12:42:11 -0700 (PDT) MIME-Version: 1.0 References: <20220829184031.1863663-1-jagan@amarulasolutions.com> <20220829184031.1863663-8-jagan@amarulasolutions.com> In-Reply-To: <20220829184031.1863663-8-jagan@amarulasolutions.com> From: Adam Ford Date: Mon, 29 Aug 2022 14:42:00 -0500 Message-ID: Subject: Re: [PATCH v4 07/12] drm: bridge: samsung-dsim: Fix PLL_P (PMS_P) offset To: Jagan Teki Cc: Andrzej Hajda , Inki Dae , Marek Szyprowski , Joonyoung Shim , Seung-Woo Kim , Kyungmin Park , Frieder Schrempf , Fancy Fang , Tim Harvey , Michael Nazzareno Trimarchi , Neil Armstrong , Robert Foss , Laurent Pinchart , Tommaso Merciai , Marek Vasut , Matteo Lisi , dri-devel , linux-samsung-soc , arm-soc , NXP Linux Team , linux-amarula X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220829_124223_142370_F7C6917F X-CRM114-Status: GOOD ( 28.57 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Mon, Aug 29, 2022 at 1:41 PM Jagan Teki wrote: > > The i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020 > with 13.7.10.1 Master PLL PMS Value setting Register mentioned PMS_P offset > range from BIT[18-13] and the upstream driver is using the same offset. > > However, offset 13 is not working on i.MX8M Mini platforms but downstream > NXP driver is using 14 [1] and it is working with i.MX8M Mini SoC. >From the line you highlighted in the link, the downstream NXP ones shows 13 if I'm reading it correctly. #define PLLCTRL_SET_P(x) REG_PUT(x, 18, 13) >From what I can tell the PMS calculation here needs to be updated for the Mini because the ranges of the FCO calculator are different. Took your series and tweaked it a bit [2] which changes a few settings, and the PMS calculator appears to more closely match the values I get from the NXP one. I think it could be further tweaked because p min and p_max also have changed. > > Not sure about whether it is reference manual documentation or something > else but this patch trusts the downstream code and fixes the PLL_P offset. > > [1] https://source.codeaurora.org/external/imx/linux-imx/tree/drivers/gpu/drm/bridge/sec-dsim.c?h=imx_5.4.47_2.2.0#n211 > [2] -https://github.com/aford173/linux/commit/a5fa184160ec9ea45a7546eaa0d8b8fc760cf3d9 > v4, v3, v2: > * none > > v1: > * updated commit message > * add downstream driver link > > Signed-off-by: Frieder Schrempf > Signed-off-by: Jagan Teki > --- > drivers/gpu/drm/bridge/samsung-dsim.c | 10 ++++++++-- > include/drm/bridge/samsung-dsim.h | 1 + > 2 files changed, 9 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/bridge/samsung-dsim.c b/drivers/gpu/drm/bridge/samsung-dsim.c > index b6883a6d4681..b6d17c0c9e58 100644 > --- a/drivers/gpu/drm/bridge/samsung-dsim.c > +++ b/drivers/gpu/drm/bridge/samsung-dsim.c > @@ -168,7 +168,7 @@ > /* DSIM_PLLCTRL */ > #define DSIM_FREQ_BAND(x) ((x) << 24) > #define DSIM_PLL_EN (1 << 23) > -#define DSIM_PLL_P(x) ((x) << 13) > +#define DSIM_PLL_P(x, offset) ((x) << (offset)) > #define DSIM_PLL_M(x) ((x) << 4) > #define DSIM_PLL_S(x) ((x) << 1) > > @@ -368,6 +368,7 @@ static const struct samsung_dsim_driver_data exynos3_dsi_driver_data = { > .max_freq = 1000, > .wait_for_reset = 1, > .num_bits_resol = 11, > + .pll_p_offset = 13, > .reg_values = reg_values, > .quirks = DSIM_QUIRK_PLAT_DATA, > }; > @@ -381,6 +382,7 @@ static const struct samsung_dsim_driver_data exynos4_dsi_driver_data = { > .max_freq = 1000, > .wait_for_reset = 1, > .num_bits_resol = 11, > + .pll_p_offset = 13, > .reg_values = reg_values, > .quirks = DSIM_QUIRK_PLAT_DATA, > }; > @@ -392,6 +394,7 @@ static const struct samsung_dsim_driver_data exynos5_dsi_driver_data = { > .max_freq = 1000, > .wait_for_reset = 1, > .num_bits_resol = 11, > + .pll_p_offset = 13, > .reg_values = reg_values, > .quirks = DSIM_QUIRK_PLAT_DATA, > }; > @@ -404,6 +407,7 @@ static const struct samsung_dsim_driver_data exynos5433_dsi_driver_data = { > .max_freq = 1500, > .wait_for_reset = 0, > .num_bits_resol = 12, > + .pll_p_offset = 13, > .reg_values = exynos5433_reg_values, > .quirks = DSIM_QUIRK_PLAT_DATA, > }; > @@ -416,6 +420,7 @@ static const struct samsung_dsim_driver_data exynos5422_dsi_driver_data = { > .max_freq = 1500, > .wait_for_reset = 1, > .num_bits_resol = 12, > + .pll_p_offset = 13, > .reg_values = exynos5422_reg_values, > .quirks = DSIM_QUIRK_PLAT_DATA, > }; > @@ -563,7 +568,8 @@ static unsigned long samsung_dsim_set_pll(struct samsung_dsim *dsi, > writel(driver_data->reg_values[PLL_TIMER], > dsi->reg_base + driver_data->plltmr_reg); > > - reg = DSIM_PLL_EN | DSIM_PLL_P(p) | DSIM_PLL_M(m) | DSIM_PLL_S(s); > + reg = DSIM_PLL_EN | DSIM_PLL_P(p, driver_data->pll_p_offset) | > + DSIM_PLL_M(m) | DSIM_PLL_S(s); > > if (driver_data->has_freqband) { > static const unsigned long freq_bands[] = { > diff --git a/include/drm/bridge/samsung-dsim.h b/include/drm/bridge/samsung-dsim.h > index e15fbfd49efe..95d3f89aec4f 100644 > --- a/include/drm/bridge/samsung-dsim.h > +++ b/include/drm/bridge/samsung-dsim.h > @@ -47,6 +47,7 @@ struct samsung_dsim_driver_data { > unsigned int max_freq; > unsigned int wait_for_reset; > unsigned int num_bits_resol; > + unsigned int pll_p_offset; > const unsigned int *reg_values; > enum samsung_dsim_quirks quirks; > }; > -- > 2.25.1 > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel