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Thu, 27 Apr 2023 12:22:10 -0700 (PDT) MIME-Version: 1.0 References: <20230427180845.127439-1-festevam@gmail.com> <20230427180845.127439-2-festevam@gmail.com> In-Reply-To: <20230427180845.127439-2-festevam@gmail.com> From: Adam Ford Date: Thu, 27 Apr 2023 14:21:59 -0500 Message-ID: Subject: Re: [PATCH 2/3] arm: dts: imx8mn: Sync with Linux 6.3 To: Fabio Estevam Cc: sbabic@denx.de, tharvey@gateworks.com, u-boot@lists.denx.de, Fabio Estevam Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean On Thu, Apr 27, 2023 at 1:08=E2=80=AFPM Fabio Estevam = wrote: > > From: Fabio Estevam > > Sync imx8mn.dtsi with Linux 6.3. > > Signed-off-by: Fabio Estevam Reviewed-by: Adam Ford > --- > arch/arm/dts/imx8mn.dtsi | 46 ++++++++++++++++++++++++++++++---------- > 1 file changed, 35 insertions(+), 11 deletions(-) > > diff --git a/arch/arm/dts/imx8mn.dtsi b/arch/arm/dts/imx8mn.dtsi > index cb2836bfbd95..9e0ddd6b7a32 100644 > --- a/arch/arm/dts/imx8mn.dtsi > +++ b/arch/arm/dts/imx8mn.dtsi > @@ -139,6 +139,7 @@ > A53_L2: l2-cache0 { > compatible =3D "cache"; > cache-level =3D <2>; > + cache-unified; > cache-size =3D <0x80000>; > cache-line-size =3D <64>; > cache-sets =3D <512>; > @@ -295,6 +296,7 @@ > sai2: sai@30020000 { > compatible =3D "fsl,imx8mn-sai", = "fsl,imx8mq-sai"; > reg =3D <0x30020000 0x10000>; > + #sound-dai-cells =3D <0>; > interrupts =3D ; > clocks =3D <&clk IMX8MN_CLK_SAI2_= IPG>, > <&clk IMX8MN_CLK_DUMMY>, > @@ -309,6 +311,7 @@ > sai3: sai@30030000 { > compatible =3D "fsl,imx8mn-sai", = "fsl,imx8mq-sai"; > reg =3D <0x30030000 0x10000>; > + #sound-dai-cells =3D <0>; > interrupts =3D ; > clocks =3D <&clk IMX8MN_CLK_SAI3_= IPG>, > <&clk IMX8MN_CLK_DUMMY>, > @@ -323,6 +326,7 @@ > sai5: sai@30050000 { > compatible =3D "fsl,imx8mn-sai", = "fsl,imx8mq-sai"; > reg =3D <0x30050000 0x10000>; > + #sound-dai-cells =3D <0>; > interrupts =3D ; > clocks =3D <&clk IMX8MN_CLK_SAI5_= IPG>, > <&clk IMX8MN_CLK_DUMMY>, > @@ -339,6 +343,7 @@ > sai6: sai@30060000 { > compatible =3D "fsl,imx8mn-sai", = "fsl,imx8mq-sai"; > reg =3D <0x30060000 0x10000>; > + #sound-dai-cells =3D <0>; > interrupts =3D ; > clocks =3D <&clk IMX8MN_CLK_SAI6_= IPG>, > <&clk IMX8MN_CLK_DUMMY>, > @@ -396,6 +401,7 @@ > sai7: sai@300b0000 { > compatible =3D "fsl,imx8mn-sai", = "fsl,imx8mq-sai"; > reg =3D <0x300b0000 0x10000>; > + #sound-dai-cells =3D <0>; > interrupts =3D ; > clocks =3D <&clk IMX8MN_CLK_SAI7_= IPG>, > <&clk IMX8MN_CLK_DUMMY>, > @@ -497,6 +503,8 @@ > compatible =3D "fsl,imx8mn-tmu", "fsl,imx= 8mm-tmu"; > reg =3D <0x30260000 0x10000>; > clocks =3D <&clk IMX8MN_CLK_TMU_ROOT>; > + nvmem-cells =3D <&tmu_calib>; > + nvmem-cell-names =3D "calib"; > #thermal-sensor-cells =3D <0>; > }; > > @@ -551,7 +559,7 @@ > reg =3D <0x30330000 0x10000>; > }; > > - gpr: iomuxc-gpr@30340000 { > + gpr: syscon@30340000 { > compatible =3D "fsl,imx8mn-iomuxc-gpr", "= syscon"; > reg =3D <0x30340000 0x10000>; > }; > @@ -563,23 +571,40 @@ > #address-cells =3D <1>; > #size-cells =3D <1>; > > - imx8mn_uid: unique-id@410 { > + /* > + * The register address below maps to the= MX8M > + * Fusemap Description Table entries this= way. > + * Assuming > + * reg =3D ; > + * then > + * Fuse Address =3D (ADDR * 4) + 0x400 > + * Note that if SIZE is greater than 4, t= hen > + * each subsequent fuse is located at off= set > + * +0x10 in Fusemap Description Table (e.= g. > + * reg =3D <0x4 0x8> describes fuses 0x41= 0 and > + * 0x420). > + */ > + imx8mn_uid: unique-id@4 { /* 0x410-0x420 = */ > reg =3D <0x4 0x8>; > }; > > - cpu_speed_grade: speed-grade@10 { > + cpu_speed_grade: speed-grade@10 { /* 0x44= 0 */ > reg =3D <0x10 4>; > }; > > - fec_mac_address: mac-address@90 { > + tmu_calib: calib@3c { /* 0x4f0 */ > + reg =3D <0x3c 4>; > + }; > + > + fec_mac_address: mac-address@90 { /* 0x64= 0 */ > reg =3D <0x90 6>; > }; > }; > > - anatop: anatop@30360000 { > - compatible =3D "fsl,imx8mn-anatop", "fsl,= imx8mm-anatop", > - "syscon"; > + anatop: clock-controller@30360000 { > + compatible =3D "fsl,imx8mn-anatop", "fsl,= imx8mm-anatop"; > reg =3D <0x30360000 0x10000>; > + #clock-cells =3D <1>; > }; > > snvs: snvs@30370000 { > @@ -662,7 +687,6 @@ > pgc_otg1: power-domain@1 { > #power-domain-cells =3D <= 0>; > reg =3D ; > - power-domains =3D <&pgc_h= siomix>; > }; > > pgc_gpumix: power-domain@2 { > @@ -1076,7 +1100,7 @@ > assigned-clock-parents =3D <&clk IMX8MN_S= YS_PLL2_500M>; > phys =3D <&usbphynop1>; > fsl,usbmisc =3D <&usbmisc1 0>; > - power-domains =3D <&pgc_otg1>; > + power-domains =3D <&pgc_hsiomix>; > status =3D "disabled"; > }; > > @@ -1094,7 +1118,6 @@ > , > , > ; > - interrupt-names =3D "gpmi0", "gpmi1", "gpmi2", "g= pmi3"; > #dma-cells =3D <1>; > dma-channels =3D <4>; > clocks =3D <&clk IMX8MN_CLK_NAND_USDHC_BUS_RAWNAN= D_CLK>; > @@ -1103,7 +1126,7 @@ > gpmi: nand-controller@33002000 { > compatible =3D "fsl,imx8mn-gpmi-nand", "fsl,imx7d= -gpmi-nand"; > #address-cells =3D <1>; > - #size-cells =3D <1>; > + #size-cells =3D <0>; > reg =3D <0x33002000 0x2000>, <0x33004000 0x4000>; > reg-names =3D "gpmi-nand", "bch"; > interrupts =3D ; > @@ -1175,5 +1198,6 @@ > assigned-clocks =3D <&clk IMX8MN_CLK_USB_PHY_REF>; > assigned-clock-parents =3D <&clk IMX8MN_SYS_PLL1_100M>; > clock-names =3D "main_clk"; > + power-domains =3D <&pgc_otg1>; > }; > }; > -- > 2.34.1 >