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[209.85.160.173]) by smtp.gmail.com with ESMTPSA id x142sm4069993qkb.136.2021.05.10.23.08.21 for (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 10 May 2021 23:08:22 -0700 (PDT) Received: by mail-qt1-f173.google.com with SMTP id t20so9559120qtx.8 for ; Mon, 10 May 2021 23:08:21 -0700 (PDT) X-Received: by 2002:a05:622a:1789:: with SMTP id s9mr493121qtk.92.1620713301839; Mon, 10 May 2021 23:08:21 -0700 (PDT) MIME-Version: 1.0 References: <20210511053134.3353286-1-alejandro@enedino.org> In-Reply-To: From: "Alejandro Hernandez Samaniego" Date: Tue, 11 May 2021 00:08:09 -0600 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [OE-core] [PATCH v2] baremetal-helloworld: Enable RISC-V 64 port To: Alistair Francis Cc: OE-core Content-Type: multipart/alternative; boundary="000000000000a3956b05c207b858" --000000000000a3956b05c207b858 Content-Type: text/plain; charset="UTF-8" On Mon, May 10, 2021, 11:59 PM Alistair Francis wrote: > On Tue, May 11, 2021 at 3:31 PM Alejandro Hernandez Samaniego > wrote: > > > > Add support for MACHINE=qemuriscv64. > > > > $ runqemu nographic > > > > KERNEL: > [tmp/deploy/images/qemuriscv64/baremetal-helloworld-image-qemuriscv64.bin] > > MACHINE: [qemuriscv64] > > FSTYPE: [bin] > > > runqemu - INFO - Running > tmp/work/x86_64-linux/qemu-helper-native/1.0-r1/recipe-sysroot-native/usr/bin/qemu-system-riscv64 > > > > Hello OpenEmbedded on RISC-V 64! > > > > Signed-off-by: Alejandro Enedino Hernandez Samaniego < > alejandro@enedino.org> > > --- > > .../baremetal-examples/baremetal-helloworld_git.bb | 5 +++-- > > meta/classes/baremetal-image.bbclass | 14 +++++++++++++- > > 2 files changed, 16 insertions(+), 3 deletions(-) > > > > diff --git a/meta-skeleton/recipes-baremetal/baremetal-examples/ > baremetal-helloworld_git.bb > b/meta-skeleton/recipes-baremetal/baremetal-examples/ > baremetal-helloworld_git.bb > > index ee945c1ff0..19ef16988f 100644 > > --- a/meta-skeleton/recipes-baremetal/baremetal-examples/ > baremetal-helloworld_git.bb > > +++ b/meta-skeleton/recipes-baremetal/baremetal-examples/ > baremetal-helloworld_git.bb > > @@ -4,7 +4,7 @@ DESCRIPTION = "These are introductory examples to > showcase the use of QEMU to ru > > LICENSE = "MIT" > > LIC_FILES_CHKSUM = "file://LICENSE;md5=39346640a23c701e4f459e05f56f4449" > > > > -SRCREV = "99f4fa4a3b266b42b52af302610b0f4f429ba5e3" > > +SRCREV = "0bf9ea216e6f76be50726a3a74e527b7bbb0ad93" > > PV = "0.1+git${SRCPV}" > > > > SRC_URI = "git:// > github.com/aehs29/baremetal-helloqemu.git;protocol=https;branch=master" > > @@ -28,12 +28,13 @@ inherit baremetal-image > > # machine that QEMU uses on OE, e.g. -machine virt -cpu cortex-a57 > > # but the examples can also be run on other architectures/machines > > # such as vexpress-a15 by overriding the setting on the machine.conf > > -COMPATIBLE_MACHINE = "qemuarmv5|qemuarm|qemuarm64" > > +COMPATIBLE_MACHINE = "qemuarmv5|qemuarm|qemuarm64|qemuriscv64" > > > > BAREMETAL_QEMUARCH ?= "" > > BAREMETAL_QEMUARCH_qemuarmv5 = "versatile" > > BAREMETAL_QEMUARCH_qemuarm = "arm" > > BAREMETAL_QEMUARCH_qemuarm64 = "aarch64" > > +BAREMETAL_QEMUARCH_qemuriscv64 = "riscv64" > > > > EXTRA_OEMAKE_append = " QEMUARCH=${BAREMETAL_QEMUARCH} V=1" > > > > diff --git a/meta/classes/baremetal-image.bbclass > b/meta/classes/baremetal-image.bbclass > > index b0f5e885b5..319b61c7cd 100644 > > --- a/meta/classes/baremetal-image.bbclass > > +++ b/meta/classes/baremetal-image.bbclass > > @@ -73,7 +73,19 @@ QB_DEFAULT_KERNEL ?= "${IMAGE_LINK_NAME}.bin" > > QB_MEM ?= "-m 256" > > QB_DEFAULT_FSTYPE ?= "bin" > > QB_DTB ?= "" > > -QB_OPT_APPEND = "-nographic" > > +QB_OPT_APPEND_append = " -nographic" > > + > > +# RISC-V tunes set the BIOS, unset, and instruct QEMU to > > +# ignore the BIOS and boot from -kernel > > +QB_DEFAULT_BIOS_qemuriscv64 = "" > > +QB_OPT_APPEND_append_qemuriscv64 = " -bios none" > > Sorry, I forgot to reply to the other thread. > > Can't you just set QB_DEFAULT_BIOS to "none"? > > Alistair > > + No problem, and nope, runqemu will behave the same way (doesn't pass -bios at all) if QB_DEFAULT_BIOS is either set to an empty string or "none" which means passing QB_OPT_APPEND is still required > + > > +# Use the medium-any code model for the RISC-V 64 bit implementation, > > +# since medlow can only access addresses below 0x80000000 and RAM > > +# starts at 0x80000000 on RISC-V 64 > > +CFLAGS_append_qemuriscv64 = " -mcmodel=medany" > > + > > > > # This next part is necessary to trick the build system into thinking > > # its building an image recipe so it generates the qemuboot.conf > > -- > > 2.25.1 > > > > > > > > > --000000000000a3956b05c207b858 Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable


On Mon, May 10, 2021, 11:59 PM Alistair Francis <alistair23@gmail.com> wrote:
On Tue, May 11, 2021 at 3:31 PM Alej= andro Hernandez Samaniego
<alejandro@enedino.org> wrote:
>
> Add support for MACHINE=3Dqemuriscv64.
>
> $ runqemu nographic
>
> KERNEL: [tmp/deploy/images/qemuriscv64/baremetal-helloworld-image-qem= uriscv64.bin]
> MACHINE: [qemuriscv64]
> FSTYPE: [bin]
>
=
> runqemu - INFO - Running tmp/work/x86_64-linux/qemu-helper-native/1.0= -r1/recipe-sysroot-native/usr/bin/qemu-system-riscv64
>
> Hello OpenEmbedded on RISC-V 64!
>
> Signed-off-by: Alejandro Enedino Hernandez Samaniego <alejandro= @enedino.org>
> ---
>=C2=A0 .../baremetal-examples/baremetal-helloworld= _git.bb |=C2=A0 5 +++--
>=C2=A0 meta/classes/baremetal-image.bbclass=C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0| 14 +++++++++++++-
>=C2=A0 2 files changed, 16 insertions(+), 3 deletions(-)
>
> diff --git a/meta-skeleton/recipes-baremetal/baremetal-examples/baremetal-helloworld_git.bb b/meta-skeleton/recipes-bare= metal/baremetal-examples/baremetal-helloworld_git.bb
> index ee945c1ff0..19ef16988f 100644
> --- a/meta-skeleton/recipes-baremetal/baremetal-examples/baremetal-helloworld_git.bb
> +++ b/meta-skeleton/recipes-baremetal/baremetal-examples/baremetal-helloworld_git.bb
> @@ -4,7 +4,7 @@ DESCRIPTION =3D "These are introductory examples= to showcase the use of QEMU to ru
>=C2=A0 LICENSE =3D "MIT"
>=C2=A0 LIC_FILES_CHKSUM =3D "file://LICENSE;md5=3D39346640a23c701= e4f459e05f56f4449"
>
> -SRCREV =3D "99f4fa4a3b266b42b52af302610b0f4f429ba5e3"
> +SRCREV =3D "0bf9ea216e6f76be50726a3a74e527b7bbb0ad93"
>=C2=A0 PV =3D "0.1+git${SRCPV}"
>
>=C2=A0 SRC_URI =3D "git://github.com/aehs29/baremetal-helloqemu.git;proto= col=3Dhttps;branch=3Dmaster"
> @@ -28,12 +28,13 @@ inherit baremetal-image
>=C2=A0 # machine that QEMU uses on OE, e.g. -machine virt -cpu cortex-= a57
>=C2=A0 # but the examples can also be run on other architectures/machi= nes
>=C2=A0 # such as vexpress-a15 by overriding the setting on the machine= .conf
> -COMPATIBLE_MACHINE =3D "qemuarmv5|qemuarm|qemuarm64"
> +COMPATIBLE_MACHINE =3D "qemuarmv5|qemuarm|qemuarm64|qemuriscv64= "
>
>=C2=A0 BAREMETAL_QEMUARCH ?=3D ""
>=C2=A0 BAREMETAL_QEMUARCH_qemuarmv5 =3D "versatile"
>=C2=A0 BAREMETAL_QEMUARCH_qemuarm =3D "arm"
>=C2=A0 BAREMETAL_QEMUARCH_qemuarm64 =3D "aarch64"
> +BAREMETAL_QEMUARCH_qemuriscv64 =3D "riscv64"
>
>=C2=A0 EXTRA_OEMAKE_append =3D " QEMUARCH=3D${BAREMETAL_QEMUARCH}= V=3D1"
>
> diff --git a/meta/classes/baremetal-image.bbclass b/meta/classes/bare= metal-image.bbclass
> index b0f5e885b5..319b61c7cd 100644
> --- a/meta/classes/baremetal-image.bbclass
> +++ b/meta/classes/baremetal-image.bbclass
> @@ -73,7 +73,19 @@ QB_DEFAULT_KERNEL ?=3D "${IMAGE_LINK_NAME}.bi= n"
>=C2=A0 QB_MEM ?=3D "-m 256"
>=C2=A0 QB_DEFAULT_FSTYPE ?=3D "bin"
>=C2=A0 QB_DTB ?=3D ""
> -QB_OPT_APPEND =3D "-nographic"
> +QB_OPT_APPEND_append =3D " -nographic"
> +
> +# RISC-V tunes set the BIOS, unset, and instruct QEMU to
> +# ignore the BIOS and boot from -kernel
> +QB_DEFAULT_BIOS_qemuriscv64 =3D ""
> +QB_OPT_APPEND_append_qemuriscv64 =3D " -bios none"

Sorry, I forgot to reply to the other thread.

Can't you just set QB_DEFAULT_BIOS to "none"?

Alistair

> +

No problem, and nope, runqemu will behave the sa= me way (doesn't pass -bios at all) if QB_DEFAULT_BIOS is either set to = an empty string or "none" which means passing QB_OPT_APPEND is st= ill required

> +
> +# Use the medium-any code model for the RISC-V 64 bit implementation= ,
> +# since medlow can only access addresses below 0x80000000 and RAM > +# starts at 0x80000000 on RISC-V 64
> +CFLAGS_append_qemuriscv64 =3D " -mcmodel=3Dmedany"
> +
>
>=C2=A0 # This next part is necessary to trick the build system into th= inking
>=C2=A0 # its building an image recipe so it generates the qemuboot.con= f
> --
> 2.25.1
>
>
>
>
--000000000000a3956b05c207b858--