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From: Michael Clark <mjc@sifive.com>
Date: Sat, 10 Mar 2018 09:54:24 +1300
Message-ID: <CAHNT7NsbNYtRtug9=gv1tPg7_XLs4b=BwK+95_3zpvy5yTVriw@mail.gmail.com>
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Subject: Re: [Qemu-devel] [PULL] RISC-V: Fix riscv_isa_string g_new0 size
 calculation
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To: Peter Maydell <peter.maydell@linaro.org>, QEMU Developers <qemu-devel@nongnu.org>
Cc: Michael Clark <mjc@sifive.com>, Palmer Dabbelt <palmer@sifive.com>, RISC-V Patches <patches@groups.riscv.org>

Apologies for jumping the gun again with a PR before a review. It was most
likely because I thought it was a critical bug fix.

I'm incorporating Eric Blake's feedback.

On Sat, Mar 10, 2018 at 9:29 AM, Michael Clark <mjc@sifive.com> wrote:

> The following changes since commit e4ae62b802cec437f877f2cadc4ef0
> 59cc0eca76:
>
>   Merge remote-tracking branch 'remotes/stefanha/tags/block-pull-request'
> into staging (2018-03-09 17:28:16 +0000)
>
> are available in the git repository at:
>
>   https://github.com/michaeljclark/riscv-qemu.git fix-riscv-isa-string
>
> for you to fetch changes up to 32b3a5716062f805a42e1cae1df95f2f869a78c1:
>
>   RISC-V: Fix isa string logic bug, use popcount to count bits (2018-03-10
> 09:17:29 +1300)
>
> ----------------------------------------------------------------
> Michael Clark (1):
>       RISC-V: Fix isa string logic bug, use popcount to count bits
>
>  target/riscv/cpu.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>