[Qemu-devel] [PULL] RISC-V QEMU Port Submission v8.2

[Qemu-devel] [PULL] RISC-V QEMU Port Submission v8.2

[Michael Clark]

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Hash: SHA1

The following changes since commit f32408f3b472a088467474ab152be3b6285b2d7b:

  misc: don't use hwaddr as a type in trace events (2018-03-06 14:24:30 +0000)

are available in the git repository at:

  https://github.com/riscv/riscv-qemu.git tags/riscv-qemu-upstream-v8.2

for you to fetch changes up to 7051b081bf6796e5e84406f6223a7c4900bf7298:

  RISC-V - Remove support for adhoc non-standard X_COP local-interrupt (2018-03-07 08:36:03 +1300)

- ----------------------------------------------------------------
QEMU RISC-V Emulation Support (RV64GC, RV32GC)

This release renames the SiFive machines to sifive_e and sifive_u
to represent the SiFive Everywhere and SiFive Unleashed platforms.
SiFive has configurable soft-core IP, so it is intended that these
machines will be extended to enable a variety of SiFive IP blocks.
The CPU definition infrastructure has been improved and there are
now vendor CPU modules including the SiFiVe E31, E51, U34 and U54
cores. The emulation accuracy for the E series has been improved
by disabling the MMU for the E series. S mode has been disabled on
cores that only support M mode and U mode. The two Spike machines
that support two privileged ISA versions have been coalesced into
one file. This series has Signed-off-by from the core contributors.

*** Known Issues ***

* Disassembler has some checkpatch warnings for the sake of code brevity
* scripts/qemu-binfmt-conf.sh has checkpatch warnings due to line length
* PMP (Physical Memory Protection) is as-of-yet unused and needs testing

*** Changelog ***

v8.2

* Rebase

v8.1

* Fix missed case of renaming spike_v1.9 to spike_v1.9.1

v8

* Added linux-user/riscv/target_elf.h during rebase
* Make resetvec configurable and clear mpp and mie on reset
* Use SiFive E31, E51, U34 and U54 cores in SiFive machines
* Define SiFive E31, E51, U34 and U54 cores
* Refactor CPU core definition in preparation for vendor cores
* Prevent S or U mode unless S or U extensions are present
* SiFive E Series cores have no MMU
* SiFive E Series cores have U mode
* Make privileged ISA v1.10 implicit in CPU types
* Remove DRAM_BASE and EXT_IO_BASE as they vary by machine
* Correctly handle mtvec and stvec alignment with respect to RVC
* Print more machine mode state in riscv_cpu_dump_state
* Make riscv_isa_string use compact extension order method
* Fix bug introduced in v6 RISCV_CPU_TYPE_NAME macro change
* Parameterize spike v1.9.1 config string
* Coalesce spike_v1.9.1 and spike_v1.10 machines
* Rename sifive_e300 to sifive_e, and sifive_u500 to sifive_u

v7

* Make spike_v1.10 the default machine
* Rename spike_v1.9 to spike_v1.9.1 to match privileged spec version
* Remove empty target/riscv/trace-events file
* Monitor ROM 32-bit reset code needs to be target endian
* Add TARGET_TIOCGPTPEER to linux-user/riscv/termbits.h
* Add -initrd support to the virt board
* Fix naming in spike machine interface header
* Update copyright notice on RISC-V Spike machines
* Update copyright notice on RISC-V HTIF Console device
* Change CPU Core and translator to GPLv2+
* Change RISC-V Disassembler to GPLv2+
* Change SiFive Test Finisher to GPLv2+
* Change SiFive CLINT to GPLv2+
* Change SiFive PRCI to GPLv2+
* Change SiFive PLIC to GPLv2+
* Change RISC-V spike machines to GPLv2+
* Change RISC-V virt machine to GPLv2+
* Change SiFive E300 machine to GPLv2+
* Change SiFive U500 machine to GPLv2+
* Change RISC-V Hart Array to GPLv2+
* Change RISC-V HTIF device to GPLv2+
* Change SiFiveUART device to GPLv2+

v6

* Drop IEEE 754-201x minimumNumber/maximumNumber for fmin/fmax
* Remove some unnecessary commented debug statements
* Change RISCV_CPU_TYPE_NAME to use riscv-cpu suffix
* Define all CPU variants for linux-user
* qemu_log calls require trailing \n
* Replace PLIC printfs with qemu_log
* Tear out unused HTIF code and eliminate shouting debug messages
* Fix illegal instruction when sfence.vma is passed (rs2) arguments
* Make updates to PTE accessed and dirty bits atomic
* Only require atomic PTE updates on MTTCG enabled guests
* Page fault if accessed or dirty bits can't be updated
* Fix get_physical_address PTE reads and writes on riscv32
* Remove erroneous comments from the PLIC
* Default enable MTTCG
* Make WFI less conservative
* Unify local interrupt handling
* Expunge HTIF interrupts
* Always access mstatus.mip under a lock
* Don't implement rdtime/rdtimeh in system mode (bbl emulates them)
* Implement insreth/cycleh for rv32 and always enable user-mode counters
* Add GDB stub support for reading and writing CSRs
* Rename ENABLE_CHARDEV #ifdef from HTIF code
* Replace bad HTIF ELF code with load_elf symbol callback
* Convert chained if else fault handlers to switch statements
* Use RISCV exception codes for linux-user page faults

v5

* Implement NaN-boxing for flw, set high order bits to 1
* Use float_muladd_negate_* flags to floatXX_muladd
* Use IEEE 754-201x minimumNumber/maximumNumber for fmin/fmax
* Fix TARGET_NR_syscalls
* Update linux-user/riscv/syscall_nr.h
* Fix FENCE.I, needs to terminate translation block
* Adjust unusual convention for interruptno >= 0

v4

* Add @riscv: since 2.12 to CpuInfoArch
* Remove misleading little-endian comment from load_kernel
* Rename cpu-model property to cpu-type
* Drop some unnecessary inline function attributes
* Don't allow GDB to set value of x0 register
* Remove unnecessary empty property lists
* Add Test Finisher device to implement poweroff in virt machine
* Implement priv ISA v1.10 trap and sret/mret xPIE/xIE behavior
* Store fflags data in fp_status
* Purge runtime users of helper_raise_exception
* Fix validate_csr
* Tidy gen_jalr
* Tidy immediate shifts
* Add gen_exception_inst_addr_mis
* Add gen_exception_debug
* Add gen_exception_illegal
* Tidy helper_fclass_*
* Split rounding mode setting to a new function
* Enforce MSTATUS_FS via TB flags
* Implement acquire/release barrier semantics
* Use atomic operations as required
* Fix FENCE and FENCE_I
* Remove commented code from spike machines
* PAGE_WRITE permissions can be set on loads if page is already dirty
* The result of format conversion on an NaN must be a quiet NaN
* Add missing process_queued_cpu_work to riscv linux-user
* Remove float(32|64)_classify from cpu.h
* Removed nonsensical unions aliasing the same type
* Use uintN_t instead of uintN_fast_t in fpu_helper.c
* Use macros for FPU exception values in softfloat_flags_to_riscv
* Move code to set round mode into set_fp_round_mode function
* Convert set_fp_exceptions from a macro to an inline function
* Convert round mode helper into an inline function
* Make fpu_helper ieee_rm array static const
* Include cpu_mmu_index in cpu_get_tb_cpu_state flags
* Eliminate MPRV influence on mmu_index
* Remove unrecoverable do_unassigned_access function
* Only update PTE accessed and dirty bits if necessary
* Remove unnecessary tlb_flush in set_mode as mode is in mmu_idx
* Remove buggy support for misa writes. misa writes are optional
  and are not implemented in any known hardware
* Always set PTE read or execute permissions during page walk
* Reorder helper function declarations to match order in helper.c
* Remove redundant variable declaration in get_physical_address
* Remove duplicated code from get_physical_address
* Use mmu_idx instead of mem_idx in riscv_cpu_get_phys_page_debug

v3

* Fix indentation in PMP and HTIF debug macros
* Fix disassembler checkpatch open brace '{' on next line errors
* Fix trailing statements on next line in decode_inst_decompress
* NOTE: the other checkpatch issues have been reviewed previously

v2

* Remove redundant NULL terminators from disassembler register arrays
* Change disassembler register name arrays to const
* Refine disassembler internal function names
* Update dates in disassembler copyright message
* Remove #ifdef CONFIG_USER_ONLY version of cpu_has_work
* Use ULL suffix on 64-bit constants
* Move riscv_cpu_mmu_index from cpu.h to helper.c
* Move riscv_cpu_hw_interrupts_pending from cpu.h to helper.c
* Remove redundant TARGET_HAS_ICE from cpu.h
* Use qemu_irq instead of void* for irq definition in cpu.h
* Remove duplicate typedef from struct CPURISCVState
* Remove redundant g_strdup from cpu_register
* Remove redundant tlb_flush from riscv_cpu_reset
* Remove redundant mode calculation from get_physical_address
* Remove redundant debug mode printf and dcsr comment
* Remove redundant clearing of MSB for bare physical addresses
* Use g_assert_not_reached for invalid mode in get_physical_address
* Use g_assert_not_reached for unreachable checks in get_physical_address
* Use g_assert_not_reached for unreachable type in raise_mmu_exception
* Return exception instead of aborting for misaligned fetches
* Move exception defines from cpu.h to cpu_bits.h
* Remove redundant breakpoint control definitions from cpu_bits.h
* Implement riscv_cpu_unassigned_access exception handling
* Log and raise exceptions for unimplemented CSRs
* Match Spike HTIF exit behavior - don’t print TEST-PASSED
* Make frm,fflags,fcsr writes trap when mstatus.FS is clear
* Use g_assert_not_reached for unreachable invalid mode
* Make hret,uret,dret generate illegal instructions
* Move riscv_cpu_dump_state and int/fpr regnames to cpu.c
* Lift interrupt flag and mask into constants in cpu_bits.h
* Change trap debugging to use qemu_log_mask LOG_TRACE
* Change CSR debugging to use qemu_log_mask LOG_TRACE
* Change PMP debugging to use qemu_log_mask LOG_TRACE
* Remove commented code from pmp.c
* Change CpuInfoRISCV qapi schema docs to Since 2.12
* Change RV feature macro to use target_ulong cast
* Remove riscv_feature and instead use misa extension flags
* Make riscv_flush_icache_syscall a no-op
* Undo checkpatch whitespace fixes in unrelated linux-user code
* Remove redudant constants and tidy up cpu_bits.h
* Make helper_fence_i a no-op
* Move include "exec/cpu-all" to end of cpu.h
* Rename set_privilege to riscv_set_mode
* Move redundant forward declaration for cpu_riscv_translate_address
* Remove TCGV_UNUSED from riscv_translate_init
* Add comment to pmp.c stating the code is untested and currently unused
* Use ctz to simplify decoding of PMP NAPOT address ranges
* Change pmp_is_in_range to use than equal for end addresses
* Fix off by one error in pmp_update_rule
* Rearrange PMP_DEBUG so that formatting is compile-time checked
* Rearrange trap debugging so that formatting is compile-time checked
* Rearrange PLIC debugging so that formatting is compile-time checked
* Use qemu_log/qemu_log_mask for HTIF logging and debugging
* Move exception and interrupt names into cpu.c
* Add Palmer Dabbelt as a RISC-V Maintainer
* Rebase against current qemu master branch

v1

* initial version based on forward port from riscv-qemu repository

*** Background ***

"RISC-V is an open, free ISA enabling a new era of processor innovation
through open standard collaboration. Born in academia and research,
RISC-V ISA delivers a new level of free, extensible software and
hardware freedom on architecture, paving the way for the next 50 years
of computing design and innovation."

The QEMU RISC-V port has been developed and maintained out-of-tree for
several years by Sagar Karandikar and Bastian Koppelmann. The RISC-V
Privileged specification has evolved substantially over this period but
has recently been solidifying. The RISC-V Base ISA has been frozon for
some time and the Privileged ISA, GCC toolchain and Linux ABI are now
quite stable. I have recently joined Sagar and Bastian as a RISC-V QEMU
Maintainer and hope to support upstreaming the port.

There are multiple vendors taping out, preparing to ship, or shipping
silicon that implements the RISC-V Privileged ISA Version 1.10. There
are also several RISC-V Soft-IP cores implementing Privileged ISA
Version 1.10 that run on FPGA such as SiFive's Freedom U500 Platform
and the U54‑MC RISC-V Core IP, among many more implementations from a
variety of vendors. See https://riscv.org/ for more details.

RISC-V support was upstreamed in binutils 2.28 and GCC 7.1 in the first
half of 2016. RISC-V support is now available in LLVM top-of-tree and
the RISC-V Linux port was accepted into Linux 4.15-rc1 late last year
and is available in the Linux 4.15 release. GLIBC 2.27 added support
for the RISC-V ISA running on Linux (requires at least binutils-2.30,
gcc-7.3.0, and linux-4.15). We believe it is timely to submit the
RISC-V QEMU port for upstream review with the goal of incorporating
RISC-V support into the upcoming QEMU 2.12 release.

The RISC-V QEMU port is still under active development, mostly with
respect to device emulation, the addition of Hypervisor support as
specified in the RISC-V Draft Privileged ISA Version 1.11, and Vector
support once the first draft is finalized later this year. We believe
now is the appropriate time for RISC-V QEMU development to be carried
out in the main QEMU repository as the code will benefit from more
rigorous review. The RISC-V QEMU port currently supports all the ISA
extensions that have been finalized and frozen in the Base ISA.

Blog post about recent additions to RISC-V QEMU: https://goo.gl/fJ4zgk

The RISC-V QEMU wiki: https://github.com/riscv/riscv-qemu/wiki

Instructions for building a busybox+dropbear root image, BBL (Berkeley
Boot Loader) and linux kernel image for use with the RISC-V QEMU
'virt' machine: https://github.com/michaeljclark/busybear-linux

*** Overview ***

The RISC-V QEMU port implements the following specifications:

* RISC-V Instruction Set Manual Volume I: User-Level ISA Version 2.2
* RISC-V Instruction Set Manual Volume II: Privileged ISA Version 1.9.1
* RISC-V Instruction Set Manual Volume II: Privileged ISA Version 1.10

The RISC-V QEMU port supports the following instruction set extensions:

* RV32GC with Supervisor-mode and User-mode (RV32IMAFDCSU)
* RV64GC with Supervisor-mode and User-mode (RV64IMAFDCSU)

The RISC-V QEMU port adds the following targets to QEMU:

* riscv32-softmmu
* riscv64-softmmu
* riscv32-linux-user
* riscv64-linux-user

The RISC-V QEMU port supports the following hardware:

* HTIF Console (Host Target Interface)
* SiFive CLINT (Core Local Interruptor) for Timer interrupts and IPIs
* SiFive PLIC (Platform Level Interrupt Controller)
* SiFive Test (Test Finisher) for exiting simulation
* SiFive UART, PRCI, AON, PWM, QSPI support is partially implemented
* VirtIO MMIO (GPEX PCI support will be added in a future patch)
* Generic 16550A UART emulation using 'hw/char/serial.c'
* MTTCG and SMP support (PLIC and CLINT) on the 'virt' machine

The RISC-V QEMU full system emulator supports 5 machines:

* 'spike_v1.9.1', CLINT, PLIC, HTIF console, config-string, Priv v1.9.1
* 'spike_v1.10', CLINT, PLIC, HTIF console, device-tree, Priv v1.10
* 'sifive_e', CLINT, PLIC, SiFive UART, HiFive1 compat, Priv v1.10
* 'sifive_u', CLINT, PLIC, SiFive UART, device-tree, Priv v1.10
* 'virt', CLINT, PLIC, 16550A UART, VirtIO, device-tree, Priv v1.10

This is a list of RISC-V QEMU Port Contributors:

* Alex Suykov
* Andreas Schwab
* Antony Pavlov
* Bastian Koppelmann
* Bruce Hoult
* Chih-Min Chao
* Daire McNamara
* Darius Rad
* David Abdurachmanov
* Hesham Almatary
* Ivan Griffin
* Jim Wilson
* Kito Cheng
* Michael Clark
* Palmer Dabbelt
* Richard Henderson
* Sagar Karandikar
* Shea Levy
* Stefan O'Rear

Notes:

* contributor email addresses available off-list on request.
* checkpatch has been run on all 23 patches.
* checkpatch exceptions are noted in patches that have errors.
* passes "make check" on full build for all targets
* tested riscv-linux-4.6.2 on 'spike_v1.9.1' machine
* tested riscv-linux-4.15 on 'spike_v1.10' and 'virt' machines
* tested SiFive HiFive1 binaries in 'sifive_e' machine
* tested RV64 on 32-bit i386

This patch series includes the following patches:

- ----------------------------------------------------------------
Michael Clark (45):
      RISC-V Maintainers
      RISC-V ELF Machine Definition
      RISC-V CPU Core Definition
      RISC-V Disassembler
      RISC-V CPU Helpers
      RISC-V FPU Support
      RISC-V GDB Stub
      RISC-V TCG Code Generation
      RISC-V Physical Memory Protection
      RISC-V Linux User Emulation
      Add symbol table callback interface to load_elf
      RISC-V HTIF Console
      RISC-V HART Array
      SiFive RISC-V CLINT Block
      SiFive RISC-V PLIC Block
      RISC-V Spike Machines
      SiFive RISC-V Test Finisher
      RISC-V VirtIO Machine
      SiFive RISC-V UART Device
      SiFive RISC-V PRCI Block
      SiFive Freedom E Series RISC-V Machine
      SiFive Freedom U Series RISC-V Machine
      RISC-V Build Infrastructure
      RISC-V - Make virt create_fdt interface consistent with other boards
      RISC-V - Replace hardcoded device-tree constants with enum values
      RISC-V - Make virt board description match spike format
      RISC-V - Use ROM base address and size constants from memory map
      RISC-V - Remove redundant identity_translate callback from load_elf
      RISC-V - Mark ROM read-only after copying in reset vector and config
      RISC-V - Remove unused class definitions from machines
      RISC-V - Make sure the emulated mask rom has space for device-tree
      RISC-V - Include hexidecimal instruction packets in disassembly
      RISC-V - Need to hold rcu_read_lock when accessing memory directly
      RISC-V - Improve page table walker spec compliance and add comments
      RISC-V - Update E order and note that add E and I are mutually exclusive
      RISC-V - Make spike and virt header guards more specific
      RISC-V - Make virt header comment consistent with source file
      RISC-V - Use memory_region_is_ram in atomic pte update
      RISC-V - Remove EM_RISCV ELF_MACHINE indirection from load_elf
      RISC-V - Ingore satp writes and return 0 for reads when no-mmu
      RISC-V - Remove braces from satp case statement with no locals
      RISC-V - riscv-qemu port supports sv39 and sv48
      RISC-V - vectored traps for asynchrounous interrupts are optional
      RISC-V - Dont' trap on writes to misa,minstret[h],mcycle[h]
      RISC-V - Remove support for adhoc non-standard X_COP local-interrupt

 MAINTAINERS                            |   11 +
 arch_init.c                            |    2 +
 configure                              |   13 +
 cpus.c                                 |    6 +
 default-configs/riscv32-linux-user.mak |    1 +
 default-configs/riscv32-softmmu.mak    |    4 +
 default-configs/riscv64-linux-user.mak |    1 +
 default-configs/riscv64-softmmu.mak    |    4 +
 disas.c                                |    2 +
 disas/Makefile.objs                    |    1 +
 disas/riscv.c                          | 3049 ++++++++++++++++++++++++++++++++
 fpu/softfloat-specialize.h             |    7 +-
 hw/core/loader.c                       |   18 +-
 hw/riscv/Makefile.objs                 |   11 +
 hw/riscv/riscv_hart.c                  |   89 +
 hw/riscv/riscv_htif.c                  |  258 +++
 hw/riscv/sifive_clint.c                |  251 +++
 hw/riscv/sifive_e.c                    |  204 +++
 hw/riscv/sifive_plic.c                 |  505 ++++++
 hw/riscv/sifive_prci.c                 |   89 +
 hw/riscv/sifive_test.c                 |   93 +
 hw/riscv/sifive_u.c                    |  316 ++++
 hw/riscv/sifive_uart.c                 |  176 ++
 hw/riscv/spike.c                       |  361 ++++
 hw/riscv/virt.c                        |  395 +++++
 include/disas/bfd.h                    |    2 +
 include/elf.h                          |    2 +
 include/hw/elf_ops.h                   |   34 +-
 include/hw/loader.h                    |   17 +-
 include/hw/riscv/riscv_hart.h          |   39 +
 include/hw/riscv/riscv_htif.h          |   61 +
 include/hw/riscv/sifive_clint.h        |   54 +
 include/hw/riscv/sifive_e.h            |   70 +
 include/hw/riscv/sifive_plic.h         |   85 +
 include/hw/riscv/sifive_prci.h         |   37 +
 include/hw/riscv/sifive_test.h         |   42 +
 include/hw/riscv/sifive_u.h            |   64 +
 include/hw/riscv/sifive_uart.h         |   71 +
 include/hw/riscv/spike.h               |   49 +
 include/hw/riscv/virt.h                |   67 +
 include/sysemu/arch_init.h             |    1 +
 linux-user/elfload.c                   |   22 +
 linux-user/main.c                      |   99 ++
 linux-user/riscv/syscall_nr.h          |  287 +++
 linux-user/riscv/target_cpu.h          |   18 +
 linux-user/riscv/target_elf.h          |   14 +
 linux-user/riscv/target_signal.h       |   23 +
 linux-user/riscv/target_structs.h      |   46 +
 linux-user/riscv/target_syscall.h      |   56 +
 linux-user/riscv/termbits.h            |  222 +++
 linux-user/signal.c                    |  203 ++-
 linux-user/syscall.c                   |    2 +
 linux-user/syscall_defs.h              |   13 +-
 qapi/misc.json                         |   17 +-
 scripts/qemu-binfmt-conf.sh            |   13 +-
 target/riscv/Makefile.objs             |    1 +
 target/riscv/cpu.c                     |  432 +++++
 target/riscv/cpu.h                     |  296 ++++
 target/riscv/cpu_bits.h                |  408 +++++
 target/riscv/cpu_user.h                |   13 +
 target/riscv/fpu_helper.c              |  373 ++++
 target/riscv/gdbstub.c                 |   62 +
 target/riscv/helper.c                  |  530 ++++++
 target/riscv/helper.h                  |   78 +
 target/riscv/instmap.h                 |  364 ++++
 target/riscv/op_helper.c               |  669 +++++++
 target/riscv/pmp.c                     |  380 ++++
 target/riscv/pmp.h                     |   64 +
 target/riscv/translate.c               | 1978 +++++++++++++++++++++
 69 files changed, 13218 insertions(+), 27 deletions(-)
 create mode 100644 default-configs/riscv32-linux-user.mak
 create mode 100644 default-configs/riscv32-softmmu.mak
 create mode 100644 default-configs/riscv64-linux-user.mak
 create mode 100644 default-configs/riscv64-softmmu.mak
 create mode 100644 disas/riscv.c
 create mode 100644 hw/riscv/Makefile.objs
 create mode 100644 hw/riscv/riscv_hart.c
 create mode 100644 hw/riscv/riscv_htif.c
 create mode 100644 hw/riscv/sifive_clint.c
 create mode 100644 hw/riscv/sifive_e.c
 create mode 100644 hw/riscv/sifive_plic.c
 create mode 100644 hw/riscv/sifive_prci.c
 create mode 100644 hw/riscv/sifive_test.c
 create mode 100644 hw/riscv/sifive_u.c
 create mode 100644 hw/riscv/sifive_uart.c
 create mode 100644 hw/riscv/spike.c
 create mode 100644 hw/riscv/virt.c
 create mode 100644 include/hw/riscv/riscv_hart.h
 create mode 100644 include/hw/riscv/riscv_htif.h
 create mode 100644 include/hw/riscv/sifive_clint.h
 create mode 100644 include/hw/riscv/sifive_e.h
 create mode 100644 include/hw/riscv/sifive_plic.h
 create mode 100644 include/hw/riscv/sifive_prci.h
 create mode 100644 include/hw/riscv/sifive_test.h
 create mode 100644 include/hw/riscv/sifive_u.h
 create mode 100644 include/hw/riscv/sifive_uart.h
 create mode 100644 include/hw/riscv/spike.h
 create mode 100644 include/hw/riscv/virt.h
 create mode 100644 linux-user/riscv/syscall_nr.h
 create mode 100644 linux-user/riscv/target_cpu.h
 create mode 100644 linux-user/riscv/target_elf.h
 create mode 100644 linux-user/riscv/target_signal.h
 create mode 100644 linux-user/riscv/target_structs.h
 create mode 100644 linux-user/riscv/target_syscall.h
 create mode 100644 linux-user/riscv/termbits.h
 create mode 100644 target/riscv/Makefile.objs
 create mode 100644 target/riscv/cpu.c
 create mode 100644 target/riscv/cpu.h
 create mode 100644 target/riscv/cpu_bits.h
 create mode 100644 target/riscv/cpu_user.h
 create mode 100644 target/riscv/fpu_helper.c
 create mode 100644 target/riscv/gdbstub.c
 create mode 100644 target/riscv/helper.c
 create mode 100644 target/riscv/helper.h
 create mode 100644 target/riscv/instmap.h
 create mode 100644 target/riscv/op_helper.c
 create mode 100644 target/riscv/pmp.c
 create mode 100644 target/riscv/pmp.h
 create mode 100644 target/riscv/translate.c
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Re: [Qemu-devel] [PULL] RISC-V QEMU Port Submission v8.2

[Michael Clark]

FYI - Travis completed builds for v8.2 and it's all green.

- https://travis-ci.org/riscv/riscv-qemu/builds/349981074

The Travis folks kindly bumped our build timeout limit so we can run the
full upstream Travis checks. I've manually tested Linux in all of the
relevant machines, including SMP in the RISC-V virt machine, along with
embedded binaries for the SiFive E series MCU. We test 'sifive_e' with MCU
samples from SiFive's Freedom E SDK. the Freedom U SDK has a
Linux buildroot setup for testing the 'virt' machine. There is additional
documentation on the wiki, such as links to the Fedora images that Richard
W. M. Jones et al have been working on.

- https://github.com/sifive/freedom-e-sdk/
- https://github.com/sifive/freedom-u-sdk/
- https://github.com/riscv/riscv-qemu/wiki

Hopefully, this PR gets merged...

On Wed, Mar 7, 2018 at 8:46 AM, Michael Clark <mjc@sifive.com> wrote:

> -----BEGIN PGP SIGNED MESSAGE-----
> Hash: SHA1
>
> The following changes since commit f32408f3b472a088467474ab152be3
> b6285b2d7b:
>
>   misc: don't use hwaddr as a type in trace events (2018-03-06 14:24:30
> +0000)
>
> are available in the git repository at:
>
>   https://github.com/riscv/riscv-qemu.git tags/riscv-qemu-upstream-v8.2
>
> for you to fetch changes up to 7051b081bf6796e5e84406f6223a7c4900bf7298:
>
>   RISC-V - Remove support for adhoc non-standard X_COP local-interrupt
> (2018-03-07 08:36:03 +1300)
>
> - ----------------------------------------------------------------
> QEMU RISC-V Emulation Support (RV64GC, RV32GC)
>
> This release renames the SiFive machines to sifive_e and sifive_u
> to represent the SiFive Everywhere and SiFive Unleashed platforms.
> SiFive has configurable soft-core IP, so it is intended that these
> machines will be extended to enable a variety of SiFive IP blocks.
> The CPU definition infrastructure has been improved and there are
> now vendor CPU modules including the SiFiVe E31, E51, U34 and U54
> cores. The emulation accuracy for the E series has been improved
> by disabling the MMU for the E series. S mode has been disabled on
> cores that only support M mode and U mode. The two Spike machines
> that support two privileged ISA versions have been coalesced into
> one file. This series has Signed-off-by from the core contributors.
>
> *** Known Issues ***
>
> * Disassembler has some checkpatch warnings for the sake of code brevity
> * scripts/qemu-binfmt-conf.sh has checkpatch warnings due to line length
> * PMP (Physical Memory Protection) is as-of-yet unused and needs testing
>
> *** Changelog ***
>
> v8.2
>
> * Rebase
>
> v8.1
>
> * Fix missed case of renaming spike_v1.9 to spike_v1.9.1
>
> v8
>
> * Added linux-user/riscv/target_elf.h during rebase
> * Make resetvec configurable and clear mpp and mie on reset
> * Use SiFive E31, E51, U34 and U54 cores in SiFive machines
> * Define SiFive E31, E51, U34 and U54 cores
> * Refactor CPU core definition in preparation for vendor cores
> * Prevent S or U mode unless S or U extensions are present
> * SiFive E Series cores have no MMU
> * SiFive E Series cores have U mode
> * Make privileged ISA v1.10 implicit in CPU types
> * Remove DRAM_BASE and EXT_IO_BASE as they vary by machine
> * Correctly handle mtvec and stvec alignment with respect to RVC
> * Print more machine mode state in riscv_cpu_dump_state
> * Make riscv_isa_string use compact extension order method
> * Fix bug introduced in v6 RISCV_CPU_TYPE_NAME macro change
> * Parameterize spike v1.9.1 config string
> * Coalesce spike_v1.9.1 and spike_v1.10 machines
> * Rename sifive_e300 to sifive_e, and sifive_u500 to sifive_u
>
> v7
>
> * Make spike_v1.10 the default machine
> * Rename spike_v1.9 to spike_v1.9.1 to match privileged spec version
> * Remove empty target/riscv/trace-events file
> * Monitor ROM 32-bit reset code needs to be target endian
> * Add TARGET_TIOCGPTPEER to linux-user/riscv/termbits.h
> * Add -initrd support to the virt board
> * Fix naming in spike machine interface header
> * Update copyright notice on RISC-V Spike machines
> * Update copyright notice on RISC-V HTIF Console device
> * Change CPU Core and translator to GPLv2+
> * Change RISC-V Disassembler to GPLv2+
> * Change SiFive Test Finisher to GPLv2+
> * Change SiFive CLINT to GPLv2+
> * Change SiFive PRCI to GPLv2+
> * Change SiFive PLIC to GPLv2+
> * Change RISC-V spike machines to GPLv2+
> * Change RISC-V virt machine to GPLv2+
> * Change SiFive E300 machine to GPLv2+
> * Change SiFive U500 machine to GPLv2+
> * Change RISC-V Hart Array to GPLv2+
> * Change RISC-V HTIF device to GPLv2+
> * Change SiFiveUART device to GPLv2+
>
> v6
>
> * Drop IEEE 754-201x minimumNumber/maximumNumber for fmin/fmax
> * Remove some unnecessary commented debug statements
> * Change RISCV_CPU_TYPE_NAME to use riscv-cpu suffix
> * Define all CPU variants for linux-user
> * qemu_log calls require trailing \n
> * Replace PLIC printfs with qemu_log
> * Tear out unused HTIF code and eliminate shouting debug messages
> * Fix illegal instruction when sfence.vma is passed (rs2) arguments
> * Make updates to PTE accessed and dirty bits atomic
> * Only require atomic PTE updates on MTTCG enabled guests
> * Page fault if accessed or dirty bits can't be updated
> * Fix get_physical_address PTE reads and writes on riscv32
> * Remove erroneous comments from the PLIC
> * Default enable MTTCG
> * Make WFI less conservative
> * Unify local interrupt handling
> * Expunge HTIF interrupts
> * Always access mstatus.mip under a lock
> * Don't implement rdtime/rdtimeh in system mode (bbl emulates them)
> * Implement insreth/cycleh for rv32 and always enable user-mode counters
> * Add GDB stub support for reading and writing CSRs
> * Rename ENABLE_CHARDEV #ifdef from HTIF code
> * Replace bad HTIF ELF code with load_elf symbol callback
> * Convert chained if else fault handlers to switch statements
> * Use RISCV exception codes for linux-user page faults
>
> v5
>
> * Implement NaN-boxing for flw, set high order bits to 1
> * Use float_muladd_negate_* flags to floatXX_muladd
> * Use IEEE 754-201x minimumNumber/maximumNumber for fmin/fmax
> * Fix TARGET_NR_syscalls
> * Update linux-user/riscv/syscall_nr.h
> * Fix FENCE.I, needs to terminate translation block
> * Adjust unusual convention for interruptno >= 0
>
> v4
>
> * Add @riscv: since 2.12 to CpuInfoArch
> * Remove misleading little-endian comment from load_kernel
> * Rename cpu-model property to cpu-type
> * Drop some unnecessary inline function attributes
> * Don't allow GDB to set value of x0 register
> * Remove unnecessary empty property lists
> * Add Test Finisher device to implement poweroff in virt machine
> * Implement priv ISA v1.10 trap and sret/mret xPIE/xIE behavior
> * Store fflags data in fp_status
> * Purge runtime users of helper_raise_exception
> * Fix validate_csr
> * Tidy gen_jalr
> * Tidy immediate shifts
> * Add gen_exception_inst_addr_mis
> * Add gen_exception_debug
> * Add gen_exception_illegal
> * Tidy helper_fclass_*
> * Split rounding mode setting to a new function
> * Enforce MSTATUS_FS via TB flags
> * Implement acquire/release barrier semantics
> * Use atomic operations as required
> * Fix FENCE and FENCE_I
> * Remove commented code from spike machines
> * PAGE_WRITE permissions can be set on loads if page is already dirty
> * The result of format conversion on an NaN must be a quiet NaN
> * Add missing process_queued_cpu_work to riscv linux-user
> * Remove float(32|64)_classify from cpu.h
> * Removed nonsensical unions aliasing the same type
> * Use uintN_t instead of uintN_fast_t in fpu_helper.c
> * Use macros for FPU exception values in softfloat_flags_to_riscv
> * Move code to set round mode into set_fp_round_mode function
> * Convert set_fp_exceptions from a macro to an inline function
> * Convert round mode helper into an inline function
> * Make fpu_helper ieee_rm array static const
> * Include cpu_mmu_index in cpu_get_tb_cpu_state flags
> * Eliminate MPRV influence on mmu_index
> * Remove unrecoverable do_unassigned_access function
> * Only update PTE accessed and dirty bits if necessary
> * Remove unnecessary tlb_flush in set_mode as mode is in mmu_idx
> * Remove buggy support for misa writes. misa writes are optional
>   and are not implemented in any known hardware
> * Always set PTE read or execute permissions during page walk
> * Reorder helper function declarations to match order in helper.c
> * Remove redundant variable declaration in get_physical_address
> * Remove duplicated code from get_physical_address
> * Use mmu_idx instead of mem_idx in riscv_cpu_get_phys_page_debug
>
> v3
>
> * Fix indentation in PMP and HTIF debug macros
> * Fix disassembler checkpatch open brace '{' on next line errors
> * Fix trailing statements on next line in decode_inst_decompress
> * NOTE: the other checkpatch issues have been reviewed previously
>
> v2
>
> * Remove redundant NULL terminators from disassembler register arrays
> * Change disassembler register name arrays to const
> * Refine disassembler internal function names
> * Update dates in disassembler copyright message
> * Remove #ifdef CONFIG_USER_ONLY version of cpu_has_work
> * Use ULL suffix on 64-bit constants
> * Move riscv_cpu_mmu_index from cpu.h to helper.c
> * Move riscv_cpu_hw_interrupts_pending from cpu.h to helper.c
> * Remove redundant TARGET_HAS_ICE from cpu.h
> * Use qemu_irq instead of void* for irq definition in cpu.h
> * Remove duplicate typedef from struct CPURISCVState
> * Remove redundant g_strdup from cpu_register
> * Remove redundant tlb_flush from riscv_cpu_reset
> * Remove redundant mode calculation from get_physical_address
> * Remove redundant debug mode printf and dcsr comment
> * Remove redundant clearing of MSB for bare physical addresses
> * Use g_assert_not_reached for invalid mode in get_physical_address
> * Use g_assert_not_reached for unreachable checks in get_physical_address
> * Use g_assert_not_reached for unreachable type in raise_mmu_exception
> * Return exception instead of aborting for misaligned fetches
> * Move exception defines from cpu.h to cpu_bits.h
> * Remove redundant breakpoint control definitions from cpu_bits.h
> * Implement riscv_cpu_unassigned_access exception handling
> * Log and raise exceptions for unimplemented CSRs
> * Match Spike HTIF exit behavior - don’t print TEST-PASSED
> * Make frm,fflags,fcsr writes trap when mstatus.FS is clear
> * Use g_assert_not_reached for unreachable invalid mode
> * Make hret,uret,dret generate illegal instructions
> * Move riscv_cpu_dump_state and int/fpr regnames to cpu.c
> * Lift interrupt flag and mask into constants in cpu_bits.h
> * Change trap debugging to use qemu_log_mask LOG_TRACE
> * Change CSR debugging to use qemu_log_mask LOG_TRACE
> * Change PMP debugging to use qemu_log_mask LOG_TRACE
> * Remove commented code from pmp.c
> * Change CpuInfoRISCV qapi schema docs to Since 2.12
> * Change RV feature macro to use target_ulong cast
> * Remove riscv_feature and instead use misa extension flags
> * Make riscv_flush_icache_syscall a no-op
> * Undo checkpatch whitespace fixes in unrelated linux-user code
> * Remove redudant constants and tidy up cpu_bits.h
> * Make helper_fence_i a no-op
> * Move include "exec/cpu-all" to end of cpu.h
> * Rename set_privilege to riscv_set_mode
> * Move redundant forward declaration for cpu_riscv_translate_address
> * Remove TCGV_UNUSED from riscv_translate_init
> * Add comment to pmp.c stating the code is untested and currently unused
> * Use ctz to simplify decoding of PMP NAPOT address ranges
> * Change pmp_is_in_range to use than equal for end addresses
> * Fix off by one error in pmp_update_rule
> * Rearrange PMP_DEBUG so that formatting is compile-time checked
> * Rearrange trap debugging so that formatting is compile-time checked
> * Rearrange PLIC debugging so that formatting is compile-time checked
> * Use qemu_log/qemu_log_mask for HTIF logging and debugging
> * Move exception and interrupt names into cpu.c
> * Add Palmer Dabbelt as a RISC-V Maintainer
> * Rebase against current qemu master branch
>
> v1
>
> * initial version based on forward port from riscv-qemu repository
>
> *** Background ***
>
> "RISC-V is an open, free ISA enabling a new era of processor innovation
> through open standard collaboration. Born in academia and research,
> RISC-V ISA delivers a new level of free, extensible software and
> hardware freedom on architecture, paving the way for the next 50 years
> of computing design and innovation."
>
> The QEMU RISC-V port has been developed and maintained out-of-tree for
> several years by Sagar Karandikar and Bastian Koppelmann. The RISC-V
> Privileged specification has evolved substantially over this period but
> has recently been solidifying. The RISC-V Base ISA has been frozon for
> some time and the Privileged ISA, GCC toolchain and Linux ABI are now
> quite stable. I have recently joined Sagar and Bastian as a RISC-V QEMU
> Maintainer and hope to support upstreaming the port.
>
> There are multiple vendors taping out, preparing to ship, or shipping
> silicon that implements the RISC-V Privileged ISA Version 1.10. There
> are also several RISC-V Soft-IP cores implementing Privileged ISA
> Version 1.10 that run on FPGA such as SiFive's Freedom U500 Platform
> and the U54‑MC RISC-V Core IP, among many more implementations from a
> variety of vendors. See https://riscv.org/ for more details.
>
> RISC-V support was upstreamed in binutils 2.28 and GCC 7.1 in the first
> half of 2016. RISC-V support is now available in LLVM top-of-tree and
> the RISC-V Linux port was accepted into Linux 4.15-rc1 late last year
> and is available in the Linux 4.15 release. GLIBC 2.27 added support
> for the RISC-V ISA running on Linux (requires at least binutils-2.30,
> gcc-7.3.0, and linux-4.15). We believe it is timely to submit the
> RISC-V QEMU port for upstream review with the goal of incorporating
> RISC-V support into the upcoming QEMU 2.12 release.
>
> The RISC-V QEMU port is still under active development, mostly with
> respect to device emulation, the addition of Hypervisor support as
> specified in the RISC-V Draft Privileged ISA Version 1.11, and Vector
> support once the first draft is finalized later this year. We believe
> now is the appropriate time for RISC-V QEMU development to be carried
> out in the main QEMU repository as the code will benefit from more
> rigorous review. The RISC-V QEMU port currently supports all the ISA
> extensions that have been finalized and frozen in the Base ISA.
>
> Blog post about recent additions to RISC-V QEMU: https://goo.gl/fJ4zgk
>
> The RISC-V QEMU wiki: https://github.com/riscv/riscv-qemu/wiki
>
> Instructions for building a busybox+dropbear root image, BBL (Berkeley
> Boot Loader) and linux kernel image for use with the RISC-V QEMU
> 'virt' machine: https://github.com/michaeljclark/busybear-linux
>
> *** Overview ***
>
> The RISC-V QEMU port implements the following specifications:
>
> * RISC-V Instruction Set Manual Volume I: User-Level ISA Version 2.2
> * RISC-V Instruction Set Manual Volume II: Privileged ISA Version 1.9.1
> * RISC-V Instruction Set Manual Volume II: Privileged ISA Version 1.10
>
> The RISC-V QEMU port supports the following instruction set extensions:
>
> * RV32GC with Supervisor-mode and User-mode (RV32IMAFDCSU)
> * RV64GC with Supervisor-mode and User-mode (RV64IMAFDCSU)
>
> The RISC-V QEMU port adds the following targets to QEMU:
>
> * riscv32-softmmu
> * riscv64-softmmu
> * riscv32-linux-user
> * riscv64-linux-user
>
> The RISC-V QEMU port supports the following hardware:
>
> * HTIF Console (Host Target Interface)
> * SiFive CLINT (Core Local Interruptor) for Timer interrupts and IPIs
> * SiFive PLIC (Platform Level Interrupt Controller)
> * SiFive Test (Test Finisher) for exiting simulation
> * SiFive UART, PRCI, AON, PWM, QSPI support is partially implemented
> * VirtIO MMIO (GPEX PCI support will be added in a future patch)
> * Generic 16550A UART emulation using 'hw/char/serial.c'
> * MTTCG and SMP support (PLIC and CLINT) on the 'virt' machine
>
> The RISC-V QEMU full system emulator supports 5 machines:
>
> * 'spike_v1.9.1', CLINT, PLIC, HTIF console, config-string, Priv v1.9.1
> * 'spike_v1.10', CLINT, PLIC, HTIF console, device-tree, Priv v1.10
> * 'sifive_e', CLINT, PLIC, SiFive UART, HiFive1 compat, Priv v1.10
> * 'sifive_u', CLINT, PLIC, SiFive UART, device-tree, Priv v1.10
> * 'virt', CLINT, PLIC, 16550A UART, VirtIO, device-tree, Priv v1.10
>
> This is a list of RISC-V QEMU Port Contributors:
>
> * Alex Suykov
> * Andreas Schwab
> * Antony Pavlov
> * Bastian Koppelmann
> * Bruce Hoult
> * Chih-Min Chao
> * Daire McNamara
> * Darius Rad
> * David Abdurachmanov
> * Hesham Almatary
> * Ivan Griffin
> * Jim Wilson
> * Kito Cheng
> * Michael Clark
> * Palmer Dabbelt
> * Richard Henderson
> * Sagar Karandikar
> * Shea Levy
> * Stefan O'Rear
>
> Notes:
>
> * contributor email addresses available off-list on request.
> * checkpatch has been run on all 23 patches.
> * checkpatch exceptions are noted in patches that have errors.
> * passes "make check" on full build for all targets
> * tested riscv-linux-4.6.2 on 'spike_v1.9.1' machine
> * tested riscv-linux-4.15 on 'spike_v1.10' and 'virt' machines
> * tested SiFive HiFive1 binaries in 'sifive_e' machine
> * tested RV64 on 32-bit i386
>
> This patch series includes the following patches:
>
> - ----------------------------------------------------------------
> Michael Clark (45):
>       RISC-V Maintainers
>       RISC-V ELF Machine Definition
>       RISC-V CPU Core Definition
>       RISC-V Disassembler
>       RISC-V CPU Helpers
>       RISC-V FPU Support
>       RISC-V GDB Stub
>       RISC-V TCG Code Generation
>       RISC-V Physical Memory Protection
>       RISC-V Linux User Emulation
>       Add symbol table callback interface to load_elf
>       RISC-V HTIF Console
>       RISC-V HART Array
>       SiFive RISC-V CLINT Block
>       SiFive RISC-V PLIC Block
>       RISC-V Spike Machines
>       SiFive RISC-V Test Finisher
>       RISC-V VirtIO Machine
>       SiFive RISC-V UART Device
>       SiFive RISC-V PRCI Block
>       SiFive Freedom E Series RISC-V Machine
>       SiFive Freedom U Series RISC-V Machine
>       RISC-V Build Infrastructure
>       RISC-V - Make virt create_fdt interface consistent with other boards
>       RISC-V - Replace hardcoded device-tree constants with enum values
>       RISC-V - Make virt board description match spike format
>       RISC-V - Use ROM base address and size constants from memory map
>       RISC-V - Remove redundant identity_translate callback from load_elf
>       RISC-V - Mark ROM read-only after copying in reset vector and config
>       RISC-V - Remove unused class definitions from machines
>       RISC-V - Make sure the emulated mask rom has space for device-tree
>       RISC-V - Include hexidecimal instruction packets in disassembly
>       RISC-V - Need to hold rcu_read_lock when accessing memory directly
>       RISC-V - Improve page table walker spec compliance and add comments
>       RISC-V - Update E order and note that add E and I are mutually
> exclusive
>       RISC-V - Make spike and virt header guards more specific
>       RISC-V - Make virt header comment consistent with source file
>       RISC-V - Use memory_region_is_ram in atomic pte update
>       RISC-V - Remove EM_RISCV ELF_MACHINE indirection from load_elf
>       RISC-V - Ingore satp writes and return 0 for reads when no-mmu
>       RISC-V - Remove braces from satp case statement with no locals
>       RISC-V - riscv-qemu port supports sv39 and sv48
>       RISC-V - vectored traps for asynchrounous interrupts are optional
>       RISC-V - Dont' trap on writes to misa,minstret[h],mcycle[h]
>       RISC-V - Remove support for adhoc non-standard X_COP local-interrupt
>
>  MAINTAINERS                            |   11 +
>  arch_init.c                            |    2 +
>  configure                              |   13 +
>  cpus.c                                 |    6 +
>  default-configs/riscv32-linux-user.mak |    1 +
>  default-configs/riscv32-softmmu.mak    |    4 +
>  default-configs/riscv64-linux-user.mak |    1 +
>  default-configs/riscv64-softmmu.mak    |    4 +
>  disas.c                                |    2 +
>  disas/Makefile.objs                    |    1 +
>  disas/riscv.c                          | 3049
> ++++++++++++++++++++++++++++++++
>  fpu/softfloat-specialize.h             |    7 +-
>  hw/core/loader.c                       |   18 +-
>  hw/riscv/Makefile.objs                 |   11 +
>  hw/riscv/riscv_hart.c                  |   89 +
>  hw/riscv/riscv_htif.c                  |  258 +++
>  hw/riscv/sifive_clint.c                |  251 +++
>  hw/riscv/sifive_e.c                    |  204 +++
>  hw/riscv/sifive_plic.c                 |  505 ++++++
>  hw/riscv/sifive_prci.c                 |   89 +
>  hw/riscv/sifive_test.c                 |   93 +
>  hw/riscv/sifive_u.c                    |  316 ++++
>  hw/riscv/sifive_uart.c                 |  176 ++
>  hw/riscv/spike.c                       |  361 ++++
>  hw/riscv/virt.c                        |  395 +++++
>  include/disas/bfd.h                    |    2 +
>  include/elf.h                          |    2 +
>  include/hw/elf_ops.h                   |   34 +-
>  include/hw/loader.h                    |   17 +-
>  include/hw/riscv/riscv_hart.h          |   39 +
>  include/hw/riscv/riscv_htif.h          |   61 +
>  include/hw/riscv/sifive_clint.h        |   54 +
>  include/hw/riscv/sifive_e.h            |   70 +
>  include/hw/riscv/sifive_plic.h         |   85 +
>  include/hw/riscv/sifive_prci.h         |   37 +
>  include/hw/riscv/sifive_test.h         |   42 +
>  include/hw/riscv/sifive_u.h            |   64 +
>  include/hw/riscv/sifive_uart.h         |   71 +
>  include/hw/riscv/spike.h               |   49 +
>  include/hw/riscv/virt.h                |   67 +
>  include/sysemu/arch_init.h             |    1 +
>  linux-user/elfload.c                   |   22 +
>  linux-user/main.c                      |   99 ++
>  linux-user/riscv/syscall_nr.h          |  287 +++
>  linux-user/riscv/target_cpu.h          |   18 +
>  linux-user/riscv/target_elf.h          |   14 +
>  linux-user/riscv/target_signal.h       |   23 +
>  linux-user/riscv/target_structs.h      |   46 +
>  linux-user/riscv/target_syscall.h      |   56 +
>  linux-user/riscv/termbits.h            |  222 +++
>  linux-user/signal.c                    |  203 ++-
>  linux-user/syscall.c                   |    2 +
>  linux-user/syscall_defs.h              |   13 +-
>  qapi/misc.json                         |   17 +-
>  scripts/qemu-binfmt-conf.sh            |   13 +-
>  target/riscv/Makefile.objs             |    1 +
>  target/riscv/cpu.c                     |  432 +++++
>  target/riscv/cpu.h                     |  296 ++++
>  target/riscv/cpu_bits.h                |  408 +++++
>  target/riscv/cpu_user.h                |   13 +
>  target/riscv/fpu_helper.c              |  373 ++++
>  target/riscv/gdbstub.c                 |   62 +
>  target/riscv/helper.c                  |  530 ++++++
>  target/riscv/helper.h                  |   78 +
>  target/riscv/instmap.h                 |  364 ++++
>  target/riscv/op_helper.c               |  669 +++++++
>  target/riscv/pmp.c                     |  380 ++++
>  target/riscv/pmp.h                     |   64 +
>  target/riscv/translate.c               | 1978 +++++++++++++++++++++
>  69 files changed, 13218 insertions(+), 27 deletions(-)
>  create mode 100644 default-configs/riscv32-linux-user.mak
>  create mode 100644 default-configs/riscv32-softmmu.mak
>  create mode 100644 default-configs/riscv64-linux-user.mak
>  create mode 100644 default-configs/riscv64-softmmu.mak
>  create mode 100644 disas/riscv.c
>  create mode 100644 hw/riscv/Makefile.objs
>  create mode 100644 hw/riscv/riscv_hart.c
>  create mode 100644 hw/riscv/riscv_htif.c
>  create mode 100644 hw/riscv/sifive_clint.c
>  create mode 100644 hw/riscv/sifive_e.c
>  create mode 100644 hw/riscv/sifive_plic.c
>  create mode 100644 hw/riscv/sifive_prci.c
>  create mode 100644 hw/riscv/sifive_test.c
>  create mode 100644 hw/riscv/sifive_u.c
>  create mode 100644 hw/riscv/sifive_uart.c
>  create mode 100644 hw/riscv/spike.c
>  create mode 100644 hw/riscv/virt.c
>  create mode 100644 include/hw/riscv/riscv_hart.h
>  create mode 100644 include/hw/riscv/riscv_htif.h
>  create mode 100644 include/hw/riscv/sifive_clint.h
>  create mode 100644 include/hw/riscv/sifive_e.h
>  create mode 100644 include/hw/riscv/sifive_plic.h
>  create mode 100644 include/hw/riscv/sifive_prci.h
>  create mode 100644 include/hw/riscv/sifive_test.h
>  create mode 100644 include/hw/riscv/sifive_u.h
>  create mode 100644 include/hw/riscv/sifive_uart.h
>  create mode 100644 include/hw/riscv/spike.h
>  create mode 100644 include/hw/riscv/virt.h
>  create mode 100644 linux-user/riscv/syscall_nr.h
>  create mode 100644 linux-user/riscv/target_cpu.h
>  create mode 100644 linux-user/riscv/target_elf.h
>  create mode 100644 linux-user/riscv/target_signal.h
>  create mode 100644 linux-user/riscv/target_structs.h
>  create mode 100644 linux-user/riscv/target_syscall.h
>  create mode 100644 linux-user/riscv/termbits.h
>  create mode 100644 target/riscv/Makefile.objs
>  create mode 100644 target/riscv/cpu.c
>  create mode 100644 target/riscv/cpu.h
>  create mode 100644 target/riscv/cpu_bits.h
>  create mode 100644 target/riscv/cpu_user.h
>  create mode 100644 target/riscv/fpu_helper.c
>  create mode 100644 target/riscv/gdbstub.c
>  create mode 100644 target/riscv/helper.c
>  create mode 100644 target/riscv/helper.h
>  create mode 100644 target/riscv/instmap.h
>  create mode 100644 target/riscv/op_helper.c
>  create mode 100644 target/riscv/pmp.c
>  create mode 100644 target/riscv/pmp.h
>  create mode 100644 target/riscv/translate.c
> -----BEGIN PGP SIGNATURE-----
>
> iF0EARECAB0WIQR8mZMOsXzYugc9Xvpr8dezV+8+TwUCWp7voQAKCRBr8dezV+8+
> T3oeAKCjyrpCLo7ClB7epIA7vebNScpy7wCgjGjRt783KuDB0bpivU0aOnuqL3g=
> =neBa
> -----END PGP SIGNATURE-----
>

Re: [Qemu-devel] [PULL] RISC-V QEMU Port Submission v8.2

[Richard W.M. Jones]

On Wed, Mar 07, 2018 at 01:09:29PM +1300, Michael Clark wrote:
> Hopefully, this PR gets merged...

I hope so too.  We've been testing v8 (substantially the same as v8.2)
extensively, including SMP.  It's building hundreds of packages a day
in the autobuilder, and being used for manual builds by several
people.

Please don't forget about the softfloat fix!  Although it's not
specific to riscv-qemu, it is required for reliable operation and I
don't see if in the v8.2 tree.

Rich.

-- 
Richard Jones, Virtualization Group, Red Hat http://people.redhat.com/~rjones
Read my programming and virtualization blog: http://rwmj.wordpress.com
virt-p2v converts physical machines to virtual machines.  Boot with a
live CD or over the network (PXE) and turn machines into KVM guests.
http://libguestfs.org/virt-v2v

Re: [Qemu-devel] [PULL] RISC-V QEMU Port Submission v8.2

[Michael Clark]

On Wed, 7 Mar 2018 at 11:11 PM, Richard W.M. Jones <rjones@redhat.com>
wrote:

> On Wed, Mar 07, 2018 at 01:09:29PM +1300, Michael Clark wrote:
> > Hopefully, this PR gets merged...
>
> I hope so too.  We've been testing v8 (substantially the same as v8.2)
> extensively, including SMP.  It's building hundreds of packages a day
> in the autobuilder, and being used for manual builds by several
> people.
>
> Please don't forget about the softfloat fix!  Although it's not
> specific to riscv-qemu, it is required for reliable operation and I
> don't see if in the v8.2 tree.


I’ll try to get it in. I’ve reviewed the new minmax code and it should not
be difficult to add IEEE-754 201x minimumNumber/maximumNumber. I just ran
out of time today.

It’s a relatively rare corner case where the RISC-V behaviour is different
when an sNaN operand and a valid operand are provided to fmin/fmax. The
IEEE-754 201x minimumNumber/maximumNumber always returns the valid operand
when passed anyNaN and a valid operand however an sNaN operand causes the
invalid flag to be raised, whereas iirc the IEEE-764 2008 minNum/maxNum
will raise the invalid flag and return the sNaN when one operand is an sNaN
and the other is valid. Both of their behaviours are the same when passed
qNaN and a valid operand.

I have the test suite which includes both signalling and quiet NaN
fmin/fmax test cases so it is easy to verify and RISC-V is the only QEMU
port to use the IEEE-754 201x  minimumNumber/maximumNumber semantics so we
can easily isolate and test the change without affecting existing code.

Michael

Re: [Qemu-devel] [PULL] RISC-V QEMU Port Submission v8.2

[Peter Maydell]

On 6 March 2018 at 19:46, Michael Clark <mjc@sifive.com> wrote:
> -----BEGIN PGP SIGNED MESSAGE-----
> Hash: SHA1
>
> The following changes since commit f32408f3b472a088467474ab152be3b6285b2d7b:
>
>   misc: don't use hwaddr as a type in trace events (2018-03-06 14:24:30 +0000)
>
> are available in the git repository at:
>
>   https://github.com/riscv/riscv-qemu.git tags/riscv-qemu-upstream-v8.2
>
> for you to fetch changes up to 7051b081bf6796e5e84406f6223a7c4900bf7298:
>
>   RISC-V - Remove support for adhoc non-standard X_COP local-interrupt (2018-03-07 08:36:03 +1300)


Hi -- I would have applied this, but some of the commits
have no signed-off-by lines.

This is important, and I've already asked for it once. We cannot
accept anything that doesn't have a clear record in the commit
message of everybody (person or company) who's contributed code
to it, indicating that they're happy for their copyrighted
contributions to be taken into QEMU under our license. Lists
of names without emails in the cover letter are not sufficient.

In fact a lot of the last part of this patchset looks like
unreviewed changes/fixes that if we were going to have them we
should have squashed into the correct patches and resent the
series for review. Please don't do this. Code review is an
important part of how the QEMU project works.

thanks
-- PMM

Re: [Qemu-devel] [PULL] RISC-V QEMU Port Submission v8.2

[Michael Clark]

On Thu, 8 Mar 2018 at 11:02 PM, Peter Maydell <peter.maydell@linaro.org>
wrote:

> On 6 March 2018 at 19:46, Michael Clark <mjc@sifive.com> wrote:
> > -----BEGIN PGP SIGNED MESSAGE-----
> > Hash: SHA1
> >
> > The following changes since commit
> f32408f3b472a088467474ab152be3b6285b2d7b:
> >
> >   misc: don't use hwaddr as a type in trace events (2018-03-06 14:24:30
> +0000)
> >
> > are available in the git repository at:
> >
> >   https://github.com/riscv/riscv-qemu.git tags/riscv-qemu-upstream-v8.2
> >
> > for you to fetch changes up to 7051b081bf6796e5e84406f6223a7c4900bf7298:
> >
> >   RISC-V - Remove support for adhoc non-standard X_COP local-interrupt
> (2018-03-07 08:36:03 +1300)
>
>
> Hi -- I would have applied this, but some of the commits
> have no signed-off-by lines.
>
> This is important, and I've already asked for it once. We cannot
> accept anything that doesn't have a clear record in the commit
> message of everybody (person or company) who's contributed code
> to it, indicating that they're happy for their copyrighted
> contributions to be taken into QEMU under our license. Lists
> of names without emails in the cover letter are not sufficient.
>
> In fact a lot of the last part of this patchset looks like
> unreviewed changes/fixes that if we were going to have them we
> should have squashed into the correct patches and resent the
> series for review. Please don't do this. Code review is an
> important part of how the QEMU project works.


You must be looking at the wrong tag. There are multiple sign-offs in all
23 commits. The tag is riscv-qemu-upstream-v8.2. Sagar and Bastian
contacted me out of band to add their sign-offs. Please look at the commits
again and tell me which commit id doesn’t have a sign-off on that tag (23
commits iirc)

Michael

>
>

Re: [Qemu-devel] [PULL] RISC-V QEMU Port Submission v8.2

[Michael Clark]

On Fri, 9 Mar 2018 at 12:10 AM, Michael Clark <mjc@sifive.com> wrote:

> On Thu, 8 Mar 2018 at 11:02 PM, Peter Maydell <peter.maydell@linaro.org>
> wrote:
>
>> On 6 March 2018 at 19:46, Michael Clark <mjc@sifive.com> wrote:
>> > -----BEGIN PGP SIGNED MESSAGE-----
>> > Hash: SHA1
>> >
>> > The following changes since commit
>> f32408f3b472a088467474ab152be3b6285b2d7b:
>> >
>> >   misc: don't use hwaddr as a type in trace events (2018-03-06 14:24:30
>> +0000)
>> >
>> > are available in the git repository at:
>> >
>> >   https://github.com/riscv/riscv-qemu.git tags/riscv-qemu-upstream-v8.2
>> >
>> > for you to fetch changes up to 7051b081bf6796e5e84406f6223a7c4900bf7298:
>> >
>> >   RISC-V - Remove support for adhoc non-standard X_COP local-interrupt
>> (2018-03-07 08:36:03 +1300)
>>
>>
>> Hi -- I would have applied this, but some of the commits
>> have no signed-off-by lines.
>>
>> This is important, and I've already asked for it once. We cannot
>> accept anything that doesn't have a clear record in the commit
>> message of everybody (person or company) who's contributed code
>> to it, indicating that they're happy for their copyrighted
>> contributions to be taken into QEMU under our license. Lists
>> of names without emails in the cover letter are not sufficient.
>>
>> In fact a lot of the last part of this patchset looks like
>> unreviewed changes/fixes that if we were going to have them we
>> should have squashed into the correct patches and resent the
>> series for review. Please don't do this. Code review is an
>> important part of how the QEMU project works.
>
>
> You must be looking at the wrong tag. There are multiple sign-offs in all
> 23 commits. The tag is riscv-qemu-upstream-v8.2. Sagar and Bastian
> contacted me out of band to add their sign-offs. Please look at the commits
> again and tell me which commit id doesn’t have a sign-off on that tag (23
> commits iirc)
>

I can forward you the mail out-of-band. I had to contact contributors to
get them to agree to change the license from MIT to GPLv2, based on a
request from Red Hat.

You are making this very hard. Do you work for Arm perchance? I really
wouldn’t be surprised if our port is being sandbagged by Arm. Apologies for
being so direct about this, but things like this happen...

I have complied with practically every review request and the sign-offs are
there. It’s a bit ridiculous.

It would be nice to find someone neutral, unrelated to Arm, to merge our PR

>

Re: [Qemu-devel] [PULL] RISC-V QEMU Port Submission v8.2

[Peter Maydell]

On 8 March 2018 at 11:10, Michael Clark <mjc@sifive.com> wrote:
>
> On Thu, 8 Mar 2018 at 11:02 PM, Peter Maydell <peter.maydell@linaro.org>
> wrote:
>>
>> On 6 March 2018 at 19:46, Michael Clark <mjc@sifive.com> wrote:
>> > -----BEGIN PGP SIGNED MESSAGE-----
>> > Hash: SHA1
>> >
>> > The following changes since commit
>> > f32408f3b472a088467474ab152be3b6285b2d7b:
>> >
>> >   misc: don't use hwaddr as a type in trace events (2018-03-06 14:24:30
>> > +0000)
>> >
>> > are available in the git repository at:
>> >
>> >   https://github.com/riscv/riscv-qemu.git tags/riscv-qemu-upstream-v8.2
>> >
>> > for you to fetch changes up to 7051b081bf6796e5e84406f6223a7c4900bf7298:
>> >
>> >   RISC-V - Remove support for adhoc non-standard X_COP local-interrupt
>> > (2018-03-07 08:36:03 +1300)
>>
>>
>> Hi -- I would have applied this, but some of the commits
>> have no signed-off-by lines.
>>
>> This is important, and I've already asked for it once. We cannot
>> accept anything that doesn't have a clear record in the commit
>> message of everybody (person or company) who's contributed code
>> to it, indicating that they're happy for their copyrighted
>> contributions to be taken into QEMU under our license. Lists
>> of names without emails in the cover letter are not sufficient.
>>
>> In fact a lot of the last part of this patchset looks like
>> unreviewed changes/fixes that if we were going to have them we
>> should have squashed into the correct patches and resent the
>> series for review. Please don't do this. Code review is an
>> important part of how the QEMU project works.
>
>
> You must be looking at the wrong tag. There are multiple sign-offs in all 23
> commits. The tag is riscv-qemu-upstream-v8.2. Sagar and Bastian contacted me
> out of band to add their sign-offs. Please look at the commits again and
> tell me which commit id doesn’t have a sign-off on that tag (23 commits
> iirc)

I'm looking at the one this email tells me to pull:
  https://github.com/riscv/riscv-qemu.git tags/riscv-qemu-upstream-v8.2
  changes up to 7051b081bf6796e5e84406f6223a7c4900bf7298

Commit 7051b081bf6796e5e84406f6223a7c4900bf7298,
9390ed5f4ca5fd3bde10ee2dcf4e7d915d1c189d,
b38548c4057fb670950a4b94efe5c03b8aba4118,
etc etc all have no signoff.

thanks
-- PHMM

Re: [Qemu-devel] [PULL] RISC-V QEMU Port Submission v8.2

[Daniel P. Berrangé]

On Thu, Mar 08, 2018 at 11:10:00AM +0000, Michael Clark wrote:
> On Thu, 8 Mar 2018 at 11:02 PM, Peter Maydell <peter.maydell@linaro.org>
> wrote:
> 
> > On 6 March 2018 at 19:46, Michael Clark <mjc@sifive.com> wrote:
> > > -----BEGIN PGP SIGNED MESSAGE-----
> > > Hash: SHA1
> > >
> > > The following changes since commit
> > f32408f3b472a088467474ab152be3b6285b2d7b:
> > >
> > >   misc: don't use hwaddr as a type in trace events (2018-03-06 14:24:30
> > +0000)
> > >
> > > are available in the git repository at:
> > >
> > >   https://github.com/riscv/riscv-qemu.git tags/riscv-qemu-upstream-v8.2
> > >
> > > for you to fetch changes up to 7051b081bf6796e5e84406f6223a7c4900bf7298:
> > >
> > >   RISC-V - Remove support for adhoc non-standard X_COP local-interrupt
> > (2018-03-07 08:36:03 +1300)
> >
> >
> > Hi -- I would have applied this, but some of the commits
> > have no signed-off-by lines.
> >
> > This is important, and I've already asked for it once. We cannot
> > accept anything that doesn't have a clear record in the commit
> > message of everybody (person or company) who's contributed code
> > to it, indicating that they're happy for their copyrighted
> > contributions to be taken into QEMU under our license. Lists
> > of names without emails in the cover letter are not sufficient.
> >
> > In fact a lot of the last part of this patchset looks like
> > unreviewed changes/fixes that if we were going to have them we
> > should have squashed into the correct patches and resent the
> > series for review. Please don't do this. Code review is an
> > important part of how the QEMU project works.
> 
> 
> You must be looking at the wrong tag. There are multiple sign-offs in all
> 23 commits. The tag is riscv-qemu-upstream-v8.2. Sagar and Bastian
> contacted me out of band to add their sign-offs. Please look at the commits
> again and tell me which commit id doesn’t have a sign-off on that tag (23
> commits iirc)

I've just looked at the "riscv-qemu-upstream-v8.2" tag and confirm that
the sign-offs all appear present and corrrect to me.

There's checkpatch failures on several commits, but you've documented
rationale for ignoring the genuine failures, and the other failures are
false positives.

Regards,
Daniel
-- 
|: https://berrange.com      -o-    https://www.flickr.com/photos/dberrange :|
|: https://libvirt.org         -o-            https://fstop138.berrange.com :|
|: https://entangle-photo.org    -o-    https://www.instagram.com/dberrange :|

Re: [Qemu-devel] [PULL] RISC-V QEMU Port Submission v8.2

[Daniel P. Berrangé]

On Thu, Mar 08, 2018 at 11:19:30AM +0000, Peter Maydell wrote:
> On 8 March 2018 at 11:10, Michael Clark <mjc@sifive.com> wrote:
> >
> > On Thu, 8 Mar 2018 at 11:02 PM, Peter Maydell <peter.maydell@linaro.org>
> > wrote:
> >>
> >> On 6 March 2018 at 19:46, Michael Clark <mjc@sifive.com> wrote:
> >> > -----BEGIN PGP SIGNED MESSAGE-----
> >> > Hash: SHA1
> >> >
> >> > The following changes since commit
> >> > f32408f3b472a088467474ab152be3b6285b2d7b:
> >> >
> >> >   misc: don't use hwaddr as a type in trace events (2018-03-06 14:24:30
> >> > +0000)
> >> >
> >> > are available in the git repository at:
> >> >
> >> >   https://github.com/riscv/riscv-qemu.git tags/riscv-qemu-upstream-v8.2
> >> >
> >> > for you to fetch changes up to 7051b081bf6796e5e84406f6223a7c4900bf7298:
> >> >
> >> >   RISC-V - Remove support for adhoc non-standard X_COP local-interrupt
> >> > (2018-03-07 08:36:03 +1300)
> >>
> >>
> >> Hi -- I would have applied this, but some of the commits
> >> have no signed-off-by lines.
> >>
> >> This is important, and I've already asked for it once. We cannot
> >> accept anything that doesn't have a clear record in the commit
> >> message of everybody (person or company) who's contributed code
> >> to it, indicating that they're happy for their copyrighted
> >> contributions to be taken into QEMU under our license. Lists
> >> of names without emails in the cover letter are not sufficient.
> >>
> >> In fact a lot of the last part of this patchset looks like
> >> unreviewed changes/fixes that if we were going to have them we
> >> should have squashed into the correct patches and resent the
> >> series for review. Please don't do this. Code review is an
> >> important part of how the QEMU project works.
> >
> >
> > You must be looking at the wrong tag. There are multiple sign-offs in all 23
> > commits. The tag is riscv-qemu-upstream-v8.2. Sagar and Bastian contacted me
> > out of band to add their sign-offs. Please look at the commits again and
> > tell me which commit id doesn’t have a sign-off on that tag (23 commits
> > iirc)
> 
> I'm looking at the one this email tells me to pull:
>   https://github.com/riscv/riscv-qemu.git tags/riscv-qemu-upstream-v8.2
>   changes up to 7051b081bf6796e5e84406f6223a7c4900bf7298
> 
> Commit 7051b081bf6796e5e84406f6223a7c4900bf7298,
> 9390ed5f4ca5fd3bde10ee2dcf4e7d915d1c189d,
> b38548c4057fb670950a4b94efe5c03b8aba4118,
> etc etc all have no signoff.

There's something peculiar going on when fetching the PR.

I did a 'git fetch riscv/riscv-qemu-upstream-v8.2' which pulled into
FETCH_HEAD. If i do 'git log FETCH_HEAD' then I see those commits
you mention as missing signoff.  If I instead do 'git log riscv-qemu-upstream-v8.2'
then all the commits have signoffs - it ranges 
4dc62b15323bb6338c4b426f76e92be55f87db8c...25fa194b7b11901561532e435beb83d046899f7a.

I'm confused why pulling the tag is populating extra commits into
FETCH_HEAD, that are seemingly not part of the tag.

Regards,
Daniel
-- 
|: https://berrange.com      -o-    https://www.flickr.com/photos/dberrange :|
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Re: [Qemu-devel] [PULL] RISC-V QEMU Port Submission v8.2

[Michael Clark]

On Fri, 9 Mar 2018 at 12:18 AM, Michael Clark <mjc@sifive.com> wrote:

> On Fri, 9 Mar 2018 at 12:10 AM, Michael Clark <mjc@sifive.com> wrote:
>
>> On Thu, 8 Mar 2018 at 11:02 PM, Peter Maydell <peter.maydell@linaro.org>
>> wrote:
>>
>>> On 6 March 2018 at 19:46, Michael Clark <mjc@sifive.com> wrote:
>>> > -----BEGIN PGP SIGNED MESSAGE-----
>>> > Hash: SHA1
>>> >
>>> > The following changes since commit
>>> f32408f3b472a088467474ab152be3b6285b2d7b:
>>> >
>>> >   misc: don't use hwaddr as a type in trace events (2018-03-06
>>> 14:24:30 +0000)
>>> >
>>> > are available in the git repository at:
>>> >
>>> >   https://github.com/riscv/riscv-qemu.git
>>> tags/riscv-qemu-upstream-v8.2
>>> >
>>> > for you to fetch changes up to
>>> 7051b081bf6796e5e84406f6223a7c4900bf7298:
>>> >
>>> >   RISC-V - Remove support for adhoc non-standard X_COP local-interrupt
>>> (2018-03-07 08:36:03 +1300)
>>>
>>>
>>> Hi -- I would have applied this, but some of the commits
>>> have no signed-off-by lines.
>>>
>>> This is important, and I've already asked for it once. We cannot
>>> accept anything that doesn't have a clear record in the commit
>>> message of everybody (person or company) who's contributed code
>>> to it, indicating that they're happy for their copyrighted
>>> contributions to be taken into QEMU under our license. Lists
>>> of names without emails in the cover letter are not sufficient.
>>>
>>> In fact a lot of the last part of this patchset looks like
>>> unreviewed changes/fixes that if we were going to have them we
>>> should have squashed into the correct patches and resent the
>>> series for review. Please don't do this. Code review is an
>>> important part of how the QEMU project works.
>>
>>
>> You must be looking at the wrong tag. There are multiple sign-offs in all
>> 23 commits. The tag is riscv-qemu-upstream-v8.2. Sagar and Bastian
>> contacted me out of band to add their sign-offs. Please look at the commits
>> again and tell me which commit id doesn’t have a sign-off on that tag (23
>> commits iirc)
>>
>
> I can forward you the mail out-of-band. I had to contact contributors to
> get them to agree to change the license from MIT to GPLv2, based on a
> request from Red Hat.
>
> You are making this very hard. Do you work for Arm perchance? I really
> wouldn’t be surprised if our port is being sandbagged by Arm. Apologies for
> being so direct about this, but things like this happen...
>
> I have complied with practically every review request and the sign-offs
> are there. It’s a bit ridiculous.
>
> It would be nice to find someone neutral, unrelated to Arm, to merge our PR
>

Some history on the origins of RISC to put things in perspective:

https://en.m.wikipedia.org/wiki/Berkeley_RISC

David Patterson worked with Andrew Waterman and Krste Asanovic on the
design of RISC-V. Sagar did most of the work on the QEMU port and he
agreeded to sign off on all patches. The SiFive patches only have sign-offs
from SiFive because SiFive was the sole contributor for its hardware model,
beside the SiFiveUART which has Stefan’s sign-off.

In any case it seems there is not enough review bandwidth in the QEMU
project as a whole and the policy to accept contributions is too strict to
be reasonable, given earnest attempts to comply with *all* review feedback.
Not impressed.

>

Re: [Qemu-devel] [PULL] RISC-V QEMU Port Submission v8.2

[Daniel P. Berrangé]

On Thu, Mar 08, 2018 at 11:33:13AM +0000, Daniel P. Berrangé wrote:
> On Thu, Mar 08, 2018 at 11:10:00AM +0000, Michael Clark wrote:
> > On Thu, 8 Mar 2018 at 11:02 PM, Peter Maydell <peter.maydell@linaro.org>
> > wrote:
> > 
> > > On 6 March 2018 at 19:46, Michael Clark <mjc@sifive.com> wrote:
> > > > -----BEGIN PGP SIGNED MESSAGE-----
> > > > Hash: SHA1
> > > >
> > > > The following changes since commit
> > > f32408f3b472a088467474ab152be3b6285b2d7b:
> > > >
> > > >   misc: don't use hwaddr as a type in trace events (2018-03-06 14:24:30
> > > +0000)
> > > >
> > > > are available in the git repository at:
> > > >
> > > >   https://github.com/riscv/riscv-qemu.git tags/riscv-qemu-upstream-v8.2
> > > >
> > > > for you to fetch changes up to 7051b081bf6796e5e84406f6223a7c4900bf7298:
> > > >
> > > >   RISC-V - Remove support for adhoc non-standard X_COP local-interrupt
> > > (2018-03-07 08:36:03 +1300)
> > >
> > >
> > > Hi -- I would have applied this, but some of the commits
> > > have no signed-off-by lines.
> > >
> > > This is important, and I've already asked for it once. We cannot
> > > accept anything that doesn't have a clear record in the commit
> > > message of everybody (person or company) who's contributed code
> > > to it, indicating that they're happy for their copyrighted
> > > contributions to be taken into QEMU under our license. Lists
> > > of names without emails in the cover letter are not sufficient.
> > >
> > > In fact a lot of the last part of this patchset looks like
> > > unreviewed changes/fixes that if we were going to have them we
> > > should have squashed into the correct patches and resent the
> > > series for review. Please don't do this. Code review is an
> > > important part of how the QEMU project works.
> > 
> > 
> > You must be looking at the wrong tag. There are multiple sign-offs in all
> > 23 commits. The tag is riscv-qemu-upstream-v8.2. Sagar and Bastian
> > contacted me out of band to add their sign-offs. Please look at the commits
> > again and tell me which commit id doesn’t have a sign-off on that tag (23
> > commits iirc)
> 
> I've just looked at the "riscv-qemu-upstream-v8.2" tag and confirm that
> the sign-offs all appear present and corrrect to me.

Actually after double checking this not correct. There are two similarly
named but subtely different tags.

Your mail referenced 'riscv-qemu-upstream-v8.2' and that does contain
extra commits without signoffs.

There is another tag 'qemu-upstream-v8.2' that contains only the
signed-off commits.

So did you mention the wrong tag in the cover letter, or push the
wrong content ?

Regards,
Daniel
-- 
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|: https://libvirt.org         -o-            https://fstop138.berrange.com :|
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Re: [Qemu-devel] [PULL] RISC-V QEMU Port Submission v8.2

[Daniel P. Berrangé]

On Thu, Mar 08, 2018 at 11:18:30AM +0000, Michael Clark wrote:
> On Fri, 9 Mar 2018 at 12:10 AM, Michael Clark <mjc@sifive.com> wrote:
> 
> > On Thu, 8 Mar 2018 at 11:02 PM, Peter Maydell <peter.maydell@linaro.org>
> > wrote:
> >
> >> On 6 March 2018 at 19:46, Michael Clark <mjc@sifive.com> wrote:
> >> > -----BEGIN PGP SIGNED MESSAGE-----
> >> > Hash: SHA1
> >> >
> >> > The following changes since commit
> >> f32408f3b472a088467474ab152be3b6285b2d7b:
> >> >
> >> >   misc: don't use hwaddr as a type in trace events (2018-03-06 14:24:30
> >> +0000)
> >> >
> >> > are available in the git repository at:
> >> >
> >> >   https://github.com/riscv/riscv-qemu.git tags/riscv-qemu-upstream-v8.2
> >> >
> >> > for you to fetch changes up to 7051b081bf6796e5e84406f6223a7c4900bf7298:
> >> >
> >> >   RISC-V - Remove support for adhoc non-standard X_COP local-interrupt
> >> (2018-03-07 08:36:03 +1300)
> >>
> >>
> >> Hi -- I would have applied this, but some of the commits
> >> have no signed-off-by lines.
> >>
> >> This is important, and I've already asked for it once. We cannot
> >> accept anything that doesn't have a clear record in the commit
> >> message of everybody (person or company) who's contributed code
> >> to it, indicating that they're happy for their copyrighted
> >> contributions to be taken into QEMU under our license. Lists
> >> of names without emails in the cover letter are not sufficient.
> >>
> >> In fact a lot of the last part of this patchset looks like
> >> unreviewed changes/fixes that if we were going to have them we
> >> should have squashed into the correct patches and resent the
> >> series for review. Please don't do this. Code review is an
> >> important part of how the QEMU project works.
> >
> >
> > You must be looking at the wrong tag. There are multiple sign-offs in all
> > 23 commits. The tag is riscv-qemu-upstream-v8.2. Sagar and Bastian
> > contacted me out of band to add their sign-offs. Please look at the commits
> > again and tell me which commit id doesn’t have a sign-off on that tag (23
> > commits iirc)
> >
> 
> I can forward you the mail out-of-band. I had to contact contributors to
> get them to agree to change the license from MIT to GPLv2, based on a
> request from Red Hat.
> 
> You are making this very hard. Do you work for Arm perchance? I really
> wouldn’t be surprised if our port is being sandbagged by Arm. Apologies for
> being so direct about this, but things like this happen...
> 
> I have complied with practically every review request and the sign-offs are
> there. It’s a bit ridiculous.
> 
> It would be nice to find someone neutral, unrelated to Arm, to merge our PR

Please stop with these ridiculous conspiracy theories right away. It is a
totally inappropriate and baseless accusation to make. 

Peter is not trying to punish you with extra rules. Over time QEMU has been 
raising the bar for *all* contributions with extra code style checks,
automated testing, and review. Unfortunately this does mean that the larger
the patch series / feature, the more work is required to get to a mergable
state, especially if the contributors are not previously familiar with QEMU
development. 

Regards,
Daniel
-- 
|: https://berrange.com      -o-    https://www.flickr.com/photos/dberrange :|
|: https://libvirt.org         -o-            https://fstop138.berrange.com :|
|: https://entangle-photo.org    -o-    https://www.instagram.com/dberrange :|

Re: [Qemu-devel] [PULL] RISC-V QEMU Port Submission v8.2

[Paolo Bonzini]

On 08/03/2018 12:18, Michael Clark wrote:
>> There are multiple sign-offs in all
>> 23 commits. The tag is riscv-qemu-upstream-v8.2

Except your cover letter lists 45 commits and, as Daniel has already confirmed,
Peter is right: these commits listed in the cover letter have no sign-off and
have not been reviewed:

      RISC-V - Make virt create_fdt interface consistent with other boards
      RISC-V - Replace hardcoded device-tree constants with enum values
      RISC-V - Make virt board description match spike format
      RISC-V - Use ROM base address and size constants from memory map
      RISC-V - Remove redundant identity_translate callback from load_elf
      RISC-V - Mark ROM read-only after copying in reset vector and config
      RISC-V - Remove unused class definitions from machines
      RISC-V - Make sure the emulated mask rom has space for device-tree
      RISC-V - Include hexidecimal instruction packets in disassembly
      RISC-V - Need to hold rcu_read_lock when accessing memory directly
      RISC-V - Improve page table walker spec compliance and add comments
      RISC-V - Update E order and note that add E and I are mutually exclusive
      RISC-V - Make spike and virt header guards more specific
      RISC-V - Make virt header comment consistent with source file
      RISC-V - Use memory_region_is_ram in atomic pte update
      RISC-V - Remove EM_RISCV ELF_MACHINE indirection from load_elf
      RISC-V - Ingore satp writes and return 0 for reads when no-mmu
      RISC-V - Remove braces from satp case statement with no locals
      RISC-V - riscv-qemu port supports sv39 and sv48
      RISC-V - vectored traps for asynchrounous interrupts are optional
      RISC-V - Dont' trap on writes to misa,minstret[h],mcycle[h]
      RISC-V - Remove support for adhoc non-standard X_COP local-interrupt

> You are making this very hard. Do you work for Arm perchance? I really
> wouldn’t be surprised if our port is being sandbagged by Arm. Apologies for
> being so direct about this, but things like this happen...
> 
> I have complied with practically every review request and the sign-offs are
> there. It’s a bit ridiculous.
> 
> It would be nice to find someone neutral, unrelated to Arm, to merge our PR

Just don't do this.  If you don't trust the maintainers, I don't see why 
the maintainers should merge the RISC-V port; no one needs an history
lesson on RISC or ARM or RISC-V either.  And you can understand that adding
and reviewing 10K lines of code requires a significant effort, that some of
the maintainers are doing in their spare time.

In fact, I looked at "RISC-V - Need to hold rcu_read_lock when accessing
memory directly" and from a first look it's wrong.  So I think you owe an
apology...

Paolo

Re: [Qemu-devel] [PULL] RISC-V QEMU Port Submission v8.2

[Stefan Hajnoczi]

On Thu, Mar 8, 2018 at 11:41 AM, Michael Clark <mjc@sifive.com> wrote:
> On Fri, 9 Mar 2018 at 12:18 AM, Michael Clark <mjc@sifive.com> wrote:
>
>> On Fri, 9 Mar 2018 at 12:10 AM, Michael Clark <mjc@sifive.com> wrote:
>>
>>> On Thu, 8 Mar 2018 at 11:02 PM, Peter Maydell <peter.maydell@linaro.org>
>>> wrote:
>>>
>>>> On 6 March 2018 at 19:46, Michael Clark <mjc@sifive.com> wrote:
>>>> > -----BEGIN PGP SIGNED MESSAGE-----
>>>> > Hash: SHA1
>>>> >
>>>> > The following changes since commit
>>>> f32408f3b472a088467474ab152be3b6285b2d7b:
>>>> >
>>>> >   misc: don't use hwaddr as a type in trace events (2018-03-06
>>>> 14:24:30 +0000)
>>>> >
>>>> > are available in the git repository at:
>>>> >
>>>> >   https://github.com/riscv/riscv-qemu.git
>>>> tags/riscv-qemu-upstream-v8.2
>>>> >
>>>> > for you to fetch changes up to
>>>> 7051b081bf6796e5e84406f6223a7c4900bf7298:
>>>> >
>>>> >   RISC-V - Remove support for adhoc non-standard X_COP local-interrupt
>>>> (2018-03-07 08:36:03 +1300)
>>>>
>>>>
>>>> Hi -- I would have applied this, but some of the commits
>>>> have no signed-off-by lines.
>>>>
>>>> This is important, and I've already asked for it once. We cannot
>>>> accept anything that doesn't have a clear record in the commit
>>>> message of everybody (person or company) who's contributed code
>>>> to it, indicating that they're happy for their copyrighted
>>>> contributions to be taken into QEMU under our license. Lists
>>>> of names without emails in the cover letter are not sufficient.
>>>>
>>>> In fact a lot of the last part of this patchset looks like
>>>> unreviewed changes/fixes that if we were going to have them we
>>>> should have squashed into the correct patches and resent the
>>>> series for review. Please don't do this. Code review is an
>>>> important part of how the QEMU project works.
>>>
>>>
>>> You must be looking at the wrong tag. There are multiple sign-offs in all
>>> 23 commits. The tag is riscv-qemu-upstream-v8.2. Sagar and Bastian
>>> contacted me out of band to add their sign-offs. Please look at the commits
>>> again and tell me which commit id doesn’t have a sign-off on that tag (23
>>> commits iirc)
>>>
>>
>> I can forward you the mail out-of-band. I had to contact contributors to
>> get them to agree to change the license from MIT to GPLv2, based on a
>> request from Red Hat.
>>
>> You are making this very hard. Do you work for Arm perchance? I really
>> wouldn’t be surprised if our port is being sandbagged by Arm. Apologies for
>> being so direct about this, but things like this happen...
>>
>> I have complied with practically every review request and the sign-offs
>> are there. It’s a bit ridiculous.
>>
>> It would be nice to find someone neutral, unrelated to Arm, to merge our PR
>>
>
> Some history on the origins of RISC to put things in perspective:
>
> https://en.m.wikipedia.org/wiki/Berkeley_RISC
>
> David Patterson worked with Andrew Waterman and Krste Asanovic on the
> design of RISC-V. Sagar did most of the work on the QEMU port and he
> agreeded to sign off on all patches. The SiFive patches only have sign-offs
> from SiFive because SiFive was the sole contributor for its hardware model,
> beside the SiFiveUART which has Stefan’s sign-off.
>
> In any case it seems there is not enough review bandwidth in the QEMU
> project as a whole and the policy to accept contributions is too strict to
> be reasonable, given earnest attempts to comply with *all* review feedback.
> Not impressed.

Please take a break and stop sending emails which are going to offend
the people you need to collaborate with in order to get RISC-V support
merged.

The issues that Peter Maydell raised are completely routine pull
request requirements.  Linux has the same Signed-off-by requirement,
so it's not a QEMU-specific hurdle.

If you want to be the RISC-V maintainer in QEMU then work with Peter
Maydell (qemu.git maintainer).

Stefan

Re: [Qemu-devel] [PULL] RISC-V QEMU Port Submission v8.2

[Daniel P. Berrangé]

On Wed, Mar 07, 2018 at 08:46:26AM +1300, Michael Clark wrote:
> -----BEGIN PGP SIGNED MESSAGE-----
> Hash: SHA1
> 
> The following changes since commit f32408f3b472a088467474ab152be3b6285b2d7b:
> 
>   misc: don't use hwaddr as a type in trace events (2018-03-06 14:24:30 +0000)
> 
> are available in the git repository at:
> 
>   https://github.com/riscv/riscv-qemu.git tags/riscv-qemu-upstream-v8.2
> 
> for you to fetch changes up to 7051b081bf6796e5e84406f6223a7c4900bf7298:
> 
>   RISC-V - Remove support for adhoc non-standard X_COP local-interrupt (2018-03-07 08:36:03 +1300)

So to move this forward in a productive way....

IIUC, the 'qemu-upstream-v8.2' branch has the correct set of 23
patches, but the 'riscv-qemu-upstream-v8.2' tag has mistakenly
gained a bunch of extra patches that were not intended for
submission yet.

So I think you likely just need to create a v8.3 branch and
tag with the correct set of 23 commits. Though, do note Paolo's
comment about logic looking wrong in one of the patches. I'm
not sure if that's something we can live with now, and fix
up in followup patches before release or not, vs should be
fixed right away.

The 'soft freeze' on next Tuesday only applies to feature
patches. So assuming we can get this initial series mergable,
you will still have time to send more pull requests with bug
fixes before release.


Regards,
Daniel
-- 
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Re: [Qemu-devel] [PULL] RISC-V QEMU Port Submission v8.2

[Paolo Bonzini]

On 08/03/2018 13:25, Daniel P. Berrangé wrote:
> So I think you likely just need to create a v8.3 branch and
> tag with the correct set of 23 commits. Though, do note Paolo's
> comment about logic looking wrong in one of the patches. I'm
> not sure if that's something we can live with now, and fix
> up in followup patches before release or not, vs should be
> fixed right away.
> 

Luckily the logic is wrong in one of the extra 22 commits.

Paolo

Re: [Qemu-devel] [patches] Re: [PULL] RISC-V QEMU Port Submission v8.2

[Palmer Dabbelt]

On Thu, 08 Mar 2018 03:41:33 PST (-0800), Michael Clark wrote:
> On Fri, 9 Mar 2018 at 12:18 AM, Michael Clark <mjc@sifive.com> wrote:
>> On Fri, 9 Mar 2018 at 12:10 AM, Michael Clark <mjc@sifive.com> wrote:
>>> On Thu, 8 Mar 2018 at 11:02 PM, Peter Maydell <peter.maydell@linaro.org>
>>> wrote:
>>>> On 6 March 2018 at 19:46, Michael Clark <mjc@sifive.com> wrote:
>> You are making this very hard. Do you work for Arm perchance? I really
>> wouldn’t be surprised if our port is being sandbagged by Arm. Apologies for
>> being so direct about this, but things like this happen...
>>
>> I have complied with practically every review request and the sign-offs
>> are there. It’s a bit ridiculous.
>>
>> It would be nice to find someone neutral, unrelated to Arm, to merge our PR
>>
>
> Some history on the origins of RISC to put things in perspective:
>
> https://en.m.wikipedia.org/wiki/Berkeley_RISC
>
> David Patterson worked with Andrew Waterman and Krste Asanovic on the
> design of RISC-V. Sagar did most of the work on the QEMU port and he
> agreeded to sign off on all patches. The SiFive patches only have sign-offs
> from SiFive because SiFive was the sole contributor for its hardware model,
> beside the SiFiveUART which has Stefan’s sign-off.
>
> In any case it seems there is not enough review bandwidth in the QEMU
> project as a whole and the policy to accept contributions is too strict to
> be reasonable, given earnest attempts to comply with *all* review feedback.
> Not impressed.

On behalf of the rest of the RISC-V QEMU team I'd like to apologize for 
Michael's comments.  That's a pretty insulting thing to say, and the whole 
thing comes off as a bit entitled: we've asked the QEMU community to do a lot 
of work for us in reviewing our port, and seeing as how none of us are QEMU 
contributors we certainly don't have any grounds to ask someone to stop 
reviewing it -- that's pretty absurd.

While I haven't been following the upstreaming process as closely as I should 
have been, as far as I can tell there's no grounds to accuse Peter, or anyone 
else, of trying to shoot down our port for any reason.  Peter, I can understand 
if you're upset, as I certainly would be.  If you don't want to help out with 
our port any more then I can understand, but I'd just like to assure you that 
we value the time you've spent on our port and hope you continue to help out!

Hopefully this doesn't derail our chances of moving forward with submitting the 
RISC-V port upstream.

Sorry!

Re: [Qemu-devel] [patches] Re: [PULL] RISC-V QEMU Port Submission v8.2

[Michael Clark]

On Fri, Mar 9, 2018 at 8:29 AM, Palmer Dabbelt <palmer@sifive.com> wrote:

> On Thu, 08 Mar 2018 03:41:33 PST (-0800), Michael Clark wrote:
>
>> On Fri, 9 Mar 2018 at 12:18 AM, Michael Clark <mjc@sifive.com> wrote:
>>
>>> On Fri, 9 Mar 2018 at 12:10 AM, Michael Clark <mjc@sifive.com> wrote:
>>>
>>>> On Thu, 8 Mar 2018 at 11:02 PM, Peter Maydell <peter.maydell@linaro.org
>>>> >
>>>> wrote:
>>>>
>>>>> On 6 March 2018 at 19:46, Michael Clark <mjc@sifive.com> wrote:
>>>>>
>>>> You are making this very hard. Do you work for Arm perchance? I really
>>> wouldn’t be surprised if our port is being sandbagged by Arm. Apologies
>>> for
>>> being so direct about this, but things like this happen...
>>>
>>> I have complied with practically every review request and the sign-offs
>>> are there. It’s a bit ridiculous.
>>>
>>> It would be nice to find someone neutral, unrelated to Arm, to merge our
>>> PR
>>>
>>>
>> Some history on the origins of RISC to put things in perspective:
>>
>> https://en.m.wikipedia.org/wiki/Berkeley_RISC
>>
>> David Patterson worked with Andrew Waterman and Krste Asanovic on the
>> design of RISC-V. Sagar did most of the work on the QEMU port and he
>> agreeded to sign off on all patches. The SiFive patches only have
>> sign-offs
>> from SiFive because SiFive was the sole contributor for its hardware
>> model,
>> beside the SiFiveUART which has Stefan’s sign-off.
>>
>> In any case it seems there is not enough review bandwidth in the QEMU
>> project as a whole and the policy to accept contributions is too strict to
>> be reasonable, given earnest attempts to comply with *all* review
>> feedback.
>> Not impressed.
>>
>
> On behalf of the rest of the RISC-V QEMU team I'd like to apologize for
> Michael's comments.  That's a pretty insulting thing to say, and the whole
> thing comes off as a bit entitled: we've asked the QEMU community to do a
> lot of work for us in reviewing our port, and seeing as how none of us are
> QEMU contributors we certainly don't have any grounds to ask someone to
> stop reviewing it -- that's pretty absurd.
>
> While I haven't been following the upstreaming process as closely as I
> should have been, as far as I can tell there's no grounds to accuse Peter,
> or anyone else, of trying to shoot down our port for any reason.  Peter, I
> can understand if you're upset, as I certainly would be.  If you don't want
> to help out with our port any more then I can understand, but I'd just like
> to assure you that we value the time you've spent on our port and hope you
> continue to help out!
>
> Hopefully this doesn't derail our chances of moving forward with
> submitting the RISC-V port upstream.
>
> Sorry!
>

I re-iterate Palmer's apology.

I shouldn't be polling git.qemu.org/qemu.git and answering emails near
to 3am in the morning after 4 months of working on trying to get the RISC-V
port in shape to go upstream.

It appears it is completely my mistake and I had tagged early deltas on top
of v8.2 instead of the tip of v8.2.

I've force pushed the 'riscv-qemu-upstream-v8.2' so only the mailing list
will hold the history of my mistake.

$ git push -f --tags
Counting objects: 1, done.
Writing objects: 100% (1/1), 6.31 KiB | 0 bytes/s, done.
Total 1 (delta 0), reused 0 (delta 0)
To git@github.com:riscv/riscv-qemu.git
 + feb8f5e...2c7f042 riscv-qemu-upstream-v8.2 -> riscv-qemu-upstream-v8.2
(forced update)

Re: [Qemu-devel] [PULL] RISC-V QEMU Port Submission v8.2

[Michael Clark]

On Fri, Mar 9, 2018 at 12:48 AM, Daniel P. Berrangé <berrange@redhat.com>
wrote:

> On Thu, Mar 08, 2018 at 11:18:30AM +0000, Michael Clark wrote:
> > On Fri, 9 Mar 2018 at 12:10 AM, Michael Clark <mjc@sifive.com> wrote:
> >
> > > On Thu, 8 Mar 2018 at 11:02 PM, Peter Maydell <
> peter.maydell@linaro.org>
> > > wrote:
> > >
> > >> On 6 March 2018 at 19:46, Michael Clark <mjc@sifive.com> wrote:
> > >> > -----BEGIN PGP SIGNED MESSAGE-----
> > >> > Hash: SHA1
> > >> >
> > >> > The following changes since commit
> > >> f32408f3b472a088467474ab152be3b6285b2d7b:
> > >> >
> > >> >   misc: don't use hwaddr as a type in trace events (2018-03-06
> 14:24:30
> > >> +0000)
> > >> >
> > >> > are available in the git repository at:
> > >> >
> > >> >   https://github.com/riscv/riscv-qemu.git
> tags/riscv-qemu-upstream-v8.2
> > >> >
> > >> > for you to fetch changes up to 7051b081bf6796e5e84406f6223a7c
> 4900bf7298:
> > >> >
> > >> >   RISC-V - Remove support for adhoc non-standard X_COP
> local-interrupt
> > >> (2018-03-07 08:36:03 +1300)
> > >>
> > >>
> > >> Hi -- I would have applied this, but some of the commits
> > >> have no signed-off-by lines.
> > >>
> > >> This is important, and I've already asked for it once. We cannot
> > >> accept anything that doesn't have a clear record in the commit
> > >> message of everybody (person or company) who's contributed code
> > >> to it, indicating that they're happy for their copyrighted
> > >> contributions to be taken into QEMU under our license. Lists
> > >> of names without emails in the cover letter are not sufficient.
> > >>
> > >> In fact a lot of the last part of this patchset looks like
> > >> unreviewed changes/fixes that if we were going to have them we
> > >> should have squashed into the correct patches and resent the
> > >> series for review. Please don't do this. Code review is an
> > >> important part of how the QEMU project works.
> > >
> > >
> > > You must be looking at the wrong tag. There are multiple sign-offs in
> all
> > > 23 commits. The tag is riscv-qemu-upstream-v8.2. Sagar and Bastian
> > > contacted me out of band to add their sign-offs. Please look at the
> commits
> > > again and tell me which commit id doesn’t have a sign-off on that tag
> (23
> > > commits iirc)
> > >
> >
> > I can forward you the mail out-of-band. I had to contact contributors to
> > get them to agree to change the license from MIT to GPLv2, based on a
> > request from Red Hat.
> >
> > You are making this very hard. Do you work for Arm perchance? I really
> > wouldn’t be surprised if our port is being sandbagged by Arm. Apologies
> for
> > being so direct about this, but things like this happen...
> >
> > I have complied with practically every review request and the sign-offs
> are
> > there. It’s a bit ridiculous.
> >
> > It would be nice to find someone neutral, unrelated to Arm, to merge our
> PR
>
> Please stop with these ridiculous conspiracy theories right away. It is a
> totally inappropriate and baseless accusation to make.
>

My apologies. I do tend towards conspiratorial thinking, and this is
related to a pain and anxiety disorder combined with insomnia. It seems the
issue is completely my fault and i'll apologise again on this email. I will
refrain from making any non-technical comments after this. I'm not trying
to make an excuse. I do tend towards conspiratorial thinking.

I'm obviously having trouble moving from a Github PR / merge flow, to a
Linux git-send-email based flow.

The Linux git-send-email based flow has a steeper learning curve... and the
mistakes are completely mine...

Sorry. I sincerely hope its accepted.

Peter is not trying to punish you with extra rules. Over time QEMU has been
> raising the bar for *all* contributions with extra code style checks,
> automated testing, and review. Unfortunately this does mean that the larger
> the patch series / feature, the more work is required to get to a mergable
> state, especially if the contributors are not previously familiar with QEMU
> development.
>
> Regards,
> Daniel
> --
> |: https://berrange.com      -o-    https://www.flickr.com/photos/
> dberrange :|
> |: https://libvirt.org         -o-
> https://fstop138.berrange.com :|
> |: https://entangle-photo.org    -o-    https://www.instagram.com/
> dberrange :|
>

Re: [Qemu-devel] [patches] Re: [PULL] RISC-V QEMU Port Submission v8.2

[Peter Maydell]

On 8 March 2018 at 19:53, Michael Clark <mjc@sifive.com> wrote:
> I re-iterate Palmer's apology.
>
> I shouldn't be polling git.qemu.org/qemu.git and answering emails near to
> 3am in the morning after 4 months of working on trying to get the RISC-V
> port in shape to go upstream.
>
> It appears it is completely my mistake and I had tagged early deltas on top
> of v8.2 instead of the tip of v8.2.
>
> I've force pushed the 'riscv-qemu-upstream-v8.2' so only the mailing list
> will hold the history of my mistake.

Thank you for the apology. On my side, I regret not starting this
email thread by just asking if you'd pushed the wrong tag by mistake,
since in retrospect that was certainly the most likely situation.

I've now merged and tested the revised tag, and pushed it upstream.

NB: there was a test failure on OpenBSD host:

TEST: tests/qom-test... (pid=64016)
  /riscv32/qom/spike_v1.9.1:                                           **
ERROR:/home/qemu/tests/qom-test.c:64:test_properties: assertion
failed: (qdict_haskey(response, "return"))
FAIL

but this seems to have been intermittent -- it was only on that one
host, and I reran the test suite there and it passed fine the second
time. So it may be nothing to do with your code; we'll see if it
comes up again.

I also had a look at running the port under valgrind, which shows
what looks like a bug in riscv_isa_string():

$ valgrind ./build/all/riscv32-softmmu/qemu-system-riscv32
[...]
==24805== Invalid read of size 1
==24805==    at 0x4C30F74: strlen (in
/usr/lib/valgrind/vgpreload_memcheck-amd64-linux.so)
==24805==    by 0x26518E: riscv_isa_string (cpu.c:399)
==24805==    by 0x25C15D: create_fdt (spike.c:125)
==24805==    by 0x25C15D: spike_v1_10_0_board_init (spike.c:199)
==24805==    by 0x2CCE1A: machine_run_board_init (machine.c:807)
==24805==    by 0x1BFF28: main (vl.c:4597)
==24805==  Address 0x3055be55 is 0 bytes after a block of size 5 alloc'd
==24805==    at 0x4C2FB55: calloc (in
/usr/lib/valgrind/vgpreload_memcheck-amd64-linux.so)
==24805==    by 0x70C8770: g_malloc0 (in
/lib/x86_64-linux-gnu/libglib-2.0.so.0.4800.2)
==24805==    by 0x26512E: riscv_isa_string (cpu.c:395)
==24805==    by 0x25C15D: create_fdt (spike.c:125)
==24805==    by 0x25C15D: spike_v1_10_0_board_init (spike.c:199)
==24805==    by 0x2CCE1A: machine_run_board_init (machine.c:807)
==24805==    by 0x1BFF28: main (vl.c:4597)

I haven't looked too hard at the code, but I suspect you're
miscalculating the length of the string and/or not writing the
trailing NUL to the string. I recommend you have a look at that,
and perhaps try running some other tests under valgrind.

thanks
-- PMM

Re: [Qemu-devel] [patches] Re: [PULL] RISC-V QEMU Port Submission v8.2

[Michael Clark]

On Sat, Mar 10, 2018 at 3:28 AM, Peter Maydell <peter.maydell@linaro.org>
wrote:

> On 8 March 2018 at 19:53, Michael Clark <mjc@sifive.com> wrote:
> > I re-iterate Palmer's apology.
> >
> > I shouldn't be polling git.qemu.org/qemu.git and answering emails near
> to
> > 3am in the morning after 4 months of working on trying to get the RISC-V
> > port in shape to go upstream.
> >
> > It appears it is completely my mistake and I had tagged early deltas on
> top
> > of v8.2 instead of the tip of v8.2.
> >
> > I've force pushed the 'riscv-qemu-upstream-v8.2' so only the mailing list
> > will hold the history of my mistake.
>
> Thank you for the apology. On my side, I regret not starting this
> email thread by just asking if you'd pushed the wrong tag by mistake,
> since in retrospect that was certainly the most likely situation.
>

No worries. It was very late at night. I was tired and a little anxious.
Thanks very much for bearing with me after my comments.


> I've now merged and tested the revised tag, and pushed it upstream.
>

That's great news.


> NB: there was a test failure on OpenBSD host:
>
> TEST: tests/qom-test... (pid=64016)
>   /riscv32/qom/spike_v1.9.1:                                           **
> ERROR:/home/qemu/tests/qom-test.c:64:test_properties: assertion
> failed: (qdict_haskey(response, "return"))
> FAIL
>
> but this seems to have been intermittent -- it was only on that one
> host, and I reran the test suite there and it passed fine the second
> time. So it may be nothing to do with your code; we'll see if it
> comes up again.
>
> I also had a look at running the port under valgrind, which shows
> what looks like a bug in riscv_isa_string():
>
> $ valgrind ./build/all/riscv32-softmmu/qemu-system-riscv32
> [...]
> ==24805== Invalid read of size 1
> ==24805==    at 0x4C30F74: strlen (in
> /usr/lib/valgrind/vgpreload_memcheck-amd64-linux.so)
> ==24805==    by 0x26518E: riscv_isa_string (cpu.c:399)
> ==24805==    by 0x25C15D: create_fdt (spike.c:125)
> ==24805==    by 0x25C15D: spike_v1_10_0_board_init (spike.c:199)
> ==24805==    by 0x2CCE1A: machine_run_board_init (machine.c:807)
> ==24805==    by 0x1BFF28: main (vl.c:4597)
> ==24805==  Address 0x3055be55 is 0 bytes after a block of size 5 alloc'd
> ==24805==    at 0x4C2FB55: calloc (in
> /usr/lib/valgrind/vgpreload_memcheck-amd64-linux.so)
> ==24805==    by 0x70C8770: g_malloc0 (in
> /lib/x86_64-linux-gnu/libglib-2.0.so.0.4800.2)
> ==24805==    by 0x26512E: riscv_isa_string (cpu.c:395)
> ==24805==    by 0x25C15D: create_fdt (spike.c:125)
> ==24805==    by 0x25C15D: spike_v1_10_0_board_init (spike.c:199)
> ==24805==    by 0x2CCE1A: machine_run_board_init (machine.c:807)
> ==24805==    by 0x1BFF28: main (vl.c:4597)
>
> I haven't looked too hard at the code, but I suspect you're
> miscalculating the length of the string and/or not writing the
> trailing NUL to the string. I recommend you have a look at that,
> and perhaps try running some other tests under valgrind.
>

Thanks very much!

I'll valgrind locally when I get time. It's very late at night here. 3.45am.

We may very well have a memory issue but it's likely restricted to the
RISC-V port and shouldn't cause any issues for other ports.

BTW - I've integrated the following 3 branches into the riscv tree:

- https://github.com/riscv/riscv-qemu/tree/softfloat-snan-abort-fix
- https://github.com/riscv/riscv-qemu/tree/riscv-qemu-upstream-v8.2
- https://github.com/michaeljclark/riscv-qemu/tree/qemu-devel

into our `riscv-all` integration branch, and we're now passing all FPU
tests, interestingly, including the NaN-boxing of single precision values
into doubles. We'll need to check that the riscv-tests testsuite is
exhastive enough... Suprised! I think Richard might have thought about
our NaN-boxing
issue or some other sort of magic is going on :-)

- https://github.com/riscv/riscv-qemu/tree/riscv-all

Michael.
--

$ sh qemu-images/run-riscv-tests.sh
rv64ua-v-amoadd_d
rv64ua-v-amoadd_w
rv64ua-v-amoand_d
rv64ua-v-amoand_w
rv64ua-v-amomax_d
rv64ua-v-amomax_w
rv64ua-v-amomaxu_d
rv64ua-v-amomaxu_w
rv64ua-v-amomin_d
rv64ua-v-amomin_w
rv64ua-v-amominu_d
rv64ua-v-amominu_w
rv64ua-v-amoor_d
rv64ua-v-amoor_w
rv64ua-v-amoswap_d
rv64ua-v-amoswap_w
rv64ua-v-amoxor_d
rv64ua-v-amoxor_w
rv64ua-v-lrsc
rv64uc-v-rvc
rv64ud-v-fadd
rv64ud-v-fclass
rv64ud-v-fcmp
rv64ud-v-fcvt
rv64ud-v-fcvt_w
rv64ud-v-fdiv
rv64ud-v-fmadd
rv64ud-v-fmin
rv64ud-v-ldst
rv64ud-v-move
rv64ud-v-recoding
rv64ud-v-structural
rv64uf-v-fadd
rv64uf-v-fclass
rv64uf-v-fcmp
rv64uf-v-fcvt
rv64uf-v-fcvt_w
rv64uf-v-fdiv
rv64uf-v-fmadd
rv64uf-v-fmin
rv64uf-v-ldst
rv64uf-v-move
rv64uf-v-recoding
rv64ui-v-add
rv64ui-v-addi
rv64ui-v-addiw
rv64ui-v-addw
rv64ui-v-and
rv64ui-v-andi
rv64ui-v-auipc
rv64ui-v-beq
rv64ui-v-bge
rv64ui-v-bgeu
rv64ui-v-blt
rv64ui-v-bltu
rv64ui-v-bne
rv64ui-v-fence_i
rv64ui-v-jal
rv64ui-v-jalr
rv64ui-v-lb
rv64ui-v-lbu
rv64ui-v-ld
rv64ui-v-lh
rv64ui-v-lhu
rv64ui-v-lui
rv64ui-v-lw
rv64ui-v-lwu
rv64ui-v-or
rv64ui-v-ori
rv64ui-v-sb
rv64ui-v-sd
rv64ui-v-sh
rv64ui-v-simple
rv64ui-v-sll
rv64ui-v-slli
rv64ui-v-slliw
rv64ui-v-sllw
rv64ui-v-slt
rv64ui-v-slti
rv64ui-v-sltiu
rv64ui-v-sltu
rv64ui-v-sra
rv64ui-v-srai
rv64ui-v-sraiw
rv64ui-v-sraw
rv64ui-v-srl
rv64ui-v-srli
rv64ui-v-srliw
rv64ui-v-srlw
rv64ui-v-sub
rv64ui-v-subw
rv64ui-v-sw
rv64ui-v-xor
rv64ui-v-xori
rv64um-v-div
rv64um-v-divu
rv64um-v-divuw
rv64um-v-divw
rv64um-v-mul
rv64um-v-mulh
rv64um-v-mulhsu
rv64um-v-mulhu
rv64um-v-mulw
rv64um-v-rem
rv64um-v-remu
rv64um-v-remuw
rv64um-v-remw

Re: [Qemu-devel] [patches] Re: [PULL] RISC-V QEMU Port Submission v8.2

[Alex Bennée]

Michael Clark <mjc@sifive.com> writes:

<snip>
>
> BTW - I've integrated the following 3 branches into the riscv tree:
>
> - https://github.com/riscv/riscv-qemu/tree/softfloat-snan-abort-fix
> - https://github.com/riscv/riscv-qemu/tree/riscv-qemu-upstream-v8.2
> - https://github.com/michaeljclark/riscv-qemu/tree/qemu-devel
>
> into our `riscv-all` integration branch, and we're now passing all FPU
> tests, interestingly, including the NaN-boxing of single precision values
> into doubles. We'll need to check that the riscv-tests testsuite is
> exhastive enough... Suprised! I think Richard might have thought about
> our NaN-boxing
> issue or some other sort of magic is going on :-)
>
> - https://github.com/riscv/riscv-qemu/tree/riscv-all

Is the SNaN patch going to get re-posted now it has had a review?

--
Alex Bennée

Re: [Qemu-devel] [patches] Re: [PULL] RISC-V QEMU Port Submission v8.2

[Peter Maydell]

On 9 March 2018 at 15:15, Alex Bennée <alex.bennee@linaro.org> wrote:
>
> Michael Clark <mjc@sifive.com> writes:
>
> <snip>
>>
>> BTW - I've integrated the following 3 branches into the riscv tree:
>>
>> - https://github.com/riscv/riscv-qemu/tree/softfloat-snan-abort-fix
>> - https://github.com/riscv/riscv-qemu/tree/riscv-qemu-upstream-v8.2
>> - https://github.com/michaeljclark/riscv-qemu/tree/qemu-devel
>>
>> into our `riscv-all` integration branch, and we're now passing all FPU
>> tests, interestingly, including the NaN-boxing of single precision values
>> into doubles. We'll need to check that the riscv-tests testsuite is
>> exhastive enough... Suprised! I think Richard might have thought about
>> our NaN-boxing
>> issue or some other sort of magic is going on :-)
>>
>> - https://github.com/riscv/riscv-qemu/tree/riscv-all
>
> Is the SNaN patch going to get re-posted now it has had a review?

I'm just in the process of applying that to master now...

-- PMM

Re: [Qemu-devel] [patches] Re: [PULL] RISC-V QEMU Port Submission v8.2

[Peter Maydell]

On 9 March 2018 at 14:28, Peter Maydell <peter.maydell@linaro.org> wrote:
> NB: there was a test failure on OpenBSD host:
>
> TEST: tests/qom-test... (pid=64016)
>   /riscv32/qom/spike_v1.9.1:                                           **
> ERROR:/home/qemu/tests/qom-test.c:64:test_properties: assertion
> failed: (qdict_haskey(response, "return"))
> FAIL
>
> but this seems to have been intermittent -- it was only on that one
> host, and I reran the test suite there and it passed fine the second
> time. So it may be nothing to do with your code; we'll see if it
> comes up again.

On a later test run I got this different one; openbsd again:

TEST: tests/test-hmp... (pid=45236)
  /riscv32/hmp/spike_v1.9.1:                                           **
ERROR:/home/qemu/qom/object.c:488:object_new_with_type: assertion
failed: (type != NULL)
Broken pipe
FAIL

My current best theory is that OpenBSD libc's memory allocator
happens to be more sensitive to a memory corruption bug in the risc
code, resulting in intermittent failures if the allocations happen
to come out the wrong way. You do have at least one invalid-write
off the end of a block according to valgrind:

==17441== Invalid write of size 1
==17441==    at 0x26517F: riscv_isa_string (cpu.c:399)
==17441==    by 0x25C14D: create_fdt (spike.c:125)
==17441==    by 0x25C14D: spike_v1_10_0_board_init (spike.c:199)
==17441==    by 0x2CCE0A: machine_run_board_init (machine.c:807)
==17441==    by 0x1BFF28: main (vl.c:4597)
==17441==  Address 0x3055c425 is 0 bytes after a block of size 5 alloc'd
==17441==    at 0x4C2FB55: calloc (in
/usr/lib/valgrind/vgpreload_memcheck-amd64-linux.so)
==17441==    by 0x70C8770: g_malloc0 (in
/lib/x86_64-linux-gnu/libglib-2.0.so.0.4800.2)
==17441==    by 0x26511E: riscv_isa_string (cpu.c:395)
==17441==    by 0x25C14D: create_fdt (spike.c:125)
==17441==    by 0x25C14D: spike_v1_10_0_board_init (spike.c:199)
==17441==    by 0x2CCE0A: machine_run_board_init (machine.c:807)
==17441==    by 0x1BFF28: main (vl.c:4597)

If you can prioritise a patch that fixes the bug in riscv_isa_string()
I'll apply that and hopefully these intermittent failures will go away.

thanks
-- PMM

Re: [Qemu-devel] [patches] Re: [PULL] RISC-V QEMU Port Submission v8.2

[Michael Clark]

On Sat, Mar 10, 2018 at 5:49 AM, Peter Maydell <peter.maydell@linaro.org>
wrote:

> On 9 March 2018 at 14:28, Peter Maydell <peter.maydell@linaro.org> wrote:
> > NB: there was a test failure on OpenBSD host:
> >
> > TEST: tests/qom-test... (pid=64016)
> >   /riscv32/qom/spike_v1.9.1:                                           **
> > ERROR:/home/qemu/tests/qom-test.c:64:test_properties: assertion
> > failed: (qdict_haskey(response, "return"))
> > FAIL
> >
> > but this seems to have been intermittent -- it was only on that one
> > host, and I reran the test suite there and it passed fine the second
> > time. So it may be nothing to do with your code; we'll see if it
> > comes up again.
>
> On a later test run I got this different one; openbsd again:
>
> TEST: tests/test-hmp... (pid=45236)
>   /riscv32/hmp/spike_v1.9.1:                                           **
> ERROR:/home/qemu/qom/object.c:488:object_new_with_type: assertion
> failed: (type != NULL)
> Broken pipe
> FAIL
>
> My current best theory is that OpenBSD libc's memory allocator
> happens to be more sensitive to a memory corruption bug in the risc
> code, resulting in intermittent failures if the allocations happen
> to come out the wrong way. You do have at least one invalid-write
> off the end of a block according to valgrind:
>
> ==17441== Invalid write of size 1
> ==17441==    at 0x26517F: riscv_isa_string (cpu.c:399)
> ==17441==    by 0x25C14D: create_fdt (spike.c:125)
> ==17441==    by 0x25C14D: spike_v1_10_0_board_init (spike.c:199)
> ==17441==    by 0x2CCE0A: machine_run_board_init (machine.c:807)
> ==17441==    by 0x1BFF28: main (vl.c:4597)
> ==17441==  Address 0x3055c425 is 0 bytes after a block of size 5 alloc'd
> ==17441==    at 0x4C2FB55: calloc (in
> /usr/lib/valgrind/vgpreload_memcheck-amd64-linux.so)
> ==17441==    by 0x70C8770: g_malloc0 (in
> /lib/x86_64-linux-gnu/libglib-2.0.so.0.4800.2)
> ==17441==    by 0x26511E: riscv_isa_string (cpu.c:395)
> ==17441==    by 0x25C14D: create_fdt (spike.c:125)
> ==17441==    by 0x25C14D: spike_v1_10_0_board_init (spike.c:199)
> ==17441==    by 0x2CCE0A: machine_run_board_init (machine.c:807)
> ==17441==    by 0x1BFF28: main (vl.c:4597)
>
> If you can prioritise a patch that fixes the bug in riscv_isa_string()
> I'll apply that and hopefully these intermittent failures will go away.
>

I'm looking at this right now.

Re: [Qemu-devel] [patches] Re: [PULL] RISC-V QEMU Port Submission v8.2

[Michael Clark]

On Sat, Mar 10, 2018 at 9:11 AM, Michael Clark <mjc@sifive.com> wrote:

>
>
> On Sat, Mar 10, 2018 at 5:49 AM, Peter Maydell <peter.maydell@linaro.org>
> wrote:
>
>> On 9 March 2018 at 14:28, Peter Maydell <peter.maydell@linaro.org> wrote:
>> > NB: there was a test failure on OpenBSD host:
>> >
>> > TEST: tests/qom-test... (pid=64016)
>> >   /riscv32/qom/spike_v1.9.1:
>>  **
>> > ERROR:/home/qemu/tests/qom-test.c:64:test_properties: assertion
>> > failed: (qdict_haskey(response, "return"))
>> > FAIL
>> >
>> > but this seems to have been intermittent -- it was only on that one
>> > host, and I reran the test suite there and it passed fine the second
>> > time. So it may be nothing to do with your code; we'll see if it
>> > comes up again.
>>
>> On a later test run I got this different one; openbsd again:
>>
>> TEST: tests/test-hmp... (pid=45236)
>>   /riscv32/hmp/spike_v1.9.1:                                           **
>> ERROR:/home/qemu/qom/object.c:488:object_new_with_type: assertion
>> failed: (type != NULL)
>> Broken pipe
>> FAIL
>>
>> My current best theory is that OpenBSD libc's memory allocator
>> happens to be more sensitive to a memory corruption bug in the risc
>> code, resulting in intermittent failures if the allocations happen
>> to come out the wrong way. You do have at least one invalid-write
>> off the end of a block according to valgrind:
>>
>> ==17441== Invalid write of size 1
>> ==17441==    at 0x26517F: riscv_isa_string (cpu.c:399)
>> ==17441==    by 0x25C14D: create_fdt (spike.c:125)
>> ==17441==    by 0x25C14D: spike_v1_10_0_board_init (spike.c:199)
>> ==17441==    by 0x2CCE0A: machine_run_board_init (machine.c:807)
>> ==17441==    by 0x1BFF28: main (vl.c:4597)
>> ==17441==  Address 0x3055c425 is 0 bytes after a block of size 5 alloc'd
>> ==17441==    at 0x4C2FB55: calloc (in
>> /usr/lib/valgrind/vgpreload_memcheck-amd64-linux.so)
>> ==17441==    by 0x70C8770: g_malloc0 (in
>> /lib/x86_64-linux-gnu/libglib-2.0.so.0.4800.2)
>> ==17441==    by 0x26511E: riscv_isa_string (cpu.c:395)
>> ==17441==    by 0x25C14D: create_fdt (spike.c:125)
>> ==17441==    by 0x25C14D: spike_v1_10_0_board_init (spike.c:199)
>> ==17441==    by 0x2CCE0A: machine_run_board_init (machine.c:807)
>> ==17441==    by 0x1BFF28: main (vl.c:4597)
>>
>> If you can prioritise a patch that fixes the bug in riscv_isa_string()
>> I'll apply that and hopefully these intermittent failures will go away.
>>
>
> I'm looking at this right now.
>

It's a glaringly obvious logic bug. The use of the wrong bit manipulation
instrinsic. I just sent a patch.