From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 11F89C10F06 for ; Fri, 15 Mar 2019 02:18:34 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id AAD8521872 for ; Fri, 15 Mar 2019 02:18:33 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="lREoL67I" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728220AbfCOCSc (ORCPT ); Thu, 14 Mar 2019 22:18:32 -0400 Received: from mail-wr1-f66.google.com ([209.85.221.66]:46614 "EHLO mail-wr1-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727304AbfCOCSb (ORCPT ); Thu, 14 Mar 2019 22:18:31 -0400 Received: by mail-wr1-f66.google.com with SMTP id 33so7928802wrb.13; Thu, 14 Mar 2019 19:18:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc:content-transfer-encoding; bh=xuuk/rNBwaXKQQzsXusdJ+tE4WGOvqqNaZWrnidZzaA=; b=lREoL67Id+bJGv6N/Ukv+JkfEC5IX8BWSY6DjuD3maXp8aPkPxPPYiVBsAAv+6JjNm /4qeJwhzIra75zywXU6MYOZW2xU8jb1EMlQY69W+zHTvIU7arTERTAR6EaR5VlCuq3iT Em+F2q+tUGY4g5y4a3WS9rgTrR+vbLu/XjMgLj9YijDSnDp0v9q9aQQKHA0Y1i7qytRk A1gMXjt2boTIG2lzHdvy/NoUukJFXCp6Hh4HZQvYqR+toAxOrOO/qFuQOSaNrlTWECul /Kc8PQ9qFdyTGTlrUx1exFDQD1wAes17Hm3iD54V27x2ADiNfhot153CO/TfJzWKjuyl 3lGw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc:content-transfer-encoding; bh=xuuk/rNBwaXKQQzsXusdJ+tE4WGOvqqNaZWrnidZzaA=; b=jAtf+sNpw4EE6dJprp3msbceKL2dzv9hAAmY8j9TP8PiLvCg6WZfPrmgxpBGciZliD TeWJjiAul13EzDyKJEBGahYK9IBjcLZL1A0ndO3M5NDn8cCbMMcyo041RKyTy7hKV+Dz CcvxWc13jbeVs5zsPGa5yeKHfF9y0qPIhfF51wKgk8YgbFxF89rviYGXhDdt2RvpGfwM 2SigV5ieZoOyWOVUM4gKxLFceY0m9nzf8RDIQD3NBev9BuL5Xg6Hxz25UtITWr6k77io gdofUa3Xek/moJ0/79bFzg5EuoopAoI5OuyPbI7faACJ6e2ar2RWZ4Wn3pIO4buXvWGH HyWQ== X-Gm-Message-State: APjAAAXqiOeq+M0qYmXMr7jwzfrM3Saiu22FZUeRo23Jzp1/z0rsbH81 V6bZGTFv7fDbdEyIx01NlMSbT/WV7HGhfESiKDY= X-Google-Smtp-Source: APXvYqwxC4j6x8EESQYASSA6L0bChxCPM2fML7Ejd6WO/VGWJE+ikb3QWDjFic8iF5h4a6G2vjRBtCeZKjYdbOVrnLU= X-Received: by 2002:adf:a147:: with SMTP id r7mr558504wrr.5.1552616307611; Thu, 14 Mar 2019 19:18:27 -0700 (PDT) MIME-Version: 1.0 References: <1552467452-538-1-git-send-email-hongxing.zhu@nxp.com> <1552467452-538-2-git-send-email-hongxing.zhu@nxp.com> In-Reply-To: From: Andrey Smirnov Date: Thu, 14 Mar 2019 19:18:15 -0700 Message-ID: Subject: Re: [RFC 2/2] PCI: imx6: Add support for i.MX8QM/QXP PCIe To: Richard Zhu Cc: "bhelgaas@google.com" , "lorenzo.pieralisi@arm.com" , "l.stach@pengutronix.de" , "linux-pci@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "linux-kernel@vger.kernel.org" Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, Mar 14, 2019 at 2:18 AM Richard Zhu wrote: > > Hi Andrey: > Thanks a lot for your review comments. > > Best Regards > Richard Zhu > Office: 86-21-28937189 > Mobile: 86-13386059786 > > > > -----Original Message----- > > From: Andrey Smirnov [mailto:andrew.smirnov@gmail.com] > > Sent: 2019=E5=B9=B43=E6=9C=8814=E6=97=A5 4:20 > > To: Richard Zhu > > Cc: bhelgaas@google.com; lorenzo.pieralisi@arm.com; > > l.stach@pengutronix.de; linux-pci@vger.kernel.org; > > linux-arm-kernel@lists.infradead.org; linux-kernel@vger.kernel.org > > Subject: Re: [RFC 2/2] PCI: imx6: Add support for i.MX8QM/QXP PCIe > > > > On Wed, Mar 13, 2019 at 2:15 AM Richard Zhu > > wrote: > > > > > > Add codes needed to support i.MX8QM/QXP PCIe. > > > - HSIO(High Speed IO) subsystem is new defined on i.MX8QM/QXP. > > > The PCIe and SATA modules are contained in the HSIO subsystem. Ther= e > > > are two PCIe, one SATA controllers and three mixed lane PHYs on > > > i.MX8QM. There are three use cases of the HSIO subsystem on > > i.MX8QM. > > > 1. PCIea 2 lanes and one SATA AHCI port. > > > 2. PCIea 1 lane, PCIeb 1 lane and one SATA AHCI port. > > > 3. PCIea 2 lanes, PCIeb 1 lane. > > > i.MX8QXP only has PCIeb controller and one lane PHY. > > > - The HSIO address map as viewed from system level is as shown below. > > > address [31:24] Local address Target Address Size > > > 5F 0 HSIO 16MB > > > 60-6F 40-4F HSIO 256MB > > > 70-7F 80-8F HSIO 256MB > > > So, the cpu_addr_fixup is required to enable i.MX8QM/QXP PCIe. > > > - Both external OSC and internal PLL can be used as PCIe reference > > > clock. > > > - clock request GPIO for controlling the PCI reference clock request > > > signal. And should be configure OD when L1SS maybe enabled later. > > > - One more power domain HSIO_GPIO and clock PCIE_PER are required by > > > i.MX8QM/QXP PCIe. > > > > > > Signed-off-by: Richard Zhu > > > --- > > > drivers/pci/controller/dwc/pci-imx6.c | 392 > > > +++++++++++++++++++++++++++++++++- > > > 1 file changed, 387 insertions(+), 5 deletions(-) > > > > > > diff --git a/drivers/pci/controller/dwc/pci-imx6.c > > > b/drivers/pci/controller/dwc/pci-imx6.c > > > index aaa9489..aacefb6 100644 > > > --- a/drivers/pci/controller/dwc/pci-imx6.c > > > +++ b/drivers/pci/controller/dwc/pci-imx6.c > > > @@ -39,6 +39,7 @@ > > > #define IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE BIT(11) > > > #define IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE GENMASK(11, > > 8) > > > #define IMX8MQ_PCIE2_BASE_ADDR 0x33c00000 > > > +#define IMX8_HSIO_PCIEB_BASE_ADDR 0x5f010000 > > > > > > #define to_imx6_pcie(x) dev_get_drvdata((x)->dev) > > > > > > @@ -48,10 +49,13 @@ enum imx6_pcie_variants { > > > IMX6QP, > > > IMX7D, > > > IMX8MQ, > > > + IMX8QM, > > > + IMX8QXP, > > > }; > > > > > > #define IMX6_PCIE_FLAG_IMX6_PHY BIT(0) > > > #define IMX6_PCIE_FLAG_IMX6_SPEED_CHANGE BIT(1) > > > +#define IMX6_PCIE_FLAG_IMX6_CPU_ADDR_FIXUP BIT(2) > > > > This is an IMX8Q* specific flag, so it probably should be called someth= ing like > > IMX6_PCIE_FLAG_IMX8Qx_CPU_ADD_FIXUP. > [Richard Zhu] Okay, would change it later. > > > > > > > > struct imx6_pcie_drvdata { > > > enum imx6_pcie_variants variant; @@ -60,10 +64,12 @@ struct > > > imx6_pcie_drvdata { > > > > > > struct imx6_pcie { > > > struct dw_pcie *pci; > > > + int clkreq_gpio; > > > > Is this really necessary? On i.MX8MQ vendor tree for some unknown reaso= n > > would reconfigure a dedicated CLKREQ_B signal as a GPIO and then use it= as > > CLKREQ signal that way instead of controlling it via dedicated bits in = register > > file, so I am wondering if that is the case with QM and QXP. > [Richard Zhu] There is a same mechanism of the CLKREQ on iMX8QM/QXP/MQ. > Up to now, this pin is configured as GPIO, because that this pin would be= pull up when OD is set > and the EP device doesn't support the L1SS at all. > Thus, the external CLK would be turned off in this scenario. > This pin would be used in OD(Open Drain) mode when L1SS is enabled. > The L1SS has been verified on iMX8MQ. But I don't have a dynamic method t= o > turn the L1SS feature on at RC side yet when the L1SS is supported by EP. > Configure CLK_REQ as GPIO here currently, and hope to figure out one solu= tion in future. > Hmm, I am afraid I still don't understand why that pin has to be controlled via GPIO subsystem. Here are my assumptions: 1. We can configure, say, PCIE0's CLKREQ as SC_P_PCIE_CTRL0_CLKREQ_B_HSIO_PCIE0_CLKREQ_B on i.MX8QM, which should be open drain just by CLKREQ's definition, and we can, if need be, configure internal pull up in the same pinmux entry 2. It is possible to driver that pin open/closed via some bits in register file. IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE in case of i.MX8MQ, maybe something else for other i.MX8 SoC given those assumptions, why would we need to introduce a new DT binding to specify a GPIO and then control it via gpio_set_value()? AFAICT, absence or presence of L1SS support should be irrelevant. Perhaps some of my assumptions is wrong? Or maybe your use-case does use a dedicated GPIO pin that can't be configure as CLKREQ_B via pinmux? > > > > > int reset_gpio; > > > bool gpio_active_high; > > > struct clk *pcie_bus; > > > struct clk *pcie_phy; > > > + struct clk *pcie_per; > > > struct clk *pcie_inbound_axi; > > > struct clk *pcie; > > > struct clk *pcie_aux; > > > @@ -77,6 +83,9 @@ struct imx6_pcie { > > > u32 tx_deemph_gen2_6db; > > > u32 tx_swing_full; > > > u32 tx_swing_low; > > > + u32 hsio_cfg; > > > + u32 ext_osc; > > > + u32 local_addr; > > > int link_gen; > > > struct regulator *vpcie; > > > void __iomem *phy_base; > > > @@ -85,6 +94,8 @@ struct imx6_pcie { > > > struct device *pd_pcie; > > > /* power domain for pcie phy */ > > > struct device *pd_pcie_phy; > > > + /* power domain for hsio gpio used by pcie */ > > > + struct device *pd_hsio_gpio; > > > const struct imx6_pcie_drvdata *drvdata; }; > > > > > > @@ -92,6 +103,7 @@ struct imx6_pcie { > > > #define PHY_PLL_LOCK_WAIT_MAX_RETRIES 2000 > > > #define PHY_PLL_LOCK_WAIT_USLEEP_MIN 50 > > > #define PHY_PLL_LOCK_WAIT_USLEEP_MAX 200 > > > +#define L2_ENTRY_WAIT_MAX_RETRIES 10000 > > > > > > /* PCIe Root Complex registers (memory-mapped) */ > > > #define PCIE_RC_IMX6_MSI_CAP 0x50 > > > @@ -157,6 +169,43 @@ struct imx6_pcie { #define > > > PHY_RX_OVRD_IN_LO_RX_DATA_EN (1 << 5) #define > > > PHY_RX_OVRD_IN_LO_RX_PLL_EN (1 << 3) > > > > > > +/* iMX8 HSIO registers */ > > > +#define IMX8QM_CSR_PHYX2_OFFSET > > 0x00000 > > > +#define IMX8QM_CSR_PHYX1_OFFSET > > 0x10000 > > > +#define IMX8QM_CSR_PHYX_STTS0_OFFSET 0x4 > > > +#define IMX8QM_CSR_PCIEA_OFFSET > > 0x20000 > > > +#define IMX8QM_CSR_PCIEB_OFFSET > > 0x30000 > > > +#define IMX8QM_CSR_PCIE_CTRL1_OFFSET 0x4 > > > +#define IMX8QM_CSR_PCIE_CTRL2_OFFSET 0x8 > > > +#define IMX8QM_CSR_PCIE_STTS0_OFFSET 0xC > > > +#define IMX8QM_CSR_MISC_OFFSET 0x50000 > > > + > > > +#define IMX8QM_CTRL_LTSSM_ENABLE BIT(4) > > > +#define IMX8QM_CTRL_READY_ENTR_L23 BIT(5) > > > +#define IMX8QM_CTRL_PM_XMT_TURNOFF BIT(9) > > > +#define IMX8QM_CTRL_BUTTON_RST_N BIT(21) > > > +#define IMX8QM_CTRL_PERST_N BIT(22) > > > +#define IMX8QM_CTRL_POWER_UP_RST_N BIT(23) > > > + > > > +#define IMX8QM_CTRL_STTS0_PM_LINKST_IN_L2 BIT(13) > > > +#define IMX8QM_CTRL_STTS0_PM_REQ_CORE_RST BIT(19) > > > +#define IMX8QM_STTS0_LANE0_TX_PLL_LOCK BIT(4) > > > +#define IMX8QM_STTS0_LANE1_TX_PLL_LOCK BIT(12) > > > + > > > +#define IMX8QM_PCIE_TYPE_MASK GENMASK(27, > > 24) > > > + > > > +#define IMX8QM_PHYX2_CTRL0_APB_MASK GENMASK(1, > > 0) > > > +#define IMX8QM_PHY_APB_RSTN_0 BIT(0) > > > +#define IMX8QM_PHY_APB_RSTN_1 BIT(1) > > > + > > > +#define IMX8QM_MISC_IOB_RXENA BIT(0) > > > +#define IMX8QM_MISC_IOB_TXENA BIT(1) > > > +#define IMX8QM_CSR_MISC_IOB_A_0_TXOE BIT(2) > > > +#define IMX8QM_CSR_MISC_IOB_A_0_M1M0_MASK GENMASK(4, > > 3) > > > +#define IMX8QM_CSR_MISC_IOB_A_0_M1M0_2 BIT(4) > > > +#define IMX8QM_MISC_PHYX1_EPCS_SEL BIT(12) > > > +#define IMX8QM_MISC_PCIE_AB_SELECT BIT(13) > > > + > > > static int pcie_phy_poll_ack(struct imx6_pcie *imx6_pcie, int > > > exp_val) { > > > struct dw_pcie *pci =3D imx6_pcie->pci; @@ -373,14 +422,65 @@ > > > static int imx6_pcie_attach_pd(struct device *dev) > > > return PTR_ERR(link); > > > } > > > > > > + switch (imx6_pcie->drvdata->variant) { > > > + case IMX8QM: > > > + case IMX8QXP: > > > + imx6_pcie->pd_hsio_gpio =3D > > dev_pm_domain_attach_by_name(dev, > > > + "hsio_gpio"); > > > + if (IS_ERR(imx6_pcie->pd_hsio_gpio)) > > > + return PTR_ERR(imx6_pcie->pd_hsio_gpio); > > > + > > > + link =3D device_link_add(dev, imx6_pcie->pd_hsio_gpio= , > > > + DL_FLAG_STATELESS | > > > + DL_FLAG_PM_RUNTIME | > > > + DL_FLAG_RPM_ACTIVE); > > > + if (!link) { > > > + dev_err(dev, "Failed to add device_link to gp= io > > pd.\n"); > > > + return -EINVAL; > > > + } > > > + > > > + break; > > > + default: > > > + break; > > > + } > > > + > > > return 0; > > > } > > > > > > static void imx6_pcie_assert_core_reset(struct imx6_pcie *imx6_pcie) > > > { > > > + u32 addr; > > > + int i; > > > struct device *dev =3D imx6_pcie->pci->dev; > > > > > > switch (imx6_pcie->drvdata->variant) { > > > + case IMX8QXP: > > > + addr =3D IMX8QM_CSR_PCIEB_OFFSET + > > > + IMX8QM_CSR_PCIE_CTRL2_OFFSET; > > > > This and similar "IMX8QM_CSR_PCIEA_OFFSET + i * SZ_64K" pattern keeps > > popping up quite frequently in the code. I think at the very least it w= ould be > > good to calculate this offset in probe and store it as a member of stru= ct > > imx6_pcie. However I do wonder if this should actually be handle by eit= her > > declaring an additional syscon regmap of additional reg/reg-name proper= ty. > > > [Richard Zhu] IMHO, I just reduce some more MACRO definitions in the code= s. > Actually, the "IMX8QM_CSR_PCIEA_OFFSET + SZ_64K" should be the IMX8QM_CSR= _PCIEB_OFFSET. > I can add some more macro-definitions, for example " IMX8QM_CSR_PCIEB_OFF= SET " to remove the calculations later. > How do you think about that? > It's ultimately up to you. I was just pointing out that the code keeps re-calculating the same thing again and again, so it might have benefited from caching that value. > > > + regmap_update_bits(imx6_pcie->iomuxc_gpr, addr, > > > + IMX8QM_CTRL_BUTTON_RST_N, > > > + IMX8QM_CTRL_BUTTON_RST_N); > > > + regmap_update_bits(imx6_pcie->iomuxc_gpr, addr, > > > + IMX8QM_CTRL_PERST_N, > > > + IMX8QM_CTRL_PERST_N); > > > + regmap_update_bits(imx6_pcie->iomuxc_gpr, addr, > > > + > > IMX8QM_CTRL_POWER_UP_RST_N, > > > + > > IMX8QM_CTRL_POWER_UP_RST_N); > > > + break; > > > + case IMX8QM: > > > + for (i =3D 0; i <=3D imx6_pcie->controller_id; i++) { > > > > This loop is a bit surprising to me. It's hard to tell why you'd iterat= e from 0 to > > controller_id. I think it'd be good to add a comment explaining the log= ic > > behind this code. > > > [Richard Zhu] Okay, comments would be added here. > /* > * In i.MX8QM, two lanes PHY and one lane PHY share the > * same calibration signal. And one lane PHY would use > * the calibration output from two lanes PHY. So PCIeA > * related resets are configured before configurating PCIeB. > */ It sounds like this code relies on the fact that PCIeA will be initialized before PCIeB. I am not sure this can be guaranteed by this driver, since it supports probe deferral and PCIeA's probing can be delayed so that PCIeB's would happen first. Am I misinterpreting this? If not maybe this should be moved out to PHY driver as well? > > > > > + addr =3D IMX8QM_CSR_PCIEA_OFFSET + i * > > SZ_64K; > > > + addr +=3D IMX8QM_CSR_PCIE_CTRL2_OFFSET; > > > + regmap_update_bits(imx6_pcie->iomuxc_gpr, > > addr, > > > + > > IMX8QM_CTRL_BUTTON_RST_N, > > > + > > IMX8QM_CTRL_BUTTON_RST_N); > > > + regmap_update_bits(imx6_pcie->iomuxc_gpr, > > addr, > > > + > > IMX8QM_CTRL_PERST_N, > > > + > > IMX8QM_CTRL_PERST_N); > > > + regmap_update_bits(imx6_pcie->iomuxc_gpr, > > addr, > > > + > > IMX8QM_CTRL_POWER_UP_RST_N, > > > + > > IMX8QM_CTRL_POWER_UP_RST_N); > > > + } > > > + break; > > > case IMX7D: > > > case IMX8MQ: > > > reset_control_assert(imx6_pcie->pciephy_reset); > > > @@ -477,6 +577,21 @@ static int imx6_pcie_enable_ref_clk(struct > > imx6_pcie *imx6_pcie) > > > > > IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE_EN, > > > > > IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE_EN); > > > break; > > > + case IMX8QXP: > > > + case IMX8QM: > > > + ret =3D > > clk_prepare_enable(imx6_pcie->pcie_inbound_axi); > > > + if (ret) { > > > + dev_err(dev, "unable to enable pcie_axi > > clock\n"); > > > + break; > > > + } > > > + ret =3D clk_prepare_enable(imx6_pcie->pcie_per); > > > + if (ret) { > > > + dev_err(dev, "unable to enable pcie_per > > clock\n"); > > > + > > clk_disable_unprepare(imx6_pcie->pcie_inbound_axi); > > > + break; > > > + } > > > + > > > + break; > > > } > > > > > > return ret; > > > @@ -501,6 +616,63 @@ static void > > imx7d_pcie_wait_for_phy_pll_lock(struct imx6_pcie *imx6_pcie) > > > dev_err(dev, "PCIe PLL lock timeout\n"); } > > > > > > +static int imx8_hsio_pcie_wait_for_phy_pll_lock(struct imx6_pcie > > > +*imx6_pcie) { > > > + u32 retries, addr, val, lock =3D 0; > > > + int ret; > > > + struct dw_pcie *pci =3D imx6_pcie->pci; > > > + struct device *dev =3D pci->dev; > > > + > > > + addr =3D IMX8QM_CSR_PCIEA_OFFSET + imx6_pcie->controller_id > > * SZ_64K; > > > + addr +=3D IMX8QM_CSR_PCIE_STTS0_OFFSET; > > > + for (retries =3D 0; retries < PHY_PLL_LOCK_WAIT_MAX_RETRIES; > > retries++) { > > > + regmap_read(imx6_pcie->iomuxc_gpr, addr, &val); > > > + if ((val & IMX8QM_CTRL_STTS0_PM_REQ_CORE_RST) > > =3D=3D 0) > > > + break; > > > + udelay(1); > > > + } > > > + > > > + if ((val & IMX8QM_CTRL_STTS0_PM_REQ_CORE_RST) !=3D 0) { > > > + dev_err(dev, "ERROR: PM_REQ_CORE_RST is still > > set.\n"); > > > + return -ENODEV; > > > + } > > > + > > > > You can really cut down on boilerplate here by using > > regmap_read_poll_timeout() > > > [Richard Zhu] Okay, would change it later. > > > > + addr =3D IMX8QM_CSR_PHYX2_OFFSET + imx6_pcie->controller_id > > * SZ_64K; > > > + addr +=3D IMX8QM_CSR_PHYX_STTS0_OFFSET; > > > + for (retries =3D 0; retries < PHY_PLL_LOCK_WAIT_MAX_RETRIES; > > retries++) { > > > + regmap_read(imx6_pcie->iomuxc_gpr, addr, &val); > > > + if (imx6_pcie->hsio_cfg =3D=3D 2) { > > > + if (imx6_pcie->controller_id =3D=3D 0) > > > + lock =3D > > IMX8QM_STTS0_LANE0_TX_PLL_LOCK; > > > + else > > > + lock =3D > > IMX8QM_STTS0_LANE1_TX_PLL_LOCK; > > > + } else if (imx6_pcie->hsio_cfg =3D=3D 3) { > > > + lock =3D > > IMX8QM_STTS0_LANE0_TX_PLL_LOCK; > > > + if (imx6_pcie->controller_id =3D=3D 0) > > > + lock |=3D > > IMX8QM_STTS0_LANE1_TX_PLL_LOCK; > > > + } else if (imx6_pcie->hsio_cfg =3D=3D 1) { > > > + lock =3D > > IMX8QM_STTS0_LANE0_TX_PLL_LOCK; > > > + lock |=3D > > IMX8QM_STTS0_LANE1_TX_PLL_LOCK; > > > + } else { > > > + dev_err(dev, "ERROR: illegal hsio_cfg > > value.\n"); > > > + return -EINVAL; > > > + } > > > + val &=3D lock; > > > + if (val =3D=3D lock) > > > + break; > > > + udelay(10); > > > + } > > > + > > > + if (retries >=3D PHY_PLL_LOCK_WAIT_MAX_RETRIES) { > > > + dev_info(dev, "pcie phy pll can't be locked.\n"); > > > + ret =3D -ENODEV; > > > + } else { > > > + dev_info(dev, "pcie phy pll is locked.\n"); > > > + } > > > + > > > > Ditto. > [Richard Zhu] Got that. Thanks. > > > > > + return ret; > > > +} > > > + > > > static void imx6_pcie_deassert_core_reset(struct imx6_pcie > > > *imx6_pcie) { > > > struct dw_pcie *pci =3D imx6_pcie->pci; @@ -553,6 +725,11 @@ > > > static void imx6_pcie_deassert_core_reset(struct imx6_pcie *imx6_pcie= ) > > > } > > > > > > switch (imx6_pcie->drvdata->variant) { > > > + case IMX8QXP: > > > + case IMX8QM: > > > + /* wait for phy pll lock firstly. */ > > > + imx8_hsio_pcie_wait_for_phy_pll_lock(imx6_pcie); > > > + break; > > > case IMX8MQ: > > > reset_control_deassert(imx6_pcie->pciephy_reset); > > > break; > > > @@ -613,25 +790,114 @@ static void > > > imx6_pcie_deassert_core_reset(struct imx6_pcie *imx6_pcie) > > > > > > static void imx6_pcie_configure_type(struct imx6_pcie *imx6_pcie) { > > > - unsigned int mask, val; > > > - > > > - if (imx6_pcie->drvdata->variant =3D=3D IMX8MQ && > > > + unsigned int offset, mask, val; > > > + > > > + if (imx6_pcie->drvdata->variant =3D=3D IMX8QM || > > > + imx6_pcie->drvdata->variant =3D=3D IMX8QXP) { > > > > Since there's now more than two possibilities, it'd probably make sense= to > > convert this code to use switch statement. > [Richard Zhu] Okay, would use switch statement later. > > > > > > + offset =3D IMX8QM_CSR_PCIEA_OFFSET + > > > + imx6_pcie->controller_id * SZ_64K; > > > + mask =3D IMX8QM_PCIE_TYPE_MASK; > > > + val =3D FIELD_PREP(IMX8QM_PCIE_TYPE_MASK, > > > + PCI_EXP_TYPE_ROOT_PORT); > > > + } else if (imx6_pcie->drvdata->variant =3D=3D IMX8MQ && > > > imx6_pcie->controller_id =3D=3D 1) { > > > + offset =3D IOMUXC_GPR12; > > > mask =3D > > IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE; > > > val =3D > > FIELD_PREP(IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE, > > > PCI_EXP_TYPE_ROOT_PORT); > > > } else { > > > + offset =3D IOMUXC_GPR12; > > > mask =3D IMX6Q_GPR12_DEVICE_TYPE; > > > val =3D FIELD_PREP(IMX6Q_GPR12_DEVICE_TYPE, > > > PCI_EXP_TYPE_ROOT_PORT); > > > } > > > > > > - regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, > > mask, val); > > > + regmap_update_bits(imx6_pcie->iomuxc_gpr, offset, mask, val); > > > } > > > > > > static void imx6_pcie_init_phy(struct imx6_pcie *imx6_pcie) { > > > switch (imx6_pcie->drvdata->variant) { > > > + case IMX8QXP: > > > + case IMX8QM: > > > + if (imx6_pcie->hsio_cfg =3D=3D 1) { > > > + regmap_update_bits(imx6_pcie->iomuxc_gpr, > > > + IMX8QM_CSR_PHYX2_OFFSET, > > > + > > IMX8QM_PHYX2_CTRL0_APB_MASK, > > > + IMX8QM_PHY_APB_RSTN_0 | > > > + IMX8QM_PHY_APB_RSTN_1); > > > + > > > + regmap_update_bits(imx6_pcie->iomuxc_gpr, > > > + IMX8QM_CSR_MISC_OFFSET, > > > + IMX8QM_MISC_PHYX1_EPCS_SEL, > > > + IMX8QM_MISC_PHYX1_EPCS_SEL); > > > + regmap_update_bits(imx6_pcie->iomuxc_gpr, > > > + IMX8QM_CSR_MISC_OFFSET, > > > + IMX8QM_MISC_PCIE_AB_SELECT, > > > + 0); > > > + } else if (imx6_pcie->hsio_cfg =3D=3D 2) { > > > + regmap_update_bits(imx6_pcie->iomuxc_gpr, > > > + IMX8QM_CSR_PHYX2_OFFSET, > > > + > > IMX8QM_PHYX2_CTRL0_APB_MASK, > > > + IMX8QM_PHY_APB_RSTN_0 | > > > + IMX8QM_PHY_APB_RSTN_1); > > > + > > > + regmap_update_bits(imx6_pcie->iomuxc_gpr, > > > + IMX8QM_CSR_MISC_OFFSET, > > > + IMX8QM_MISC_PHYX1_EPCS_SEL, > > > + IMX8QM_MISC_PHYX1_EPCS_SEL); > > > + regmap_update_bits(imx6_pcie->iomuxc_gpr, > > > + IMX8QM_CSR_MISC_OFFSET, > > > + IMX8QM_MISC_PCIE_AB_SELECT, > > > + IMX8QM_MISC_PCIE_AB_SELECT); > > > + } else if (imx6_pcie->hsio_cfg =3D=3D 3) { > > > + if (imx6_pcie->controller_id) > > > + > > regmap_update_bits(imx6_pcie->iomuxc_gpr, > > > + > > IMX8QM_CSR_PHYX1_OFFSET, > > > + > > IMX8QM_PHY_APB_RSTN_0, > > > + > > IMX8QM_PHY_APB_RSTN_0); > > > + else > > > + > > regmap_update_bits(imx6_pcie->iomuxc_gpr, > > > + > > IMX8QM_CSR_PHYX2_OFFSET, > > > + > > IMX8QM_PHYX2_CTRL0_APB_MASK, > > > + > > IMX8QM_PHY_APB_RSTN_0 | > > > + > > IMX8QM_PHY_APB_RSTN_1); > > > + > > > + regmap_update_bits(imx6_pcie->iomuxc_gpr, > > > + IMX8QM_CSR_MISC_OFFSET, > > > + IMX8QM_MISC_PHYX1_EPCS_SEL, > > 0); > > > + regmap_update_bits(imx6_pcie->iomuxc_gpr, > > > + IMX8QM_CSR_MISC_OFFSET, > > > + IMX8QM_MISC_PCIE_AB_SELECT, > > > + IMX8QM_MISC_PCIE_AB_SELECT); > > > + } > > > + > > > > This doesn't look controller independent/local. What would happen if > > controller 0 specifies hsio_cfg =3D=3D 2 and controller 1 specifies hsi= o_cfg =3D=3D 1? > > > [Richard Zhu]Yes, it is. There are usage dependences between PCIeA/PCIeB = and SATA in HSIO subsystem. > BTW, It's impossible for controller 1 to specify the hsio_cfg to "1", whe= n controller 0 specifies hsio_cfg=3D=3D2. > There are three usage cases of the HSIO. > Hsio_cfg pciea pcieb sata > 1 2lanes No Enabled > 2 1lane 1lane Enabled > 3 2lanes 1lane No > So, the possible hsio_cfg values for PCIeB is 2 or 3. If I understand you correctly, I think what you mean by "impossible" is that in order things to work correctly when first controller is configured as hsio_cfg =3D=3D 1, second contoller _has_ to be specified with hsio_cfg !=3D 1. However, what I am trying to point out is that it is an implicit dependency between the two controllers and AFAICT there's no enforcement of it preventing me/user from creating a DT file where hsio_cfg =3D <1> for both controllers. Moving this configuration into a separate PHY driver should solve this, however. > > > > + if (imx6_pcie->ext_osc) { > > > + regmap_update_bits(imx6_pcie->iomuxc_gpr, > > > + IMX8QM_CSR_MISC_OFFSET, > > > + IMX8QM_MISC_IOB_RXENA, > > > + IMX8QM_MISC_IOB_RXENA); > > > + regmap_update_bits(imx6_pcie->iomuxc_gpr, > > > + IMX8QM_CSR_MISC_OFFSET, > > > + IMX8QM_MISC_IOB_TXENA, 0); > > > + } else { > > > + /* Try to used the internal pll as ref clk */ > > > + regmap_update_bits(imx6_pcie->iomuxc_gpr, > > > + IMX8QM_CSR_MISC_OFFSET, > > > + IMX8QM_MISC_IOB_RXENA, 0); > > > + regmap_update_bits(imx6_pcie->iomuxc_gpr, > > > + IMX8QM_CSR_MISC_OFFSET, > > > + IMX8QM_MISC_IOB_TXENA, > > > + IMX8QM_MISC_IOB_TXENA); > > > + regmap_update_bits(imx6_pcie->iomuxc_gpr, > > > + IMX8QM_CSR_MISC_OFFSET, > > > + > > IMX8QM_CSR_MISC_IOB_A_0_TXOE | > > > + > > IMX8QM_CSR_MISC_IOB_A_0_M1M0_MASK, > > > + > > IMX8QM_CSR_MISC_IOB_A_0_TXOE | > > > + > > IMX8QM_CSR_MISC_IOB_A_0_M1M0_2); > > > + } > > > > Same here. It looks like specifying "ext_osc" for one controller and le= aving it > > out for another would lead to different outcome based on which controll= er > > gets initialized first. > > > > It seems that maybe abstracting all of this away via a generic PHY subs= ystem > > would be a better path. See for example pci-dra7xx.c which looks like i= t might > > be a good example. > > > [Richard Zhu] Okay, would following your suggestions. > Thanks a lot. > > > + > > > + break; > > > case IMX8MQ: > > > /* > > > * TODO: Currently this code assumes external @@ > > > -763,6 +1029,7 @@ static int imx6_pcie_wait_for_speed_change(struct > > > imx6_pcie *imx6_pcie) > > > > > > static void imx6_pcie_ltssm_enable(struct device *dev) { > > > + u32 val; > > > struct imx6_pcie *imx6_pcie =3D dev_get_drvdata(dev); > > > > > > switch (imx6_pcie->drvdata->variant) { @@ -777,6 +1044,15 > > @@ > > > static void imx6_pcie_ltssm_enable(struct device *dev) > > > case IMX8MQ: > > > reset_control_deassert(imx6_pcie->apps_reset); > > > break; > > > + case IMX8QXP: > > > + case IMX8QM: > > > + val =3D IMX8QM_CSR_PCIEA_OFFSET + > > > + imx6_pcie->controller_id * SZ_64K; > > > + regmap_update_bits(imx6_pcie->iomuxc_gpr, > > > + val + > > IMX8QM_CSR_PCIE_CTRL2_OFFSET, > > > + IMX8QM_CTRL_LTSSM_ENABLE, > > > + IMX8QM_CTRL_LTSSM_ENABLE); > > > + break; > > > } > > > } > > > > > > @@ -908,13 +1184,25 @@ static int imx6_add_pcie_port(struct imx6_pcie > > *imx6_pcie, > > > return 0; > > > } > > > > > > +static u64 imx6_pcie_cpu_addr_fixup(struct dw_pcie *pcie, u64 > > > +cpu_addr) { > > > + struct pcie_port *pp =3D &pcie->pp; > > > + struct imx6_pcie *imx6_pcie =3D to_imx6_pcie(pcie); > > > + > > > + if (imx6_pcie->drvdata->flags & > > IMX6_PCIE_FLAG_IMX6_CPU_ADDR_FIXUP) > > > + return (cpu_addr + imx6_pcie->local_addr - > > > + pp->mem_base); > > > > If you do > > > > cpu_addr +=3D mx6_pcie->local_addr - pp->mem_base; > > > > you won't need an else below. > > > [Richard Zhu] You're right. Thanks. > > > > + else > > > + return cpu_addr; > > > +} > > > + > > > static const struct dw_pcie_ops dw_pcie_ops =3D { > > > - /* No special ops needed, but pcie-designware still expects t= his > > struct */ > > > + .cpu_addr_fixup =3D imx6_pcie_cpu_addr_fixup, > > > }; > > > > > > #ifdef CONFIG_PM_SLEEP > > > static void imx6_pcie_ltssm_disable(struct device *dev) { > > > + u32 val; > > > struct imx6_pcie *imx6_pcie =3D dev_get_drvdata(dev); > > > > > > switch (imx6_pcie->drvdata->variant) { @@ -926,6 +1214,17 > > @@ > > > static void imx6_pcie_ltssm_disable(struct device *dev) > > > case IMX7D: > > > reset_control_assert(imx6_pcie->apps_reset); > > > break; > > > + case IMX8QXP: > > > + case IMX8QM: > > > + val =3D IMX8QM_CSR_PCIEA_OFFSET + > > > + imx6_pcie->controller_id * SZ_64K; > > > + regmap_update_bits(imx6_pcie->iomuxc_gpr, > > > + val + > > IMX8QM_CSR_PCIE_CTRL2_OFFSET, > > > + IMX8QM_CTRL_LTSSM_ENABLE, 0); > > > + regmap_update_bits(imx6_pcie->iomuxc_gpr, > > > + val + > > IMX8QM_CSR_PCIE_CTRL2_OFFSET, > > > + IMX8QM_CTRL_READY_ENTR_L23, > > 0); > > > + break; > > > default: > > > dev_err(dev, "ltssm_disable not supported\n"); > > > } > > > @@ -933,6 +1232,8 @@ static void imx6_pcie_ltssm_disable(struct devic= e > > > *dev) > > > > > > static void imx6_pcie_pm_turnoff(struct imx6_pcie *imx6_pcie) { > > > + int i; > > > + u32 addr, val; > > > struct device *dev =3D imx6_pcie->pci->dev; > > > > > > /* Some variants have a turnoff reset in DT */ @@ -951,6 > > > +1252,34 @@ static void imx6_pcie_pm_turnoff(struct imx6_pcie > > *imx6_pcie) > > > regmap_update_bits(imx6_pcie->iomuxc_gpr, > > IOMUXC_GPR12, > > > > > IMX6SX_GPR12_PCIE_PM_TURN_OFF, 0); > > > break; > > > + case IMX8QXP: > > > + case IMX8QM: > > > + addr =3D IMX8QM_CSR_PCIEA_OFFSET + > > > + imx6_pcie->controller_id * SZ_64K; > > > + regmap_update_bits(imx6_pcie->iomuxc_gpr, > > > + addr + > > IMX8QM_CSR_PCIE_CTRL2_OFFSET, > > > + > > IMX8QM_CTRL_PM_XMT_TURNOFF, > > > + > > IMX8QM_CTRL_PM_XMT_TURNOFF); > > > + regmap_update_bits(imx6_pcie->iomuxc_gpr, > > > + addr + > > IMX8QM_CSR_PCIE_CTRL2_OFFSET, > > > + > > IMX8QM_CTRL_PM_XMT_TURNOFF, 0); > > > > Is setting IMX8QM_CTRL_PM_XMT_TURNOFF on and then off necessary? I'd > > add a comment to highlight that this is intentional. > > > [Richard Zhu] Designer suggest to do so. One PME message would be kicked = off on the link after these turn on/off operations. > Yup, good to hear, that's exactly what I'd put in the comment :-) > > > + regmap_update_bits(imx6_pcie->iomuxc_gpr, > > > + addr + > > IMX8QM_CSR_PCIE_CTRL2_OFFSET, > > > + IMX8QM_CTRL_READY_ENTR_L23, > > > + > > IMX8QM_CTRL_READY_ENTR_L23); > > > + /* check the L2 is entered or not. */ > > > + for (i =3D 0; i < L2_ENTRY_WAIT_MAX_RETRIES; i++) { > > > + regmap_read(imx6_pcie->iomuxc_gpr, > > > + addr + > > IMX8QM_CSR_PCIE_STTS0_OFFSET, > > > + &val); > > > + if (val & > > IMX8QM_CTRL_STTS0_PM_LINKST_IN_L2) > > > + break; > > > + udelay(10); > > > + } > > > + if ((val & IMX8QM_CTRL_STTS0_PM_LINKST_IN_L2) =3D=3D > > 0) > > > + dev_err(dev, "PCIE%d can't enter into L2.\n", > > > + > > imx6_pcie->controller_id); > > > > regmap_read_poll_timeout() > > > [Richard Zhu] Okay, would use regmap_read_poll_timeout() in next version. > > > > + break; > > > default: > > > dev_err(dev, "PME_Turn_Off not implemented\n"); > > > return; > > > @@ -985,6 +1314,11 @@ static void imx6_pcie_clk_disable(struct > > imx6_pcie *imx6_pcie) > > > case IMX8MQ: > > > clk_disable_unprepare(imx6_pcie->pcie_aux); > > > break; > > > + case IMX8QXP: > > > + case IMX8QM: > > > + clk_disable_unprepare(imx6_pcie->pcie_per); > > > + clk_disable_unprepare(imx6_pcie->pcie_inbound_axi); > > > > You can probably piggy back on IMX6SX since it has "pcie_inbound_axi" a= s > > well. > > > [Richard Zhu] Okay, would follow your suggestion. Thanks. > Would change like below. > case IMX8QXP: > case IMX8QM: > clk_disable_unprepare(imx6_pcie->pcie_per); > case IMX6SX: > clk_disable_unprepare(imx6_pcie->pcie_inbound_axi); > break; > > > > + break; > > > default: > > > break; > > > } > > > @@ -1084,7 +1418,26 @@ static int imx6_pcie_probe(struct > > platform_device *pdev) > > > if (IS_ERR(pci->dbi_base)) > > > return PTR_ERR(pci->dbi_base); > > > > > > + if (of_property_read_u32(node, "hsio-cfg", > > &imx6_pcie->hsio_cfg)) > > > + imx6_pcie->hsio_cfg =3D 0; > > > + if (of_property_read_u32(node, "ext_osc", &imx6_pcie->ext_osc= ) > > < 0) > > > + imx6_pcie->ext_osc =3D 0; > > > + if (of_property_read_u32(node, "local-addr", > > &imx6_pcie->local_addr)) > > > + imx6_pcie->local_addr =3D 0; > > > > All of these properties will be initialized to zero by kzalloc and > > of_property_read_u32() won't modify output variable unless it is succes= sful, > > so you can probably skip error checking. > [Richard Zhu] Okay, would remove the error checking. > > > > > > + > > > /* Fetch GPIOs */ > > > + imx6_pcie->clkreq_gpio =3D of_get_named_gpio(node, "clkreq-gp= io", > > 0); > > > + if (gpio_is_valid(imx6_pcie->clkreq_gpio)) { > > > + ret =3D devm_gpio_request_one(&pdev->dev, > > imx6_pcie->clkreq_gpio, > > > + > > GPIOF_OUT_INIT_LOW, "PCIe CLKREQ"); > > > + if (ret) { > > > + dev_err(&pdev->dev, "unable to get clkreq > > gpio\n"); > > > + return ret; > > > + } > > > + } else if (imx6_pcie->clkreq_gpio =3D=3D -EPROBE_DEFER) { > > > + return imx6_pcie->clkreq_gpio; > > > + } > > > + > > > imx6_pcie->reset_gpio =3D of_get_named_gpio(node, "reset-gpio= ", > > 0); > > > imx6_pcie->gpio_active_high =3D of_property_read_bool(node, > > > > > > "reset-gpio-active-high"); @@ -1155,6 +1508,25 @@ static int > > imx6_pcie_probe(struct platform_device *pdev) > > > return PTR_ERR(imx6_pcie->pcie_aux); > > > } > > > break; > > > + case IMX8QM: > > > + case IMX8QXP: > > > + if (dbi_base->start =3D=3D IMX8_HSIO_PCIEB_BASE_ADDR) > > > + imx6_pcie->controller_id =3D 1; > > > + > > > + imx6_pcie->pcie_per =3D devm_clk_get(dev, "pcie_per")= ; > > > + if (IS_ERR(imx6_pcie->pcie_per)) { > > > + dev_err(dev, "pcie_per clock source missing > > or invalid\n"); > > > + return PTR_ERR(imx6_pcie->pcie_per); > > > + } > > > + > > > + imx6_pcie->pcie_inbound_axi =3D > > devm_clk_get(&pdev->dev, > > > + "pcie_inbound_axi"); > > > + if (IS_ERR(imx6_pcie->pcie_inbound_axi)) { > > > + dev_err(&pdev->dev, > > > + "pcie clock source missing or > > invalid\n"); > > > + return > > PTR_ERR(imx6_pcie->pcie_inbound_axi); > > > + } > > > > On i.MX8MQ "pcie_bus" clock in vendor tree wasn't actually pointing to > > actual PCIE bus clock, so it might be worth checking if that's the case= for > > i.MX8QM/X and you actually need one more clock. > [Richard Zhu] Regarding to my understanding, iMX PCIe module is connected= to AXI bus. > Thus, the AXI related clock can be treated as bus clock. Correct me if my= understand is wrong. > So, I use the pcie_bus clock for i.MX8QM/QXP PCIe in the dts binding. > Otherwise, I can use another new clock in codes to support i.MX8QM/QXP PC= Ies. > So, "pcie_bus" is supposed to be the clock driving PCIE bus itself. In this case the clock that is controlled by CLKREQ_B. On i.MX8MQ EVK that was an external 100 Mhz oscillator, so the final patch has "pcie_bus" pointing to a dedicated "fixed-clock": https://lore.kernel.org/lkml/20190220015857.7136-6-andrew.smirnov@gmail.com= /T/#u Originally vendor tree was using "pcie_bus" to point at IMX8MQ_CLK_PCIE1_AUX. If the situation on i.MX8QM/QXP is similar, then, yeah, I think it should be moved out into a separate clock. Thanks, Andrey Smirnov From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.7 required=3.0 tests=DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED,DKIM_VALID,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E9A02C43381 for ; Fri, 15 Mar 2019 02:18:42 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id B3B2421872 for ; Fri, 15 Mar 2019 02:18:42 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="G/fNPeSB"; dkim=fail reason="signature verification failed" (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="lREoL67I" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org B3B2421872 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:To:Subject:Message-ID:Date:From: In-Reply-To:References:MIME-Version:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=WYNwVt78fA/EAtUX6ufyhedJOIvD2oA0NHLyQBV2PMI=; b=G/fNPeSBh73lcQ vmkgKk7M1TSxuC4aBVTH/4eA79XOSaiGVdG986KL2UeZV4RKi9EhAIXOKR6M+tHsWLhBtK4oml/rX 5R5sr3zWwrjZVgh9EsE1hVVoQKU64/yHshE8xTBHfguYZC1drtUedXcItbQnHroBixUCuHIA5duo3 DIjVvd9BB1w1MeRYgA8jTn5VYSPoi6YdVTY1OcHAZanHZAZjYpalJQ5rwtx0CcpWqfnuEqIhFQV3U MiM1bwzAceuNaZPz139E/m07qvjQTQYNDopbRYEyCY2Z7APaJF1mWcl5+PszChi5b/sUfO4C5Qujy XDkH1Y0O7BmkFQ1kjkDA==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1h4cQc-0000F8-MA; Fri, 15 Mar 2019 02:18:34 +0000 Received: from mail-wr1-x441.google.com ([2a00:1450:4864:20::441]) by bombadil.infradead.org with esmtps (Exim 4.90_1 #2 (Red Hat Linux)) id 1h4cQY-0000Ek-0U for linux-arm-kernel@lists.infradead.org; Fri, 15 Mar 2019 02:18:32 +0000 Received: by mail-wr1-x441.google.com with SMTP id p1so7923114wrs.8 for ; Thu, 14 Mar 2019 19:18:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc:content-transfer-encoding; bh=xuuk/rNBwaXKQQzsXusdJ+tE4WGOvqqNaZWrnidZzaA=; b=lREoL67Id+bJGv6N/Ukv+JkfEC5IX8BWSY6DjuD3maXp8aPkPxPPYiVBsAAv+6JjNm /4qeJwhzIra75zywXU6MYOZW2xU8jb1EMlQY69W+zHTvIU7arTERTAR6EaR5VlCuq3iT Em+F2q+tUGY4g5y4a3WS9rgTrR+vbLu/XjMgLj9YijDSnDp0v9q9aQQKHA0Y1i7qytRk A1gMXjt2boTIG2lzHdvy/NoUukJFXCp6Hh4HZQvYqR+toAxOrOO/qFuQOSaNrlTWECul /Kc8PQ9qFdyTGTlrUx1exFDQD1wAes17Hm3iD54V27x2ADiNfhot153CO/TfJzWKjuyl 3lGw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc:content-transfer-encoding; bh=xuuk/rNBwaXKQQzsXusdJ+tE4WGOvqqNaZWrnidZzaA=; b=VOMSRanKzKZDHrJbA2Fa1GnDwGStNklHT8LknyKd4wZUIbqd/ZCwLdd+PiAd71QDbh y6i3TKYzJFMcYq0r9BNuWX+74zicJ2bhxyLqTgco3lQPL5COJ7AhpvEEsQmEyjlfHy2U Qgxl3E+6JnwtYb7A6mseCMqfyh5k2UTwvnJuXWrUrBxSxRj7HOQUcRfcSaMsQN3fCttN OH2lOkGQyZqUfSV4WEsXi7CAThon4zis43uVlDzX2eU1vvggMK78oFNo1kg8V9Tnw3d2 QPGiKkSuM8YkbgHiNeboCwyyRnFOQT0GFtbKuKxdlKv+2s0X1ucJ0aCMRlmGExge3tJH Zx3Q== X-Gm-Message-State: APjAAAVPuKu4eiteNLF0+pETy0PZ4nxEuU0U38YHmaPeIBMW1XE+d3kE hrMfop5tY4EPL0tyt3xifXXx5Uso8C9o3c7bd1E= X-Google-Smtp-Source: APXvYqwxC4j6x8EESQYASSA6L0bChxCPM2fML7Ejd6WO/VGWJE+ikb3QWDjFic8iF5h4a6G2vjRBtCeZKjYdbOVrnLU= X-Received: by 2002:adf:a147:: with SMTP id r7mr558504wrr.5.1552616307611; Thu, 14 Mar 2019 19:18:27 -0700 (PDT) MIME-Version: 1.0 References: <1552467452-538-1-git-send-email-hongxing.zhu@nxp.com> <1552467452-538-2-git-send-email-hongxing.zhu@nxp.com> In-Reply-To: From: Andrey Smirnov Date: Thu, 14 Mar 2019 19:18:15 -0700 Message-ID: Subject: Re: [RFC 2/2] PCI: imx6: Add support for i.MX8QM/QXP PCIe To: Richard Zhu X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190314_191830_093236_2DD01405 X-CRM114-Status: GOOD ( 39.16 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "lorenzo.pieralisi@arm.com" , "linux-pci@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "bhelgaas@google.com" , "linux-arm-kernel@lists.infradead.org" , "l.stach@pengutronix.de" Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org T24gVGh1LCBNYXIgMTQsIDIwMTkgYXQgMjoxOCBBTSBSaWNoYXJkIFpodSA8aG9uZ3hpbmcuemh1 QG54cC5jb20+IHdyb3RlOgo+Cj4gSGkgQW5kcmV5Ogo+IFRoYW5rcyBhIGxvdCBmb3IgeW91ciBy ZXZpZXcgY29tbWVudHMuCj4KPiBCZXN0IFJlZ2FyZHMKPiBSaWNoYXJkIFpodQo+IE9mZmljZTog ODYtMjEtMjg5MzcxODkKPiBNb2JpbGU6IDg2LTEzMzg2MDU5Nzg2Cj4KPgo+ID4gLS0tLS1Pcmln aW5hbCBNZXNzYWdlLS0tLS0KPiA+IEZyb206IEFuZHJleSBTbWlybm92IFttYWlsdG86YW5kcmV3 LnNtaXJub3ZAZ21haWwuY29tXQo+ID4gU2VudDogMjAxOeW5tDPmnIgxNOaXpSA0OjIwCj4gPiBU bzogUmljaGFyZCBaaHUgPGhvbmd4aW5nLnpodUBueHAuY29tPgo+ID4gQ2M6IGJoZWxnYWFzQGdv b2dsZS5jb207IGxvcmVuem8ucGllcmFsaXNpQGFybS5jb207Cj4gPiBsLnN0YWNoQHBlbmd1dHJv bml4LmRlOyBsaW51eC1wY2lAdmdlci5rZXJuZWwub3JnOwo+ID4gbGludXgtYXJtLWtlcm5lbEBs aXN0cy5pbmZyYWRlYWQub3JnOyBsaW51eC1rZXJuZWxAdmdlci5rZXJuZWwub3JnCj4gPiBTdWJq ZWN0OiBSZTogW1JGQyAyLzJdIFBDSTogaW14NjogQWRkIHN1cHBvcnQgZm9yIGkuTVg4UU0vUVhQ IFBDSWUKPiA+Cj4gPiBPbiBXZWQsIE1hciAxMywgMjAxOSBhdCAyOjE1IEFNIFJpY2hhcmQgWmh1 IDxob25neGluZy56aHVAbnhwLmNvbT4KPiA+IHdyb3RlOgo+ID4gPgo+ID4gPiBBZGQgY29kZXMg bmVlZGVkIHRvIHN1cHBvcnQgaS5NWDhRTS9RWFAgUENJZS4KPiA+ID4gLSBIU0lPKEhpZ2ggU3Bl ZWQgSU8pIHN1YnN5c3RlbSBpcyBuZXcgZGVmaW5lZCBvbiBpLk1YOFFNL1FYUC4KPiA+ID4gICBU aGUgUENJZSBhbmQgU0FUQSBtb2R1bGVzIGFyZSBjb250YWluZWQgaW4gdGhlIEhTSU8gc3Vic3lz dGVtLiBUaGVyZQo+ID4gPiAgIGFyZSB0d28gUENJZSwgb25lIFNBVEEgY29udHJvbGxlcnMgYW5k IHRocmVlIG1peGVkIGxhbmUgUEhZcyBvbgo+ID4gPiAgIGkuTVg4UU0uIFRoZXJlIGFyZSB0aHJl ZSB1c2UgY2FzZXMgb2YgdGhlIEhTSU8gc3Vic3lzdGVtIG9uCj4gPiBpLk1YOFFNLgo+ID4gPiAg IDEuIFBDSWVhIDIgbGFuZXMgYW5kIG9uZSBTQVRBIEFIQ0kgcG9ydC4KPiA+ID4gICAyLiBQQ0ll YSAxIGxhbmUsIFBDSWViIDEgbGFuZSBhbmQgb25lIFNBVEEgQUhDSSBwb3J0Lgo+ID4gPiAgIDMu IFBDSWVhIDIgbGFuZXMsIFBDSWViIDEgbGFuZS4KPiA+ID4gICBpLk1YOFFYUCBvbmx5IGhhcyBQ Q0llYiBjb250cm9sbGVyIGFuZCBvbmUgbGFuZSBQSFkuCj4gPiA+IC0gVGhlIEhTSU8gYWRkcmVz cyBtYXAgYXMgdmlld2VkIGZyb20gc3lzdGVtIGxldmVsIGlzIGFzIHNob3duIGJlbG93Lgo+ID4g PiAgIGFkZHJlc3MgWzMxOjI0XSAgICBMb2NhbCBhZGRyZXNzICAgIFRhcmdldCAgICBBZGRyZXNz IFNpemUKPiA+ID4gICA1RiAgICAgICAgICAgICAgICAgMCAgICAgICAgICAgICAgICBIU0lPICAg ICAgMTZNQgo+ID4gPiAgIDYwLTZGICAgICAgICAgICAgICA0MC00RiAgICAgICAgICAgIEhTSU8g ICAgICAyNTZNQgo+ID4gPiAgIDcwLTdGICAgICAgICAgICAgICA4MC04RiAgICAgICAgICAgIEhT SU8gICAgICAyNTZNQgo+ID4gPiAgIFNvLCB0aGUgY3B1X2FkZHJfZml4dXAgaXMgcmVxdWlyZWQg dG8gZW5hYmxlIGkuTVg4UU0vUVhQIFBDSWUuCj4gPiA+IC0gQm90aCBleHRlcm5hbCBPU0MgYW5k IGludGVybmFsIFBMTCBjYW4gYmUgdXNlZCBhcyBQQ0llIHJlZmVyZW5jZQo+ID4gPiAgIGNsb2Nr Lgo+ID4gPiAtIGNsb2NrIHJlcXVlc3QgR1BJTyBmb3IgY29udHJvbGxpbmcgdGhlIFBDSSByZWZl cmVuY2UgY2xvY2sgcmVxdWVzdAo+ID4gPiAgIHNpZ25hbC4gQW5kIHNob3VsZCBiZSBjb25maWd1 cmUgT0Qgd2hlbiBMMVNTIG1heWJlIGVuYWJsZWQgbGF0ZXIuCj4gPiA+IC0gT25lIG1vcmUgcG93 ZXIgZG9tYWluIEhTSU9fR1BJTyBhbmQgY2xvY2sgUENJRV9QRVIgYXJlIHJlcXVpcmVkIGJ5Cj4g PiA+ICAgaS5NWDhRTS9RWFAgUENJZS4KPiA+ID4KPiA+ID4gU2lnbmVkLW9mZi1ieTogUmljaGFy ZCBaaHUgPGhvbmd4aW5nLnpodUBueHAuY29tPgo+ID4gPiAtLS0KPiA+ID4gIGRyaXZlcnMvcGNp L2NvbnRyb2xsZXIvZHdjL3BjaS1pbXg2LmMgfCAzOTIKPiA+ID4gKysrKysrKysrKysrKysrKysr KysrKysrKysrKysrKysrLQo+ID4gPiAgMSBmaWxlIGNoYW5nZWQsIDM4NyBpbnNlcnRpb25zKCsp LCA1IGRlbGV0aW9ucygtKQo+ID4gPgo+ID4gPiBkaWZmIC0tZ2l0IGEvZHJpdmVycy9wY2kvY29u dHJvbGxlci9kd2MvcGNpLWlteDYuYwo+ID4gPiBiL2RyaXZlcnMvcGNpL2NvbnRyb2xsZXIvZHdj L3BjaS1pbXg2LmMKPiA+ID4gaW5kZXggYWFhOTQ4OS4uYWFjZWZiNiAxMDA2NDQKPiA+ID4gLS0t IGEvZHJpdmVycy9wY2kvY29udHJvbGxlci9kd2MvcGNpLWlteDYuYwo+ID4gPiArKysgYi9kcml2 ZXJzL3BjaS9jb250cm9sbGVyL2R3Yy9wY2ktaW14Ni5jCj4gPiA+IEBAIC0zOSw2ICszOSw3IEBA Cj4gPiA+ICAjZGVmaW5lIElNWDhNUV9HUFJfUENJRV9DTEtfUkVRX09WRVJSSURFICAgICAgIEJJ VCgxMSkKPiA+ID4gICNkZWZpbmUgSU1YOE1RX0dQUjEyX1BDSUUyX0NUUkxfREVWSUNFX1RZUEUg ICAgR0VOTUFTSygxMSwKPiA+IDgpCj4gPiA+ICAjZGVmaW5lIElNWDhNUV9QQ0lFMl9CQVNFX0FE RFIgICAgICAgICAgICAgICAgIDB4MzNjMDAwMDAKPiA+ID4gKyNkZWZpbmUgSU1YOF9IU0lPX1BD SUVCX0JBU0VfQUREUiAgICAgICAgICAgICAgMHg1ZjAxMDAwMAo+ID4gPgo+ID4gPiAgI2RlZmlu ZSB0b19pbXg2X3BjaWUoeCkgICAgICAgIGRldl9nZXRfZHJ2ZGF0YSgoeCktPmRldikKPiA+ID4K PiA+ID4gQEAgLTQ4LDEwICs0OSwxMyBAQCBlbnVtIGlteDZfcGNpZV92YXJpYW50cyB7Cj4gPiA+ ICAgICAgICAgSU1YNlFQLAo+ID4gPiAgICAgICAgIElNWDdELAo+ID4gPiAgICAgICAgIElNWDhN USwKPiA+ID4gKyAgICAgICBJTVg4UU0sCj4gPiA+ICsgICAgICAgSU1YOFFYUCwKPiA+ID4gIH07 Cj4gPiA+Cj4gPiA+ICAjZGVmaW5lIElNWDZfUENJRV9GTEFHX0lNWDZfUEhZICAgICAgICAgICAg ICAgICAgICAgICAgQklUKDApCj4gPiA+ICAjZGVmaW5lIElNWDZfUENJRV9GTEFHX0lNWDZfU1BF RURfQ0hBTkdFICAgICAgIEJJVCgxKQo+ID4gPiArI2RlZmluZSBJTVg2X1BDSUVfRkxBR19JTVg2 X0NQVV9BRERSX0ZJWFVQICAgICBCSVQoMikKPiA+Cj4gPiBUaGlzIGlzIGFuIElNWDhRKiBzcGVj aWZpYyBmbGFnLCBzbyBpdCBwcm9iYWJseSBzaG91bGQgYmUgY2FsbGVkIHNvbWV0aGluZyBsaWtl Cj4gPiBJTVg2X1BDSUVfRkxBR19JTVg4UXhfQ1BVX0FERF9GSVhVUC4KPiBbUmljaGFyZCBaaHVd IE9rYXksIHdvdWxkIGNoYW5nZSBpdCBsYXRlci4KPiA+Cj4gPiA+Cj4gPiA+ICBzdHJ1Y3QgaW14 Nl9wY2llX2RydmRhdGEgewo+ID4gPiAgICAgICAgIGVudW0gaW14Nl9wY2llX3ZhcmlhbnRzIHZh cmlhbnQ7IEBAIC02MCwxMCArNjQsMTIgQEAgc3RydWN0Cj4gPiA+IGlteDZfcGNpZV9kcnZkYXRh IHsKPiA+ID4KPiA+ID4gIHN0cnVjdCBpbXg2X3BjaWUgewo+ID4gPiAgICAgICAgIHN0cnVjdCBk d19wY2llICAgICAgICAgICpwY2k7Cj4gPiA+ICsgICAgICAgaW50ICAgICAgICAgICAgICAgICAg ICAgY2xrcmVxX2dwaW87Cj4gPgo+ID4gSXMgdGhpcyByZWFsbHkgbmVjZXNzYXJ5PyBPbiBpLk1Y OE1RIHZlbmRvciB0cmVlIGZvciBzb21lIHVua25vd24gcmVhc29uCj4gPiB3b3VsZCByZWNvbmZp Z3VyZSBhIGRlZGljYXRlZCBDTEtSRVFfQiBzaWduYWwgYXMgYSBHUElPIGFuZCB0aGVuIHVzZSBp dCBhcwo+ID4gQ0xLUkVRIHNpZ25hbCB0aGF0IHdheSBpbnN0ZWFkIG9mIGNvbnRyb2xsaW5nIGl0 IHZpYSBkZWRpY2F0ZWQgYml0cyBpbiByZWdpc3Rlcgo+ID4gZmlsZSwgc28gSSBhbSB3b25kZXJp bmcgaWYgdGhhdCBpcyB0aGUgY2FzZSB3aXRoIFFNIGFuZCBRWFAuCj4gW1JpY2hhcmQgWmh1XSBU aGVyZSBpcyBhIHNhbWUgbWVjaGFuaXNtIG9mIHRoZSBDTEtSRVEgb24gaU1YOFFNL1FYUC9NUS4K PiBVcCB0byBub3csIHRoaXMgcGluIGlzIGNvbmZpZ3VyZWQgYXMgR1BJTywgYmVjYXVzZSB0aGF0 IHRoaXMgcGluIHdvdWxkIGJlIHB1bGwgdXAgd2hlbiBPRCBpcyBzZXQKPiBhbmQgdGhlIEVQIGRl dmljZSBkb2Vzbid0IHN1cHBvcnQgdGhlIEwxU1MgYXQgYWxsLgo+IFRodXMsIHRoZSBleHRlcm5h bCBDTEsgd291bGQgYmUgdHVybmVkIG9mZiBpbiB0aGlzIHNjZW5hcmlvLgo+IFRoaXMgcGluIHdv dWxkIGJlIHVzZWQgaW4gT0QoT3BlbiBEcmFpbikgbW9kZSB3aGVuIEwxU1MgaXMgZW5hYmxlZC4K PiBUaGUgTDFTUyBoYXMgYmVlbiB2ZXJpZmllZCBvbiBpTVg4TVEuIEJ1dCBJIGRvbid0IGhhdmUg YSBkeW5hbWljIG1ldGhvZCB0bwo+IHR1cm4gdGhlIEwxU1MgZmVhdHVyZSBvbiBhdCBSQyBzaWRl IHlldCB3aGVuIHRoZSBMMVNTIGlzIHN1cHBvcnRlZCBieSBFUC4KPiBDb25maWd1cmUgQ0xLX1JF USBhcyBHUElPIGhlcmUgY3VycmVudGx5LCBhbmQgaG9wZSB0byBmaWd1cmUgb3V0IG9uZSBzb2x1 dGlvbiBpbiBmdXR1cmUuCj4KCkhtbSwgSSBhbSBhZnJhaWQgSSBzdGlsbCBkb24ndCB1bmRlcnN0 YW5kIHdoeSB0aGF0IHBpbiBoYXMgdG8gYmUKY29udHJvbGxlZCB2aWEgR1BJTyBzdWJzeXN0ZW0u IEhlcmUgYXJlIG15IGFzc3VtcHRpb25zOgoKMS4gV2UgY2FuIGNvbmZpZ3VyZSwgc2F5LCBQQ0lF MCdzIENMS1JFUSBhcwpTQ19QX1BDSUVfQ1RSTDBfQ0xLUkVRX0JfSFNJT19QQ0lFMF9DTEtSRVFf QiBvbiBpLk1YOFFNLCB3aGljaCBzaG91bGQKYmUgb3BlbiBkcmFpbiBqdXN0IGJ5IENMS1JFUSdz IGRlZmluaXRpb24sIGFuZCB3ZSBjYW4sIGlmIG5lZWQgYmUsCmNvbmZpZ3VyZSBpbnRlcm5hbCBw dWxsIHVwIGluIHRoZSBzYW1lIHBpbm11eCBlbnRyeQoKMi4gSXQgaXMgcG9zc2libGUgdG8gZHJp dmVyIHRoYXQgcGluIG9wZW4vY2xvc2VkIHZpYSBzb21lIGJpdHMgaW4KcmVnaXN0ZXIgZmlsZS4g SU1YOE1RX0dQUl9QQ0lFX0NMS19SRVFfT1ZFUlJJREUgaW4gY2FzZSBvZiBpLk1YOE1RLAptYXli ZSBzb21ldGhpbmcgZWxzZSBmb3Igb3RoZXIgaS5NWDggU29DCgpnaXZlbiB0aG9zZSBhc3N1bXB0 aW9ucywgd2h5IHdvdWxkIHdlIG5lZWQgdG8gaW50cm9kdWNlIGEgbmV3IERUCmJpbmRpbmcgdG8g c3BlY2lmeSBhIEdQSU8gYW5kIHRoZW4gY29udHJvbCBpdCB2aWEgZ3Bpb19zZXRfdmFsdWUoKT8K QUZBSUNULCBhYnNlbmNlIG9yIHByZXNlbmNlIG9mIEwxU1Mgc3VwcG9ydCBzaG91bGQgYmUgaXJy ZWxldmFudC4KUGVyaGFwcyBzb21lIG9mIG15IGFzc3VtcHRpb25zIGlzIHdyb25nPyBPciBtYXli ZSB5b3VyIHVzZS1jYXNlIGRvZXMKdXNlIGEgZGVkaWNhdGVkIEdQSU8gcGluIHRoYXQgY2FuJ3Qg YmUgY29uZmlndXJlIGFzIENMS1JFUV9CIHZpYQpwaW5tdXg/Cgo+ID4KPiA+ID4gICAgICAgICBp bnQgICAgICAgICAgICAgICAgICAgICByZXNldF9ncGlvOwo+ID4gPiAgICAgICAgIGJvb2wgICAg ICAgICAgICAgICAgICAgIGdwaW9fYWN0aXZlX2hpZ2g7Cj4gPiA+ICAgICAgICAgc3RydWN0IGNs ayAgICAgICAgICAgICAgKnBjaWVfYnVzOwo+ID4gPiAgICAgICAgIHN0cnVjdCBjbGsgICAgICAg ICAgICAgICpwY2llX3BoeTsKPiA+ID4gKyAgICAgICBzdHJ1Y3QgY2xrICAgICAgICAgICAgICAq cGNpZV9wZXI7Cj4gPiA+ICAgICAgICAgc3RydWN0IGNsayAgICAgICAgICAgICAgKnBjaWVfaW5i b3VuZF9heGk7Cj4gPiA+ICAgICAgICAgc3RydWN0IGNsayAgICAgICAgICAgICAgKnBjaWU7Cj4g PiA+ICAgICAgICAgc3RydWN0IGNsayAgICAgICAgICAgICAgKnBjaWVfYXV4Owo+ID4gPiBAQCAt NzcsNiArODMsOSBAQCBzdHJ1Y3QgaW14Nl9wY2llIHsKPiA+ID4gICAgICAgICB1MzIgICAgICAg ICAgICAgICAgICAgICB0eF9kZWVtcGhfZ2VuMl82ZGI7Cj4gPiA+ICAgICAgICAgdTMyICAgICAg ICAgICAgICAgICAgICAgdHhfc3dpbmdfZnVsbDsKPiA+ID4gICAgICAgICB1MzIgICAgICAgICAg ICAgICAgICAgICB0eF9zd2luZ19sb3c7Cj4gPiA+ICsgICAgICAgdTMyICAgICAgICAgICAgICAg ICAgICAgaHNpb19jZmc7Cj4gPiA+ICsgICAgICAgdTMyICAgICAgICAgICAgICAgICAgICAgZXh0 X29zYzsKPiA+ID4gKyAgICAgICB1MzIgICAgICAgICAgICAgICAgICAgICBsb2NhbF9hZGRyOwo+ ID4gPiAgICAgICAgIGludCAgICAgICAgICAgICAgICAgICAgIGxpbmtfZ2VuOwo+ID4gPiAgICAg ICAgIHN0cnVjdCByZWd1bGF0b3IgICAgICAgICp2cGNpZTsKPiA+ID4gICAgICAgICB2b2lkIF9f aW9tZW0gICAgICAgICAgICAqcGh5X2Jhc2U7Cj4gPiA+IEBAIC04NSw2ICs5NCw4IEBAIHN0cnVj dCBpbXg2X3BjaWUgewo+ID4gPiAgICAgICAgIHN0cnVjdCBkZXZpY2UgICAgICAgICAgICpwZF9w Y2llOwo+ID4gPiAgICAgICAgIC8qIHBvd2VyIGRvbWFpbiBmb3IgcGNpZSBwaHkgKi8KPiA+ID4g ICAgICAgICBzdHJ1Y3QgZGV2aWNlICAgICAgICAgICAqcGRfcGNpZV9waHk7Cj4gPiA+ICsgICAg ICAgLyogcG93ZXIgZG9tYWluIGZvciBoc2lvIGdwaW8gdXNlZCBieSBwY2llICovCj4gPiA+ICsg ICAgICAgc3RydWN0IGRldmljZSAgICAgICAgICAgKnBkX2hzaW9fZ3BpbzsKPiA+ID4gICAgICAg ICBjb25zdCBzdHJ1Y3QgaW14Nl9wY2llX2RydmRhdGEgKmRydmRhdGE7ICB9Owo+ID4gPgo+ID4g PiBAQCAtOTIsNiArMTAzLDcgQEAgc3RydWN0IGlteDZfcGNpZSB7Cj4gPiA+ICAjZGVmaW5lIFBI WV9QTExfTE9DS19XQUlUX01BWF9SRVRSSUVTICAyMDAwCj4gPiA+ICAjZGVmaW5lIFBIWV9QTExf TE9DS19XQUlUX1VTTEVFUF9NSU4gICA1MAo+ID4gPiAgI2RlZmluZSBQSFlfUExMX0xPQ0tfV0FJ VF9VU0xFRVBfTUFYICAgMjAwCj4gPiA+ICsjZGVmaW5lIEwyX0VOVFJZX1dBSVRfTUFYX1JFVFJJ RVMgICAgICAxMDAwMAo+ID4gPgo+ID4gPiAgLyogUENJZSBSb290IENvbXBsZXggcmVnaXN0ZXJz IChtZW1vcnktbWFwcGVkKSAqLwo+ID4gPiAgI2RlZmluZSBQQ0lFX1JDX0lNWDZfTVNJX0NBUCAg ICAgICAgICAgICAgICAgICAweDUwCj4gPiA+IEBAIC0xNTcsNiArMTY5LDQzIEBAIHN0cnVjdCBp bXg2X3BjaWUgeyAgI2RlZmluZQo+ID4gPiBQSFlfUlhfT1ZSRF9JTl9MT19SWF9EQVRBX0VOICgx IDw8IDUpICAjZGVmaW5lCj4gPiA+IFBIWV9SWF9PVlJEX0lOX0xPX1JYX1BMTF9FTiAoMSA8PCAz KQo+ID4gPgo+ID4gPiArLyogaU1YOCBIU0lPIHJlZ2lzdGVycyAqLwo+ID4gPiArI2RlZmluZSBJ TVg4UU1fQ1NSX1BIWVgyX09GRlNFVAo+ID4gMHgwMDAwMAo+ID4gPiArI2RlZmluZSBJTVg4UU1f Q1NSX1BIWVgxX09GRlNFVAo+ID4gMHgxMDAwMAo+ID4gPiArI2RlZmluZSBJTVg4UU1fQ1NSX1BI WVhfU1RUUzBfT0ZGU0VUICAgICAgICAgICAweDQKPiA+ID4gKyNkZWZpbmUgSU1YOFFNX0NTUl9Q Q0lFQV9PRkZTRVQKPiA+IDB4MjAwMDAKPiA+ID4gKyNkZWZpbmUgSU1YOFFNX0NTUl9QQ0lFQl9P RkZTRVQKPiA+IDB4MzAwMDAKPiA+ID4gKyNkZWZpbmUgSU1YOFFNX0NTUl9QQ0lFX0NUUkwxX09G RlNFVCAgICAgICAgICAgMHg0Cj4gPiA+ICsjZGVmaW5lIElNWDhRTV9DU1JfUENJRV9DVFJMMl9P RkZTRVQgICAgICAgICAgIDB4OAo+ID4gPiArI2RlZmluZSBJTVg4UU1fQ1NSX1BDSUVfU1RUUzBf T0ZGU0VUICAgICAgICAgICAweEMKPiA+ID4gKyNkZWZpbmUgSU1YOFFNX0NTUl9NSVNDX09GRlNF VCAgICAgICAgICAgICAgICAgMHg1MDAwMAo+ID4gPiArCj4gPiA+ICsjZGVmaW5lIElNWDhRTV9D VFJMX0xUU1NNX0VOQUJMRSAgICAgICAgICAgICAgIEJJVCg0KQo+ID4gPiArI2RlZmluZSBJTVg4 UU1fQ1RSTF9SRUFEWV9FTlRSX0wyMyAgICAgICAgICAgICBCSVQoNSkKPiA+ID4gKyNkZWZpbmUg SU1YOFFNX0NUUkxfUE1fWE1UX1RVUk5PRkYgICAgICAgICAgICAgQklUKDkpCj4gPiA+ICsjZGVm aW5lIElNWDhRTV9DVFJMX0JVVFRPTl9SU1RfTiAgICAgICAgICAgICAgIEJJVCgyMSkKPiA+ID4g KyNkZWZpbmUgSU1YOFFNX0NUUkxfUEVSU1RfTiAgICAgICAgICAgICAgICAgICAgQklUKDIyKQo+ ID4gPiArI2RlZmluZSBJTVg4UU1fQ1RSTF9QT1dFUl9VUF9SU1RfTiAgICAgICAgICAgICBCSVQo MjMpCj4gPiA+ICsKPiA+ID4gKyNkZWZpbmUgSU1YOFFNX0NUUkxfU1RUUzBfUE1fTElOS1NUX0lO X0wyICAgICAgQklUKDEzKQo+ID4gPiArI2RlZmluZSBJTVg4UU1fQ1RSTF9TVFRTMF9QTV9SRVFf Q09SRV9SU1QgICAgICBCSVQoMTkpCj4gPiA+ICsjZGVmaW5lIElNWDhRTV9TVFRTMF9MQU5FMF9U WF9QTExfTE9DSyAgICAgICAgIEJJVCg0KQo+ID4gPiArI2RlZmluZSBJTVg4UU1fU1RUUzBfTEFO RTFfVFhfUExMX0xPQ0sgICAgICAgICBCSVQoMTIpCj4gPiA+ICsKPiA+ID4gKyNkZWZpbmUgSU1Y OFFNX1BDSUVfVFlQRV9NQVNLICAgICAgICAgICAgICAgICAgR0VOTUFTSygyNywKPiA+IDI0KQo+ ID4gPiArCj4gPiA+ICsjZGVmaW5lIElNWDhRTV9QSFlYMl9DVFJMMF9BUEJfTUFTSyAgICAgICAg ICAgIEdFTk1BU0soMSwKPiA+IDApCj4gPiA+ICsjZGVmaW5lIElNWDhRTV9QSFlfQVBCX1JTVE5f MCAgICAgICAgICAgICAgICAgIEJJVCgwKQo+ID4gPiArI2RlZmluZSBJTVg4UU1fUEhZX0FQQl9S U1ROXzEgICAgICAgICAgICAgICAgICBCSVQoMSkKPiA+ID4gKwo+ID4gPiArI2RlZmluZSBJTVg4 UU1fTUlTQ19JT0JfUlhFTkEgICAgICAgICAgICAgICAgICBCSVQoMCkKPiA+ID4gKyNkZWZpbmUg SU1YOFFNX01JU0NfSU9CX1RYRU5BICAgICAgICAgICAgICAgICAgQklUKDEpCj4gPiA+ICsjZGVm aW5lIElNWDhRTV9DU1JfTUlTQ19JT0JfQV8wX1RYT0UgICAgICAgICAgIEJJVCgyKQo+ID4gPiAr I2RlZmluZSBJTVg4UU1fQ1NSX01JU0NfSU9CX0FfMF9NMU0wX01BU0sgICAgICBHRU5NQVNLKDQs Cj4gPiAzKQo+ID4gPiArI2RlZmluZSBJTVg4UU1fQ1NSX01JU0NfSU9CX0FfMF9NMU0wXzIgICAg ICAgICBCSVQoNCkKPiA+ID4gKyNkZWZpbmUgSU1YOFFNX01JU0NfUEhZWDFfRVBDU19TRUwgICAg ICAgICAgICAgQklUKDEyKQo+ID4gPiArI2RlZmluZSBJTVg4UU1fTUlTQ19QQ0lFX0FCX1NFTEVD VCAgICAgICAgICAgICBCSVQoMTMpCj4gPiA+ICsKPiA+ID4gIHN0YXRpYyBpbnQgcGNpZV9waHlf cG9sbF9hY2soc3RydWN0IGlteDZfcGNpZSAqaW14Nl9wY2llLCBpbnQKPiA+ID4gZXhwX3ZhbCkg IHsKPiA+ID4gICAgICAgICBzdHJ1Y3QgZHdfcGNpZSAqcGNpID0gaW14Nl9wY2llLT5wY2k7IEBA IC0zNzMsMTQgKzQyMiw2NSBAQAo+ID4gPiBzdGF0aWMgaW50IGlteDZfcGNpZV9hdHRhY2hfcGQo c3RydWN0IGRldmljZSAqZGV2KQo+ID4gPiAgICAgICAgICAgICAgICAgcmV0dXJuIFBUUl9FUlIo bGluayk7Cj4gPiA+ICAgICAgICAgfQo+ID4gPgo+ID4gPiArICAgICAgIHN3aXRjaCAoaW14Nl9w Y2llLT5kcnZkYXRhLT52YXJpYW50KSB7Cj4gPiA+ICsgICAgICAgY2FzZSBJTVg4UU06Cj4gPiA+ ICsgICAgICAgY2FzZSBJTVg4UVhQOgo+ID4gPiArICAgICAgICAgICAgICAgaW14Nl9wY2llLT5w ZF9oc2lvX2dwaW8gPQo+ID4gZGV2X3BtX2RvbWFpbl9hdHRhY2hfYnlfbmFtZShkZXYsCj4gPiA+ ICsgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgImhzaW9fZ3BpbyIpOwo+ID4gPiArICAg ICAgICAgICAgICAgaWYgKElTX0VSUihpbXg2X3BjaWUtPnBkX2hzaW9fZ3BpbykpCj4gPiA+ICsg ICAgICAgICAgICAgICAgICAgICAgIHJldHVybiBQVFJfRVJSKGlteDZfcGNpZS0+cGRfaHNpb19n cGlvKTsKPiA+ID4gKwo+ID4gPiArICAgICAgICAgICAgICAgbGluayA9IGRldmljZV9saW5rX2Fk ZChkZXYsIGlteDZfcGNpZS0+cGRfaHNpb19ncGlvLAo+ID4gPiArICAgICAgICAgICAgICAgICAg ICAgICAgICAgICAgIERMX0ZMQUdfU1RBVEVMRVNTIHwKPiA+ID4gKyAgICAgICAgICAgICAgICAg ICAgICAgICAgICAgICBETF9GTEFHX1BNX1JVTlRJTUUgfAo+ID4gPiArICAgICAgICAgICAgICAg ICAgICAgICAgICAgICAgIERMX0ZMQUdfUlBNX0FDVElWRSk7Cj4gPiA+ICsgICAgICAgICAgICAg ICBpZiAoIWxpbmspIHsKPiA+ID4gKyAgICAgICAgICAgICAgICAgICAgICAgZGV2X2VycihkZXYs ICJGYWlsZWQgdG8gYWRkIGRldmljZV9saW5rIHRvIGdwaW8KPiA+IHBkLlxuIik7Cj4gPiA+ICsg ICAgICAgICAgICAgICAgICAgICAgIHJldHVybiAtRUlOVkFMOwo+ID4gPiArICAgICAgICAgICAg ICAgfQo+ID4gPiArCj4gPiA+ICsgICAgICAgICAgICAgICBicmVhazsKPiA+ID4gKyAgICAgICBk ZWZhdWx0Ogo+ID4gPiArICAgICAgICAgICAgICAgYnJlYWs7Cj4gPiA+ICsgICAgICAgfQo+ID4g PiArCj4gPiA+ICAgICAgICAgcmV0dXJuIDA7Cj4gPiA+ICB9Cj4gPiA+Cj4gPiA+ICBzdGF0aWMg dm9pZCBpbXg2X3BjaWVfYXNzZXJ0X2NvcmVfcmVzZXQoc3RydWN0IGlteDZfcGNpZSAqaW14Nl9w Y2llKQo+ID4gPiB7Cj4gPiA+ICsgICAgICAgdTMyIGFkZHI7Cj4gPiA+ICsgICAgICAgaW50IGk7 Cj4gPiA+ICAgICAgICAgc3RydWN0IGRldmljZSAqZGV2ID0gaW14Nl9wY2llLT5wY2ktPmRldjsK PiA+ID4KPiA+ID4gICAgICAgICBzd2l0Y2ggKGlteDZfcGNpZS0+ZHJ2ZGF0YS0+dmFyaWFudCkg ewo+ID4gPiArICAgICAgIGNhc2UgSU1YOFFYUDoKPiA+ID4gKyAgICAgICAgICAgICAgIGFkZHIg PSBJTVg4UU1fQ1NSX1BDSUVCX09GRlNFVCArCj4gPiA+ICsgSU1YOFFNX0NTUl9QQ0lFX0NUUkwy X09GRlNFVDsKPiA+Cj4gPiBUaGlzIGFuZCBzaW1pbGFyICJJTVg4UU1fQ1NSX1BDSUVBX09GRlNF VCArIGkgKiBTWl82NEsiIHBhdHRlcm4ga2VlcHMKPiA+IHBvcHBpbmcgdXAgcXVpdGUgZnJlcXVl bnRseSBpbiB0aGUgY29kZS4gSSB0aGluayBhdCB0aGUgdmVyeSBsZWFzdCBpdCB3b3VsZCBiZQo+ ID4gZ29vZCB0byBjYWxjdWxhdGUgdGhpcyBvZmZzZXQgaW4gcHJvYmUgYW5kIHN0b3JlIGl0IGFz IGEgbWVtYmVyIG9mIHN0cnVjdAo+ID4gaW14Nl9wY2llLiBIb3dldmVyIEkgZG8gd29uZGVyIGlm IHRoaXMgc2hvdWxkIGFjdHVhbGx5IGJlIGhhbmRsZSBieSBlaXRoZXIKPiA+IGRlY2xhcmluZyBh biBhZGRpdGlvbmFsIHN5c2NvbiByZWdtYXAgb2YgYWRkaXRpb25hbCByZWcvcmVnLW5hbWUgcHJv cGVydHkuCj4gPgo+IFtSaWNoYXJkIFpodV0gSU1ITywgSSBqdXN0IHJlZHVjZSBzb21lIG1vcmUg TUFDUk8gZGVmaW5pdGlvbnMgaW4gdGhlIGNvZGVzLgo+IEFjdHVhbGx5LCB0aGUgIklNWDhRTV9D U1JfUENJRUFfT0ZGU0VUICsgU1pfNjRLIiBzaG91bGQgYmUgdGhlIElNWDhRTV9DU1JfUENJRUJf T0ZGU0VULgo+IEkgY2FuIGFkZCBzb21lIG1vcmUgbWFjcm8tZGVmaW5pdGlvbnMsIGZvciBleGFt cGxlICIgSU1YOFFNX0NTUl9QQ0lFQl9PRkZTRVQgIiB0byByZW1vdmUgdGhlIGNhbGN1bGF0aW9u cyBsYXRlci4KPiBIb3cgZG8geW91IHRoaW5rIGFib3V0IHRoYXQ/Cj4KCkl0J3MgdWx0aW1hdGVs eSB1cCB0byB5b3UuIEkgd2FzIGp1c3QgcG9pbnRpbmcgb3V0IHRoYXQgdGhlIGNvZGUga2VlcHMK cmUtY2FsY3VsYXRpbmcgdGhlIHNhbWUgdGhpbmcgYWdhaW4gYW5kIGFnYWluLCBzbyBpdCBtaWdo dCBoYXZlCmJlbmVmaXRlZCBmcm9tIGNhY2hpbmcgdGhhdCB2YWx1ZS4KCj4gPiA+ICsgICAgICAg ICAgICAgICByZWdtYXBfdXBkYXRlX2JpdHMoaW14Nl9wY2llLT5pb211eGNfZ3ByLCBhZGRyLAo+ ID4gPiArICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgIElNWDhRTV9DVFJMX0JVVFRPTl9S U1RfTiwKPiA+ID4gKyAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICBJTVg4UU1fQ1RSTF9C VVRUT05fUlNUX04pOwo+ID4gPiArICAgICAgICAgICAgICAgcmVnbWFwX3VwZGF0ZV9iaXRzKGlt eDZfcGNpZS0+aW9tdXhjX2dwciwgYWRkciwKPiA+ID4gKyAgICAgICAgICAgICAgICAgICAgICAg ICAgICAgICBJTVg4UU1fQ1RSTF9QRVJTVF9OLAo+ID4gPiArICAgICAgICAgICAgICAgICAgICAg ICAgICAgICAgIElNWDhRTV9DVFJMX1BFUlNUX04pOwo+ID4gPiArICAgICAgICAgICAgICAgcmVn bWFwX3VwZGF0ZV9iaXRzKGlteDZfcGNpZS0+aW9tdXhjX2dwciwgYWRkciwKPiA+ID4gKwo+ID4g SU1YOFFNX0NUUkxfUE9XRVJfVVBfUlNUX04sCj4gPiA+ICsKPiA+IElNWDhRTV9DVFJMX1BPV0VS X1VQX1JTVF9OKTsKPiA+ID4gKyAgICAgICAgICAgICAgIGJyZWFrOwo+ID4gPiArICAgICAgIGNh c2UgSU1YOFFNOgo+ID4gPiArICAgICAgICAgICAgICAgZm9yIChpID0gMDsgaSA8PSBpbXg2X3Bj aWUtPmNvbnRyb2xsZXJfaWQ7IGkrKykgewo+ID4KPiA+IFRoaXMgbG9vcCBpcyBhIGJpdCBzdXJw cmlzaW5nIHRvIG1lLiBJdCdzIGhhcmQgdG8gdGVsbCB3aHkgeW91J2QgaXRlcmF0ZSBmcm9tIDAg dG8KPiA+IGNvbnRyb2xsZXJfaWQuIEkgdGhpbmsgaXQnZCBiZSBnb29kIHRvIGFkZCBhIGNvbW1l bnQgZXhwbGFpbmluZyB0aGUgbG9naWMKPiA+IGJlaGluZCB0aGlzIGNvZGUuCj4gPgo+IFtSaWNo YXJkIFpodV0gT2theSwgY29tbWVudHMgd291bGQgYmUgYWRkZWQgaGVyZS4KPiAvKgo+ICAqICBJ biBpLk1YOFFNLCB0d28gbGFuZXMgUEhZIGFuZCBvbmUgbGFuZSBQSFkgc2hhcmUgdGhlCj4gICog IHNhbWUgY2FsaWJyYXRpb24gc2lnbmFsLiBBbmQgb25lIGxhbmUgUEhZIHdvdWxkIHVzZQo+ICAq ICB0aGUgY2FsaWJyYXRpb24gb3V0cHV0IGZyb20gdHdvIGxhbmVzIFBIWS4gU28gUENJZUEKPiAg KiAgcmVsYXRlZCByZXNldHMgYXJlIGNvbmZpZ3VyZWQgYmVmb3JlIGNvbmZpZ3VyYXRpbmcgUENJ ZUIuCj4gICovCgpJdCBzb3VuZHMgbGlrZSB0aGlzIGNvZGUgcmVsaWVzIG9uIHRoZSBmYWN0IHRo YXQgUENJZUEgd2lsbCBiZQppbml0aWFsaXplZCBiZWZvcmUgUENJZUIuIEkgYW0gbm90IHN1cmUg dGhpcyBjYW4gYmUgZ3VhcmFudGVlZCBieSB0aGlzCmRyaXZlciwgc2luY2UgaXQgc3VwcG9ydHMg cHJvYmUgZGVmZXJyYWwgYW5kIFBDSWVBJ3MgcHJvYmluZyBjYW4gYmUKZGVsYXllZCBzbyB0aGF0 ICBQQ0llQidzIHdvdWxkIGhhcHBlbiBmaXJzdC4gQW0gSSBtaXNpbnRlcnByZXRpbmcKdGhpcz8g SWYgbm90IG1heWJlIHRoaXMgc2hvdWxkIGJlIG1vdmVkIG91dCB0byBQSFkgZHJpdmVyIGFzIHdl bGw/Cgo+ID4KPiA+ID4gKyAgICAgICAgICAgICAgICAgICAgICAgYWRkciA9IElNWDhRTV9DU1Jf UENJRUFfT0ZGU0VUICsgaSAqCj4gPiBTWl82NEs7Cj4gPiA+ICsgICAgICAgICAgICAgICAgICAg ICAgIGFkZHIgKz0gSU1YOFFNX0NTUl9QQ0lFX0NUUkwyX09GRlNFVDsKPiA+ID4gKyAgICAgICAg ICAgICAgICAgICAgICAgcmVnbWFwX3VwZGF0ZV9iaXRzKGlteDZfcGNpZS0+aW9tdXhjX2dwciwK PiA+IGFkZHIsCj4gPiA+ICsKPiA+IElNWDhRTV9DVFJMX0JVVFRPTl9SU1RfTiwKPiA+ID4gKwo+ ID4gSU1YOFFNX0NUUkxfQlVUVE9OX1JTVF9OKTsKPiA+ID4gKyAgICAgICAgICAgICAgICAgICAg ICAgcmVnbWFwX3VwZGF0ZV9iaXRzKGlteDZfcGNpZS0+aW9tdXhjX2dwciwKPiA+IGFkZHIsCj4g PiA+ICsKPiA+IElNWDhRTV9DVFJMX1BFUlNUX04sCj4gPiA+ICsKPiA+IElNWDhRTV9DVFJMX1BF UlNUX04pOwo+ID4gPiArICAgICAgICAgICAgICAgICAgICAgICByZWdtYXBfdXBkYXRlX2JpdHMo aW14Nl9wY2llLT5pb211eGNfZ3ByLAo+ID4gYWRkciwKPiA+ID4gKwo+ID4gSU1YOFFNX0NUUkxf UE9XRVJfVVBfUlNUX04sCj4gPiA+ICsKPiA+IElNWDhRTV9DVFJMX1BPV0VSX1VQX1JTVF9OKTsK PiA+ID4gKyAgICAgICAgICAgICAgIH0KPiA+ID4gKyAgICAgICAgICAgICAgIGJyZWFrOwo+ID4g PiAgICAgICAgIGNhc2UgSU1YN0Q6Cj4gPiA+ICAgICAgICAgY2FzZSBJTVg4TVE6Cj4gPiA+ICAg ICAgICAgICAgICAgICByZXNldF9jb250cm9sX2Fzc2VydChpbXg2X3BjaWUtPnBjaWVwaHlfcmVz ZXQpOwo+ID4gPiBAQCAtNDc3LDYgKzU3NywyMSBAQCBzdGF0aWMgaW50IGlteDZfcGNpZV9lbmFi bGVfcmVmX2NsayhzdHJ1Y3QKPiA+IGlteDZfcGNpZSAqaW14Nl9wY2llKQo+ID4gPgo+ID4gSU1Y OE1RX0dQUl9QQ0lFX0NMS19SRVFfT1ZFUlJJREVfRU4sCj4gPiA+Cj4gPiBJTVg4TVFfR1BSX1BD SUVfQ0xLX1JFUV9PVkVSUklERV9FTik7Cj4gPiA+ICAgICAgICAgICAgICAgICBicmVhazsKPiA+ ID4gKyAgICAgICBjYXNlIElNWDhRWFA6Cj4gPiA+ICsgICAgICAgY2FzZSBJTVg4UU06Cj4gPiA+ ICsgICAgICAgICAgICAgICByZXQgPQo+ID4gY2xrX3ByZXBhcmVfZW5hYmxlKGlteDZfcGNpZS0+ cGNpZV9pbmJvdW5kX2F4aSk7Cj4gPiA+ICsgICAgICAgICAgICAgICBpZiAocmV0KSB7Cj4gPiA+ ICsgICAgICAgICAgICAgICAgICAgICAgIGRldl9lcnIoZGV2LCAidW5hYmxlIHRvIGVuYWJsZSBw Y2llX2F4aQo+ID4gY2xvY2tcbiIpOwo+ID4gPiArICAgICAgICAgICAgICAgICAgICAgICBicmVh azsKPiA+ID4gKyAgICAgICAgICAgICAgIH0KPiA+ID4gKyAgICAgICAgICAgICAgIHJldCA9IGNs a19wcmVwYXJlX2VuYWJsZShpbXg2X3BjaWUtPnBjaWVfcGVyKTsKPiA+ID4gKyAgICAgICAgICAg ICAgIGlmIChyZXQpIHsKPiA+ID4gKyAgICAgICAgICAgICAgICAgICAgICAgZGV2X2VycihkZXYs ICJ1bmFibGUgdG8gZW5hYmxlIHBjaWVfcGVyCj4gPiBjbG9ja1xuIik7Cj4gPiA+ICsKPiA+IGNs a19kaXNhYmxlX3VucHJlcGFyZShpbXg2X3BjaWUtPnBjaWVfaW5ib3VuZF9heGkpOwo+ID4gPiAr ICAgICAgICAgICAgICAgICAgICAgICBicmVhazsKPiA+ID4gKyAgICAgICAgICAgICAgIH0KPiA+ ID4gKwo+ID4gPiArICAgICAgICAgICAgICAgYnJlYWs7Cj4gPiA+ICAgICAgICAgfQo+ID4gPgo+ ID4gPiAgICAgICAgIHJldHVybiByZXQ7Cj4gPiA+IEBAIC01MDEsNiArNjE2LDYzIEBAIHN0YXRp YyB2b2lkCj4gPiBpbXg3ZF9wY2llX3dhaXRfZm9yX3BoeV9wbGxfbG9jayhzdHJ1Y3QgaW14Nl9w Y2llICppbXg2X3BjaWUpCj4gPiA+ICAgICAgICAgZGV2X2VycihkZXYsICJQQ0llIFBMTCBsb2Nr IHRpbWVvdXRcbiIpOyAgfQo+ID4gPgo+ID4gPiArc3RhdGljIGludCBpbXg4X2hzaW9fcGNpZV93 YWl0X2Zvcl9waHlfcGxsX2xvY2soc3RydWN0IGlteDZfcGNpZQo+ID4gPiArKmlteDZfcGNpZSkg ewo+ID4gPiArICAgICAgIHUzMiByZXRyaWVzLCBhZGRyLCB2YWwsIGxvY2sgPSAwOwo+ID4gPiAr ICAgICAgIGludCByZXQ7Cj4gPiA+ICsgICAgICAgc3RydWN0IGR3X3BjaWUgKnBjaSA9IGlteDZf cGNpZS0+cGNpOwo+ID4gPiArICAgICAgIHN0cnVjdCBkZXZpY2UgKmRldiA9IHBjaS0+ZGV2Owo+ ID4gPiArCj4gPiA+ICsgICAgICAgYWRkciA9IElNWDhRTV9DU1JfUENJRUFfT0ZGU0VUICsgaW14 Nl9wY2llLT5jb250cm9sbGVyX2lkCj4gPiAqIFNaXzY0SzsKPiA+ID4gKyAgICAgICBhZGRyICs9 IElNWDhRTV9DU1JfUENJRV9TVFRTMF9PRkZTRVQ7Cj4gPiA+ICsgICAgICAgZm9yIChyZXRyaWVz ID0gMDsgcmV0cmllcyA8IFBIWV9QTExfTE9DS19XQUlUX01BWF9SRVRSSUVTOwo+ID4gcmV0cmll cysrKSB7Cj4gPiA+ICsgICAgICAgICAgICAgICByZWdtYXBfcmVhZChpbXg2X3BjaWUtPmlvbXV4 Y19ncHIsIGFkZHIsICZ2YWwpOwo+ID4gPiArICAgICAgICAgICAgICAgaWYgKCh2YWwgJiBJTVg4 UU1fQ1RSTF9TVFRTMF9QTV9SRVFfQ09SRV9SU1QpCj4gPiA9PSAwKQo+ID4gPiArICAgICAgICAg ICAgICAgICAgICAgICBicmVhazsKPiA+ID4gKyAgICAgICAgICAgICAgIHVkZWxheSgxKTsKPiA+ ID4gKyAgICAgICB9Cj4gPiA+ICsKPiA+ID4gKyAgICAgICBpZiAoKHZhbCAmIElNWDhRTV9DVFJM X1NUVFMwX1BNX1JFUV9DT1JFX1JTVCkgIT0gMCkgewo+ID4gPiArICAgICAgICAgICAgICAgZGV2 X2VycihkZXYsICJFUlJPUjogUE1fUkVRX0NPUkVfUlNUIGlzIHN0aWxsCj4gPiBzZXQuXG4iKTsK PiA+ID4gKyAgICAgICAgICAgICAgIHJldHVybiAtRU5PREVWOwo+ID4gPiArICAgICAgIH0KPiA+ ID4gKwo+ID4KPiA+IFlvdSBjYW4gcmVhbGx5IGN1dCBkb3duIG9uIGJvaWxlcnBsYXRlIGhlcmUg YnkgdXNpbmcKPiA+IHJlZ21hcF9yZWFkX3BvbGxfdGltZW91dCgpCj4gPgo+IFtSaWNoYXJkIFpo dV0gT2theSwgd291bGQgY2hhbmdlIGl0IGxhdGVyLgo+Cj4gPiA+ICsgICAgICAgYWRkciA9IElN WDhRTV9DU1JfUEhZWDJfT0ZGU0VUICsgaW14Nl9wY2llLT5jb250cm9sbGVyX2lkCj4gPiAqIFNa XzY0SzsKPiA+ID4gKyAgICAgICBhZGRyICs9IElNWDhRTV9DU1JfUEhZWF9TVFRTMF9PRkZTRVQ7 Cj4gPiA+ICsgICAgICAgZm9yIChyZXRyaWVzID0gMDsgcmV0cmllcyA8IFBIWV9QTExfTE9DS19X QUlUX01BWF9SRVRSSUVTOwo+ID4gcmV0cmllcysrKSB7Cj4gPiA+ICsgICAgICAgICAgICAgICBy ZWdtYXBfcmVhZChpbXg2X3BjaWUtPmlvbXV4Y19ncHIsIGFkZHIsICZ2YWwpOwo+ID4gPiArICAg ICAgICAgICAgICAgaWYgKGlteDZfcGNpZS0+aHNpb19jZmcgPT0gMikgewo+ID4gPiArICAgICAg ICAgICAgICAgICAgICAgICBpZiAoaW14Nl9wY2llLT5jb250cm9sbGVyX2lkID09IDApCj4gPiA+ ICsgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgbG9jayA9Cj4gPiBJTVg4UU1fU1RUUzBf TEFORTBfVFhfUExMX0xPQ0s7Cj4gPiA+ICsgICAgICAgICAgICAgICAgICAgICAgIGVsc2UKPiA+ ID4gKyAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICBsb2NrID0KPiA+IElNWDhRTV9TVFRT MF9MQU5FMV9UWF9QTExfTE9DSzsKPiA+ID4gKyAgICAgICAgICAgICAgIH0gZWxzZSBpZiAoaW14 Nl9wY2llLT5oc2lvX2NmZyA9PSAzKSB7Cj4gPiA+ICsgICAgICAgICAgICAgICAgICAgICAgIGxv Y2sgPQo+ID4gSU1YOFFNX1NUVFMwX0xBTkUwX1RYX1BMTF9MT0NLOwo+ID4gPiArICAgICAgICAg ICAgICAgICAgICAgICBpZiAoaW14Nl9wY2llLT5jb250cm9sbGVyX2lkID09IDApCj4gPiA+ICsg ICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgbG9jayB8PQo+ID4gSU1YOFFNX1NUVFMwX0xB TkUxX1RYX1BMTF9MT0NLOwo+ID4gPiArICAgICAgICAgICAgICAgfSBlbHNlIGlmIChpbXg2X3Bj aWUtPmhzaW9fY2ZnID09IDEpIHsKPiA+ID4gKyAgICAgICAgICAgICAgICAgICAgICAgbG9jayA9 Cj4gPiBJTVg4UU1fU1RUUzBfTEFORTBfVFhfUExMX0xPQ0s7Cj4gPiA+ICsgICAgICAgICAgICAg ICAgICAgICAgIGxvY2sgfD0KPiA+IElNWDhRTV9TVFRTMF9MQU5FMV9UWF9QTExfTE9DSzsKPiA+ ID4gKyAgICAgICAgICAgICAgIH0gZWxzZSB7Cj4gPiA+ICsgICAgICAgICAgICAgICAgICAgICAg IGRldl9lcnIoZGV2LCAiRVJST1I6IGlsbGVnYWwgaHNpb19jZmcKPiA+IHZhbHVlLlxuIik7Cj4g PiA+ICsgICAgICAgICAgICAgICAgICAgICAgIHJldHVybiAtRUlOVkFMOwo+ID4gPiArICAgICAg ICAgICAgICAgfQo+ID4gPiArICAgICAgICAgICAgICAgdmFsICY9IGxvY2s7Cj4gPiA+ICsgICAg ICAgICAgICAgICBpZiAodmFsID09IGxvY2spCj4gPiA+ICsgICAgICAgICAgICAgICAgICAgICAg IGJyZWFrOwo+ID4gPiArICAgICAgICAgICAgICAgdWRlbGF5KDEwKTsKPiA+ID4gKyAgICAgICB9 Cj4gPiA+ICsKPiA+ID4gKyAgICAgICBpZiAocmV0cmllcyA+PSBQSFlfUExMX0xPQ0tfV0FJVF9N QVhfUkVUUklFUykgewo+ID4gPiArICAgICAgICAgICAgICAgZGV2X2luZm8oZGV2LCAicGNpZSBw aHkgcGxsIGNhbid0IGJlIGxvY2tlZC5cbiIpOwo+ID4gPiArICAgICAgICAgICAgICAgcmV0ID0g LUVOT0RFVjsKPiA+ID4gKyAgICAgICB9IGVsc2Ugewo+ID4gPiArICAgICAgICAgICAgICAgZGV2 X2luZm8oZGV2LCAicGNpZSBwaHkgcGxsIGlzIGxvY2tlZC5cbiIpOwo+ID4gPiArICAgICAgIH0K PiA+ID4gKwo+ID4KPiA+IERpdHRvLgo+IFtSaWNoYXJkIFpodV0gR290IHRoYXQuIFRoYW5rcy4K PiA+Cj4gPiA+ICsgICAgICAgcmV0dXJuIHJldDsKPiA+ID4gK30KPiA+ID4gKwo+ID4gPiAgc3Rh dGljIHZvaWQgaW14Nl9wY2llX2RlYXNzZXJ0X2NvcmVfcmVzZXQoc3RydWN0IGlteDZfcGNpZQo+ ID4gPiAqaW14Nl9wY2llKSAgewo+ID4gPiAgICAgICAgIHN0cnVjdCBkd19wY2llICpwY2kgPSBp bXg2X3BjaWUtPnBjaTsgQEAgLTU1Myw2ICs3MjUsMTEgQEAKPiA+ID4gc3RhdGljIHZvaWQgaW14 Nl9wY2llX2RlYXNzZXJ0X2NvcmVfcmVzZXQoc3RydWN0IGlteDZfcGNpZSAqaW14Nl9wY2llKQo+ ID4gPiAgICAgICAgIH0KPiA+ID4KPiA+ID4gICAgICAgICBzd2l0Y2ggKGlteDZfcGNpZS0+ZHJ2 ZGF0YS0+dmFyaWFudCkgewo+ID4gPiArICAgICAgIGNhc2UgSU1YOFFYUDoKPiA+ID4gKyAgICAg ICBjYXNlIElNWDhRTToKPiA+ID4gKyAgICAgICAgICAgICAgIC8qIHdhaXQgZm9yIHBoeSBwbGwg bG9jayBmaXJzdGx5LiAqLwo+ID4gPiArICAgICAgICAgICAgICAgaW14OF9oc2lvX3BjaWVfd2Fp dF9mb3JfcGh5X3BsbF9sb2NrKGlteDZfcGNpZSk7Cj4gPiA+ICsgICAgICAgICAgICAgICBicmVh azsKPiA+ID4gICAgICAgICBjYXNlIElNWDhNUToKPiA+ID4gICAgICAgICAgICAgICAgIHJlc2V0 X2NvbnRyb2xfZGVhc3NlcnQoaW14Nl9wY2llLT5wY2llcGh5X3Jlc2V0KTsKPiA+ID4gICAgICAg ICAgICAgICAgIGJyZWFrOwo+ID4gPiBAQCAtNjEzLDI1ICs3OTAsMTE0IEBAIHN0YXRpYyB2b2lk Cj4gPiA+IGlteDZfcGNpZV9kZWFzc2VydF9jb3JlX3Jlc2V0KHN0cnVjdCBpbXg2X3BjaWUgKmlt eDZfcGNpZSkKPiA+ID4KPiA+ID4gIHN0YXRpYyB2b2lkIGlteDZfcGNpZV9jb25maWd1cmVfdHlw ZShzdHJ1Y3QgaW14Nl9wY2llICppbXg2X3BjaWUpICB7Cj4gPiA+IC0gICAgICAgdW5zaWduZWQg aW50IG1hc2ssIHZhbDsKPiA+ID4gLQo+ID4gPiAtICAgICAgIGlmIChpbXg2X3BjaWUtPmRydmRh dGEtPnZhcmlhbnQgPT0gSU1YOE1RICYmCj4gPiA+ICsgICAgICAgdW5zaWduZWQgaW50IG9mZnNl dCwgbWFzaywgdmFsOwo+ID4gPiArCj4gPiA+ICsgICAgICAgaWYgKGlteDZfcGNpZS0+ZHJ2ZGF0 YS0+dmFyaWFudCA9PSBJTVg4UU0gfHwKPiA+ID4gKyAgICAgICAgICAgaW14Nl9wY2llLT5kcnZk YXRhLT52YXJpYW50ID09IElNWDhRWFApIHsKPiA+Cj4gPiBTaW5jZSB0aGVyZSdzIG5vdyBtb3Jl IHRoYW4gdHdvIHBvc3NpYmlsaXRpZXMsIGl0J2QgcHJvYmFibHkgbWFrZSBzZW5zZSB0bwo+ID4g Y29udmVydCB0aGlzIGNvZGUgdG8gdXNlIHN3aXRjaCBzdGF0ZW1lbnQuCj4gW1JpY2hhcmQgWmh1 XSBPa2F5LCB3b3VsZCB1c2Ugc3dpdGNoIHN0YXRlbWVudCBsYXRlci4KPgo+ID4KPiA+ID4gKyAg ICAgICAgICAgICAgIG9mZnNldCA9IElNWDhRTV9DU1JfUENJRUFfT0ZGU0VUICsKPiA+ID4gKyAg ICAgICAgICAgICAgICAgICAgICAgaW14Nl9wY2llLT5jb250cm9sbGVyX2lkICogU1pfNjRLOwo+ ID4gPiArICAgICAgICAgICAgICAgbWFzayAgID0gSU1YOFFNX1BDSUVfVFlQRV9NQVNLOwo+ID4g PiArICAgICAgICAgICAgICAgdmFsICAgID0gRklFTERfUFJFUChJTVg4UU1fUENJRV9UWVBFX01B U0ssCj4gPiA+ICsgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgIFBDSV9FWFBfVFlQ RV9ST09UX1BPUlQpOwo+ID4gPiArICAgICAgIH0gZWxzZSBpZiAoaW14Nl9wY2llLT5kcnZkYXRh LT52YXJpYW50ID09IElNWDhNUSAmJgo+ID4gPiAgICAgICAgICAgICBpbXg2X3BjaWUtPmNvbnRy b2xsZXJfaWQgPT0gMSkgewo+ID4gPiArICAgICAgICAgICAgICAgb2Zmc2V0ID0gSU9NVVhDX0dQ UjEyOwo+ID4gPiAgICAgICAgICAgICAgICAgbWFzayAgID0KPiA+IElNWDhNUV9HUFIxMl9QQ0lF Ml9DVFJMX0RFVklDRV9UWVBFOwo+ID4gPiAgICAgICAgICAgICAgICAgdmFsICAgID0KPiA+IEZJ RUxEX1BSRVAoSU1YOE1RX0dQUjEyX1BDSUUyX0NUUkxfREVWSUNFX1RZUEUsCj4gPiA+ICAgICAg ICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgIFBDSV9FWFBfVFlQRV9ST09UX1BPUlQpOwo+ ID4gPiAgICAgICAgIH0gZWxzZSB7Cj4gPiA+ICsgICAgICAgICAgICAgICBvZmZzZXQgPSBJT01V WENfR1BSMTI7Cj4gPiA+ICAgICAgICAgICAgICAgICBtYXNrID0gSU1YNlFfR1BSMTJfREVWSUNF X1RZUEU7Cj4gPiA+ICAgICAgICAgICAgICAgICB2YWwgID0gRklFTERfUFJFUChJTVg2UV9HUFIx Ml9ERVZJQ0VfVFlQRSwKPiA+ID4gICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgIFBD SV9FWFBfVFlQRV9ST09UX1BPUlQpOwo+ID4gPiAgICAgICAgIH0KPiA+ID4KPiA+ID4gLSAgICAg ICByZWdtYXBfdXBkYXRlX2JpdHMoaW14Nl9wY2llLT5pb211eGNfZ3ByLCBJT01VWENfR1BSMTIs Cj4gPiBtYXNrLCB2YWwpOwo+ID4gPiArICAgICAgIHJlZ21hcF91cGRhdGVfYml0cyhpbXg2X3Bj aWUtPmlvbXV4Y19ncHIsIG9mZnNldCwgbWFzaywgdmFsKTsKPiA+ID4gIH0KPiA+ID4KPiA+ID4g IHN0YXRpYyB2b2lkIGlteDZfcGNpZV9pbml0X3BoeShzdHJ1Y3QgaW14Nl9wY2llICppbXg2X3Bj aWUpICB7Cj4gPiA+ICAgICAgICAgc3dpdGNoIChpbXg2X3BjaWUtPmRydmRhdGEtPnZhcmlhbnQp IHsKPiA+ID4gKyAgICAgICBjYXNlIElNWDhRWFA6Cj4gPiA+ICsgICAgICAgY2FzZSBJTVg4UU06 Cj4gPiA+ICsgICAgICAgICAgICAgICBpZiAoaW14Nl9wY2llLT5oc2lvX2NmZyA9PSAxKSB7Cj4g PiA+ICsgICAgICAgICAgICAgICAgICAgICAgIHJlZ21hcF91cGRhdGVfYml0cyhpbXg2X3BjaWUt PmlvbXV4Y19ncHIsCj4gPiA+ICsgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgSU1YOFFN X0NTUl9QSFlYMl9PRkZTRVQsCj4gPiA+ICsKPiA+IElNWDhRTV9QSFlYMl9DVFJMMF9BUEJfTUFT SywKPiA+ID4gKyAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICBJTVg4UU1fUEhZX0FQQl9S U1ROXzAgfAo+ID4gPiArICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgIElNWDhRTV9QSFlf QVBCX1JTVE5fMSk7Cj4gPiA+ICsKPiA+ID4gKyAgICAgICAgICAgICAgICAgICAgICAgcmVnbWFw X3VwZGF0ZV9iaXRzKGlteDZfcGNpZS0+aW9tdXhjX2dwciwKPiA+ID4gKyAgICAgICAgICAgICAg ICAgICAgICAgICAgICAgICBJTVg4UU1fQ1NSX01JU0NfT0ZGU0VULAo+ID4gPiArICAgICAgICAg ICAgICAgICAgICAgICAgICAgICAgIElNWDhRTV9NSVNDX1BIWVgxX0VQQ1NfU0VMLAo+ID4gPiAr ICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgIElNWDhRTV9NSVNDX1BIWVgxX0VQQ1NfU0VM KTsKPiA+ID4gKyAgICAgICAgICAgICAgICAgICAgICAgcmVnbWFwX3VwZGF0ZV9iaXRzKGlteDZf cGNpZS0+aW9tdXhjX2dwciwKPiA+ID4gKyAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICBJ TVg4UU1fQ1NSX01JU0NfT0ZGU0VULAo+ID4gPiArICAgICAgICAgICAgICAgICAgICAgICAgICAg ICAgIElNWDhRTV9NSVNDX1BDSUVfQUJfU0VMRUNULAo+ID4gPiArICAgICAgICAgICAgICAgICAg ICAgICAgICAgICAgIDApOwo+ID4gPiArICAgICAgICAgICAgICAgfSBlbHNlIGlmIChpbXg2X3Bj aWUtPmhzaW9fY2ZnID09IDIpIHsKPiA+ID4gKyAgICAgICAgICAgICAgICAgICAgICAgcmVnbWFw X3VwZGF0ZV9iaXRzKGlteDZfcGNpZS0+aW9tdXhjX2dwciwKPiA+ID4gKyAgICAgICAgICAgICAg ICAgICAgICAgICAgICAgICBJTVg4UU1fQ1NSX1BIWVgyX09GRlNFVCwKPiA+ID4gKwo+ID4gSU1Y OFFNX1BIWVgyX0NUUkwwX0FQQl9NQVNLLAo+ID4gPiArICAgICAgICAgICAgICAgICAgICAgICAg ICAgICAgIElNWDhRTV9QSFlfQVBCX1JTVE5fMCB8Cj4gPiA+ICsgICAgICAgICAgICAgICAgICAg ICAgICAgICAgICAgSU1YOFFNX1BIWV9BUEJfUlNUTl8xKTsKPiA+ID4gKwo+ID4gPiArICAgICAg ICAgICAgICAgICAgICAgICByZWdtYXBfdXBkYXRlX2JpdHMoaW14Nl9wY2llLT5pb211eGNfZ3By LAo+ID4gPiArICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgIElNWDhRTV9DU1JfTUlTQ19P RkZTRVQsCj4gPiA+ICsgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgSU1YOFFNX01JU0Nf UEhZWDFfRVBDU19TRUwsCj4gPiA+ICsgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgSU1Y OFFNX01JU0NfUEhZWDFfRVBDU19TRUwpOwo+ID4gPiArICAgICAgICAgICAgICAgICAgICAgICBy ZWdtYXBfdXBkYXRlX2JpdHMoaW14Nl9wY2llLT5pb211eGNfZ3ByLAo+ID4gPiArICAgICAgICAg ICAgICAgICAgICAgICAgICAgICAgIElNWDhRTV9DU1JfTUlTQ19PRkZTRVQsCj4gPiA+ICsgICAg ICAgICAgICAgICAgICAgICAgICAgICAgICAgSU1YOFFNX01JU0NfUENJRV9BQl9TRUxFQ1QsCj4g PiA+ICsgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgSU1YOFFNX01JU0NfUENJRV9BQl9T RUxFQ1QpOwo+ID4gPiArICAgICAgICAgICAgICAgfSBlbHNlIGlmIChpbXg2X3BjaWUtPmhzaW9f Y2ZnID09IDMpIHsKPiA+ID4gKyAgICAgICAgICAgICAgICAgICAgICAgaWYgKGlteDZfcGNpZS0+ Y29udHJvbGxlcl9pZCkKPiA+ID4gKwo+ID4gcmVnbWFwX3VwZGF0ZV9iaXRzKGlteDZfcGNpZS0+ aW9tdXhjX2dwciwKPiA+ID4gKwo+ID4gSU1YOFFNX0NTUl9QSFlYMV9PRkZTRVQsCj4gPiA+ICsK PiA+IElNWDhRTV9QSFlfQVBCX1JTVE5fMCwKPiA+ID4gKwo+ID4gSU1YOFFNX1BIWV9BUEJfUlNU Tl8wKTsKPiA+ID4gKyAgICAgICAgICAgICAgICAgICAgICAgZWxzZQo+ID4gPiArCj4gPiByZWdt YXBfdXBkYXRlX2JpdHMoaW14Nl9wY2llLT5pb211eGNfZ3ByLAo+ID4gPiArCj4gPiBJTVg4UU1f Q1NSX1BIWVgyX09GRlNFVCwKPiA+ID4gKwo+ID4gSU1YOFFNX1BIWVgyX0NUUkwwX0FQQl9NQVNL LAo+ID4gPiArCj4gPiBJTVg4UU1fUEhZX0FQQl9SU1ROXzAgfAo+ID4gPiArCj4gPiBJTVg4UU1f UEhZX0FQQl9SU1ROXzEpOwo+ID4gPiArCj4gPiA+ICsgICAgICAgICAgICAgICAgICAgICAgIHJl Z21hcF91cGRhdGVfYml0cyhpbXg2X3BjaWUtPmlvbXV4Y19ncHIsCj4gPiA+ICsgICAgICAgICAg ICAgICAgICAgICAgICAgICAgICAgSU1YOFFNX0NTUl9NSVNDX09GRlNFVCwKPiA+ID4gKyAgICAg ICAgICAgICAgICAgICAgICAgICAgICAgICBJTVg4UU1fTUlTQ19QSFlYMV9FUENTX1NFTCwKPiA+ IDApOwo+ID4gPiArICAgICAgICAgICAgICAgICAgICAgICByZWdtYXBfdXBkYXRlX2JpdHMoaW14 Nl9wY2llLT5pb211eGNfZ3ByLAo+ID4gPiArICAgICAgICAgICAgICAgICAgICAgICAgICAgICAg IElNWDhRTV9DU1JfTUlTQ19PRkZTRVQsCj4gPiA+ICsgICAgICAgICAgICAgICAgICAgICAgICAg ICAgICAgSU1YOFFNX01JU0NfUENJRV9BQl9TRUxFQ1QsCj4gPiA+ICsgICAgICAgICAgICAgICAg ICAgICAgICAgICAgICAgSU1YOFFNX01JU0NfUENJRV9BQl9TRUxFQ1QpOwo+ID4gPiArICAgICAg ICAgICAgICAgfQo+ID4gPiArCj4gPgo+ID4gVGhpcyBkb2Vzbid0IGxvb2sgY29udHJvbGxlciBp bmRlcGVuZGVudC9sb2NhbC4gV2hhdCB3b3VsZCBoYXBwZW4gaWYKPiA+IGNvbnRyb2xsZXIgMCBz cGVjaWZpZXMgaHNpb19jZmcgPT0gMiBhbmQgY29udHJvbGxlciAxIHNwZWNpZmllcyBoc2lvX2Nm ZyA9PSAxPwo+ID4KPiBbUmljaGFyZCBaaHVdWWVzLCBpdCBpcy4gVGhlcmUgYXJlIHVzYWdlIGRl cGVuZGVuY2VzIGJldHdlZW4gUENJZUEvUENJZUIgYW5kIFNBVEEgaW4gSFNJTyBzdWJzeXN0ZW0u Cj4gQlRXLCBJdCdzIGltcG9zc2libGUgZm9yIGNvbnRyb2xsZXIgMSB0byBzcGVjaWZ5IHRoZSBo c2lvX2NmZyB0byAiMSIsIHdoZW4gY29udHJvbGxlciAwIHNwZWNpZmllcyBoc2lvX2NmZz09Mi4K PiBUaGVyZSBhcmUgdGhyZWUgdXNhZ2UgY2FzZXMgb2YgdGhlIEhTSU8uCj4gSHNpb19jZmcgICAg cGNpZWEgICAgcGNpZWIgICAgc2F0YQo+IDEgICAgICAgICAgMmxhbmVzICAgTm8gICAgICBFbmFi bGVkCj4gMiAgICAgICAgICAxbGFuZSAgICAxbGFuZSAgICBFbmFibGVkCj4gMyAgICAgICAgICAy bGFuZXMgICAxbGFuZSAgICBObwo+IFNvLCB0aGUgcG9zc2libGUgaHNpb19jZmcgdmFsdWVzIGZv ciBQQ0llQiBpcyAyIG9yIDMuCgpJZiBJIHVuZGVyc3RhbmQgeW91IGNvcnJlY3RseSwgSSB0aGlu ayB3aGF0IHlvdSBtZWFuIGJ5ICJpbXBvc3NpYmxlIgppcyB0aGF0IGluIG9yZGVyIHRoaW5ncyB0 byB3b3JrIGNvcnJlY3RseSB3aGVuIGZpcnN0IGNvbnRyb2xsZXIgaXMKY29uZmlndXJlZCBhcyBo c2lvX2NmZyA9PSAxLCBzZWNvbmQgY29udG9sbGVyIF9oYXNfIHRvIGJlIHNwZWNpZmllZAp3aXRo IGhzaW9fY2ZnICE9IDEuIEhvd2V2ZXIsIHdoYXQgSSBhbSB0cnlpbmcgdG8gcG9pbnQgb3V0IGlz IHRoYXQgaXQKaXMgYW4gaW1wbGljaXQgZGVwZW5kZW5jeSBiZXR3ZWVuIHRoZSB0d28gY29udHJv bGxlcnMgYW5kIEFGQUlDVAp0aGVyZSdzIG5vIGVuZm9yY2VtZW50IG9mIGl0IHByZXZlbnRpbmcg bWUvdXNlciBmcm9tIGNyZWF0aW5nIGEgRFQKZmlsZSB3aGVyZSBoc2lvX2NmZyA9IDwxPiBmb3Ig Ym90aCBjb250cm9sbGVycy4gTW92aW5nIHRoaXMKY29uZmlndXJhdGlvbiBpbnRvIGEgc2VwYXJh dGUgUEhZIGRyaXZlciBzaG91bGQgc29sdmUgdGhpcywgaG93ZXZlci4KCj4KPiA+ID4gKyAgICAg ICAgICAgICAgIGlmIChpbXg2X3BjaWUtPmV4dF9vc2MpIHsKPiA+ID4gKyAgICAgICAgICAgICAg ICAgICAgICAgcmVnbWFwX3VwZGF0ZV9iaXRzKGlteDZfcGNpZS0+aW9tdXhjX2dwciwKPiA+ID4g KyAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICBJTVg4UU1fQ1NSX01JU0NfT0ZGU0VULAo+ ID4gPiArICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgIElNWDhRTV9NSVNDX0lPQl9SWEVO QSwKPiA+ID4gKyAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICBJTVg4UU1fTUlTQ19JT0Jf UlhFTkEpOwo+ID4gPiArICAgICAgICAgICAgICAgICAgICAgICByZWdtYXBfdXBkYXRlX2JpdHMo aW14Nl9wY2llLT5pb211eGNfZ3ByLAo+ID4gPiArICAgICAgICAgICAgICAgICAgICAgICAgICAg ICAgIElNWDhRTV9DU1JfTUlTQ19PRkZTRVQsCj4gPiA+ICsgICAgICAgICAgICAgICAgICAgICAg ICAgICAgICAgSU1YOFFNX01JU0NfSU9CX1RYRU5BLCAwKTsKPiA+ID4gKyAgICAgICAgICAgICAg IH0gZWxzZSB7Cj4gPiA+ICsgICAgICAgICAgICAgICAgICAgICAgIC8qIFRyeSB0byB1c2VkIHRo ZSBpbnRlcm5hbCBwbGwgYXMgcmVmIGNsayAqLwo+ID4gPiArICAgICAgICAgICAgICAgICAgICAg ICByZWdtYXBfdXBkYXRlX2JpdHMoaW14Nl9wY2llLT5pb211eGNfZ3ByLAo+ID4gPiArICAgICAg ICAgICAgICAgICAgICAgICAgICAgICAgIElNWDhRTV9DU1JfTUlTQ19PRkZTRVQsCj4gPiA+ICsg ICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgSU1YOFFNX01JU0NfSU9CX1JYRU5BLCAwKTsK PiA+ID4gKyAgICAgICAgICAgICAgICAgICAgICAgcmVnbWFwX3VwZGF0ZV9iaXRzKGlteDZfcGNp ZS0+aW9tdXhjX2dwciwKPiA+ID4gKyAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICBJTVg4 UU1fQ1NSX01JU0NfT0ZGU0VULAo+ID4gPiArICAgICAgICAgICAgICAgICAgICAgICAgICAgICAg IElNWDhRTV9NSVNDX0lPQl9UWEVOQSwKPiA+ID4gKyAgICAgICAgICAgICAgICAgICAgICAgICAg ICAgICBJTVg4UU1fTUlTQ19JT0JfVFhFTkEpOwo+ID4gPiArICAgICAgICAgICAgICAgICAgICAg ICByZWdtYXBfdXBkYXRlX2JpdHMoaW14Nl9wY2llLT5pb211eGNfZ3ByLAo+ID4gPiArICAgICAg ICAgICAgICAgICAgICAgICAgICAgICAgIElNWDhRTV9DU1JfTUlTQ19PRkZTRVQsCj4gPiA+ICsK PiA+IElNWDhRTV9DU1JfTUlTQ19JT0JfQV8wX1RYT0UgfAo+ID4gPiArCj4gPiBJTVg4UU1fQ1NS X01JU0NfSU9CX0FfMF9NMU0wX01BU0ssCj4gPiA+ICsKPiA+IElNWDhRTV9DU1JfTUlTQ19JT0Jf QV8wX1RYT0UgfAo+ID4gPiArCj4gPiBJTVg4UU1fQ1NSX01JU0NfSU9CX0FfMF9NMU0wXzIpOwo+ ID4gPiArICAgICAgICAgICAgICAgfQo+ID4KPiA+IFNhbWUgaGVyZS4gSXQgbG9va3MgbGlrZSBz cGVjaWZ5aW5nICJleHRfb3NjIiBmb3Igb25lIGNvbnRyb2xsZXIgYW5kIGxlYXZpbmcgaXQKPiA+ IG91dCBmb3IgYW5vdGhlciB3b3VsZCBsZWFkIHRvIGRpZmZlcmVudCBvdXRjb21lIGJhc2VkIG9u IHdoaWNoIGNvbnRyb2xsZXIKPiA+IGdldHMgaW5pdGlhbGl6ZWQgZmlyc3QuCj4gPgo+ID4gSXQg c2VlbXMgdGhhdCBtYXliZSBhYnN0cmFjdGluZyBhbGwgb2YgdGhpcyBhd2F5IHZpYSBhIGdlbmVy aWMgUEhZIHN1YnN5c3RlbQo+ID4gd291bGQgYmUgYSBiZXR0ZXIgcGF0aC4gU2VlIGZvciBleGFt cGxlIHBjaS1kcmE3eHguYyB3aGljaCBsb29rcyBsaWtlIGl0IG1pZ2h0Cj4gPiBiZSBhIGdvb2Qg ZXhhbXBsZS4KPiA+Cj4gW1JpY2hhcmQgWmh1XSBPa2F5LCB3b3VsZCBmb2xsb3dpbmcgeW91ciBz dWdnZXN0aW9ucy4KPiBUaGFua3MgYSBsb3QuCj4gPiA+ICsKPiA+ID4gKyAgICAgICAgICAgICAg IGJyZWFrOwo+ID4gPiAgICAgICAgIGNhc2UgSU1YOE1ROgo+ID4gPiAgICAgICAgICAgICAgICAg LyoKPiA+ID4gICAgICAgICAgICAgICAgICAqIFRPRE86IEN1cnJlbnRseSB0aGlzIGNvZGUgYXNz dW1lcyBleHRlcm5hbCBAQAo+ID4gPiAtNzYzLDYgKzEwMjksNyBAQCBzdGF0aWMgaW50IGlteDZf cGNpZV93YWl0X2Zvcl9zcGVlZF9jaGFuZ2Uoc3RydWN0Cj4gPiA+IGlteDZfcGNpZSAqaW14Nl9w Y2llKQo+ID4gPgo+ID4gPiAgc3RhdGljIHZvaWQgaW14Nl9wY2llX2x0c3NtX2VuYWJsZShzdHJ1 Y3QgZGV2aWNlICpkZXYpICB7Cj4gPiA+ICsgICAgICAgdTMyIHZhbDsKPiA+ID4gICAgICAgICBz dHJ1Y3QgaW14Nl9wY2llICppbXg2X3BjaWUgPSBkZXZfZ2V0X2RydmRhdGEoZGV2KTsKPiA+ID4K PiA+ID4gICAgICAgICBzd2l0Y2ggKGlteDZfcGNpZS0+ZHJ2ZGF0YS0+dmFyaWFudCkgeyBAQCAt Nzc3LDYgKzEwNDQsMTUKPiA+IEBACj4gPiA+IHN0YXRpYyB2b2lkIGlteDZfcGNpZV9sdHNzbV9l bmFibGUoc3RydWN0IGRldmljZSAqZGV2KQo+ID4gPiAgICAgICAgIGNhc2UgSU1YOE1ROgo+ID4g PiAgICAgICAgICAgICAgICAgcmVzZXRfY29udHJvbF9kZWFzc2VydChpbXg2X3BjaWUtPmFwcHNf cmVzZXQpOwo+ID4gPiAgICAgICAgICAgICAgICAgYnJlYWs7Cj4gPiA+ICsgICAgICAgY2FzZSBJ TVg4UVhQOgo+ID4gPiArICAgICAgIGNhc2UgSU1YOFFNOgo+ID4gPiArICAgICAgICAgICAgICAg dmFsID0gSU1YOFFNX0NTUl9QQ0lFQV9PRkZTRVQgKwo+ID4gPiArICAgICAgICAgICAgICAgICAg ICAgICBpbXg2X3BjaWUtPmNvbnRyb2xsZXJfaWQgKiBTWl82NEs7Cj4gPiA+ICsgICAgICAgICAg ICAgICByZWdtYXBfdXBkYXRlX2JpdHMoaW14Nl9wY2llLT5pb211eGNfZ3ByLAo+ID4gPiArICAg ICAgICAgICAgICAgICAgICAgICAgICAgICAgIHZhbCArCj4gPiBJTVg4UU1fQ1NSX1BDSUVfQ1RS TDJfT0ZGU0VULAo+ID4gPiArICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgIElNWDhRTV9D VFJMX0xUU1NNX0VOQUJMRSwKPiA+ID4gKyAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICBJ TVg4UU1fQ1RSTF9MVFNTTV9FTkFCTEUpOwo+ID4gPiArICAgICAgICAgICAgICAgYnJlYWs7Cj4g PiA+ICAgICAgICAgfQo+ID4gPiAgfQo+ID4gPgo+ID4gPiBAQCAtOTA4LDEzICsxMTg0LDI1IEBA IHN0YXRpYyBpbnQgaW14Nl9hZGRfcGNpZV9wb3J0KHN0cnVjdCBpbXg2X3BjaWUKPiA+ICppbXg2 X3BjaWUsCj4gPiA+ICAgICAgICAgcmV0dXJuIDA7Cj4gPiA+ICB9Cj4gPiA+Cj4gPiA+ICtzdGF0 aWMgdTY0IGlteDZfcGNpZV9jcHVfYWRkcl9maXh1cChzdHJ1Y3QgZHdfcGNpZSAqcGNpZSwgdTY0 Cj4gPiA+ICtjcHVfYWRkcikgewo+ID4gPiArICAgICAgIHN0cnVjdCBwY2llX3BvcnQgKnBwID0g JnBjaWUtPnBwOwo+ID4gPiArICAgICAgIHN0cnVjdCBpbXg2X3BjaWUgKmlteDZfcGNpZSA9IHRv X2lteDZfcGNpZShwY2llKTsKPiA+ID4gKwo+ID4gPiArICAgICAgIGlmIChpbXg2X3BjaWUtPmRy dmRhdGEtPmZsYWdzICYKPiA+IElNWDZfUENJRV9GTEFHX0lNWDZfQ1BVX0FERFJfRklYVVApCj4g PiA+ICsgICAgICAgICAgICAgICByZXR1cm4gKGNwdV9hZGRyICsgaW14Nl9wY2llLT5sb2NhbF9h ZGRyIC0KPiA+ID4gKyBwcC0+bWVtX2Jhc2UpOwo+ID4KPiA+IElmIHlvdSBkbwo+ID4KPiA+IGNw dV9hZGRyICs9IG14Nl9wY2llLT5sb2NhbF9hZGRyIC0gcHAtPm1lbV9iYXNlOwo+ID4KPiA+IHlv dSB3b24ndCBuZWVkIGFuIGVsc2UgYmVsb3cuCj4gPgo+IFtSaWNoYXJkIFpodV0gWW91J3JlIHJp Z2h0LiBUaGFua3MuCj4KPiA+ID4gKyAgICAgICBlbHNlCj4gPiA+ICsgICAgICAgICAgICAgICBy ZXR1cm4gY3B1X2FkZHI7Cj4gPiA+ICt9Cj4gPiA+ICsKPiA+ID4gIHN0YXRpYyBjb25zdCBzdHJ1 Y3QgZHdfcGNpZV9vcHMgZHdfcGNpZV9vcHMgPSB7Cj4gPiA+IC0gICAgICAgLyogTm8gc3BlY2lh bCBvcHMgbmVlZGVkLCBidXQgcGNpZS1kZXNpZ253YXJlIHN0aWxsIGV4cGVjdHMgdGhpcwo+ID4g c3RydWN0ICovCj4gPiA+ICsgICAgICAgLmNwdV9hZGRyX2ZpeHVwID0gaW14Nl9wY2llX2NwdV9h ZGRyX2ZpeHVwLAo+ID4gPiAgfTsKPiA+ID4KPiA+ID4gICNpZmRlZiBDT05GSUdfUE1fU0xFRVAK PiA+ID4gIHN0YXRpYyB2b2lkIGlteDZfcGNpZV9sdHNzbV9kaXNhYmxlKHN0cnVjdCBkZXZpY2Ug KmRldikgIHsKPiA+ID4gKyAgICAgICB1MzIgdmFsOwo+ID4gPiAgICAgICAgIHN0cnVjdCBpbXg2 X3BjaWUgKmlteDZfcGNpZSA9IGRldl9nZXRfZHJ2ZGF0YShkZXYpOwo+ID4gPgo+ID4gPiAgICAg ICAgIHN3aXRjaCAoaW14Nl9wY2llLT5kcnZkYXRhLT52YXJpYW50KSB7IEBAIC05MjYsNiArMTIx NCwxNwo+ID4gQEAKPiA+ID4gc3RhdGljIHZvaWQgaW14Nl9wY2llX2x0c3NtX2Rpc2FibGUoc3Ry dWN0IGRldmljZSAqZGV2KQo+ID4gPiAgICAgICAgIGNhc2UgSU1YN0Q6Cj4gPiA+ICAgICAgICAg ICAgICAgICByZXNldF9jb250cm9sX2Fzc2VydChpbXg2X3BjaWUtPmFwcHNfcmVzZXQpOwo+ID4g PiAgICAgICAgICAgICAgICAgYnJlYWs7Cj4gPiA+ICsgICAgICAgY2FzZSBJTVg4UVhQOgo+ID4g PiArICAgICAgIGNhc2UgSU1YOFFNOgo+ID4gPiArICAgICAgICAgICAgICAgdmFsID0gSU1YOFFN X0NTUl9QQ0lFQV9PRkZTRVQgKwo+ID4gPiArICAgICAgICAgICAgICAgICAgICAgICBpbXg2X3Bj aWUtPmNvbnRyb2xsZXJfaWQgKiBTWl82NEs7Cj4gPiA+ICsgICAgICAgICAgICAgICByZWdtYXBf dXBkYXRlX2JpdHMoaW14Nl9wY2llLT5pb211eGNfZ3ByLAo+ID4gPiArICAgICAgICAgICAgICAg ICAgICAgICAgICAgICAgIHZhbCArCj4gPiBJTVg4UU1fQ1NSX1BDSUVfQ1RSTDJfT0ZGU0VULAo+ ID4gPiArICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgIElNWDhRTV9DVFJMX0xUU1NNX0VO QUJMRSwgMCk7Cj4gPiA+ICsgICAgICAgICAgICAgICByZWdtYXBfdXBkYXRlX2JpdHMoaW14Nl9w Y2llLT5pb211eGNfZ3ByLAo+ID4gPiArICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgIHZh bCArCj4gPiBJTVg4UU1fQ1NSX1BDSUVfQ1RSTDJfT0ZGU0VULAo+ID4gPiArICAgICAgICAgICAg ICAgICAgICAgICAgICAgICAgIElNWDhRTV9DVFJMX1JFQURZX0VOVFJfTDIzLAo+ID4gMCk7Cj4g PiA+ICsgICAgICAgICAgICAgICBicmVhazsKPiA+ID4gICAgICAgICBkZWZhdWx0Ogo+ID4gPiAg ICAgICAgICAgICAgICAgZGV2X2VycihkZXYsICJsdHNzbV9kaXNhYmxlIG5vdCBzdXBwb3J0ZWRc biIpOwo+ID4gPiAgICAgICAgIH0KPiA+ID4gQEAgLTkzMyw2ICsxMjMyLDggQEAgc3RhdGljIHZv aWQgaW14Nl9wY2llX2x0c3NtX2Rpc2FibGUoc3RydWN0IGRldmljZQo+ID4gPiAqZGV2KQo+ID4g Pgo+ID4gPiAgc3RhdGljIHZvaWQgaW14Nl9wY2llX3BtX3R1cm5vZmYoc3RydWN0IGlteDZfcGNp ZSAqaW14Nl9wY2llKSAgewo+ID4gPiArICAgICAgIGludCBpOwo+ID4gPiArICAgICAgIHUzMiBh ZGRyLCB2YWw7Cj4gPiA+ICAgICAgICAgc3RydWN0IGRldmljZSAqZGV2ID0gaW14Nl9wY2llLT5w Y2ktPmRldjsKPiA+ID4KPiA+ID4gICAgICAgICAvKiBTb21lIHZhcmlhbnRzIGhhdmUgYSB0dXJu b2ZmIHJlc2V0IGluIERUICovIEBAIC05NTEsNgo+ID4gPiArMTI1MiwzNCBAQCBzdGF0aWMgdm9p ZCBpbXg2X3BjaWVfcG1fdHVybm9mZihzdHJ1Y3QgaW14Nl9wY2llCj4gPiAqaW14Nl9wY2llKQo+ ID4gPiAgICAgICAgICAgICAgICAgcmVnbWFwX3VwZGF0ZV9iaXRzKGlteDZfcGNpZS0+aW9tdXhj X2dwciwKPiA+IElPTVVYQ19HUFIxMiwKPiA+ID4KPiA+IElNWDZTWF9HUFIxMl9QQ0lFX1BNX1RV Uk5fT0ZGLCAwKTsKPiA+ID4gICAgICAgICAgICAgICAgIGJyZWFrOwo+ID4gPiArICAgICAgIGNh c2UgSU1YOFFYUDoKPiA+ID4gKyAgICAgICBjYXNlIElNWDhRTToKPiA+ID4gKyAgICAgICAgICAg ICAgIGFkZHIgPSBJTVg4UU1fQ1NSX1BDSUVBX09GRlNFVCArCj4gPiA+ICsgICAgICAgICAgICAg ICAgICAgICAgIGlteDZfcGNpZS0+Y29udHJvbGxlcl9pZCAqIFNaXzY0SzsKPiA+ID4gKyAgICAg ICAgICAgICAgIHJlZ21hcF91cGRhdGVfYml0cyhpbXg2X3BjaWUtPmlvbXV4Y19ncHIsCj4gPiA+ ICsgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgYWRkciArCj4gPiBJTVg4UU1fQ1NSX1BD SUVfQ1RSTDJfT0ZGU0VULAo+ID4gPiArCj4gPiBJTVg4UU1fQ1RSTF9QTV9YTVRfVFVSTk9GRiwK PiA+ID4gKwo+ID4gSU1YOFFNX0NUUkxfUE1fWE1UX1RVUk5PRkYpOwo+ID4gPiArICAgICAgICAg ICAgICAgcmVnbWFwX3VwZGF0ZV9iaXRzKGlteDZfcGNpZS0+aW9tdXhjX2dwciwKPiA+ID4gKyAg ICAgICAgICAgICAgICAgICAgICAgICAgICAgICBhZGRyICsKPiA+IElNWDhRTV9DU1JfUENJRV9D VFJMMl9PRkZTRVQsCj4gPiA+ICsKPiA+IElNWDhRTV9DVFJMX1BNX1hNVF9UVVJOT0ZGLCAwKTsK PiA+Cj4gPiBJcyBzZXR0aW5nIElNWDhRTV9DVFJMX1BNX1hNVF9UVVJOT0ZGIG9uIGFuZCB0aGVu IG9mZiBuZWNlc3Nhcnk/IEknZAo+ID4gYWRkIGEgY29tbWVudCB0byBoaWdobGlnaHQgdGhhdCB0 aGlzIGlzIGludGVudGlvbmFsLgo+ID4KPiBbUmljaGFyZCBaaHVdIERlc2lnbmVyIHN1Z2dlc3Qg dG8gZG8gc28uIE9uZSBQTUUgbWVzc2FnZSB3b3VsZCBiZSBraWNrZWQgb2ZmIG9uIHRoZSBsaW5r IGFmdGVyIHRoZXNlIHR1cm4gb24vb2ZmIG9wZXJhdGlvbnMuCj4KCll1cCwgZ29vZCB0byBoZWFy LCB0aGF0J3MgZXhhY3RseSB3aGF0IEknZCBwdXQgaW4gdGhlIGNvbW1lbnQgOi0pCgo+ID4gPiAr ICAgICAgICAgICAgICAgcmVnbWFwX3VwZGF0ZV9iaXRzKGlteDZfcGNpZS0+aW9tdXhjX2dwciwK PiA+ID4gKyAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICBhZGRyICsKPiA+IElNWDhRTV9D U1JfUENJRV9DVFJMMl9PRkZTRVQsCj4gPiA+ICsgICAgICAgICAgICAgICAgICAgICAgICAgICAg ICAgSU1YOFFNX0NUUkxfUkVBRFlfRU5UUl9MMjMsCj4gPiA+ICsKPiA+IElNWDhRTV9DVFJMX1JF QURZX0VOVFJfTDIzKTsKPiA+ID4gKyAgICAgICAgICAgICAgIC8qIGNoZWNrIHRoZSBMMiBpcyBl bnRlcmVkIG9yIG5vdC4gKi8KPiA+ID4gKyAgICAgICAgICAgICAgIGZvciAoaSA9IDA7IGkgPCBM Ml9FTlRSWV9XQUlUX01BWF9SRVRSSUVTOyBpKyspIHsKPiA+ID4gKyAgICAgICAgICAgICAgICAg ICAgICAgcmVnbWFwX3JlYWQoaW14Nl9wY2llLT5pb211eGNfZ3ByLAo+ID4gPiArICAgICAgICAg ICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgYWRkciArCj4gPiBJTVg4UU1fQ1NSX1BDSUVf U1RUUzBfT0ZGU0VULAo+ID4gPiArICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAg ICAgJnZhbCk7Cj4gPiA+ICsgICAgICAgICAgICAgICAgICAgICAgIGlmICh2YWwgJgo+ID4gSU1Y OFFNX0NUUkxfU1RUUzBfUE1fTElOS1NUX0lOX0wyKQo+ID4gPiArICAgICAgICAgICAgICAgICAg ICAgICAgICAgICAgIGJyZWFrOwo+ID4gPiArICAgICAgICAgICAgICAgICAgICAgICB1ZGVsYXko MTApOwo+ID4gPiArICAgICAgICAgICAgICAgfQo+ID4gPiArICAgICAgICAgICAgICAgaWYgKCh2 YWwgJiBJTVg4UU1fQ1RSTF9TVFRTMF9QTV9MSU5LU1RfSU5fTDIpID09Cj4gPiAwKQo+ID4gPiAr ICAgICAgICAgICAgICAgICAgICAgICBkZXZfZXJyKGRldiwgIlBDSUUlZCBjYW4ndCBlbnRlciBp bnRvIEwyLlxuIiwKPiA+ID4gKwo+ID4gaW14Nl9wY2llLT5jb250cm9sbGVyX2lkKTsKPiA+Cj4g PiByZWdtYXBfcmVhZF9wb2xsX3RpbWVvdXQoKQo+ID4KPiBbUmljaGFyZCBaaHVdIE9rYXksIHdv dWxkIHVzZSByZWdtYXBfcmVhZF9wb2xsX3RpbWVvdXQoKSBpbiBuZXh0IHZlcnNpb24uCj4KPiA+ ID4gKyAgICAgICAgICAgICAgIGJyZWFrOwo+ID4gPiAgICAgICAgIGRlZmF1bHQ6Cj4gPiA+ICAg ICAgICAgICAgICAgICBkZXZfZXJyKGRldiwgIlBNRV9UdXJuX09mZiBub3QgaW1wbGVtZW50ZWRc biIpOwo+ID4gPiAgICAgICAgICAgICAgICAgcmV0dXJuOwo+ID4gPiBAQCAtOTg1LDYgKzEzMTQs MTEgQEAgc3RhdGljIHZvaWQgaW14Nl9wY2llX2Nsa19kaXNhYmxlKHN0cnVjdAo+ID4gaW14Nl9w Y2llICppbXg2X3BjaWUpCj4gPiA+ICAgICAgICAgY2FzZSBJTVg4TVE6Cj4gPiA+ICAgICAgICAg ICAgICAgICBjbGtfZGlzYWJsZV91bnByZXBhcmUoaW14Nl9wY2llLT5wY2llX2F1eCk7Cj4gPiA+ ICAgICAgICAgICAgICAgICBicmVhazsKPiA+ID4gKyAgICAgICBjYXNlIElNWDhRWFA6Cj4gPiA+ ICsgICAgICAgY2FzZSBJTVg4UU06Cj4gPiA+ICsgICAgICAgICAgICAgICBjbGtfZGlzYWJsZV91 bnByZXBhcmUoaW14Nl9wY2llLT5wY2llX3Blcik7Cj4gPiA+ICsgICAgICAgICAgICAgICBjbGtf ZGlzYWJsZV91bnByZXBhcmUoaW14Nl9wY2llLT5wY2llX2luYm91bmRfYXhpKTsKPiA+Cj4gPiBZ b3UgY2FuIHByb2JhYmx5IHBpZ2d5IGJhY2sgb24gSU1YNlNYIHNpbmNlIGl0IGhhcyAicGNpZV9p bmJvdW5kX2F4aSIgYXMKPiA+IHdlbGwuCj4gPgo+IFtSaWNoYXJkIFpodV0gT2theSwgd291bGQg Zm9sbG93IHlvdXIgc3VnZ2VzdGlvbi4gVGhhbmtzLgo+IFdvdWxkIGNoYW5nZSBsaWtlIGJlbG93 Lgo+ICAgICAgICAgY2FzZSBJTVg4UVhQOgo+ICAgICAgICAgY2FzZSBJTVg4UU06Cj4gICAgICAg ICAgICAgICAgIGNsa19kaXNhYmxlX3VucHJlcGFyZShpbXg2X3BjaWUtPnBjaWVfcGVyKTsKPiAg ICAgICAgIGNhc2UgSU1YNlNYOgo+ICAgICAgICAgICAgICAgICBjbGtfZGlzYWJsZV91bnByZXBh cmUoaW14Nl9wY2llLT5wY2llX2luYm91bmRfYXhpKTsKPiAgICAgICAgICAgICAgICAgYnJlYWs7 Cj4KPiA+ID4gKyAgICAgICAgICAgICAgIGJyZWFrOwo+ID4gPiAgICAgICAgIGRlZmF1bHQ6Cj4g PiA+ICAgICAgICAgICAgICAgICBicmVhazsKPiA+ID4gICAgICAgICB9Cj4gPiA+IEBAIC0xMDg0 LDcgKzE0MTgsMjYgQEAgc3RhdGljIGludCBpbXg2X3BjaWVfcHJvYmUoc3RydWN0Cj4gPiBwbGF0 Zm9ybV9kZXZpY2UgKnBkZXYpCj4gPiA+ICAgICAgICAgaWYgKElTX0VSUihwY2ktPmRiaV9iYXNl KSkKPiA+ID4gICAgICAgICAgICAgICAgIHJldHVybiBQVFJfRVJSKHBjaS0+ZGJpX2Jhc2UpOwo+ ID4gPgo+ID4gPiArICAgICAgIGlmIChvZl9wcm9wZXJ0eV9yZWFkX3UzMihub2RlLCAiaHNpby1j ZmciLAo+ID4gJmlteDZfcGNpZS0+aHNpb19jZmcpKQo+ID4gPiArICAgICAgICAgICAgICAgaW14 Nl9wY2llLT5oc2lvX2NmZyA9IDA7Cj4gPiA+ICsgICAgICAgaWYgKG9mX3Byb3BlcnR5X3JlYWRf dTMyKG5vZGUsICJleHRfb3NjIiwgJmlteDZfcGNpZS0+ZXh0X29zYykKPiA+IDwgMCkKPiA+ID4g KyAgICAgICAgICAgICAgIGlteDZfcGNpZS0+ZXh0X29zYyA9IDA7Cj4gPiA+ICsgICAgICAgaWYg KG9mX3Byb3BlcnR5X3JlYWRfdTMyKG5vZGUsICJsb2NhbC1hZGRyIiwKPiA+ICZpbXg2X3BjaWUt PmxvY2FsX2FkZHIpKQo+ID4gPiArICAgICAgICAgICAgICAgaW14Nl9wY2llLT5sb2NhbF9hZGRy ID0gMDsKPiA+Cj4gPiBBbGwgb2YgdGhlc2UgcHJvcGVydGllcyB3aWxsIGJlIGluaXRpYWxpemVk IHRvIHplcm8gYnkga3phbGxvYyBhbmQKPiA+IG9mX3Byb3BlcnR5X3JlYWRfdTMyKCkgd29uJ3Qg bW9kaWZ5IG91dHB1dCB2YXJpYWJsZSB1bmxlc3MgaXQgaXMgc3VjY2Vzc2Z1bCwKPiA+IHNvIHlv dSBjYW4gcHJvYmFibHkgc2tpcCBlcnJvciBjaGVja2luZy4KPiBbUmljaGFyZCBaaHVdIE9rYXks IHdvdWxkIHJlbW92ZSB0aGUgZXJyb3IgY2hlY2tpbmcuCj4KPiA+Cj4gPiA+ICsKPiA+ID4gICAg ICAgICAvKiBGZXRjaCBHUElPcyAqLwo+ID4gPiArICAgICAgIGlteDZfcGNpZS0+Y2xrcmVxX2dw aW8gPSBvZl9nZXRfbmFtZWRfZ3Bpbyhub2RlLCAiY2xrcmVxLWdwaW8iLAo+ID4gMCk7Cj4gPiA+ ICsgICAgICAgaWYgKGdwaW9faXNfdmFsaWQoaW14Nl9wY2llLT5jbGtyZXFfZ3BpbykpIHsKPiA+ ID4gKyAgICAgICAgICAgICAgIHJldCA9IGRldm1fZ3Bpb19yZXF1ZXN0X29uZSgmcGRldi0+ZGV2 LAo+ID4gaW14Nl9wY2llLT5jbGtyZXFfZ3BpbywKPiA+ID4gKwo+ID4gR1BJT0ZfT1VUX0lOSVRf TE9XLCAiUENJZSBDTEtSRVEiKTsKPiA+ID4gKyAgICAgICAgICAgICAgIGlmIChyZXQpIHsKPiA+ ID4gKyAgICAgICAgICAgICAgICAgICAgICAgZGV2X2VycigmcGRldi0+ZGV2LCAidW5hYmxlIHRv IGdldCBjbGtyZXEKPiA+IGdwaW9cbiIpOwo+ID4gPiArICAgICAgICAgICAgICAgICAgICAgICBy ZXR1cm4gcmV0Owo+ID4gPiArICAgICAgICAgICAgICAgfQo+ID4gPiArICAgICAgIH0gZWxzZSBp ZiAoaW14Nl9wY2llLT5jbGtyZXFfZ3BpbyA9PSAtRVBST0JFX0RFRkVSKSB7Cj4gPiA+ICsgICAg ICAgICAgICAgICByZXR1cm4gaW14Nl9wY2llLT5jbGtyZXFfZ3BpbzsKPiA+ID4gKyAgICAgICB9 Cj4gPiA+ICsKPiA+ID4gICAgICAgICBpbXg2X3BjaWUtPnJlc2V0X2dwaW8gPSBvZl9nZXRfbmFt ZWRfZ3Bpbyhub2RlLCAicmVzZXQtZ3BpbyIsCj4gPiAwKTsKPiA+ID4gICAgICAgICBpbXg2X3Bj aWUtPmdwaW9fYWN0aXZlX2hpZ2ggPSBvZl9wcm9wZXJ0eV9yZWFkX2Jvb2wobm9kZSwKPiA+ID4K PiA+ID4gInJlc2V0LWdwaW8tYWN0aXZlLWhpZ2giKTsgQEAgLTExNTUsNiArMTUwOCwyNSBAQCBz dGF0aWMgaW50Cj4gPiBpbXg2X3BjaWVfcHJvYmUoc3RydWN0IHBsYXRmb3JtX2RldmljZSAqcGRl dikKPiA+ID4gICAgICAgICAgICAgICAgICAgICAgICAgcmV0dXJuIFBUUl9FUlIoaW14Nl9wY2ll LT5wY2llX2F1eCk7Cj4gPiA+ICAgICAgICAgICAgICAgICB9Cj4gPiA+ICAgICAgICAgICAgICAg ICBicmVhazsKPiA+ID4gKyAgICAgICBjYXNlIElNWDhRTToKPiA+ID4gKyAgICAgICBjYXNlIElN WDhRWFA6Cj4gPiA+ICsgICAgICAgICAgICAgICBpZiAoZGJpX2Jhc2UtPnN0YXJ0ID09IElNWDhf SFNJT19QQ0lFQl9CQVNFX0FERFIpCj4gPiA+ICsgICAgICAgICAgICAgICAgICAgICAgIGlteDZf cGNpZS0+Y29udHJvbGxlcl9pZCA9IDE7Cj4gPiA+ICsKPiA+ID4gKyAgICAgICAgICAgICAgIGlt eDZfcGNpZS0+cGNpZV9wZXIgPSBkZXZtX2Nsa19nZXQoZGV2LCAicGNpZV9wZXIiKTsKPiA+ID4g KyAgICAgICAgICAgICAgIGlmIChJU19FUlIoaW14Nl9wY2llLT5wY2llX3BlcikpIHsKPiA+ID4g KyAgICAgICAgICAgICAgICAgICAgICAgZGV2X2VycihkZXYsICJwY2llX3BlciBjbG9jayBzb3Vy Y2UgbWlzc2luZwo+ID4gb3IgaW52YWxpZFxuIik7Cj4gPiA+ICsgICAgICAgICAgICAgICAgICAg ICAgIHJldHVybiBQVFJfRVJSKGlteDZfcGNpZS0+cGNpZV9wZXIpOwo+ID4gPiArICAgICAgICAg ICAgICAgfQo+ID4gPiArCj4gPiA+ICsgICAgICAgICAgICAgICBpbXg2X3BjaWUtPnBjaWVfaW5i b3VuZF9heGkgPQo+ID4gZGV2bV9jbGtfZ2V0KCZwZGV2LT5kZXYsCj4gPiA+ICsgICAgICAgICAg ICAgICAgICAgICAgICAgICAgICAgInBjaWVfaW5ib3VuZF9heGkiKTsKPiA+ID4gKyAgICAgICAg ICAgICAgIGlmIChJU19FUlIoaW14Nl9wY2llLT5wY2llX2luYm91bmRfYXhpKSkgewo+ID4gPiAr ICAgICAgICAgICAgICAgICAgICAgICBkZXZfZXJyKCZwZGV2LT5kZXYsCj4gPiA+ICsgICAgICAg ICAgICAgICAgICAgICAgICAgICAgICAgInBjaWUgY2xvY2sgc291cmNlIG1pc3Npbmcgb3IKPiA+ IGludmFsaWRcbiIpOwo+ID4gPiArICAgICAgICAgICAgICAgICAgICAgICByZXR1cm4KPiA+IFBU Ul9FUlIoaW14Nl9wY2llLT5wY2llX2luYm91bmRfYXhpKTsKPiA+ID4gKyAgICAgICAgICAgICAg IH0KPiA+Cj4gPiBPbiBpLk1YOE1RICJwY2llX2J1cyIgY2xvY2sgaW4gdmVuZG9yIHRyZWUgd2Fz bid0IGFjdHVhbGx5IHBvaW50aW5nIHRvCj4gPiBhY3R1YWwgUENJRSBidXMgY2xvY2ssIHNvIGl0 IG1pZ2h0IGJlIHdvcnRoIGNoZWNraW5nIGlmIHRoYXQncyB0aGUgY2FzZSBmb3IKPiA+IGkuTVg4 UU0vWCBhbmQgeW91IGFjdHVhbGx5IG5lZWQgb25lIG1vcmUgY2xvY2suCj4gW1JpY2hhcmQgWmh1 XSBSZWdhcmRpbmcgdG8gbXkgdW5kZXJzdGFuZGluZywgaU1YIFBDSWUgbW9kdWxlIGlzIGNvbm5l Y3RlZCB0byBBWEkgYnVzLgo+IFRodXMsIHRoZSBBWEkgcmVsYXRlZCBjbG9jayBjYW4gYmUgdHJl YXRlZCBhcyBidXMgY2xvY2suIENvcnJlY3QgbWUgaWYgbXkgdW5kZXJzdGFuZCBpcyB3cm9uZy4K PiBTbywgSSB1c2UgdGhlIHBjaWVfYnVzIGNsb2NrIGZvciBpLk1YOFFNL1FYUCBQQ0llIGluIHRo ZSBkdHMgYmluZGluZy4KPiBPdGhlcndpc2UsIEkgY2FuIHVzZSBhbm90aGVyIG5ldyBjbG9jayBp biBjb2RlcyB0byBzdXBwb3J0IGkuTVg4UU0vUVhQIFBDSWVzLgo+CgpTbywgInBjaWVfYnVzIiBp cyBzdXBwb3NlZCB0byBiZSB0aGUgY2xvY2sgZHJpdmluZyBQQ0lFIGJ1cyBpdHNlbGYuIEluCnRo aXMgY2FzZSB0aGUgY2xvY2sgdGhhdCBpcyBjb250cm9sbGVkIGJ5IENMS1JFUV9CLiBPbiBpLk1Y OE1RIEVWSwp0aGF0IHdhcyBhbiBleHRlcm5hbCAxMDAgTWh6IG9zY2lsbGF0b3IsIHNvIHRoZSBm aW5hbCBwYXRjaCBoYXMKInBjaWVfYnVzIiBwb2ludGluZyB0byBhIGRlZGljYXRlZCAiZml4ZWQt Y2xvY2siOgpodHRwczovL2xvcmUua2VybmVsLm9yZy9sa21sLzIwMTkwMjIwMDE1ODU3LjcxMzYt Ni1hbmRyZXcuc21pcm5vdkBnbWFpbC5jb20vVC8jdQoKT3JpZ2luYWxseSB2ZW5kb3IgdHJlZSB3 YXMgdXNpbmcgInBjaWVfYnVzIiB0byBwb2ludCBhdApJTVg4TVFfQ0xLX1BDSUUxX0FVWC4gSWYg dGhlIHNpdHVhdGlvbiBvbiBpLk1YOFFNL1FYUCBpcyBzaW1pbGFyLAp0aGVuLCB5ZWFoLCBJIHRo aW5rIGl0IHNob3VsZCBiZSBtb3ZlZCBvdXQgaW50byBhIHNlcGFyYXRlIGNsb2NrLgoKVGhhbmtz LApBbmRyZXkgU21pcm5vdgoKX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19f X19fX19fX18KbGludXgtYXJtLWtlcm5lbCBtYWlsaW5nIGxpc3QKbGludXgtYXJtLWtlcm5lbEBs aXN0cy5pbmZyYWRlYWQub3JnCmh0dHA6Ly9saXN0cy5pbmZyYWRlYWQub3JnL21haWxtYW4vbGlz dGluZm8vbGludXgtYXJtLWtlcm5lbAo=