From mboxrd@z Thu Jan 1 00:00:00 1970 From: Michal Simek Date: Thu, 30 Apr 2020 09:34:06 +0200 Subject: [PATCH] xilinx: Introduce board_late_init_xilinx() In-Reply-To: <1c80f929f9ff22330c791c3c4441b487ad271b16.1586335808.git.michal.simek@xilinx.com> References: <1c80f929f9ff22330c791c3c4441b487ad271b16.1586335808.git.michal.simek@xilinx.com> Message-ID: List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de st 8. 4. 2020 v 10:50 odes?latel Michal Simek napsal: > > This function should keep common shared late configurations for Xilinx > SoCs. > > Signed-off-by: Michal Simek > --- > > board/xilinx/common/board.c | 8 ++++++++ > board/xilinx/common/board.h | 12 ++++++++++++ > board/xilinx/versal/board.c | 5 ++--- > board/xilinx/zynq/board.c | 5 ++--- > board/xilinx/zynqmp/zynqmp.c | 5 ++--- > 5 files changed, 26 insertions(+), 9 deletions(-) > create mode 100644 board/xilinx/common/board.h > > diff --git a/board/xilinx/common/board.c b/board/xilinx/common/board.c > index e83c692f2174..7c191e53fb71 100644 > --- a/board/xilinx/common/board.c > +++ b/board/xilinx/common/board.c > @@ -8,6 +8,7 @@ > #include > #include > #include > +#include "board.h" > > int zynq_board_read_rom_ethaddr(unsigned char *ethaddr) > { > @@ -71,3 +72,10 @@ void *board_fdt_blob_setup(void) > return NULL; > } > #endif > + > +int board_late_init_xilinx(void) > +{ > + env_set_hex("script_offset_f", CONFIG_BOOT_SCRIPT_OFFSET); > + > + return 0; > +} > diff --git a/board/xilinx/common/board.h b/board/xilinx/common/board.h > new file mode 100644 > index 000000000000..180dfbca1082 > --- /dev/null > +++ b/board/xilinx/common/board.h > @@ -0,0 +1,12 @@ > +/* SPDX-License-Identifier: GPL-2.0 */ > +/* > + * (C) Copyright 2020 Xilinx, Inc. > + * Michal Simek > + */ > + > +#ifndef _BOARD_XILINX_COMMON_BOARD_H > +#define _BOARD_XILINX_COMMON_BOARD_H > + > +int board_late_init_xilinx(void); > + > +#endif /* BOARD_XILINX_COMMON_BOARD_H */ > diff --git a/board/xilinx/versal/board.c b/board/xilinx/versal/board.c > index 75aedb092922..908ea87163f8 100644 > --- a/board/xilinx/versal/board.c > +++ b/board/xilinx/versal/board.c > @@ -17,6 +17,7 @@ > #include > #include > #include > +#include "../common/board.h" > > DECLARE_GLOBAL_DATA_PTR; > > @@ -204,9 +205,7 @@ int board_late_init(void) > initrd_hi = round_down(initrd_hi, SZ_16M); > env_set_addr("initrd_high", (void *)initrd_hi); > > - env_set_hex("script_offset_f", CONFIG_BOOT_SCRIPT_OFFSET); > - > - return 0; > + return board_late_init_xilinx(); > } > > int dram_init_banksize(void) > diff --git a/board/xilinx/zynq/board.c b/board/xilinx/zynq/board.c > index 420a5ca66311..2164eac8d518 100644 > --- a/board/xilinx/zynq/board.c > +++ b/board/xilinx/zynq/board.c > @@ -17,6 +17,7 @@ > #include > #include > #include > +#include "../common/board.h" > > DECLARE_GLOBAL_DATA_PTR; > > @@ -76,9 +77,7 @@ int board_late_init(void) > > env_set("boot_targets", new_targets); > > - env_set_hex("script_offset_f", CONFIG_BOOT_SCRIPT_OFFSET); > - > - return 0; > + return board_late_init_xilinx(); > } > > #if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE) > diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c > index 3c92b1a5825f..b2172356ad0a 100644 > --- a/board/xilinx/zynqmp/zynqmp.c > +++ b/board/xilinx/zynqmp/zynqmp.c > @@ -27,6 +27,7 @@ > #include > #include > #include > +#include "../common/board.h" > > #include "pm_cfg_obj.h" > > @@ -695,11 +696,9 @@ int board_late_init(void) > initrd_hi = round_down(initrd_hi, SZ_16M); > env_set_addr("initrd_high", (void *)initrd_hi); > > - env_set_hex("script_offset_f", CONFIG_BOOT_SCRIPT_OFFSET); > - > reset_reason(); > > - return 0; > + return board_late_init_xilinx(); > } > #endif > > -- > 2.26.0 > Applied but also fix antminer and topic Makefiles. Thanks, Michal -- Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91 w: www.monstr.eu p: +42-0-721842854 Maintainer of Linux kernel - Xilinx Microblaze Maintainer of Linux kernel - Xilinx Zynq ARM and ZynqMP ARM64 SoCs U-Boot custodian - Xilinx Microblaze/Zynq/ZynqMP/Versal SoCs