Re: [PATCH v2] net: zynq: Add support for mdio bus address decoding

[Michal Simek <monstr@monstr.eu>]

po 6. 12. 2021 v 14:53 odesílatel Michal Simek <michal.simek@xilinx.com> napsal:
>
> Xilinx DTS files are using two way how to describe ethernet phy.
>
> The first (already supported) has phy as subnode of gem node.
> eth {
>         phy-handle = <&phy0>;
>          phy0: ethernet-phy@21 {
>                 ...
>         };
> };
>
> The second has mdio subnode (with mdio name) which has phy subnode. This
> structure allow hadling MDIO reset signal (based on Linux mdio.yaml)
> eth {
>         phy-handle = <&phy0>;
>         mdio {
>                 phy0: ethernet-phy@21 {
>                         ...
>                 };
>         };
> };
>
> This patch adds support for the second case where mdio subnode
> is found driver will look at its parent to find out which gem is handling
> MDIO bus.
>
> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
> ---
>
> Changes in v2:
> - update commit message
>
>  drivers/net/zynq_gem.c | 3 +++
>  1 file changed, 3 insertions(+)
>
> diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c
> index 3e227725022d..fece077066df 100644
> --- a/drivers/net/zynq_gem.c
> +++ b/drivers/net/zynq_gem.c
> @@ -846,6 +846,9 @@ static int zynq_gem_of_to_plat(struct udevice *dev)
>                                                           SPEED_1000);
>
>                 parent = ofnode_get_parent(phandle_args.node);
> +               if (ofnode_name_eq(parent, "mdio"))
> +                       parent = ofnode_get_parent(parent);
> +
>                 addr = ofnode_get_addr(parent);
>                 if (addr != FDT_ADDR_T_NONE) {
>                         debug("MDIO bus not found %s\n", dev->name);
> --
> 2.33.1
>

Applied.
M

-- 
Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel - Xilinx Microblaze
Maintainer of Linux kernel - Xilinx Zynq ARM and ZynqMP ARM64 SoCs
U-Boot custodian - Xilinx Microblaze/Zynq/ZynqMP/Versal SoCs