From mboxrd@z Thu Jan 1 00:00:00 1970 From: Michal Simek Date: Thu, 30 Apr 2020 09:34:40 +0200 Subject: [PATCH] clk: versal: Fix watchdog clock issue In-Reply-To: <2dcf621848c491daf6cf4c7b0ff525687ecdc8c6.1586764375.git.michal.simek@xilinx.com> References: <2dcf621848c491daf6cf4c7b0ff525687ecdc8c6.1586764375.git.michal.simek@xilinx.com> Message-ID: List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de po 13. 4. 2020 v 9:53 odes?latel Michal Simek napsal: > > From: T Karthik Reddy > > Enable mux based clocks to populate LPD_LSBUS clock to xilinx_wwdt > driver. Skip reading clock rate for the mux based clocks with > parent clock id is zero. > > Signed-off-by: T Karthik Reddy > Signed-off-by: Ashok Reddy Soma > Signed-off-by: Michal Simek > --- > > drivers/clk/clk_versal.c | 5 ++++- > 1 file changed, 4 insertions(+), 1 deletion(-) > > diff --git a/drivers/clk/clk_versal.c b/drivers/clk/clk_versal.c > index d3673a5c8b81..075a08380d84 100644 > --- a/drivers/clk/clk_versal.c > +++ b/drivers/clk/clk_versal.c > @@ -503,6 +503,9 @@ static u64 versal_clock_calc(u32 clk_id) > NODE_CLASS_MASK) == NODE_SUBCLASS_CLOCK_REF) > return versal_clock_ref(clk_id); > > + if (!parent_id) > + return 0; > + > clk_rate = versal_clock_calc(parent_id); > > if (versal_clock_div(clk_id)) { > @@ -526,7 +529,7 @@ static int versal_clock_get_rate(u32 clk_id, u64 *clk_rate) > NODE_CLASS_MASK) == NODE_SUBCLASS_CLOCK_OUT && > ((clk_id >> NODE_CLASS_SHIFT) & > NODE_CLASS_MASK) == NODE_CLASS_CLOCK) { > - if (!versal_clock_gate(clk_id)) > + if (!versal_clock_gate(clk_id) && !versal_clock_mux(clk_id)) > return -EINVAL; > *clk_rate = versal_clock_calc(clk_id); > return 0; > -- > 2.26.0 > Applied. M -- Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91 w: www.monstr.eu p: +42-0-721842854 Maintainer of Linux kernel - Xilinx Microblaze Maintainer of Linux kernel - Xilinx Zynq ARM and ZynqMP ARM64 SoCs U-Boot custodian - Xilinx Microblaze/Zynq/ZynqMP/Versal SoCs