From mboxrd@z Thu Jan  1 00:00:00 1970
From: Alexander Kjeldaas <alexander.kjeldaas-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Subject: Re: PCIe3 atomics requirement for amdkfd
Date: Sat, 23 Dec 2017 17:26:25 +0100
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Cc: Felix Kuehling <felix.kuehling-5C7GfCeVMHo@public.gmane.org>, amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org, tstellar-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org

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 Can the atomic ops work on the modified risers used for mining?

On Dec 23, 2017 16:41, "Felix K=C3=BChling" <felix.kuehling-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> wrot=
e:

> As I understand it, it would require changes in the ROCr Runtime and in
> the firmware (MEC microcode). It also changes the programming model, so
> it may affect certain applications or higher level language runtimes
> that rely on atomic operations.
>
> Regards,
>   Felix
>
>
> Am 19.12.2017 um 16:04 schrieb Tom Stellard:
> > Hi,
> >
> > How hard of a requirement is PCIe3 atomics for dGPUs with the amdkfd
> > kernel driver?  Is it possible to make modifications to the
> runtime/kernel
> > driver to drop this requirement?
> >
> > -Tom
> > _______________________________________________
> > amd-gfx mailing list
> > amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
> > https://lists.freedesktop.org/mailman/listinfo/amd-gfx
>
>
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
>
>

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<div dir=3D"auto">=C2=A0Can the atomic ops work on the modified risers used=
 for mining?</div><div class=3D"gmail_extra"><br><div class=3D"gmail_quote"=
>On Dec 23, 2017 16:41, &quot;Felix K=C3=BChling&quot; &lt;<a href=3D"mailt=
o:felix.kuehling-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org">felix.kuehling-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org</a>&gt; wrote:<br type=
=3D"attribution"><blockquote class=3D"gmail_quote" style=3D"margin:0 0 0 .8=
ex;border-left:1px #ccc solid;padding-left:1ex">As I understand it, it woul=
d require changes in the ROCr Runtime and in<br>
the firmware (MEC microcode). It also changes the programming model, so<br>
it may affect certain applications or higher level language runtimes<br>
that rely on atomic operations.<br>
<br>
Regards,<br>
=C2=A0 Felix<br>
<br>
<br>
Am 19.12.2017 um 16:04 schrieb Tom Stellard:<br>
&gt; Hi,<br>
&gt;<br>
&gt; How hard of a requirement is PCIe3 atomics for dGPUs with the amdkfd<b=
r>
&gt; kernel driver?=C2=A0 Is it possible to make modifications to the runti=
me/kernel<br>
&gt; driver to drop this requirement?<br>
&gt;<br>
&gt; -Tom<br>
&gt; ______________________________<wbr>_________________<br>
&gt; amd-gfx mailing list<br>
&gt; <a href=3D"mailto:amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org">amd-gfx-PD4FTy7X32mqWrfYKbYh0A@public.gmane.org=
ktop.org</a><br>
&gt; <a href=3D"https://lists.freedesktop.org/mailman/listinfo/amd-gfx" rel=
=3D"noreferrer" target=3D"_blank">https://lists.freedesktop.org/<wbr>mailma=
n/listinfo/amd-gfx</a><br>
<br>
<br>
<br>______________________________<wbr>_________________<br>
amd-gfx mailing list<br>
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org</a><br>
<a href=3D"https://lists.freedesktop.org/mailman/listinfo/amd-gfx" rel=3D"n=
oreferrer" target=3D"_blank">https://lists.freedesktop.org/<wbr>mailman/lis=
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<br></blockquote></div></div>

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