From mboxrd@z Thu Jan  1 00:00:00 1970
From: Luis Araneda <luaraneda@gmail.com>
Date: Fri, 20 Jul 2018 12:17:44 -0400
Subject: [U-Boot] [RFC PATCH 0/4] arm: zynq: implement FPGA load from SPL
In-Reply-To: <cfd4e417-7015-aa22-7112-6c6651dea0a7@xilinx.com>
References: <20180718074141.16539-1-luaraneda@gmail.com>
 <8d595d25-d5d2-b434-6cb2-2522dd07cf43@xilinx.com>
 <CAHbBuxrQcTp2wUnSzD0bFVaEyG3YCKqSfVBcJs7AMSWiHZEYfQ@mail.gmail.com>
 <c0682b7a-31d9-f0c4-80d9-88c29eea7e35@xilinx.com>
 <CAHbBuxoorHa2-WJ5=rVcofoOinSZ-Lc7WuXzyag3cQV0cR4+mQ@mail.gmail.com>
 <cfd4e417-7015-aa22-7112-6c6651dea0a7@xilinx.com>
Message-ID: <CAHbBuxrwYZpHLj5FpkRq9U4iXyQzpv_-OvkCeBPfOyJ_a7bkwg@mail.gmail.com>
List-Id: <u-boot.lists.denx.de>
MIME-Version: 1.0
Content-Type: text/plain; charset="us-ascii"
Content-Transfer-Encoding: 7bit
To: u-boot@lists.denx.de

Hi Michal,

On Fri, Jul 20, 2018 at 6:38 AM Michal Simek <michal.simek@xilinx.com> wrote:
> On 20.7.2018 01:37, Luis Araneda wrote:
> > Hi Michal,
> >
> > On Thu, Jul 19, 2018 at 2:23 AM Michal Simek <michal.simek@xilinx.com> wrote:
> We need that functionality first but then enable it for all boards is
> fine for me and via one patch.

Ok

> Can you please be more specific what time1/time2 and time3 means?

The exact location of time 1/2/3 are on the attached diff file, and
they are placed within the spl_load_simple_fit() function.
They represent, roughly:
- time1: Time to load the the FIT image
- time2: Time to extract (and decompress)
  the FPGA image from the FIT image
- time3: Time to program the FPGA

Thanks,

Luis Araneda.