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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Huacai Chen , =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= , QEMU Developers , Huacai Chen , Aleksandar Rikalo , Aurelien Jarno Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" =D0=BD=D0=B5=D0=B4, 3. =D0=BC=D0=B0=D1=98 2020. =D1=83 12:24 Huacai Chen =D1=98=D0=B5 =D0=BD=D0=B0=D0=BF=D0=B8=D1=81=D0=B0=D0= =BE/=D0=BB=D0=B0: > > Currently, KVM/MIPS only deliver I/O interrupt via IP2, this patch add > IP3 delivery as well, because Loongson-3 based machine use both IRQ2 > (CPU's IP2) and IRQ3 (CPU's IP3). > > Signed-off-by: Huacai Chen > Co-developed-by: Jiaxun Yang > --- Reviewed-by: Aleksandar Markovic > hw/mips/mips_int.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/hw/mips/mips_int.c b/hw/mips/mips_int.c > index 796730b..982ce34 100644 > --- a/hw/mips/mips_int.c > +++ b/hw/mips/mips_int.c > @@ -48,14 +48,14 @@ static void cpu_mips_irq_request(void *opaque, int ir= q, int level) > if (level) { > env->CP0_Cause |=3D 1 << (irq + CP0Ca_IP); > > - if (kvm_enabled() && irq =3D=3D 2) { > + if (kvm_enabled() && (irq =3D=3D 2 || irq =3D=3D 3)) { > kvm_mips_set_interrupt(cpu, irq, level); > } > > } else { > env->CP0_Cause &=3D ~(1 << (irq + CP0Ca_IP)); > > - if (kvm_enabled() && irq =3D=3D 2) { > + if (kvm_enabled() && (irq =3D=3D 2 || irq =3D=3D 3)) { > kvm_mips_set_interrupt(cpu, irq, level); > } > } > -- > 2.7.0 >