Re: [PATCH] firmware: export x86_64 platform flash bios region via sysfs - Hans-Gert Dahmen

From: Hans-Gert Dahmen <hans-gert.dahmen@immu.ne>
To: Andy Shevchenko <andy.shevchenko@gmail.com>
Cc: Richard Hughes <hughsient@gmail.com>,
	Ard Biesheuvel <ardb@kernel.org>,
	Mika Westerberg <mika.westerberg@linux.intel.com>,
	Mauro Lima <mauro.lima@eclypsium.com>,
	Greg KH <gregkh@linuxfoundation.org>,
	"akpm@linux-foundation.org" <akpm@linux-foundation.org>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	Philipp Deppenwiese <philipp.deppenwiese@immu.ne>,
	"platform-driver-x86@vger.kernel.org" 
	<platform-driver-x86@vger.kernel.org>
Subject: Re: [PATCH] firmware: export x86_64 platform flash bios region via sysfs
Date: Thu, 11 Nov 2021 15:33:05 +0100	[thread overview]
Message-ID: <CAHifhD5bGZOcZFNsHYFeecikHGUts73U4k6=aUVNTKEeETW5rQ@mail.gmail.com> (raw)
In-Reply-To: <CAHp75Vfk5WHWiQxwmqEzVEymgpvjxKWEZbaQ9+=Et7N63Ps=Ng@mail.gmail.com>

Am Do., 11. Nov. 2021 um 14:55 Uhr schrieb Andy Shevchenko
<andy.shevchenko@gmail.com>:
>
> On Thu, Nov 11, 2021 at 2:56 PM Hans-Gert Dahmen
> <hans-gert.dahmen@immu.ne> wrote:
> >
> > Am Do., 11. Nov. 2021 um 13:46 Uhr schrieb Andy Shevchenko
> > <andy.shevchenko@gmail.com>:
> > >
> > > On Thu, Nov 11, 2021 at 1:46 PM Richard Hughes <hughsient@gmail.com> wrote:
> > > > On Thu, 11 Nov 2021 at 10:33, Mika Westerberg
> > > > <mika.westerberg@linux.intel.com> wrote:
> > >
> > > > it's always going to work on x64 -- if the system firmware isn't available at that offset then the platform just isn't going to boot.
> > >
> > > Well, it's _usual_ case, but in general the assumption is simply
> > > incorrect. Btw, have you checked it on Coreboot enabled platforms?
> > > What about bare metal configurations where the bootloader provides
> > > services to the OS?
> >
> > No it is always the case. I suggest you go read your own Intel specs
> > and datasheets
>
> Point me out, please, chapters in SDM (I never really read it in full,
> it's kinda 10x Bible size). What x86 expects is 16 bytes at the end of
> 1Mb physical address space that the CPU runs at first.

So you do not know what you are talking about, am I correct? Starting
from 386 the first instruction is executed at 0xFFFFFFF0h. What you
are referring to is the 8086 reset vector and that was like 40 years
ago.

Please refer to SDM volume 3A, chapter 9, section 9.1.4 "First
Instruction Executed", paragraph two. Just watch out for the hex
number train starting with FFFFF... then you will find it. This is
what requires the memory range to be mapped. Modern Intel CPUs require
larger portions, because of the ACM loading and XuCode and whatnot.
Please refer to the email [1] from me linked below where I reference
all PCH datasheets of the x64 era to prove that 16MB are mapped
hard-wired. Note that the range cannot be turned off and will read
back 0xFF's if the PCH registers are configured to not be backed by
the actual SPI flash contents.

[1] https://lkml.org/lkml/2021/6/24/379

>
> > before spreading further FUD. I have experienced u-root
> > and coreboot developers sitting right next to me in my office and they
> > were among the ones suggesting my patch. This is just laughable,
> > please stop it Andy.
>
> Yeah, zillion people can't ever make a mistake... I see.
>
> --
> With Best Regards,
> Andy Shevchenko

Hans-Gert