From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-3.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS,URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B434AC432BE for ; Wed, 28 Jul 2021 14:12:55 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 9A85560F9D for ; Wed, 28 Jul 2021 14:12:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236686AbhG1OMz (ORCPT ); Wed, 28 Jul 2021 10:12:55 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35222 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236671AbhG1OMz (ORCPT ); Wed, 28 Jul 2021 10:12:55 -0400 Received: from mail-ej1-x632.google.com (mail-ej1-x632.google.com [IPv6:2a00:1450:4864:20::632]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B700CC061757 for ; Wed, 28 Jul 2021 07:12:53 -0700 (PDT) Received: by mail-ej1-x632.google.com with SMTP id go31so4846024ejc.6 for ; Wed, 28 Jul 2021 07:12:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=hev-cc.20150623.gappssmtp.com; s=20150623; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=/kKRjCxopM8CkRMr4454ANstYPAv6D8HKTh0ZierECM=; b=L2uJr1MQKghT3ab4sSk4dze+O9j9Xgbz6p7ykN5TpJQtSXGd5Ra2mXQepbnEg3CsWd BUs28X/bc3+ABhDPkhiBwAUFzJOB+a65wRVU0hvAsSfDoEO4tp0rg90s7jhd4V0BFcB6 34Cew36g7LMtFDAyq6gV+Qw5mCme1rdtj+8rBjtO9Rhx2Nb21cSviQsmKCSTG6BZgeSM YqsuRd6BQCDBOw9Bcorf+Gou7G0PfzCzFagvEMYXQuy3rFvE05w7gtdPjnq9wBQGRYbH 5zFuPHgc/7SbaIlKXu66oaajtTa8aGKumdsLZZ6H8QzK2tPX4OVx3jdt0kr+yEJksurP CnEQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=/kKRjCxopM8CkRMr4454ANstYPAv6D8HKTh0ZierECM=; b=oOVFkEGC1luCdIQBKyLE8HD4nqa3aewfNgZCL26xQyciOI0XejRJstCcjb7Ax/lWa0 Q2zVMDG/AT2Rw2YVu8kDkFGP7e91nvdnAs24Q6//wo8kNOuGp733PVz1JeWBqtL8pMGA P7y+f47swoaeIMLCt76lev38nPRMarVLxHrgDvIDFwFHRjqHJz/c7/Jcfl20sBYlEbSM 3bxv4XFSliADMvWg7zV9VLEX8ruv1prE92ZgSjrcXE3wjwaAeOaZ/W+nnjrRd219hjb1 4ev2H0BLJXVdAoBiWoHiv7mS49GVUWcEr4qYMOS6uvg/I2xD50ZYchcTVO8hpFYXBFLG G9nQ== X-Gm-Message-State: AOAM533793+M99N3Y9OqTvbOQFrk4U3H2LFTzc5K1hNnSxycE6BbNc6N r6n4bTeIJdn9N48qqIGXaRhokYm73PNG+DjfOoq1Eg== X-Google-Smtp-Source: ABdhPJyIsQJ99idYHjog4sLH7SuUbrJrJj5wlhQV0jtVGnHGdvRupAYNriNUkcK6hQhfLu1z58/mSd0pxgw58i8M0+A= X-Received: by 2002:a17:906:c0d1:: with SMTP id bn17mr17229751ejb.511.1627481572316; Wed, 28 Jul 2021 07:12:52 -0700 (PDT) MIME-Version: 1.0 References: <20210728114822.1243-1-wangrui@loongson.cn> In-Reply-To: From: Hev Date: Wed, 28 Jul 2021 22:12:41 +0800 Message-ID: Subject: Re: [RFC PATCH v1 1/5] locking/atomic: Implement atomic_fetch_and_or To: Boqun Feng Cc: Rui Wang , Peter Zijlstra , Ingo Molnar , Will Deacon , Arnd Bergmann , Waiman Long , Guo Ren , linux-arch@vger.kernel.org, Xuefeng Li , Huacai Chen , Jiaxun Yang , Huacai Chen Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-arch@vger.kernel.org Hi, Boqun, On Wed, Jul 28, 2021 at 8:15 PM Boqun Feng wrote: > > Hi, > > Thanks for the patchset. Seems that your git send-email command doesn't > add the "In-Reply-to" tag for patch #2 to #5, so they are not threaded > to patch #1. Not a big deal, but archives or email clients use that > information to organize emails. You may want to check the command. Also, > note that you can always use "--dry-run" option to preview the headers > of your patchset ("--dry-run" won't do the actual send). Thanks for your advice. > > On Wed, Jul 28, 2021 at 07:48:22PM +0800, Rui Wang wrote: > > From: wangrui > > > > This patch introduce a new atomic primitive 'and_or', It may be have three > > types of implemeations: > > > > * The generic implementation is based on arch_cmpxchg. > > * The hardware supports atomic 'and_or' of single instruction. > > * The hardware supports LL/SC style atomic operations: > > > > 1: ll v1, mem > > and t1, v1, arg1 > > or t1, t1, arg2 > > sc t1, mem > > beq t1, 0, 1b > > > > Now that all the architectures have implemented it. > > > > Signed-by-off: Rui Wang > > Signed-by-off: hev > > First, this should be "Signed-off-by" ;-) Second, is the second > "Signed-off-by" a mistake? Beginner's luck :-) > > I will look into this for a review, in the meanwhile, but please add > some tests in lib/atomic64_test.c, not only it will do the test at > runtime, also it will generate asm code which helps people to review. > > Regards, > Boqun > Regards, Rui