Re: [PATCH] LoongArch: Add qspinlock support

From: hev <r@hev.cc>
To: Guo Ren <guoren@kernel.org>
Cc: Arnd Bergmann <arnd@arndb.de>, WANG Xuerui <kernel@xen0n.name>,
	 Huacai Chen <chenhuacai@loongson.cn>,
	Huacai Chen <chenhuacai@kernel.org>,
	 loongarch@lists.linux.dev,
	linux-arch <linux-arch@vger.kernel.org>,
	 Xuefeng Li <lixuefeng@loongson.cn>,
	Jiaxun Yang <jiaxun.yang@flygoat.com>,
	 Peter Zijlstra <peterz@infradead.org>,
	Will Deacon <will@kernel.org>, Ingo Molnar <mingo@redhat.com>
Subject: Re: [PATCH] LoongArch: Add qspinlock support
Date: Sun, 19 Jun 2022 23:38:16 +0800	[thread overview]
Message-ID: <CAHirt9jJpX0N=z1mLJtvsdsv7hPqAX+t+Eg1nr-_QQRLrt5wuw@mail.gmail.com> (raw)
In-Reply-To: <CAJF2gTQbb_RmF6Hn5E91waamecRZ+B7FRxo_GT23wkc0ydN4ug@mail.gmail.com>

On Sun, Jun 19, 2022 at 11:06 PM Guo Ren <guoren@kernel.org> wrote:
>
> On Sun, Jun 19, 2022 at 12:28 PM hev <r@hev.cc> wrote:
> >
> > Hello,
> >
> > On Sat, Jun 18, 2022 at 8:59 PM WANG Xuerui <kernel@xen0n.name> wrote:
> > >
> > > On 6/18/22 01:45, Guo Ren wrote:
> > > >
> > > >> I see that the qspinlock() code actually calls a 'relaxed' version of xchg16(),
> > > >> but you only implement the one with the full barrier. Is it possible to
> > > >> directly provide a relaxed version that has something less than the
> > > >> __WEAK_LLSC_MB?
> > > > I am also curious that __WEAK_LLSC_MB is very magic. How does it
> > > > prevent preceded accesses from happening after sc for a strong
> > > > cmpxchg?
> > > >
> > > > #define __cmpxchg_asm(ld, st, m, old, new)                              \
> > > > ({                                                                      \
> > > >          __typeof(old) __ret;                                            \
> > > >                                                                          \
> > > >          __asm__ __volatile__(                                           \
> > > >          "1:     " ld "  %0, %2          # __cmpxchg_asm \n"             \
> > > >          "       bne     %0, %z3, 2f                     \n"             \
> > > >          "       or      $t0, %z4, $zero                 \n"             \
> > > >          "       " st "  $t0, %1                         \n"             \
> > > >          "       beq     $zero, $t0, 1b                  \n"             \
> > > >          "2:                                             \n"             \
> > > >          __WEAK_LLSC_MB                                                  \
> > > >
> > > > And its __smp_mb__xxx are just defined as a compiler barrier()?
> > > > #define __smp_mb__before_atomic()       barrier()
> > > > #define __smp_mb__after_atomic()        barrier()
> > > I know this one. There is only one type of barrier defined in the v1.00
> > > of LoongArch, that is the full barrier, but this is going to change.
> > > Huacai hinted in the bringup patchset that 3A6000 and later models would
> > > have finer-grained barriers. So these indeed could be relaxed in the
> > > future, just that Huacai has to wait for their embargo to expire.
> > >
> >
> > IIRC, The Loongson LL/SC behaves differently than others:
> >
> > Loongson:
> > LL: Full barrier + Load exclusive
> > SC: Store conditional + Full barrier
> How about your "am"#asm_op"_db."?
>
> Full barrier + AMO + Full barrier ?

Yes. AMO without '_db' is relaxed.

hev