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[209.85.167.49]) by smtp.gmail.com with ESMTPSA id o12sm1326320lfl.66.2019.04.05.09.21.16 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 05 Apr 2019 09:21:16 -0700 (PDT) Received: by mail-lf1-f49.google.com with SMTP id v14so4863407lfi.0 for ; Fri, 05 Apr 2019 09:21:16 -0700 (PDT) X-Received: by 2002:ac2:44c3:: with SMTP id d3mr6977387lfm.14.1554480928669; Fri, 05 Apr 2019 09:15:28 -0700 (PDT) MIME-Version: 1.0 References: <20190405135936.7266-1-will.deacon@arm.com> <20190405160919.GA7857@fuggles.cambridge.arm.com> In-Reply-To: <20190405160919.GA7857@fuggles.cambridge.arm.com> From: Linus Torvalds Date: Fri, 5 Apr 2019 06:15:12 -1000 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH v2 00/21] Remove Mysterious Macro Intended to Obscure Weird Behaviours (mmiowb()) To: Will Deacon Cc: linux-arch , Linux List Kernel Mailing , "Paul E. McKenney" , Benjamin Herrenschmidt , Michael Ellerman , Arnd Bergmann , Peter Zijlstra , Andrea Parri , Palmer Dabbelt , Daniel Lustig , David Howells , Alan Stern , "Maciej W. Rozycki" , Paul Burton , Ingo Molnar , Yoshinori Sato , Rich Felker , Tony Luck , Mikulas Patocka , Akira Yokosawa , Luis Chamberlain , Nicholas Piggin Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, Apr 5, 2019 at 6:09 AM Will Deacon wrote: > > > > Or did I miss something? I think the ia64() mb/rmb/wmb stuff only > > works on normal memory on ia64. > > I was worried about RISC-V, but actually their wmb() is "fence ow,ow" > which I think is stronger than their mmiowb() "fence o,w" implementation. Also with smp_store_release -> smp_load_acquire kind of ordering? Again, this is not at all a NAK - I think we should do this - just perhaps a request to add a note to the commit and make people aware of the issue. I suspect very few drivers use non-locking serialization to begin with. Linus From mboxrd@z Thu Jan 1 00:00:00 1970 From: Linus Torvalds Subject: Re: [PATCH v2 00/21] Remove Mysterious Macro Intended to Obscure Weird Behaviours (mmiowb()) Date: Fri, 5 Apr 2019 06:15:12 -1000 Message-ID: References: <20190405135936.7266-1-will.deacon@arm.com> <20190405160919.GA7857@fuggles.cambridge.arm.com> Mime-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Return-path: In-Reply-To: <20190405160919.GA7857@fuggles.cambridge.arm.com> Sender: linux-kernel-owner@vger.kernel.org To: Will Deacon Cc: linux-arch , Linux List Kernel Mailing , "Paul E. McKenney" , Benjamin Herrenschmidt , Michael Ellerman , Arnd Bergmann , Peter Zijlstra , Andrea Parri , Palmer Dabbelt , Daniel Lustig , David Howells , Alan Stern , "Maciej W. Rozycki" , Paul Burton , Ingo Molnar , Yoshinori Sato , Rich Felker , Tony Luck , Mikulas Patocka List-Id: linux-arch.vger.kernel.org On Fri, Apr 5, 2019 at 6:09 AM Will Deacon wrote: > > > > Or did I miss something? I think the ia64() mb/rmb/wmb stuff only > > works on normal memory on ia64. > > I was worried about RISC-V, but actually their wmb() is "fence ow,ow" > which I think is stronger than their mmiowb() "fence o,w" implementation. Also with smp_store_release -> smp_load_acquire kind of ordering? Again, this is not at all a NAK - I think we should do this - just perhaps a request to add a note to the commit and make people aware of the issue. I suspect very few drivers use non-locking serialization to begin with. Linus