From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2A042C433F5 for ; Wed, 22 Dec 2021 12:05:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240368AbhLVMFG (ORCPT ); Wed, 22 Dec 2021 07:05:06 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57400 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235474AbhLVMFG (ORCPT ); Wed, 22 Dec 2021 07:05:06 -0500 Received: from mail-ed1-x530.google.com (mail-ed1-x530.google.com [IPv6:2a00:1450:4864:20::530]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 95944C061574; Wed, 22 Dec 2021 04:05:05 -0800 (PST) Received: by mail-ed1-x530.google.com with SMTP id f5so7765518edq.6; Wed, 22 Dec 2021 04:05:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=C5DstKb3qwgFc6Y9dnMNuAHiqD0iQ2gm6zNA7e4o3gk=; b=SPr3wdk79tZ7YJvNb32ojoleSxkyK2x/dWtV5IwUCTfR0x3C7o4NVKY2ClHnNTAf0N SOEwc7h/cs4yIp1GDO6J8iov7vVAhrT46ZRc1SwMatasaViKUc6lkI8lWf0eIjVHi4Vy MXBeqJlim/Qke//N8Z7jJVkw0nJC9vcJ4m6/HeIHsaZSvj3IEERcFQppJ06xax1YZZEF C/R5lxjS1jcg6ZdknCl+mQaAEJsY0XrjXub6H+li0RvBY4fBgvFoWqg5NgQD9ewByM8C ZmFP5+YIgNW0YJsyWHxlaCqCGG4RO+INGMbHSx8nqAJbgs7IezWbcn24FOzI/id+vlrA GCmQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=C5DstKb3qwgFc6Y9dnMNuAHiqD0iQ2gm6zNA7e4o3gk=; b=BctTjAyG++1FJgFoJNzHfxPdAIWmK0X4XhSTrvor2IvKa34KrMU9c/hGdzapv9Yzv2 QGfwetZTB3ldtgOg41/lZ+Kedul/8AZjHAupcbE70QyngSQ3vd8Zage89CcJC8yEVqLx axeJdAyT3gyTIv+V2ucNCEbqw5FDNLGT48ok1Y0T9ZfbSslo2Qxp9BNcwhwSBb+unFGP NN5UjEmxvzgZEBh73UmuKfeeVMDL4A4uR13+T4W0FIE40zgcUHmOE3YxWtz4Y/OJq3F1 U3hvH1G4n1k5bcrw6q1zkJfLO0bwgBwFihWIJe+RqzFNXGneAxB0YtR2E2YfWoFDiJnT QkEw== X-Gm-Message-State: AOAM533ZD44vxe0Vbh91Kri/XbHCICWCBx3MVdH1Optv11lYRrF0nClt srRXS99hYtWT4TDpPd61md/26ZiTs/KzNjnTrVyvoAlK6SI= X-Google-Smtp-Source: ABdhPJw6ar+HbOMGr2+HtbupdwrwAK0c3qZcDouEw6sctXge1TZ8f+bMKEEMq8TwXmY8YyY67NPzQDK4Wsppd+qsYBg= X-Received: by 2002:a17:907:6d8d:: with SMTP id sb13mr2243612ejc.132.1640174703757; Wed, 22 Dec 2021 04:05:03 -0800 (PST) MIME-Version: 1.0 References: <20211220211854.89452-1-nbd@nbd.name> <20211220211854.89452-14-nbd@nbd.name> In-Reply-To: <20211220211854.89452-14-nbd@nbd.name> From: Andy Shevchenko Date: Wed, 22 Dec 2021 14:03:04 +0200 Message-ID: Subject: Re: [PATCH v8 13/14] gpio: Add support for Airoha EN7523 GPIO controller To: Felix Fietkau Cc: linux-arm Mailing List , Linus Walleij , Bartosz Golaszewski , john , Linux Kernel Mailing List , "open list:GPIO SUBSYSTEM" Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org On Tue, Dec 21, 2021 at 12:02 AM Felix Fietkau wrote: > > From: John Crispin > > Airoha's GPIO controller on their ARM EN7523 SoCs consists of two banks of 32 > GPIOs. Each instance in DT is for a single bank. FWIW, Reviewed-by: Andy Shevchenko A couple of minor comments and one about headers below. > Signed-off-by: John Crispin > Signed-off-by: Felix Fietkau > --- > drivers/gpio/Kconfig | 9 +++ > drivers/gpio/Makefile | 1 + > drivers/gpio/gpio-en7523.c | 134 +++++++++++++++++++++++++++++++++++++ > 3 files changed, 144 insertions(+) > create mode 100644 drivers/gpio/gpio-en7523.c > > diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig > index 072ed610f9c6..e4a34272504f 100644 > --- a/drivers/gpio/Kconfig > +++ b/drivers/gpio/Kconfig > @@ -247,6 +247,15 @@ config GPIO_EM > help > Say yes here to support GPIO on Renesas Emma Mobile SoCs. > > +config GPIO_EN7523 > + tristate "Airoha GPIO support" > + depends on ARCH_AIROHA > + default ARCH_AIROHA > + select GPIO_GENERIC > + select GPIOLIB_IRQCHIP > + help > + Say yes here to support the GPIO controller on Airoha EN7523. Checkpatch nowadays wants a better description. Also add a paragraph at the end, like many other drivers do, what the module would be if selected as M. > config GPIO_EP93XX > def_bool y > depends on ARCH_EP93XX > diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile > index 71ee9fc2ff83..d2269ee0948e 100644 > --- a/drivers/gpio/Makefile > +++ b/drivers/gpio/Makefile > @@ -56,6 +56,7 @@ obj-$(CONFIG_GPIO_DLN2) += gpio-dln2.o > obj-$(CONFIG_GPIO_DWAPB) += gpio-dwapb.o > obj-$(CONFIG_GPIO_EIC_SPRD) += gpio-eic-sprd.o > obj-$(CONFIG_GPIO_EM) += gpio-em.o > +obj-$(CONFIG_GPIO_EN7523) += gpio-en7523.o > obj-$(CONFIG_GPIO_EP93XX) += gpio-ep93xx.o > obj-$(CONFIG_GPIO_EXAR) += gpio-exar.o > obj-$(CONFIG_GPIO_F7188X) += gpio-f7188x.o > diff --git a/drivers/gpio/gpio-en7523.c b/drivers/gpio/gpio-en7523.c > new file mode 100644 > index 000000000000..67631396cd93 > --- /dev/null > +++ b/drivers/gpio/gpio-en7523.c > @@ -0,0 +1,134 @@ > +// SPDX-License-Identifier: GPL-2.0-only > + > +#include > +#include > +#include > +#include > +#include Missed headers types.h for _iomem, etc. io.h for I/O accessors. bits.h for BIT(), etc. > +#define AIROHA_GPIO_MAX 32 > + > +/** > + * airoha_gpio_ctrl - Airoha GPIO driver data > + * @gc: Associated gpio_chip instance. > + * @data: The data register. > + * @dir0: The direction register for the lower 16 pins. > + * @dir1: The direction register for the higher 16 pins. > + * @output: The output enable register. > + */ > +struct airoha_gpio_ctrl { > + struct gpio_chip gc; > + void __iomem *data; > + void __iomem *dir[2]; > + void __iomem *output; > +}; > + > +static struct airoha_gpio_ctrl *gc_to_ctrl(struct gpio_chip *gc) > +{ > + return container_of(gc, struct airoha_gpio_ctrl, gc); > +} > + > +static int airoha_dir_set(struct gpio_chip *gc, unsigned int gpio, > + int val, int out) > +{ > + struct airoha_gpio_ctrl *ctrl = gc_to_ctrl(gc); > + u32 dir = ioread32(ctrl->dir[gpio / 16]); > + u32 output = ioread32(ctrl->output); > + u32 mask = BIT((gpio % 16) * 2); > + > + if (out) { > + dir |= mask; > + output |= BIT(gpio); > + } else { > + dir &= ~mask; > + output &= ~BIT(gpio); > + } > + > + iowrite32(dir, ctrl->dir[gpio / 16]); > + > + if (out) > + gc->set(gc, gpio, val); > + > + iowrite32(output, ctrl->output); > + > + return 0; > +} > + > +static int airoha_dir_out(struct gpio_chip *gc, unsigned int gpio, > + int val) > +{ > + return airoha_dir_set(gc, gpio, val, 1); > +} > + > +static int airoha_dir_in(struct gpio_chip *gc, unsigned int gpio) > +{ > + return airoha_dir_set(gc, gpio, 0, 0); > +} > + > +static int airoha_get_dir(struct gpio_chip *gc, unsigned int gpio) > +{ > + struct airoha_gpio_ctrl *ctrl = gc_to_ctrl(gc); > + u32 dir = ioread32(ctrl->dir[gpio / 16]); > + u32 mask = BIT((gpio % 16) * 2); > + > + return (dir & mask) ? GPIO_LINE_DIRECTION_OUT : GPIO_LINE_DIRECTION_IN; > +} > +static const struct of_device_id airoha_gpio_of_match[] = { > + { .compatible = "airoha,en7523-gpio" }, > + { } > +}; > +MODULE_DEVICE_TABLE(of, airoha_gpio_of_match); Move this below, closer to its user. > +static int airoha_gpio_probe(struct platform_device *pdev) > +{ > + struct device *dev = &pdev->dev; > + struct airoha_gpio_ctrl *ctrl; > + int err; > + > + ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL); > + if (!ctrl) > + return -ENOMEM; > + > + ctrl->data = devm_platform_ioremap_resource(pdev, 0); > + if (IS_ERR(ctrl->data)) > + return PTR_ERR(ctrl->data); > + > + ctrl->dir[0] = devm_platform_ioremap_resource(pdev, 1); > + if (IS_ERR(ctrl->dir[0])) > + return PTR_ERR(ctrl->dir[0]); > + > + ctrl->dir[1] = devm_platform_ioremap_resource(pdev, 2); > + if (IS_ERR(ctrl->dir[1])) > + return PTR_ERR(ctrl->dir[1]); > + > + ctrl->output = devm_platform_ioremap_resource(pdev, 3); > + if (IS_ERR(ctrl->output)) > + return PTR_ERR(ctrl->output); > + > + err = bgpio_init(&ctrl->gc, dev, 4, ctrl->data, NULL, > + NULL, NULL, NULL, 0); > + if (err) > + return dev_err_probe(dev, err, "unable to init generic GPIO"); > + > + ctrl->gc.ngpio = AIROHA_GPIO_MAX; > + ctrl->gc.owner = THIS_MODULE; > + ctrl->gc.direction_output = airoha_dir_out; > + ctrl->gc.direction_input = airoha_dir_in; > + ctrl->gc.get_direction = airoha_get_dir; > + > + return devm_gpiochip_add_data(dev, &ctrl->gc, ctrl); > +} > + > +static struct platform_driver airoha_gpio_driver = { > + .driver = { > + .name = "airoha-gpio", > + .of_match_table = airoha_gpio_of_match, > + }, > + .probe = airoha_gpio_probe, > +}; > +module_platform_driver(airoha_gpio_driver); > + > +MODULE_DESCRIPTION("Airoha GPIO support"); > +MODULE_AUTHOR("John Crispin "); > +MODULE_LICENSE("GPL v2"); > -- > 2.34.1 > -- With Best Regards, Andy Shevchenko From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A559DC433F5 for ; Wed, 22 Dec 2021 12:06:34 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:Subject:Message-ID:Date:From: In-Reply-To:References:MIME-Version:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=ojln+J3Ag/k4GAp7vmKm242S7cbi3dasFvqymJitYWA=; b=yVs6EoiwwZUmCX PvvM+oM3OERShboQNlCbzySzqPgTZ13JZpZ3/aJieS3uQMU/FqisqI/PuvQfa930tLyJyMOBRVqrf /xCFT8d65BJbj+URd63g6EWzbKCQoSRyq1ie0wdDSLq0dK7SuyyWkToQPgwupjfSQYb55b1ymFHTD VcIbDc0B8y8QtsE0gBP6Rqf+Sf2NCS8oZSqkPepRmY/0M7q0XYVv/u/QVY8a6oDuBzYLyEE/qk1+G ImEZ3/WFCFJW9ynv0AlFkCRRrj93IDdBv4UZzSCZg+biQIZHdMHzZsEHnagev2bhVFGiE1+xjDLMR Q0fOWWwljRys3u9EwBlA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1n00Mn-00AE3H-Vl; Wed, 22 Dec 2021 12:05:10 +0000 Received: from mail-ed1-x534.google.com ([2a00:1450:4864:20::534]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1n00Mk-00AE28-3A for linux-arm-kernel@lists.infradead.org; Wed, 22 Dec 2021 12:05:07 +0000 Received: by mail-ed1-x534.google.com with SMTP id o20so7666459eds.10 for ; Wed, 22 Dec 2021 04:05:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=C5DstKb3qwgFc6Y9dnMNuAHiqD0iQ2gm6zNA7e4o3gk=; b=SPr3wdk79tZ7YJvNb32ojoleSxkyK2x/dWtV5IwUCTfR0x3C7o4NVKY2ClHnNTAf0N SOEwc7h/cs4yIp1GDO6J8iov7vVAhrT46ZRc1SwMatasaViKUc6lkI8lWf0eIjVHi4Vy MXBeqJlim/Qke//N8Z7jJVkw0nJC9vcJ4m6/HeIHsaZSvj3IEERcFQppJ06xax1YZZEF C/R5lxjS1jcg6ZdknCl+mQaAEJsY0XrjXub6H+li0RvBY4fBgvFoWqg5NgQD9ewByM8C ZmFP5+YIgNW0YJsyWHxlaCqCGG4RO+INGMbHSx8nqAJbgs7IezWbcn24FOzI/id+vlrA GCmQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=C5DstKb3qwgFc6Y9dnMNuAHiqD0iQ2gm6zNA7e4o3gk=; b=2aP4fE8TWXHlgwJNyTcB7tRro2GOVkQcxv5NT3rSSmk+hW8nT3RMgbG1ANRHllgH9v RJOygFcSgVH4WJfdar1DK5YOuD+Zk2IDUlWWuiccmaPsTLuuKot0unFryYPEtO23Fey0 scQV3YS7FukBWLAc85h5PsEgf9/39+0ddqEbnCZrZi97zBJSdYUX1F182gSiak4z1Nqk 9XTIUcNEVAMt5sPR8fsmtx8+0FkinXLfHtKn9xWXiYa1b4PPwGL0Teayjq04fHfg0X3g NaN94iAdo6s4LQQDVLljPrySUxNULiExN0nW0r9mwMA/2twJ/edXBGORWZO3/vqA15bh L8tw== X-Gm-Message-State: AOAM531AEsDsF3csykttnJHIdYvHRTP48M8QjnDiKoxIPxIW4idNHcm9 G7biOZ9HHdPaz0PU1nR2KUrOSwqYRD1eLfXPcv8= X-Google-Smtp-Source: ABdhPJw6ar+HbOMGr2+HtbupdwrwAK0c3qZcDouEw6sctXge1TZ8f+bMKEEMq8TwXmY8YyY67NPzQDK4Wsppd+qsYBg= X-Received: by 2002:a17:907:6d8d:: with SMTP id sb13mr2243612ejc.132.1640174703757; Wed, 22 Dec 2021 04:05:03 -0800 (PST) MIME-Version: 1.0 References: <20211220211854.89452-1-nbd@nbd.name> <20211220211854.89452-14-nbd@nbd.name> In-Reply-To: <20211220211854.89452-14-nbd@nbd.name> From: Andy Shevchenko Date: Wed, 22 Dec 2021 14:03:04 +0200 Message-ID: Subject: Re: [PATCH v8 13/14] gpio: Add support for Airoha EN7523 GPIO controller To: Felix Fietkau Cc: linux-arm Mailing List , Linus Walleij , Bartosz Golaszewski , john , Linux Kernel Mailing List , "open list:GPIO SUBSYSTEM" X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211222_040506_186028_36E657C1 X-CRM114-Status: GOOD ( 29.52 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Tue, Dec 21, 2021 at 12:02 AM Felix Fietkau wrote: > > From: John Crispin > > Airoha's GPIO controller on their ARM EN7523 SoCs consists of two banks of 32 > GPIOs. Each instance in DT is for a single bank. FWIW, Reviewed-by: Andy Shevchenko A couple of minor comments and one about headers below. > Signed-off-by: John Crispin > Signed-off-by: Felix Fietkau > --- > drivers/gpio/Kconfig | 9 +++ > drivers/gpio/Makefile | 1 + > drivers/gpio/gpio-en7523.c | 134 +++++++++++++++++++++++++++++++++++++ > 3 files changed, 144 insertions(+) > create mode 100644 drivers/gpio/gpio-en7523.c > > diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig > index 072ed610f9c6..e4a34272504f 100644 > --- a/drivers/gpio/Kconfig > +++ b/drivers/gpio/Kconfig > @@ -247,6 +247,15 @@ config GPIO_EM > help > Say yes here to support GPIO on Renesas Emma Mobile SoCs. > > +config GPIO_EN7523 > + tristate "Airoha GPIO support" > + depends on ARCH_AIROHA > + default ARCH_AIROHA > + select GPIO_GENERIC > + select GPIOLIB_IRQCHIP > + help > + Say yes here to support the GPIO controller on Airoha EN7523. Checkpatch nowadays wants a better description. Also add a paragraph at the end, like many other drivers do, what the module would be if selected as M. > config GPIO_EP93XX > def_bool y > depends on ARCH_EP93XX > diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile > index 71ee9fc2ff83..d2269ee0948e 100644 > --- a/drivers/gpio/Makefile > +++ b/drivers/gpio/Makefile > @@ -56,6 +56,7 @@ obj-$(CONFIG_GPIO_DLN2) += gpio-dln2.o > obj-$(CONFIG_GPIO_DWAPB) += gpio-dwapb.o > obj-$(CONFIG_GPIO_EIC_SPRD) += gpio-eic-sprd.o > obj-$(CONFIG_GPIO_EM) += gpio-em.o > +obj-$(CONFIG_GPIO_EN7523) += gpio-en7523.o > obj-$(CONFIG_GPIO_EP93XX) += gpio-ep93xx.o > obj-$(CONFIG_GPIO_EXAR) += gpio-exar.o > obj-$(CONFIG_GPIO_F7188X) += gpio-f7188x.o > diff --git a/drivers/gpio/gpio-en7523.c b/drivers/gpio/gpio-en7523.c > new file mode 100644 > index 000000000000..67631396cd93 > --- /dev/null > +++ b/drivers/gpio/gpio-en7523.c > @@ -0,0 +1,134 @@ > +// SPDX-License-Identifier: GPL-2.0-only > + > +#include > +#include > +#include > +#include > +#include Missed headers types.h for _iomem, etc. io.h for I/O accessors. bits.h for BIT(), etc. > +#define AIROHA_GPIO_MAX 32 > + > +/** > + * airoha_gpio_ctrl - Airoha GPIO driver data > + * @gc: Associated gpio_chip instance. > + * @data: The data register. > + * @dir0: The direction register for the lower 16 pins. > + * @dir1: The direction register for the higher 16 pins. > + * @output: The output enable register. > + */ > +struct airoha_gpio_ctrl { > + struct gpio_chip gc; > + void __iomem *data; > + void __iomem *dir[2]; > + void __iomem *output; > +}; > + > +static struct airoha_gpio_ctrl *gc_to_ctrl(struct gpio_chip *gc) > +{ > + return container_of(gc, struct airoha_gpio_ctrl, gc); > +} > + > +static int airoha_dir_set(struct gpio_chip *gc, unsigned int gpio, > + int val, int out) > +{ > + struct airoha_gpio_ctrl *ctrl = gc_to_ctrl(gc); > + u32 dir = ioread32(ctrl->dir[gpio / 16]); > + u32 output = ioread32(ctrl->output); > + u32 mask = BIT((gpio % 16) * 2); > + > + if (out) { > + dir |= mask; > + output |= BIT(gpio); > + } else { > + dir &= ~mask; > + output &= ~BIT(gpio); > + } > + > + iowrite32(dir, ctrl->dir[gpio / 16]); > + > + if (out) > + gc->set(gc, gpio, val); > + > + iowrite32(output, ctrl->output); > + > + return 0; > +} > + > +static int airoha_dir_out(struct gpio_chip *gc, unsigned int gpio, > + int val) > +{ > + return airoha_dir_set(gc, gpio, val, 1); > +} > + > +static int airoha_dir_in(struct gpio_chip *gc, unsigned int gpio) > +{ > + return airoha_dir_set(gc, gpio, 0, 0); > +} > + > +static int airoha_get_dir(struct gpio_chip *gc, unsigned int gpio) > +{ > + struct airoha_gpio_ctrl *ctrl = gc_to_ctrl(gc); > + u32 dir = ioread32(ctrl->dir[gpio / 16]); > + u32 mask = BIT((gpio % 16) * 2); > + > + return (dir & mask) ? GPIO_LINE_DIRECTION_OUT : GPIO_LINE_DIRECTION_IN; > +} > +static const struct of_device_id airoha_gpio_of_match[] = { > + { .compatible = "airoha,en7523-gpio" }, > + { } > +}; > +MODULE_DEVICE_TABLE(of, airoha_gpio_of_match); Move this below, closer to its user. > +static int airoha_gpio_probe(struct platform_device *pdev) > +{ > + struct device *dev = &pdev->dev; > + struct airoha_gpio_ctrl *ctrl; > + int err; > + > + ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL); > + if (!ctrl) > + return -ENOMEM; > + > + ctrl->data = devm_platform_ioremap_resource(pdev, 0); > + if (IS_ERR(ctrl->data)) > + return PTR_ERR(ctrl->data); > + > + ctrl->dir[0] = devm_platform_ioremap_resource(pdev, 1); > + if (IS_ERR(ctrl->dir[0])) > + return PTR_ERR(ctrl->dir[0]); > + > + ctrl->dir[1] = devm_platform_ioremap_resource(pdev, 2); > + if (IS_ERR(ctrl->dir[1])) > + return PTR_ERR(ctrl->dir[1]); > + > + ctrl->output = devm_platform_ioremap_resource(pdev, 3); > + if (IS_ERR(ctrl->output)) > + return PTR_ERR(ctrl->output); > + > + err = bgpio_init(&ctrl->gc, dev, 4, ctrl->data, NULL, > + NULL, NULL, NULL, 0); > + if (err) > + return dev_err_probe(dev, err, "unable to init generic GPIO"); > + > + ctrl->gc.ngpio = AIROHA_GPIO_MAX; > + ctrl->gc.owner = THIS_MODULE; > + ctrl->gc.direction_output = airoha_dir_out; > + ctrl->gc.direction_input = airoha_dir_in; > + ctrl->gc.get_direction = airoha_get_dir; > + > + return devm_gpiochip_add_data(dev, &ctrl->gc, ctrl); > +} > + > +static struct platform_driver airoha_gpio_driver = { > + .driver = { > + .name = "airoha-gpio", > + .of_match_table = airoha_gpio_of_match, > + }, > + .probe = airoha_gpio_probe, > +}; > +module_platform_driver(airoha_gpio_driver); > + > +MODULE_DESCRIPTION("Airoha GPIO support"); > +MODULE_AUTHOR("John Crispin "); > +MODULE_LICENSE("GPL v2"); > -- > 2.34.1 > -- With Best Regards, Andy Shevchenko _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel