From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-ej1-f48.google.com (mail-ej1-f48.google.com [209.85.218.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 31614EA4 for ; Tue, 21 Jun 2022 09:22:42 +0000 (UTC) Received: by mail-ej1-f48.google.com with SMTP id ay16so6774743ejb.6 for ; Tue, 21 Jun 2022 02:22:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=nwSBD3PTloVRfceK56G2aCfoof4Hwc6nnq2tpaiVX1E=; b=SZC4AJowoOWLiXUnJNCXlRo+Fy21+43HuGqupG34NYAHev8FNX9LB4nFwui2g2ERc/ 2nAJjFE7gSxwK3AKqYoV1+xDYo3j7xKpCHwaEkBrfpjwItcvjJqbKZBmsBC6S6wk0LeP jECzrOFPrp+pM5SPwC+6kLb36nf+Eql2JHp+xmKVEp9KBopfkHCProz5vj1URUzLxuOc 2gtMsViSY39FbLby9xOKwyFIHQnssNg0xndDzN3H/27fb1evpypF3YvV3oswAKpp+Rdc 8SQN3kqU5KrBqva1r+R8tUi0Xkhp826IwLzXg6j6O1xwnr3vjRymNISR9wMWgtdGEpu5 ffSQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=nwSBD3PTloVRfceK56G2aCfoof4Hwc6nnq2tpaiVX1E=; b=fPofENgW/FociU8UpbPGy8OBaLKCkm3Gg6ijbBGCvO7IY0xw0RouHbhkofhas+gPVa 1u/nlTpLEFdpW8wrqeneBHo4hYep/mYDZGhYKWPd2lyINo+jy7lcfxlz54BcJxDj0P/4 9OX/S+0/XUeftfYGulA+dBgnhi3hg94dYLH/kgjHfBbXXSiJIsLeOt6ZJWLWQUdNWRcK BZx7zeP+NjvMtrj0hrKKTr4/CymfL5Hu5KX7oh2Dg5av44p9GfFOais5iDRRmDNtHUS+ ty3p3LZljE63y1xKkd1lgNwrsHShZXnLIGMTWmHFvFg1DIVJYQxzZDNSv/etv4RyW+8O xebA== X-Gm-Message-State: AJIora//CpLp3y0qggGpuHg2rneT0ttEB+5c1XYwhikRSBdOo4yX8ZCz xmxrmyag5dyJWbIYCg42OtMDqG8YrXqXtLF77IE= X-Google-Smtp-Source: AGRyM1st5l8YH2ggqJetd23NizO1SBXRfCSKIN2Ag6+snWa4U1k/4MnJ2Of8mZI6rssF1UlaIrePIaWD6CbQW7kd1/8= X-Received: by 2002:a17:906:149:b0:711:fca6:bc2f with SMTP id 9-20020a170906014900b00711fca6bc2fmr25088970ejh.497.1655803360410; Tue, 21 Jun 2022 02:22:40 -0700 (PDT) Precedence: bulk X-Mailing-List: linux-sunxi@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 References: <20220620200644.1961936-1-aidanmacdonald.0x0@gmail.com> <20220620200644.1961936-5-aidanmacdonald.0x0@gmail.com> In-Reply-To: <20220620200644.1961936-5-aidanmacdonald.0x0@gmail.com> From: Andy Shevchenko Date: Tue, 21 Jun 2022 11:22:03 +0200 Message-ID: Subject: Re: [PATCH 04/49] regmap-irq: Introduce config registers for irq types To: Aidan MacDonald Cc: Mark Brown , Andy Gross , Bjorn Andersson , Srinivas Kandagatla , Banajit Goswami , Greg Kroah-Hartman , "Rafael J. Wysocki" , Chanwoo Choi , Krzysztof Kozlowski , Bartlomiej Zolnierkiewicz , MyungJoo Ham , Michael Walle , Linus Walleij , Bartosz Golaszewski , Thomas Gleixner , Marc Zyngier , Lee Jones , Manivannan Sadhasivam , Cristian Ciocaltea , Chen-Yu Tsai , tharvey@gateworks.com, rjones@gateworks.com, Matti Vaittinen , orsonzhai@gmail.com, baolin.wang7@gmail.com, zhang.lyra@gmail.com, Jernej Skrabec , Samuel Holland , Liam Girdwood , Jaroslav Kysela , Takashi Iwai , Linux Kernel Mailing List , "open list:GPIO SUBSYSTEM" , linux-actions@lists.infradead.org, linux-arm-msm , linux-arm Mailing List , linux-sunxi@lists.linux.dev, ALSA Development Mailing List Content-Type: text/plain; charset="UTF-8" On Mon, Jun 20, 2022 at 10:08 PM Aidan MacDonald wrote: > > Config registers provide a more uniform approach to handling irq type > registers. They are essentially an extension of the virtual registers > used by the qcom-pm8008 driver. > > Config registers can be represented as a 2D array: > > config_base[0] reg0,0 reg0,1 reg0,2 reg0,3 > config_base[1] reg1,0 reg1,1 reg1,2 reg1,3 > config_base[2] reg2,0 reg2,1 reg2,2 reg2,3 > > There are 'num_config_bases' base registers, each of which is used to > address 'num_config_regs' registers. The addresses are calculated in > the same way as for other bases. It is assumed that an irq's type is > controlled by one column of registers; that column is identified by > the irq's 'type_reg_offset'. > > The set_type_config() callback is responsible for updating the config > register contents. It receives an array of buffers (each represents a > row of registers) and the index of the column to update, along with > the 'struct regmap_irq' description and requested irq type. > > Buffered values are written to registers in regmap_irq_sync_unlock(). > Note that the entire register contents are overwritten, which is a > minor change in behavior from type registers via 'type_base'. ... > + ret = regmap_write(map, reg, d->config_buf[i][j]); > + if (ret != 0) if (ret) > + dev_err(d->map->dev, > + "Failed to write config %x: %d\n", > + reg, ret); > + } ... > + * regmap_irq_set_type_config_simple() - Simple IRQ type configuration callback. > + * Redundant line. ... > + d->config_buf = kcalloc(chip->num_config_bases, > + sizeof(*d->config_buf), GFP_KERNEL); > + if (!d->config_buf) > + goto err_alloc; > + > + for (i = 0; i < chip->num_config_regs; i++) { > + d->config_buf[i] = kcalloc(chip->num_config_regs, > + sizeof(unsigned int), Can it be sizeof(**d->config_buf) ? > + GFP_KERNEL); > + if (!d->config_buf[i]) > + goto err_alloc; > + } -- With Best Regards, Andy Shevchenko From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9DFCBC433EF for ; Tue, 21 Jun 2022 09:23:40 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:Subject:Message-ID:Date:From: In-Reply-To:References:MIME-Version:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=8CQQ3Ot3kXQFGTZaIeCES2qHNb5jyHeEtv2zLpixjKs=; b=x3wrgLVg/EfdD7 sz0aQCc4BzT4Rw3qoIxBNN3QRsOHTWBwh/NlIFnGL/1ymx6Lt0w9sGPjsbx8qt6ZGiu1pS4kKShwC KmS8ZLPl3LikRioYe4LjTvbdpr6JSSsygaSt6dY0X73j9AqR/JET+XLnbv3MBefR3vevtZQJ6fAUs eepjkXl+hhk2/KyL6gx1TjdIHrQVx7B8/lDuYw3j9Opbic67CTHGKWtqMtD+wE3rlHxOi+A3QZrUd yU3Py3UMAK66JyklM5LAwEXhKpbUhc2tcpkmg+WkvDXIsHI4eFWuB3nyRQUPYiQQ0uDRPTVKKws8c FJMcmP728V2EOaglhLKQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1o3a5t-004bSS-Dt; Tue, 21 Jun 2022 09:22:45 +0000 Received: from mail-ej1-x62c.google.com ([2a00:1450:4864:20::62c]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1o3a5q-004bR1-P5; Tue, 21 Jun 2022 09:22:44 +0000 Received: by mail-ej1-x62c.google.com with SMTP id g25so26106459ejh.9; Tue, 21 Jun 2022 02:22:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=nwSBD3PTloVRfceK56G2aCfoof4Hwc6nnq2tpaiVX1E=; b=SZC4AJowoOWLiXUnJNCXlRo+Fy21+43HuGqupG34NYAHev8FNX9LB4nFwui2g2ERc/ 2nAJjFE7gSxwK3AKqYoV1+xDYo3j7xKpCHwaEkBrfpjwItcvjJqbKZBmsBC6S6wk0LeP jECzrOFPrp+pM5SPwC+6kLb36nf+Eql2JHp+xmKVEp9KBopfkHCProz5vj1URUzLxuOc 2gtMsViSY39FbLby9xOKwyFIHQnssNg0xndDzN3H/27fb1evpypF3YvV3oswAKpp+Rdc 8SQN3kqU5KrBqva1r+R8tUi0Xkhp826IwLzXg6j6O1xwnr3vjRymNISR9wMWgtdGEpu5 ffSQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=nwSBD3PTloVRfceK56G2aCfoof4Hwc6nnq2tpaiVX1E=; b=fA/kRU3tSokal7gsR7Wc05pg9MZyp0YZVyO75aqS/92Qyr6h1FbS7XOIp5Hsr0Q/oO q9glDPZ2eynWPIxno9Jdnpt8W/EaLaUKEnuQgbdKNth90MdKmEx3v/6feih8uGnrET55 F1lQkkEBEiyYbNhQ47ZSD4mwtWjNfrQlbLrN5rjAQViSJL+Tf8e0OzD+Q8bfQQCnL4ia ppwc0ePZK1L3J+zRJCFN8Fn/EHlU2OGuLABASdKuFo5nCJ2Oio5cWq5UP4fg7GYhP3FK ps4LC6KYB4ox87t4LbmtQG3Aiw5Fewz/WaSmh0dXDdQQSAeSUYgZx8W5UUZYgtUgNQEi FeKg== X-Gm-Message-State: AJIora8qPbqgNz3fN3JMrNDSJ99vThKJIa0Pk7b5utVmVJUNoMfvwB3J MDtjbTyT6Y8C4+3BGBuIs+R5Fs/P4YECm3PpgtpvJGa3pZIIhA== X-Google-Smtp-Source: AGRyM1st5l8YH2ggqJetd23NizO1SBXRfCSKIN2Ag6+snWa4U1k/4MnJ2Of8mZI6rssF1UlaIrePIaWD6CbQW7kd1/8= X-Received: by 2002:a17:906:149:b0:711:fca6:bc2f with SMTP id 9-20020a170906014900b00711fca6bc2fmr25088970ejh.497.1655803360410; Tue, 21 Jun 2022 02:22:40 -0700 (PDT) MIME-Version: 1.0 References: <20220620200644.1961936-1-aidanmacdonald.0x0@gmail.com> <20220620200644.1961936-5-aidanmacdonald.0x0@gmail.com> In-Reply-To: <20220620200644.1961936-5-aidanmacdonald.0x0@gmail.com> From: Andy Shevchenko Date: Tue, 21 Jun 2022 11:22:03 +0200 Message-ID: Subject: Re: [PATCH 04/49] regmap-irq: Introduce config registers for irq types To: Aidan MacDonald Cc: Mark Brown , Andy Gross , Bjorn Andersson , Srinivas Kandagatla , Banajit Goswami , Greg Kroah-Hartman , "Rafael J. Wysocki" , Chanwoo Choi , Krzysztof Kozlowski , Bartlomiej Zolnierkiewicz , MyungJoo Ham , Michael Walle , Linus Walleij , Bartosz Golaszewski , Thomas Gleixner , Marc Zyngier , Lee Jones , Manivannan Sadhasivam , Cristian Ciocaltea , Chen-Yu Tsai , tharvey@gateworks.com, rjones@gateworks.com, Matti Vaittinen , orsonzhai@gmail.com, baolin.wang7@gmail.com, zhang.lyra@gmail.com, Jernej Skrabec , Samuel Holland , Liam Girdwood , Jaroslav Kysela , Takashi Iwai , Linux Kernel Mailing List , "open list:GPIO SUBSYSTEM" , linux-actions@lists.infradead.org, linux-arm-msm , linux-arm Mailing List , linux-sunxi@lists.linux.dev, ALSA Development Mailing List X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220621_022242_870957_29CB8ABC X-CRM114-Status: GOOD ( 22.13 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Mon, Jun 20, 2022 at 10:08 PM Aidan MacDonald wrote: > > Config registers provide a more uniform approach to handling irq type > registers. They are essentially an extension of the virtual registers > used by the qcom-pm8008 driver. > > Config registers can be represented as a 2D array: > > config_base[0] reg0,0 reg0,1 reg0,2 reg0,3 > config_base[1] reg1,0 reg1,1 reg1,2 reg1,3 > config_base[2] reg2,0 reg2,1 reg2,2 reg2,3 > > There are 'num_config_bases' base registers, each of which is used to > address 'num_config_regs' registers. The addresses are calculated in > the same way as for other bases. It is assumed that an irq's type is > controlled by one column of registers; that column is identified by > the irq's 'type_reg_offset'. > > The set_type_config() callback is responsible for updating the config > register contents. It receives an array of buffers (each represents a > row of registers) and the index of the column to update, along with > the 'struct regmap_irq' description and requested irq type. > > Buffered values are written to registers in regmap_irq_sync_unlock(). > Note that the entire register contents are overwritten, which is a > minor change in behavior from type registers via 'type_base'. ... > + ret = regmap_write(map, reg, d->config_buf[i][j]); > + if (ret != 0) if (ret) > + dev_err(d->map->dev, > + "Failed to write config %x: %d\n", > + reg, ret); > + } ... > + * regmap_irq_set_type_config_simple() - Simple IRQ type configuration callback. > + * Redundant line. ... > + d->config_buf = kcalloc(chip->num_config_bases, > + sizeof(*d->config_buf), GFP_KERNEL); > + if (!d->config_buf) > + goto err_alloc; > + > + for (i = 0; i < chip->num_config_regs; i++) { > + d->config_buf[i] = kcalloc(chip->num_config_regs, > + sizeof(unsigned int), Can it be sizeof(**d->config_buf) ? > + GFP_KERNEL); > + if (!d->config_buf[i]) > + goto err_alloc; > + } -- With Best Regards, Andy Shevchenko _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from alsa0.perex.cz (alsa0.perex.cz [77.48.224.243]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 77D1DC433EF for ; Wed, 22 Jun 2022 15:38:40 +0000 (UTC) Received: from alsa1.perex.cz (alsa1.perex.cz [207.180.221.201]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by alsa0.perex.cz (Postfix) with ESMTPS id 495CC1FEC; Wed, 22 Jun 2022 17:37:48 +0200 (CEST) DKIM-Filter: OpenDKIM Filter v2.11.0 alsa0.perex.cz 495CC1FEC DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; 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Tue, 21 Jun 2022 02:22:40 -0700 (PDT) MIME-Version: 1.0 References: <20220620200644.1961936-1-aidanmacdonald.0x0@gmail.com> <20220620200644.1961936-5-aidanmacdonald.0x0@gmail.com> In-Reply-To: <20220620200644.1961936-5-aidanmacdonald.0x0@gmail.com> From: Andy Shevchenko Date: Tue, 21 Jun 2022 11:22:03 +0200 Message-ID: Subject: Re: [PATCH 04/49] regmap-irq: Introduce config registers for irq types To: Aidan MacDonald Content-Type: text/plain; charset="UTF-8" X-Mailman-Approved-At: Wed, 22 Jun 2022 17:23:18 +0200 Cc: ALSA Development Mailing List , Banajit Goswami , "Rafael J. Wysocki" , Linus Walleij , Bjorn Andersson , Srinivas Kandagatla , MyungJoo Ham , Lee Jones , Samuel Holland , Marc Zyngier , Bartosz Golaszewski , Manivannan Sadhasivam , Krzysztof Kozlowski , Jernej Skrabec , Chanwoo Choi , Chen-Yu Tsai , Andy Gross , orsonzhai@gmail.com, linux-sunxi@lists.linux.dev, Bartlomiej Zolnierkiewicz , linux-arm-msm , tharvey@gateworks.com, linux-actions@lists.infradead.org, "open list:GPIO SUBSYSTEM" , Mark Brown , Takashi Iwai , Thomas Gleixner , Cristian Ciocaltea , linux-arm Mailing List , rjones@gateworks.com, Greg Kroah-Hartman , Liam Girdwood , Linux Kernel Mailing List , Michael Walle , zhang.lyra@gmail.com, baolin.wang7@gmail.com, Matti Vaittinen X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: alsa-devel-bounces@alsa-project.org Sender: "Alsa-devel" On Mon, Jun 20, 2022 at 10:08 PM Aidan MacDonald wrote: > > Config registers provide a more uniform approach to handling irq type > registers. They are essentially an extension of the virtual registers > used by the qcom-pm8008 driver. > > Config registers can be represented as a 2D array: > > config_base[0] reg0,0 reg0,1 reg0,2 reg0,3 > config_base[1] reg1,0 reg1,1 reg1,2 reg1,3 > config_base[2] reg2,0 reg2,1 reg2,2 reg2,3 > > There are 'num_config_bases' base registers, each of which is used to > address 'num_config_regs' registers. The addresses are calculated in > the same way as for other bases. It is assumed that an irq's type is > controlled by one column of registers; that column is identified by > the irq's 'type_reg_offset'. > > The set_type_config() callback is responsible for updating the config > register contents. It receives an array of buffers (each represents a > row of registers) and the index of the column to update, along with > the 'struct regmap_irq' description and requested irq type. > > Buffered values are written to registers in regmap_irq_sync_unlock(). > Note that the entire register contents are overwritten, which is a > minor change in behavior from type registers via 'type_base'. ... > + ret = regmap_write(map, reg, d->config_buf[i][j]); > + if (ret != 0) if (ret) > + dev_err(d->map->dev, > + "Failed to write config %x: %d\n", > + reg, ret); > + } ... > + * regmap_irq_set_type_config_simple() - Simple IRQ type configuration callback. > + * Redundant line. ... > + d->config_buf = kcalloc(chip->num_config_bases, > + sizeof(*d->config_buf), GFP_KERNEL); > + if (!d->config_buf) > + goto err_alloc; > + > + for (i = 0; i < chip->num_config_regs; i++) { > + d->config_buf[i] = kcalloc(chip->num_config_regs, > + sizeof(unsigned int), Can it be sizeof(**d->config_buf) ? > + GFP_KERNEL); > + if (!d->config_buf[i]) > + goto err_alloc; > + } -- With Best Regards, Andy Shevchenko