From mboxrd@z Thu Jan 1 00:00:00 1970 From: Andy Shevchenko Subject: Re: [PATCH V17 1/3] dmaengine: qcom_hidma: implement lower level hardware interface Date: Tue, 26 Apr 2016 18:10:00 +0300 Message-ID: References: <1460384473-5775-1-git-send-email-okaya@codeaurora.org> <1460384473-5775-2-git-send-email-okaya@codeaurora.org> <20160426032805.GA2274@localhost> <571F8397.5000803@codeaurora.org> Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Return-path: In-Reply-To: <571F8397.5000803-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org> Sender: devicetree-owner-u79uwXL29TY76Z2rM5mHXA@public.gmane.org To: Sinan Kaya Cc: Vinod Koul , dmaengine , Timur Tabi , devicetree , Christopher Covington , Jon Masters , shankerd-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org, vikrams-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org, Marc Zyngier , Mark Rutland , eric.auger-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org, Andy Gross , Arnd Bergmann , linux-arm-msm-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-arm Mailing List , Dan Williams , "linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org" List-Id: linux-arm-msm@vger.kernel.org On Tue, Apr 26, 2016 at 6:04 PM, Sinan Kaya wrote: > On 4/25/2016 11:28 PM, Vinod Koul wrote: >> On Mon, Apr 11, 2016 at 10:21:11AM -0400, Sinan Kaya wrote: >>> + while (cause) { >>> + if ((cause & BIT(HIDMA_IRQ_TR_CH_INVALID_TRE_BIT_POS)) || >>> + (cause & BIT(HIDMA_IRQ_TR_CH_TRE_RD_RSP_ER_BIT_POS)) || >>> + (cause & BIT(HIDMA_IRQ_EV_CH_WR_RESP_BIT_POS)) || >>> + (cause & BIT(HIDMA_IRQ_TR_CH_DATA_RD_ER_BIT_POS)) || >>> + (cause & BIT(HIDMA_IRQ_TR_CH_DATA_WR_ER_BIT_POS))) { >> >> Switch please > > Cause is a combined status register. Let's say it contains 0x41. I need to check > if bit 0 or bit 6 is set in this value for each case condition. The value is not 0x40 > or 0x1. > > I created macro like this instead. > > +#define HIDMA_IS_ERR_INTERRUPT(cause) \ > + (cause & BIT(HIDMA_IRQ_TR_CH_INVALID_TRE_BIT_POS)) || \ > + (cause & BIT(HIDMA_IRQ_TR_CH_TRE_RD_RSP_ER_BIT_POS)) || \ > + (cause & BIT(HIDMA_IRQ_EV_CH_WR_RESP_BIT_POS)) || \ > + (cause & BIT(HIDMA_IRQ_TR_CH_DATA_RD_ER_BIT_POS)) || \ > + (cause & BIT(HIDMA_IRQ_TR_CH_DATA_WR_ER_BIT_POS)) This looks overheaded. #define HIDMA_XXX (BIT(a) | BIT (b) ... BIT(n)) > > and replaced the if statement as follows > > if (HIDMA_IS_ERR_INTERRUPT(cause)) { if (cause & HIDMA_XXX) { -- With Best Regards, Andy Shevchenko -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752231AbcDZPKK (ORCPT ); Tue, 26 Apr 2016 11:10:10 -0400 Received: from mail-ob0-f178.google.com ([209.85.214.178]:36109 "EHLO mail-ob0-f178.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751363AbcDZPKH (ORCPT ); Tue, 26 Apr 2016 11:10:07 -0400 MIME-Version: 1.0 In-Reply-To: <571F8397.5000803@codeaurora.org> References: <1460384473-5775-1-git-send-email-okaya@codeaurora.org> <1460384473-5775-2-git-send-email-okaya@codeaurora.org> <20160426032805.GA2274@localhost> <571F8397.5000803@codeaurora.org> Date: Tue, 26 Apr 2016 18:10:00 +0300 Message-ID: Subject: Re: [PATCH V17 1/3] dmaengine: qcom_hidma: implement lower level hardware interface From: Andy Shevchenko To: Sinan Kaya Cc: Vinod Koul , dmaengine , Timur Tabi , devicetree , Christopher Covington , Jon Masters , shankerd@codeaurora.org, vikrams@codeaurora.org, Marc Zyngier , Mark Rutland , eric.auger@linaro.org, Andy Gross , Arnd Bergmann , linux-arm-msm@vger.kernel.org, linux-arm Mailing List , Dan Williams , "linux-kernel@vger.kernel.org" Content-Type: text/plain; charset=UTF-8 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, Apr 26, 2016 at 6:04 PM, Sinan Kaya wrote: > On 4/25/2016 11:28 PM, Vinod Koul wrote: >> On Mon, Apr 11, 2016 at 10:21:11AM -0400, Sinan Kaya wrote: >>> + while (cause) { >>> + if ((cause & BIT(HIDMA_IRQ_TR_CH_INVALID_TRE_BIT_POS)) || >>> + (cause & BIT(HIDMA_IRQ_TR_CH_TRE_RD_RSP_ER_BIT_POS)) || >>> + (cause & BIT(HIDMA_IRQ_EV_CH_WR_RESP_BIT_POS)) || >>> + (cause & BIT(HIDMA_IRQ_TR_CH_DATA_RD_ER_BIT_POS)) || >>> + (cause & BIT(HIDMA_IRQ_TR_CH_DATA_WR_ER_BIT_POS))) { >> >> Switch please > > Cause is a combined status register. Let's say it contains 0x41. I need to check > if bit 0 or bit 6 is set in this value for each case condition. The value is not 0x40 > or 0x1. > > I created macro like this instead. > > +#define HIDMA_IS_ERR_INTERRUPT(cause) \ > + (cause & BIT(HIDMA_IRQ_TR_CH_INVALID_TRE_BIT_POS)) || \ > + (cause & BIT(HIDMA_IRQ_TR_CH_TRE_RD_RSP_ER_BIT_POS)) || \ > + (cause & BIT(HIDMA_IRQ_EV_CH_WR_RESP_BIT_POS)) || \ > + (cause & BIT(HIDMA_IRQ_TR_CH_DATA_RD_ER_BIT_POS)) || \ > + (cause & BIT(HIDMA_IRQ_TR_CH_DATA_WR_ER_BIT_POS)) This looks overheaded. #define HIDMA_XXX (BIT(a) | BIT (b) ... BIT(n)) > > and replaced the if statement as follows > > if (HIDMA_IS_ERR_INTERRUPT(cause)) { if (cause & HIDMA_XXX) { -- With Best Regards, Andy Shevchenko From mboxrd@z Thu Jan 1 00:00:00 1970 From: andy.shevchenko@gmail.com (Andy Shevchenko) Date: Tue, 26 Apr 2016 18:10:00 +0300 Subject: [PATCH V17 1/3] dmaengine: qcom_hidma: implement lower level hardware interface In-Reply-To: <571F8397.5000803@codeaurora.org> References: <1460384473-5775-1-git-send-email-okaya@codeaurora.org> <1460384473-5775-2-git-send-email-okaya@codeaurora.org> <20160426032805.GA2274@localhost> <571F8397.5000803@codeaurora.org> Message-ID: To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On Tue, Apr 26, 2016 at 6:04 PM, Sinan Kaya wrote: > On 4/25/2016 11:28 PM, Vinod Koul wrote: >> On Mon, Apr 11, 2016 at 10:21:11AM -0400, Sinan Kaya wrote: >>> + while (cause) { >>> + if ((cause & BIT(HIDMA_IRQ_TR_CH_INVALID_TRE_BIT_POS)) || >>> + (cause & BIT(HIDMA_IRQ_TR_CH_TRE_RD_RSP_ER_BIT_POS)) || >>> + (cause & BIT(HIDMA_IRQ_EV_CH_WR_RESP_BIT_POS)) || >>> + (cause & BIT(HIDMA_IRQ_TR_CH_DATA_RD_ER_BIT_POS)) || >>> + (cause & BIT(HIDMA_IRQ_TR_CH_DATA_WR_ER_BIT_POS))) { >> >> Switch please > > Cause is a combined status register. Let's say it contains 0x41. I need to check > if bit 0 or bit 6 is set in this value for each case condition. The value is not 0x40 > or 0x1. > > I created macro like this instead. > > +#define HIDMA_IS_ERR_INTERRUPT(cause) \ > + (cause & BIT(HIDMA_IRQ_TR_CH_INVALID_TRE_BIT_POS)) || \ > + (cause & BIT(HIDMA_IRQ_TR_CH_TRE_RD_RSP_ER_BIT_POS)) || \ > + (cause & BIT(HIDMA_IRQ_EV_CH_WR_RESP_BIT_POS)) || \ > + (cause & BIT(HIDMA_IRQ_TR_CH_DATA_RD_ER_BIT_POS)) || \ > + (cause & BIT(HIDMA_IRQ_TR_CH_DATA_WR_ER_BIT_POS)) This looks overheaded. #define HIDMA_XXX (BIT(a) | BIT (b) ... BIT(n)) > > and replaced the if statement as follows > > if (HIDMA_IS_ERR_INTERRUPT(cause)) { if (cause & HIDMA_XXX) { -- With Best Regards, Andy Shevchenko