From mboxrd@z Thu Jan 1 00:00:00 1970 From: Zhi Li Subject: Re: [PATCH V12 2/4] drivers/perf: imx_ddr: Add ddr performance counter support Date: Thu, 13 Jun 2019 12:04:37 -0500 Message-ID: References: <1556736193-29411-1-git-send-email-Frank.Li@nxp.com> <1556736193-29411-2-git-send-email-Frank.Li@nxp.com> <20190613112320.GA18966@fuggles.cambridge.arm.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <20190613112320.GA18966@fuggles.cambridge.arm.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=m.gmane.org@lists.infradead.org To: Will Deacon Cc: "mark.rutland@arm.com" , Aisheng Dong , "devicetree@vger.kernel.org" , "andrew.smirnov@gmail.com" , "festevam@gmail.com" , "s.hauer@pengutronix.de" , Frank Li , "robh+dt@kernel.org" , dl-linux-imx , "kernel@pengutronix.de" , "shawnguo@kernel.org" , "linux-arm-kernel@lists.infradead.org" List-Id: devicetree@vger.kernel.org On Thu, Jun 13, 2019 at 6:23 AM Will Deacon wrote: > > On Wed, May 01, 2019 at 06:43:29PM +0000, Frank Li wrote: > > Add ddr performance monitor support for iMX8QXP > > > > There are 4 counters for ddr perfomance events. > > counter 0 is dedicated for cycles. > > you choose any up to 3 no cycles events. > > > > for example: > > > > perf stat -a -e imx8_ddr0/read-cycles/,imx8_ddr0/write-cycles/,imx8_ddr0/precharge/ ls > > perf stat -a -e imx8_ddr0/cycles/,imx8_ddr0/read-access/,imx8_ddr0/write-access/ ls > > I've pushed patches 1, 2 and 4 out with some minor tweaks to: > > https://git.kernel.org/pub/scm/linux/kernel/git/will/linux.git/log/?h=for-next/perf > > I'll leave the actual .dts change to go via the soc tree, since last time > I took one of those it just resulted in conflicts. > > Frank, Andrey: Please could you try to run the perf fuzzer on this before > it lands in mainline? It has a good track record of finding nasty PMU driver > bugs, but it obviously requires access to hardware which implements the PMU: > > http://web.eece.maine.edu/~vweaver/projects/perf_events/fuzzer/ Okay, how long should be run generally? I need make sure it can pass without my patches at our platform. Best regards Frank Li > > Cheers, > > Will From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.5 required=3.0 tests=DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED,DKIM_VALID,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,MENTIONS_GIT_HOSTING, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id CE2B4C46477 for ; Thu, 13 Jun 2019 17:05:13 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id A14A9206BB for ; Thu, 13 Jun 2019 17:05:13 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="o8l2UADk"; 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a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=EnPkPuY0upC8b7jCW297iBQZhVtXmFo88c6fyE9w1Gc=; b=DfDzdz4ei9JsTxLpgIQm52byn5xwanW1CmehuiXiflKHfeEi9HFjJ3mDcKE/xvVMky ERo0RLkZslBplINSPQjV33Qw7Bf8xgmTJ6OHUICLHf8s6IUm/C0kv3Hzok0gP7NkTpde dsFtMfnuAqA4USs0PHYULm/vKat8M7rVthwk6wGd5+sgg8UHjXCqbtHPEx4uxX07sVci rssUQcvsv0Gjrw7jIs+nosM+cn9LpDBVMaOn8u90iZ1RNsKLEvCeQZlbwsxj4y4ED2XJ IkSSjQmM1blEsaYcM9gMU3Eya5Y1zPQ0KsQTxx3O9HD74is4WlkjeTQMHxi9FJI1t6Ma iLeQ== X-Gm-Message-State: APjAAAWaMovvhU4MfQZzt9BiheMD0wHpaX8nhZ5gwbnvMKEeHfqGYOL/ E0qcuhfH8Tg2d9EH/QzadjHLekieQ1FSvH+2wQQ= X-Google-Smtp-Source: APXvYqxcMn+Xp7KK1rDTtjbiF/s9/qMAS0Od0rblM/JIyaXggdbRc5s5/qqZIPwozR39yiq+kN0sCF0Q4lr+B/T1BU4= X-Received: by 2002:a63:158:: with SMTP id 85mr32252700pgb.101.1560445489065; Thu, 13 Jun 2019 10:04:49 -0700 (PDT) MIME-Version: 1.0 References: <1556736193-29411-1-git-send-email-Frank.Li@nxp.com> <1556736193-29411-2-git-send-email-Frank.Li@nxp.com> <20190613112320.GA18966@fuggles.cambridge.arm.com> In-Reply-To: <20190613112320.GA18966@fuggles.cambridge.arm.com> From: Zhi Li Date: Thu, 13 Jun 2019 12:04:37 -0500 Message-ID: Subject: Re: [PATCH V12 2/4] drivers/perf: imx_ddr: Add ddr performance counter support To: Will Deacon X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190613_100450_155449_C87FAB62 X-CRM114-Status: GOOD ( 12.92 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "mark.rutland@arm.com" , Aisheng Dong , "devicetree@vger.kernel.org" , "andrew.smirnov@gmail.com" , "festevam@gmail.com" , "s.hauer@pengutronix.de" , Frank Li , "robh+dt@kernel.org" , dl-linux-imx , "kernel@pengutronix.de" , "shawnguo@kernel.org" , "linux-arm-kernel@lists.infradead.org" Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Thu, Jun 13, 2019 at 6:23 AM Will Deacon wrote: > > On Wed, May 01, 2019 at 06:43:29PM +0000, Frank Li wrote: > > Add ddr performance monitor support for iMX8QXP > > > > There are 4 counters for ddr perfomance events. > > counter 0 is dedicated for cycles. > > you choose any up to 3 no cycles events. > > > > for example: > > > > perf stat -a -e imx8_ddr0/read-cycles/,imx8_ddr0/write-cycles/,imx8_ddr0/precharge/ ls > > perf stat -a -e imx8_ddr0/cycles/,imx8_ddr0/read-access/,imx8_ddr0/write-access/ ls > > I've pushed patches 1, 2 and 4 out with some minor tweaks to: > > https://git.kernel.org/pub/scm/linux/kernel/git/will/linux.git/log/?h=for-next/perf > > I'll leave the actual .dts change to go via the soc tree, since last time > I took one of those it just resulted in conflicts. > > Frank, Andrey: Please could you try to run the perf fuzzer on this before > it lands in mainline? It has a good track record of finding nasty PMU driver > bugs, but it obviously requires access to hardware which implements the PMU: > > http://web.eece.maine.edu/~vweaver/projects/perf_events/fuzzer/ Okay, how long should be run generally? I need make sure it can pass without my patches at our platform. Best regards Frank Li > > Cheers, > > Will _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel