From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52987) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aPuKO-0005Oz-W0 for qemu-devel@nongnu.org; Sun, 31 Jan 2016 10:54:17 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1aPuKN-0003ow-MZ for qemu-devel@nongnu.org; Sun, 31 Jan 2016 10:54:16 -0500 Received: from mail-wm0-x242.google.com ([2a00:1450:400c:c09::242]:36057) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aPuKN-0003or-Bb for qemu-devel@nongnu.org; Sun, 31 Jan 2016 10:54:15 -0500 Received: by mail-wm0-x242.google.com with SMTP id 128so5382678wmz.3 for ; Sun, 31 Jan 2016 07:54:14 -0800 (PST) MIME-Version: 1.0 In-Reply-To: <56AB9A22.7020201@codeaurora.org> References: <1445361732-16257-1-git-send-email-shlomopongratz@gmail.com> <56AB9A22.7020201@codeaurora.org> Date: Sun, 31 Jan 2016 17:54:14 +0200 Message-ID: From: Shlomo Pongratz Content-Type: multipart/alternative; boundary=089e013d1caeb01447052aa347c1 Subject: Re: [Qemu-devel] [PATCH RFC V5 0/9] Implement GIC-500 from GICv3 family for arm64 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Christopher Covington Cc: "peter.maydell@linaro.org" , "eric.auger@linaro.org" , Shlomo Pongratz , "p.fedin@samsung.com" , "qemu-devel@nongnu.org" , "shannon.zhao@linaro.org" , "ashoks@broadcom.com" , "imammedo@redhat.com" --089e013d1caeb01447052aa347c1 Content-Type: text/plain; charset=UTF-8 On Friday, January 29, 2016, Christopher Covington wrote: > On 10/20/2015 01:22 PM, Shlomo Pongratz wrote: > > From: Shlomo Pongratz > > > > > This patch is a first step multicores support for arm64. > > > > This implemntation was tested up to 100 cores. > > > > Things left to do: > > > > Support SPI, ITS and ITS CONTROL, note that this patch porpose is to > enable > > running multi cores using the "virt" virtual machine and this goal is > achived > > without that. > > > > Add GICv2 backwards competability. Since there is a GICv2 implementation > I > > can't see the pusprose for it. > > > > Special thanks to Peter Crostwaite whose patch to th Linux (kernel) i.e. > > Implement cpu_relax as yield solved the problem of the boot process > getting > > stuck for 24 cores and more. > > > > Figure out why virtual machine name changed from virt-v3 to > virt-v3-machine > > Hi Shlomo, > > Were you planning on another revision of this patchset? Are there any > things you would like help with? > > Peter, > > Do you have any thoughts about what is essential and what isn't for a > first wave of TCG GICv3 patches to be mergeable? > > Thanks, > Christopher Covington > > -- > Qualcomm Innovation Center, Inc. > Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, > a Linux Foundation Collaborative Project > Hi, I will do a new revision of the GICv3. I needed to get a time slot from my employee in order to do the work and I got one starting next week. Best regards, S.P. --089e013d1caeb01447052aa347c1 Content-Type: text/html; charset=UTF-8 Content-Transfer-Encoding: quoted-printable

On Friday, January 29, 2016, Christopher Covington <cov@codeaurora.org> wrote:
On 10/20/2015 01:22 PM, Shlomo Pongratz wrote:
> From: Shlomo Pongratz <shlomo.pongratz@hu= awei.com>
>
> This patch is a first step multicores support for arm64.
>
> This implemntation was tested up to 100 cores.
>
> Things left to do:
>
> Support SPI, ITS and ITS CONTROL, note that this patch porpose is to e= nable
> running multi cores using the "virt" virtual machine and thi= s goal is achived
> without that.
>
> Add GICv2 backwards competability. Since there is a GICv2 implementati= on I
> can't see the pusprose for it.
>
> Special thanks to Peter Crostwaite whose patch to th Linux (kernel) i.= e.
> Implement cpu_relax as yield solved the problem of the boot process ge= tting
> stuck for 24 cores and more.
>
> Figure out why virtual machine name changed from virt-v3 to virt-v3-ma= chine

Hi Shlomo,

Were you planning on another revision of this patchset? Are there any
things you would like help with?

Peter,

Do you have any thoughts about what is essential and what isn't for a first wave of TCG GICv3 patches to be mergeable?

Thanks,
Christopher Covington

--
Qualcomm Innovation Center, Inc.
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

Hi,

I will do a new revision of the GICv3.
=
I needed to get a time slot from my employee in order to do the work a= nd I got one starting next week.

Best regards,

S.P. =C2=A0=C2=A0
--089e013d1caeb01447052aa347c1--