From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38542) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Yw5dN-0003NF-4o for qemu-devel@nongnu.org; Sat, 23 May 2015 05:22:22 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Yw5dK-0006uS-P1 for qemu-devel@nongnu.org; Sat, 23 May 2015 05:22:21 -0400 Received: from mail-yk0-x229.google.com ([2607:f8b0:4002:c07::229]:33841) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Yw5dK-0006uM-K7 for qemu-devel@nongnu.org; Sat, 23 May 2015 05:22:18 -0400 Received: by ykfl8 with SMTP id l8so1606392ykf.1 for ; Sat, 23 May 2015 02:22:17 -0700 (PDT) MIME-Version: 1.0 In-Reply-To: <007b01d0945b$6dee6860$49cb3920$@samsung.com> References: <1430921082-16779-1-git-send-email-shlomopongratz@gmail.com> <1430921082-16779-2-git-send-email-shlomopongratz@gmail.com> <000601d093de$79adf210$6d09d630$@samsung.com> <007b01d0945b$6dee6860$49cb3920$@samsung.com> Date: Sat, 23 May 2015 12:22:17 +0300 Message-ID: From: Shlomo Pongratz Content-Type: multipart/alternative; boundary=001a11c1cd302534390516bc505e Subject: Re: [Qemu-devel] [PATCH RFC V2 1/4] Use Aff1 with mpidr List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Pavel Fedin Cc: "peter.maydell@linaro.org" , "qemu-devel@nongnu.org" , Ashok Kumar , Shlomo Pongratz --001a11c1cd302534390516bc505e Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable On Friday, May 22, 2015, Pavel Fedin wrote: > Hello! > > > The GIC-500 provides registers for managing interrupt sources, interrup= t > behavior, and interrupt > > routing to one or more cores. It supports: > > =E2=80=A2 Multiprocessor environments with up to 128 cores. > > =E2=80=A2 Up to 32 affinity-level 1 clusters. > > =E2=80=A2 Up to eight cores for each cluster. > > > I guess your hardware uses different GIC. > > Heh, yes, looks like that. And perhaps it's somewhat non-standard... > I will study kvmtool and try to come up with some good solution. > > By the way, since you're referring to documentation... TRM you have > mentioned contains references to "GIC architecture reference manual v3.0"= , > which i was unable to find. On ARM resource center i see only v2 of the > manual. And it looks like you have it because otherwise you would not get > description of many registers. Can you point me at a correct place ? > > Kind regards, > Pavel Fedin > Expert Engineer > Samsung Electronics Research center Russia > > > Hi Pavel, We have a copy at work which I came from ARM, I'm sure that since Samsung manufactures ARM SoC under licence you can put your hand on one. I can also add that most of my work was done using the GIC-500 document and by looking for what the Linux (kernel) is doing. Only recently I was able to put my hand on the GICv3, but It only confirmed what I already assumed. Best regards, S.P. --001a11c1cd302534390516bc505e Content-Type: text/html; charset=UTF-8 Content-Transfer-Encoding: quoted-printable
On Friday, May 22, 2015, Pavel Fedin <p.fedin@samsung.com> wrote:
=C2=A0Hello!

> The GIC-500 provides registers for managing interrupt sources, interru= pt behavior, and interrupt
> routing to one or more cores. It supports:
> =E2=80=A2 Multiprocessor environments with up to 128 cores.
> =E2=80=A2 Up to 32 affinity-level 1 clusters.
> =E2=80=A2 Up to eight cores for each cluster.

> I guess your hardware uses different GIC.

=C2=A0Heh, yes, looks like that. And perhaps it's somewhat non-standard= ...
=C2=A0I will study kvmtool and try to come up with some good solution.

=C2=A0By the way, since you're referring to documentation... TRM you ha= ve mentioned contains references to "GIC architecture reference manual= v3.0", which i was unable to find. On ARM resource center i see only = v2 of the manual. And it looks like you have it because otherwise you would= not get description of many registers. Can you point me at a correct place= ?

Kind regards,
Pavel Fedin
Expert Engineer
Samsung Electronics Research center Russia


Hi Pavel,

We have a copy at = work which I came from ARM, I'm sure that since Samsung manufactures AR= M SoC under licence you can put your hand on one.
I can also add = that most of my work was done using the GIC-500 document and by looking for= what the Linux (kernel) is doing. Only recently I was able to put my hand = on the GICv3, but It only confirmed what I already assumed.

<= /div>
Best regards,

S.P.

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