From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 40DC2C433F5 for ; Tue, 2 Nov 2021 15:45:30 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 1B1E7604AC for ; Tue, 2 Nov 2021 15:45:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234162AbhKBPsD (ORCPT ); Tue, 2 Nov 2021 11:48:03 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59436 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231361AbhKBPr7 (ORCPT ); Tue, 2 Nov 2021 11:47:59 -0400 Received: from mail-wm1-x32b.google.com (mail-wm1-x32b.google.com [IPv6:2a00:1450:4864:20::32b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9F647C061714; Tue, 2 Nov 2021 08:45:24 -0700 (PDT) Received: by mail-wm1-x32b.google.com with SMTP id v127so15929074wme.5; Tue, 02 Nov 2021 08:45:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc:content-transfer-encoding; bh=oIykopvcWEmxVEkfNC3dgfAMuhJk89I9yxZdFrfrLyY=; b=NXwFLg3whNd+9Nkioovkzccugez6vLSyVeaz69yv0iI5DOvqAMuZCSP9hMD6h2nfES HPBxphhkGTHJxUKAED7L+nz4JnTpuFpHC88feWNsztuGjud5NdCc5PngvHdUhJkC+gms bBm72Jb0sp8hxtV5OttEq6BWZTzkux5i0jxaTZknB4yNttAe971OdzxOSqAvX1ZJaS59 NREcJfVNjGf8RtuNF/RrCXB03KJZ4PtK3cqTtv3MQ6KZgz8o3WPJhmPuDUNOC8d4Qc3A SyGme9gy2AqqIwYH2qexyLHWLRXzEXYurvchicvoMOGQ+U6Ifec11/QCxIxpxtlaL5Pp taaw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc:content-transfer-encoding; bh=oIykopvcWEmxVEkfNC3dgfAMuhJk89I9yxZdFrfrLyY=; b=rl67bb/io0d6Qlx631/03U8EooTdxGqV3gVP9biT2rVU5nlwGOL7UFsxDP2fkxDeMj vvdMj8eSupoTIAtZdNjNUb1i/fPHDMLfB5K9UEX1Jb2s7p378cV56RI6ppiiB5UAqzCA kz6VitJM+Ru06T2mzfiA+UJjhnlUHQpVp0oQFsGkiaYnE/GOgVlrRJsTUvHR/X3n5Jtx GnS9joeQoBPOFDk8HyetsWwUs0ocYy0mgh0MNc/EiW9fx8TurCa1BtwBr22QsMmHdJ/J wM0dc0Hh1c9nhE2ISR+xL5WfrsSJFuPcv0zZqF8JHlng1ilMQM7+T2NXXB6KqIWIpuI7 jkdw== X-Gm-Message-State: AOAM530J95EE7b846PS0hXXU0Ydvi2QSbLcmrnuQ2uBzusA0ysXGR9hg xINA/nSNPA+vqpYNQhNbXb0vO4HRmVeAOMF+q/c= X-Google-Smtp-Source: ABdhPJxAxEXiUc4bHDnuL0cSFIkXN1ocKgHMUC217BwCqZkTrK6N7aYrgCy28CWNVRnHAMN0n/S0eZaVCql16BNd/E8= X-Received: by 2002:a1c:740e:: with SMTP id p14mr7923263wmc.109.1635867923171; Tue, 02 Nov 2021 08:45:23 -0700 (PDT) MIME-Version: 1.0 References: <20211102145642.724820-1-tongtiangen@huawei.com> In-Reply-To: <20211102145642.724820-1-tongtiangen@huawei.com> From: =?UTF-8?B?QmrDtnJuIFTDtnBlbA==?= Date: Tue, 2 Nov 2021 16:45:11 +0100 Message-ID: Subject: Re: [PATCH bpf-next] riscv, bpf: fix some compiler error To: Tong Tiangen Cc: Paul Walmsley , Palmer Dabbelt , Palmer Dabbelt , Albert Ou , Alexei Starovoitov , Daniel Borkmann , Andrii Nakryiko , Martin KaFai Lau , Song Liu , Yonghong Song , John Fastabend , KP Singh , linux-riscv , LKML , Netdev , bpf Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, 2 Nov 2021 at 15:40, Tong Tiangen wrote: > > This patch fix two compile errors: > 1. when CONFIG_BPF_JIT and CONFIG_ARCH_32I is open, There is the followin= g > compiler error: > error: undefined symbol: rv_bpf_fixup_exception > Good catch for the RV32! > 2. when CONFIG_BPF_JIT and CONFIG_ARCH_64I is open, There is the followin= g > compiler error (W=3D1): > error: no previous prototype for 'rv_bpf_fixup_exception' > > In this patch, asm/extable.h is introduced, the rv_bpf_fixup_exception > function declaration is added to this file. in addition, the definition o= f > exception_table_entry is moved from asm-generic/extable.h to this file. > This is way too complicated. More below. > Fixes: 252c765bd764 ("riscv, bpf: Add BPF exception tables") > Signed-off-by: Tong Tiangen > --- > arch/riscv/include/asm/Kbuild | 1 - > arch/riscv/include/asm/extable.h | 49 ++++++++++++++++++++++++++++++++ > arch/riscv/include/asm/uaccess.h | 13 --------- > arch/riscv/mm/extable.c | 8 +----- > 4 files changed, 50 insertions(+), 21 deletions(-) > create mode 100644 arch/riscv/include/asm/extable.h > > diff --git a/arch/riscv/include/asm/Kbuild b/arch/riscv/include/asm/Kbuil= d > index 445ccc97305a..57b86fd9916c 100644 > --- a/arch/riscv/include/asm/Kbuild > +++ b/arch/riscv/include/asm/Kbuild > @@ -1,6 +1,5 @@ > # SPDX-License-Identifier: GPL-2.0 > generic-y +=3D early_ioremap.h > -generic-y +=3D extable.h > generic-y +=3D flat.h > generic-y +=3D kvm_para.h > generic-y +=3D user.h > diff --git a/arch/riscv/include/asm/extable.h b/arch/riscv/include/asm/ex= table.h > new file mode 100644 > index 000000000000..aa0332b053fb > --- /dev/null > +++ b/arch/riscv/include/asm/extable.h > @@ -0,0 +1,49 @@ > +/* SPDX-License-Identifier: GPL-2.0 */ > +#ifndef __ASM_EXTABLE_H > +#define __ASM_EXTABLE_H > + > +/* > + * The exception table consists of pairs of addresses: the first is the > + * address of an instruction that is allowed to fault, and the second is > + * the address at which the program should continue. No registers are > + * modified, so it is entirely up to the continuation code to figure out > + * what to do. > + * > + * All the routines below use bits of fixup code that are out of line > + * with the main instruction path. This means when everything is well, > + * we don't even have to jump over them. Further, they do not intrude > + * on our cache or tlb entries. > + */ > +struct exception_table_entry { > + unsigned long insn, fixup; > +}; > + > +struct pt_regs; > +int fixup_exception(struct pt_regs *regs); > + > +#if defined(CONFIG_MMU) > +static inline bool rv_in_bpf_jit(struct pt_regs *regs) > +{ > + if (!IS_ENABLED(CONFIG_BPF_JIT) || !IS_ENABLED(CONFIG_64BIT)) > + return false; > + > + return regs->epc >=3D BPF_JIT_REGION_START && regs->epc < BPF_JIT= _REGION_END; > +} > +#else > +static inline bool rv_in_bpf_jit(struct pt_regs *regs) > +{ > + return false; > +} > +#endif > + > +#if defined(CONFIG_BPF_JIT) && defined(CONFIG_64BIT) > +int rv_bpf_fixup_exception(const struct exception_table_entry *ex, struc= t pt_regs *regs); > +#else > +static inline int rv_bpf_fixup_exception(const struct exception_table_en= try *ex, > + struct pt_regs *regs) > +{ > + return 0; > +} > +#endif > + > +#endif > diff --git a/arch/riscv/include/asm/uaccess.h b/arch/riscv/include/asm/ua= ccess.h > index f314ff44c48d..96ea91dc0e9c 100644 > --- a/arch/riscv/include/asm/uaccess.h > +++ b/arch/riscv/include/asm/uaccess.h > @@ -56,19 +56,6 @@ static inline int __access_ok(unsigned long addr, unsi= gned long size) > return size <=3D TASK_SIZE && addr <=3D TASK_SIZE - size; > } > > -/* > - * The exception table consists of pairs of addresses: the first is the > - * address of an instruction that is allowed to fault, and the second is > - * the address at which the program should continue. No registers are > - * modified, so it is entirely up to the continuation code to figure out > - * what to do. > - * > - * All the routines below use bits of fixup code that are out of line > - * with the main instruction path. This means when everything is well, > - * we don't even have to jump over them. Further, they do not intrude > - * on our cache or tlb entries. > - */ > - > #define __LSW 0 > #define __MSW 1 > > diff --git a/arch/riscv/mm/extable.c b/arch/riscv/mm/extable.c > index 18bf338303b6..264f465db5bb 100644 > --- a/arch/riscv/mm/extable.c > +++ b/arch/riscv/mm/extable.c > @@ -11,10 +11,6 @@ > #include > #include > > -#ifdef CONFIG_BPF_JIT > -int rv_bpf_fixup_exception(const struct exception_table_entry *ex, struc= t pt_regs *regs); > -#endif > - > int fixup_exception(struct pt_regs *regs) > { > const struct exception_table_entry *fixup; > @@ -23,10 +19,8 @@ int fixup_exception(struct pt_regs *regs) > if (!fixup) > return 0; > > -#ifdef CONFIG_BPF_JIT > - if (regs->epc >=3D BPF_JIT_REGION_START && regs->epc < BPF_JIT_RE= GION_END) > + if (rv_in_bpf_jit(regs)) > return rv_bpf_fixup_exception(fixup, regs); > -#endif > The only changes that are needed are: 1. Simply gate with CONFIG_BPF_JIT && CONFIG_ARCH_RV64I, instead of of CONFIG_BPF_JIT 2. Forward declaration of the rv_bpf_fixup_exception() in bpf_jit_comp64.c. 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2021 16:45:11 +0100 Message-ID: Subject: Re: [PATCH bpf-next] riscv, bpf: fix some compiler error To: Tong Tiangen Cc: Paul Walmsley , Palmer Dabbelt , Palmer Dabbelt , Albert Ou , Alexei Starovoitov , Daniel Borkmann , Andrii Nakryiko , Martin KaFai Lau , Song Liu , Yonghong Song , John Fastabend , KP Singh , linux-riscv , LKML , Netdev , bpf X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211102_084525_538086_D4260F3F X-CRM114-Status: GOOD ( 33.23 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org T24gVHVlLCAyIE5vdiAyMDIxIGF0IDE1OjQwLCBUb25nIFRpYW5nZW4gPHRvbmd0aWFuZ2VuQGh1 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