* spi-thunderx (OcteonTX) max SPI frequency
@ 2021-09-22 16:14 Tim Harvey
2021-09-30 0:51 ` Tim Harvey
0 siblings, 1 reply; 2+ messages in thread
From: Tim Harvey @ 2021-09-22 16:14 UTC (permalink / raw)
To: linux-spi, David Daney, Jan Glauber
Greetings,
Does anyone know why the MAX spi frequency for the spi-thunderx driver
would be 16MHz? The CN81XX HM states the SPI clock frequency can go up
to 50MHz.
The driver was originally for Octeon (I'm thinking this was CN7xxx
SoC's?) which perhaps were limited to 16MHz yet I downloaded a CN70XX
ref manual and it shows 25MHz.
I don't know my history regarding the Cavium (now Marvell) SoC's well
enough to know exactly what Octeon means or meant vs ThunderX. Hoping
someone from Marvell can answer this.
Best regards,
Tim
^ permalink raw reply [flat|nested] 2+ messages in thread
* Re: spi-thunderx (OcteonTX) max SPI frequency
2021-09-22 16:14 spi-thunderx (OcteonTX) max SPI frequency Tim Harvey
@ 2021-09-30 0:51 ` Tim Harvey
0 siblings, 0 replies; 2+ messages in thread
From: Tim Harvey @ 2021-09-30 0:51 UTC (permalink / raw)
To: linux-spi, David Daney, Jan Glauber, aron Williams,
Suneel Garapati, Stefan Roese, Chandrakala Chavva, Jagan Teki
On Wed, Sep 22, 2021 at 9:14 AM Tim Harvey <tharvey@gateworks.com> wrote:
>
> Greetings,
>
> Does anyone know why the MAX spi frequency for the spi-thunderx driver
> would be 16MHz? The CN81XX HM states the SPI clock frequency can go up
> to 50MHz.
>
> The driver was originally for Octeon (I'm thinking this was CN7xxx
> SoC's?) which perhaps were limited to 16MHz yet I downloaded a CN70XX
> ref manual and it shows 25MHz.
>
> I don't know my history regarding the Cavium (now Marvell) SoC's well
> enough to know exactly what Octeon means or meant vs ThunderX. Hoping
> someone from Marvell can answer this.
>
Adding some more Marvell folk to this thread including those involved
in the octeon-spi driver contributed to U-Boot to support the Octeon
II/III and OcteonTX/TX2 SoC which was allowed to run up to 50MHz [1]
My theory is that the Linux driver originally supported the Octeon I
SoC (still not clear what chip(s) that actually refers to) which was
likely 16MHz and that the driver should be patched to support 50MHz
for the SoC's that support it. I'm happy to submit a patch but I need
Marvell to step up and explain what chips are capable of 50MHz and
which are limited to 16MHz. All the Marvell reference manuals are
under NDA and this makes it a bit difficult to figure out.
Best Regards,
Tim
[1] https://github.com/u-boot/u-boot/commit/7853cc05984c60e616163c9b17c14d9a50300abe
^ permalink raw reply [flat|nested] 2+ messages in thread
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