From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 389E8C6FA82 for ; Wed, 14 Sep 2022 17:10:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229744AbiINRKI (ORCPT ); Wed, 14 Sep 2022 13:10:08 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56676 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229518AbiINRKG (ORCPT ); Wed, 14 Sep 2022 13:10:06 -0400 Received: from mail-oa1-x36.google.com (mail-oa1-x36.google.com [IPv6:2001:4860:4864:20::36]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DDD4321E1D for ; Wed, 14 Sep 2022 10:10:03 -0700 (PDT) Received: by mail-oa1-x36.google.com with SMTP id 586e51a60fabf-12b542cb1d3so32992660fac.13 for ; Wed, 14 Sep 2022 10:10:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gateworks-com.20210112.gappssmtp.com; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date; bh=L6YhEh0UYxe2tPeB9Bs5zIhc3gbVkQ/Hoe4Ilc/R8DI=; b=zapowfMLZG6nfuKhIaOEKqurE8nHf+m0lG9E4Hi9bjj0S0ZyKLFdodnrgeUZtOI0rb vTmX8K6g2kmX7rUtUMjnImvjBJMi22CluiHOAjhxG7L4H8xlKr+xbg1kZRoGZvSGJw8K HPRNo7jozmxDWJP68L5vaf5tLCfvQGqxodV4UV0D/3BVEn3M+YxepKAm7UlhCgfRpZNo UvTqcd1UP5IMAQo6z2XRKT1Yh9/gUuUq2ZgJCRRDOecB4oX+7Ai3EtR1zJ2xeqimnTK4 yB5oIda938tiCaV6kurWJy0tuIHeeiwb41hkYaiYwkux2cCCQ9DBESndrpUaruy9AxQq MY9Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date; bh=L6YhEh0UYxe2tPeB9Bs5zIhc3gbVkQ/Hoe4Ilc/R8DI=; b=T1TW6nn9CcbD97y9pMFNafdTUnWBYxDrCjhc81xHEUEmUWPctAUiKhyks1i6I7W/t9 wj3OhonK/fZafatkNug73wCW9+wzo0szsf+jPxi8jyVjMf5HjpEWpCC2OMoG0/0NzcYP +ngtMnwms8yqNyNwPu51yC9N/uRi8HSgG8K4T/9wWtmWH3EQFCYe8cw+Jw/dsTzPqVMw aRpY14auzgVLFaw3BGm+wEiHHlzj66F0ZEFWMmCO8jhp3mWsI1l31VFV2PHeXdR2OU2k qhtBBajFFUwIOVB+cJJDgZY5KapgBwnznY48BV5NjH/KSQp9fk7CplxKqWUxY4+A24te 9hTg== X-Gm-Message-State: ACgBeo2YlnHWq3ED3ftAaCJ99vYiKMLXNjGebQOhwXzt4GOs9BeS72Dg PZ8TbpbT1Oxpj+BDJrz20qTOrQeH0VC+MAIjjwvHcg== X-Google-Smtp-Source: AA6agR7ixBrehjh+uaYWhVhkcOhLhwy9Hd2Lp8tza6xcOsSAGXpYrRtPGVvl/Tu+9j1KD/zQEfu+HWFjxJM3KHklmeI= X-Received: by 2002:a05:6808:1444:b0:344:f010:27d8 with SMTP id x4-20020a056808144400b00344f01027d8mr2273353oiv.33.1663175403154; Wed, 14 Sep 2022 10:10:03 -0700 (PDT) MIME-Version: 1.0 References: <20220908154903.4100386-1-tharvey@gateworks.com> <2530681.Lt9SDvczpP@steina-w> In-Reply-To: From: Tim Harvey Date: Wed, 14 Sep 2022 10:09:51 -0700 Message-ID: Subject: Re: [PATCH] arm64: dts: imx8mp-venice-gw74xx: add PCIe support To: Shawn Guo Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, NXP Linux Team , Fabio Estevam , Pengutronix Kernel Team , Sascha Hauer , Krzysztof Kozlowski , Rob Herring , Alexander Stein Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, Sep 9, 2022 at 10:42 AM Tim Harvey wrote: > > On Thu, Sep 8, 2022 at 10:59 PM Alexander Stein > wrote: > > > > Hi Tim, > > > > Am Donnerstag, 8. September 2022, 17:49:03 CEST schrieb Tim Harvey: > > > Add PCIe support on the Gateworks GW74xx board. While at it, > > > fix the related gpio line names from the previous incorrect values. > > > > > > Signed-off-by: Tim Harvey > > > --- > > > .../dts/freescale/imx8mp-venice-gw74xx.dts | 40 +++++++++++++++++-- > > > 1 file changed, 37 insertions(+), 3 deletions(-) > > > > > > diff --git a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts > > > b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts index > > > e0fe356b662d..7644db61d631 100644 > > > --- a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts > > > +++ b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts > > > @@ -8,6 +8,7 @@ > > > #include > > > #include > > > #include > > > +#include > > > > > > #include "imx8mp.dtsi" > > > > > > @@ -100,6 +101,12 @@ led-1 { > > > }; > > > }; > > > > > > + pcie0_refclk: pcie0-refclk { > > > + compatible = "fixed-clock"; > > > + #clock-cells = <0>; > > > + clock-frequency = <100000000>; > > > + }; > > > + > > > pps { > > > compatible = "pps-gpio"; > > > pinctrl-names = "default"; > > > @@ -215,8 +222,8 @@ &gpio1 { > > > &gpio2 { > > > gpio-line-names = > > > "", "", "", "", "", "", "", "", > > > - "", "", "", "", "", "", "", "", > > > - "pcie3_wdis#", "", "", "pcie1_wdis@", "pcie2_wdis#", "", > > "", "", > > > + "", "", "", "", "", "", "pcie3_wdis#", "", > > > + "", "", "pcie2_wdis#", "", "", "", "", "", > > > "", "", "", "", "", "", "", ""; > > > }; > > > > > > @@ -562,6 +569,28 @@ &i2c4 { > > > status = "okay"; > > > }; > > > > > > +&pcie_phy { > > > + fsl,refclk-pad-mode = ; > > > + fsl,clkreq-unsupported; > > > + clocks = <&pcie0_refclk>; > > > + clock-names = "ref"; > > > + status = "okay"; > > > +}; > > > + > > > +&pcie { > > > + pinctrl-names = "default"; > > > + pinctrl-0 = <&pinctrl_pcie0>; > > > + reset-gpio = <&gpio2 17 GPIO_ACTIVE_LOW>; > > > + clocks = <&clk IMX8MP_CLK_HSIO_ROOT>, > > > + <&clk IMX8MP_CLK_PCIE_ROOT>, > > > + <&clk IMX8MP_CLK_HSIO_AXI>; > > > + clock-names = "pcie", "pcie_aux", "pcie_bus"; > > > > With the still pending dt-binding patch at [1] the clock order shall be > > "pcie", "pcie_bus", "pcie_phy". > > > > Best regards, > > Alexander > > > > [1] https://lore.kernel.org/lkml/20220822184701.25246-2-Sergey.Semin@baikalelectronics.ru/ > > > > Alexander, > > Interesting... the imx8pm-evk PCIe patch was accepted with the > bindings I used which are current. So I suppose if/when the patch you > pointed to gets accepted some existing bindings will need to change to > be compliant. > > Best Regards, > > Tim Shawn, I'm unclear if this patch needs to change. I believe the patch adheres to the current bindings and if the bindings change it would require all the imx8m boards to have their bindings updated to agree with it. I'm also unclear if the order of the clocks really makes any difference here. Best Regards, Tim From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2A243C6FA82 for ; Wed, 14 Sep 2022 17:11:28 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:Subject:Message-ID:Date:From: In-Reply-To:References:MIME-Version:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=yfXgu8LZ2cGvfizKhnKqCU8heTbqcgYVZsWk/ayQpaU=; b=eyT2pmknT9mELt dn2kaqT1bII6buZlrj65xxX7pfraR5EkWX9vieNof6s6FjyMsh5P++M1belmhxZoE5lLiDkzKOIz9 9DsVSrgigjuVWmVYPzKn65S38njaq4tmrnvT1OWZAyoyT2Tl9gcQga5UTsvs2cGC45On1wZz6l3MI GjBlGnUzN9h4bsCg1B+y+nSty7NdZpAzrksnoyFvuFcpj0umYdtRBHfEOrgQxk1Byc//S9WWFpsqq GBcUyrPKwxjP9sMIAJxlk5VVSBv0ERMj0iD+j2etS/Gbbq1UGZTi0NlEh7MYx9RvjHw67jPcrvUnM YOO9dGVGWsHBXJmDVkEA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1oYVts-005eBR-Bc; Wed, 14 Sep 2022 17:10:13 +0000 Received: from mail-oa1-x36.google.com ([2001:4860:4864:20::36]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1oYVtl-005e98-E9 for linux-arm-kernel@lists.infradead.org; Wed, 14 Sep 2022 17:10:07 +0000 Received: by mail-oa1-x36.google.com with SMTP id 586e51a60fabf-1274ec87ad5so42838748fac.0 for ; Wed, 14 Sep 2022 10:10:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gateworks-com.20210112.gappssmtp.com; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date; bh=L6YhEh0UYxe2tPeB9Bs5zIhc3gbVkQ/Hoe4Ilc/R8DI=; b=zapowfMLZG6nfuKhIaOEKqurE8nHf+m0lG9E4Hi9bjj0S0ZyKLFdodnrgeUZtOI0rb vTmX8K6g2kmX7rUtUMjnImvjBJMi22CluiHOAjhxG7L4H8xlKr+xbg1kZRoGZvSGJw8K HPRNo7jozmxDWJP68L5vaf5tLCfvQGqxodV4UV0D/3BVEn3M+YxepKAm7UlhCgfRpZNo UvTqcd1UP5IMAQo6z2XRKT1Yh9/gUuUq2ZgJCRRDOecB4oX+7Ai3EtR1zJ2xeqimnTK4 yB5oIda938tiCaV6kurWJy0tuIHeeiwb41hkYaiYwkux2cCCQ9DBESndrpUaruy9AxQq MY9Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date; bh=L6YhEh0UYxe2tPeB9Bs5zIhc3gbVkQ/Hoe4Ilc/R8DI=; b=uYktGJqsu/FUuOF96ttaeyVHU8QscbryBbk/HsXPC8hMxSGmcGrQtNJrYzl+HXdUi7 SnZ2KBQbAbVoStJmqH8k4wq+PYnL+AzwOxdPOkRmQK6tH+q5pCtd4LAgWeAWLfPd/jk3 qJor2G7SngNlIeIMVPWs86t15uFnLAbttXN+Pz2syhhWwf3xl7YZVO993RDVkPO1o5bZ dQyQwTWjm+atA9Z30WdS1W2Xr0pI+BFWya+BrPNQrVpxBvt1x61VUxN9UKtExRxePG2o 1OXPBDuwox0wqEZ8/oyeVEJIa9uKdhl8i0CxPvuIlzA76PNe3Lw53GZnrFyWicGbhCad MT+Q== X-Gm-Message-State: ACgBeo0o/s4p8zzMv6l7OHbrrRPbFJcPOcNbXPkJClln0OpFApmOVKER 1FzqJW+OrR5znxO4zV2cklwv1+qBF7h+njcCoUkJRg== X-Google-Smtp-Source: AA6agR7ixBrehjh+uaYWhVhkcOhLhwy9Hd2Lp8tza6xcOsSAGXpYrRtPGVvl/Tu+9j1KD/zQEfu+HWFjxJM3KHklmeI= X-Received: by 2002:a05:6808:1444:b0:344:f010:27d8 with SMTP id x4-20020a056808144400b00344f01027d8mr2273353oiv.33.1663175403154; Wed, 14 Sep 2022 10:10:03 -0700 (PDT) MIME-Version: 1.0 References: <20220908154903.4100386-1-tharvey@gateworks.com> <2530681.Lt9SDvczpP@steina-w> In-Reply-To: From: Tim Harvey Date: Wed, 14 Sep 2022 10:09:51 -0700 Message-ID: Subject: Re: [PATCH] arm64: dts: imx8mp-venice-gw74xx: add PCIe support To: Shawn Guo Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, NXP Linux Team , Fabio Estevam , Pengutronix Kernel Team , Sascha Hauer , Krzysztof Kozlowski , Rob Herring , Alexander Stein X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220914_101005_725335_C252115F X-CRM114-Status: GOOD ( 27.77 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Fri, Sep 9, 2022 at 10:42 AM Tim Harvey wrote: > > On Thu, Sep 8, 2022 at 10:59 PM Alexander Stein > wrote: > > > > Hi Tim, > > > > Am Donnerstag, 8. September 2022, 17:49:03 CEST schrieb Tim Harvey: > > > Add PCIe support on the Gateworks GW74xx board. While at it, > > > fix the related gpio line names from the previous incorrect values. > > > > > > Signed-off-by: Tim Harvey > > > --- > > > .../dts/freescale/imx8mp-venice-gw74xx.dts | 40 +++++++++++++++++-- > > > 1 file changed, 37 insertions(+), 3 deletions(-) > > > > > > diff --git a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts > > > b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts index > > > e0fe356b662d..7644db61d631 100644 > > > --- a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts > > > +++ b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts > > > @@ -8,6 +8,7 @@ > > > #include > > > #include > > > #include > > > +#include > > > > > > #include "imx8mp.dtsi" > > > > > > @@ -100,6 +101,12 @@ led-1 { > > > }; > > > }; > > > > > > + pcie0_refclk: pcie0-refclk { > > > + compatible = "fixed-clock"; > > > + #clock-cells = <0>; > > > + clock-frequency = <100000000>; > > > + }; > > > + > > > pps { > > > compatible = "pps-gpio"; > > > pinctrl-names = "default"; > > > @@ -215,8 +222,8 @@ &gpio1 { > > > &gpio2 { > > > gpio-line-names = > > > "", "", "", "", "", "", "", "", > > > - "", "", "", "", "", "", "", "", > > > - "pcie3_wdis#", "", "", "pcie1_wdis@", "pcie2_wdis#", "", > > "", "", > > > + "", "", "", "", "", "", "pcie3_wdis#", "", > > > + "", "", "pcie2_wdis#", "", "", "", "", "", > > > "", "", "", "", "", "", "", ""; > > > }; > > > > > > @@ -562,6 +569,28 @@ &i2c4 { > > > status = "okay"; > > > }; > > > > > > +&pcie_phy { > > > + fsl,refclk-pad-mode = ; > > > + fsl,clkreq-unsupported; > > > + clocks = <&pcie0_refclk>; > > > + clock-names = "ref"; > > > + status = "okay"; > > > +}; > > > + > > > +&pcie { > > > + pinctrl-names = "default"; > > > + pinctrl-0 = <&pinctrl_pcie0>; > > > + reset-gpio = <&gpio2 17 GPIO_ACTIVE_LOW>; > > > + clocks = <&clk IMX8MP_CLK_HSIO_ROOT>, > > > + <&clk IMX8MP_CLK_PCIE_ROOT>, > > > + <&clk IMX8MP_CLK_HSIO_AXI>; > > > + clock-names = "pcie", "pcie_aux", "pcie_bus"; > > > > With the still pending dt-binding patch at [1] the clock order shall be > > "pcie", "pcie_bus", "pcie_phy". > > > > Best regards, > > Alexander > > > > [1] https://lore.kernel.org/lkml/20220822184701.25246-2-Sergey.Semin@baikalelectronics.ru/ > > > > Alexander, > > Interesting... the imx8pm-evk PCIe patch was accepted with the > bindings I used which are current. So I suppose if/when the patch you > pointed to gets accepted some existing bindings will need to change to > be compliant. > > Best Regards, > > Tim Shawn, I'm unclear if this patch needs to change. I believe the patch adheres to the current bindings and if the bindings change it would require all the imx8m boards to have their bindings updated to agree with it. I'm also unclear if the order of the clocks really makes any difference here. Best Regards, Tim _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel