From mboxrd@z Thu Jan 1 00:00:00 1970 From: Adrian Chadd Date: Mon, 12 Sep 2011 12:26:01 +0800 Subject: [ath9k-devel] interrupt handling (ar9002/ar9003): why is BCNMISC checked before ISR_RAC ? Message-ID: List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: ath9k-devel@lists.ath9k.org Hi all, I have a few questions about the interrupt handling in ath9k (since FreeBSD's interrupt code is much the same.) Why is it that the BCNMISC flag in AR_ISR is checked in the AR_ISR read, -before- the AR_ISR_RAC register is read? Isn't it possible that there's a subtle race condition here, where reading AR_ISR for the BCNMISC flag will return 0, or some bits in AR_ISR_S2 are 0, but the condition that triggers them happens between the reads there, and the subsequent read from AR_ISR_RAC? (which then atomically copies them to _S registers and 0's the status registers?) Second question: why is there ATH9K_HW_CAP_RAC_SUPPORTED ? It's set for the AR9300_20 and later. The AR9002 routines don't even use that bit - they always use AR_ISR_RAC and the _S shadow registers. Is it something that doesn't exist for AR9300 1.0 ? (is that even public?) Thanks, Adrian