From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.9 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1D1F1C2D0E2 for ; Thu, 24 Sep 2020 10:08:55 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id C1C72239CF for ; Thu, 24 Sep 2020 10:08:54 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="Zu8WYvJO" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726818AbgIXKIy (ORCPT ); Thu, 24 Sep 2020 06:08:54 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45746 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726645AbgIXKIy (ORCPT ); Thu, 24 Sep 2020 06:08:54 -0400 Received: from mail-ej1-x643.google.com (mail-ej1-x643.google.com [IPv6:2a00:1450:4864:20::643]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E4BBDC0613CE for ; Thu, 24 Sep 2020 03:08:53 -0700 (PDT) Received: by mail-ej1-x643.google.com with SMTP id e23so3700060eja.3 for ; Thu, 24 Sep 2020 03:08:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=4Q/+ty8YH/7NC+1r/Q91xVAqEVNqsmZiYUT5XFfJbQs=; b=Zu8WYvJOls7Q3Fig3eJ0obXiUA4sepajGBI1MfS/tQysKqSQF9j1ANoJ2TXbCXlW+w hE8eyTVtwx5QcXnj+6V7hopYH53BkNlPKVE+q9DhDM0d3Lhk+Zv2dM5N51QpxUzxNPBB /qw0oNhzLvB50dzfi5h/mTfRzPy5X41IdaXsoWlVML8LZc85XeYQGG0kMsJM3qVJEKkF tf/Fl05NuSxRn2OEdnnjc55Hm1xSxXktdbky2ruFaFHZ+JaPbYdceyCTYYnQFvZsfdcH Bu134OnCRei7Soz9IZaix7pnYjRvvSu37Ojtn7mjZKzD/OS0Goamuu61T9ekZ7EBeMMV TiXA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=4Q/+ty8YH/7NC+1r/Q91xVAqEVNqsmZiYUT5XFfJbQs=; b=k8L9Qc4I7oHnU5wFD699RgQYzp+BupPa8UFXilYJGYnbx08UC5YqXyUKSd7SArzG3U npeCxtrlxXFkvx4e+yXFvfNID23dySS32V/YkejIA1vTEeFGWLncKKF7z6mySTelgYG2 6Ib0P+nQBZnmHmk/s/aBTIJL4b4f8IM1LZBteNQqZ/BOaCJSGGPwIn13uUvnrV0/FM5o li9SKJhlfGuQx4Fm4hfeb3lBq4Z7Ew14xVUPICv/oaptbwBgyMLfafvMMutOIbAirRfO FD4nu59wLSwOyRWEts82nRP8p7nnmukt4zIz5qVnCJND2ey/WntPquWkHhO/oMJaPRdc lO/w== X-Gm-Message-State: AOAM532e8VIXnVBJK7GhVryXFY1woV5vxo+Pb2bsZzFsbtzupg42onFY XEixCVqa/ZXthZMwWAtjMeLGZcrjqiMGVuKmDNA1rw== X-Google-Smtp-Source: ABdhPJwg8H6W0jtI8Nv0SsAaB2g5hijEHEmrvpNirWvkgIcXzahSN2l3t0nwJAI10Ib0A0IcGvR8QXY0cogJW35JcY8= X-Received: by 2002:a17:906:35d5:: with SMTP id p21mr207888ejb.194.1600942132576; Thu, 24 Sep 2020 03:08:52 -0700 (PDT) MIME-Version: 1.0 References: <20200911084119.1080694-1-suzuki.poulose@arm.com> <20200911084119.1080694-20-suzuki.poulose@arm.com> In-Reply-To: From: Mike Leach Date: Thu, 24 Sep 2020 11:08:41 +0100 Message-ID: Subject: Re: [PATCH 19/19] dts: bindings: coresight: ETMv4.4 system register access only units To: Suzuki K Poulose Cc: linux-arm-kernel , Coresight ML , Mathieu Poirier , Leo Yan , anshuman.khandual@arm.com, devicetree@vger.kernel.org, Rob Herring Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Hi suzuki, On Thu, 24 Sep 2020 at 10:43, Suzuki K Poulose wrote: > > On 09/18/2020 04:35 PM, Mike Leach wrote: > > On Fri, 11 Sep 2020 at 09:41, Suzuki K Poulose wrote: > >> > >> Document the bindings for ETMv4.4 and later with only system register > >> access. > >> > >> Cc: devicetree@vger.kernel.org > >> Cc: Mathieu Poirier > >> Cc: Mike Leach > >> Reviewed-by: Rob Herring > >> Signed-off-by: Suzuki K Poulose > >> --- > >> Documentation/devicetree/bindings/arm/coresight.txt | 6 +++++- > >> 1 file changed, 5 insertions(+), 1 deletion(-) > >> > >> diff --git a/Documentation/devicetree/bindings/arm/coresight.txt b/Documentation/devicetree/bindings/arm/coresight.txt > >> index d711676b4a51..cfe47bdda728 100644 > >> --- a/Documentation/devicetree/bindings/arm/coresight.txt > >> +++ b/Documentation/devicetree/bindings/arm/coresight.txt > >> @@ -34,9 +34,13 @@ its hardware characteristcs. > >> Program Flow Trace Macrocell: > >> "arm,coresight-etm3x", "arm,primecell"; > >> > >> - - Embedded Trace Macrocell (version 4.x): > >> + - Embedded Trace Macrocell (version 4.x), with memory mapped access. > >> "arm,coresight-etm4x", "arm,primecell"; > >> > >> + - Embedded Trace Macrocell (version 4.4 and later) with system > >> + register access only. > >> + "arm,coresight-etm-v4.4"; > > > > Any version of ETM can implement register access - including those pre > > ETM 4.4. Perhaps the new name should simply reflect sys reg access > > rather than a version. > > > > You're right. I got it confused with the v8.4 SelfHosted Extensions, which > mandates the sysreg access and makes the mem I/O obsolete. How about : > > "arm,coresight-etm4x-sysreg" ? > > Seems reasonable. Perhaps ensure that the accompanying comment mentions that this is aarch64 access (to cover the unlikely event that some outlier implementation does come along with v8 aarch32 + ETMv4 + sysreg access!) > > Given that the two compatibility strings should be mutually exclusive > > for a given device, should the bindings doc (or at least the etm4x > > component part) be re-written into the .yaml format so that this can > > be enforced? > > I will take a look, haven't played with the yaml. > I used it to describe the CTI bindings as these were brand new. Reasonably straight forwards - there are plenty of examples and the checking tools are pretty good. Regards Mike > Thanks for the review ! > > Suzuki -- Mike Leach Principal Engineer, ARM Ltd. Manchester Design Centre. UK From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-10.9 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 76C0EC4363D for ; Thu, 24 Sep 2020 10:10:33 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 1554C21D24 for ; Thu, 24 Sep 2020 10:10:32 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="TbT7R4ba"; dkim=fail reason="signature verification failed" (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="Zu8WYvJO" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 1554C21D24 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:To:Subject:Message-ID:Date:From:In-Reply-To: References:MIME-Version:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=9/uD90ysIm2rfBkifTCncVHdRCc0nwESlbBZlTeTDzw=; b=TbT7R4babCJue3l5ugcV4D8OZ il/UDOIQrUhxi+YrKA0WrrtCsrbUZ2gyvn8utsO6ZBsq+1I4JWaPFZnYTuNVskIkpjox5OVr+hYOY O7flXD3ypUO0eQVqtvaHZ5evItxqf3VxotT1Nqz/2VUZbvy6E5HbTB0vwtVI3oYTbSxxRxPTqBdw5 Md3MWIGiDM1bGaYJYTuZpqDruAgPTc4X4Zp3X3qMIiS+PHD59mIVDaiRwz1dE1rks9uzz/RZeBuo2 Akki3u3+jegyeZioWpNDVUpmh3qr3uy6YUpZixYMGdmUaR6qSJQdA5itNu1EfatynDN6qFaKCE9Hp h0bl1cOSQ==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kLOBN-0002Wd-8R; Thu, 24 Sep 2020 10:08:57 +0000 Received: from mail-ej1-x643.google.com ([2a00:1450:4864:20::643]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1kLOBK-0002Vd-0s for linux-arm-kernel@lists.infradead.org; Thu, 24 Sep 2020 10:08:55 +0000 Received: by mail-ej1-x643.google.com with SMTP id lo4so3632206ejb.8 for ; Thu, 24 Sep 2020 03:08:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=4Q/+ty8YH/7NC+1r/Q91xVAqEVNqsmZiYUT5XFfJbQs=; b=Zu8WYvJOls7Q3Fig3eJ0obXiUA4sepajGBI1MfS/tQysKqSQF9j1ANoJ2TXbCXlW+w hE8eyTVtwx5QcXnj+6V7hopYH53BkNlPKVE+q9DhDM0d3Lhk+Zv2dM5N51QpxUzxNPBB /qw0oNhzLvB50dzfi5h/mTfRzPy5X41IdaXsoWlVML8LZc85XeYQGG0kMsJM3qVJEKkF tf/Fl05NuSxRn2OEdnnjc55Hm1xSxXktdbky2ruFaFHZ+JaPbYdceyCTYYnQFvZsfdcH Bu134OnCRei7Soz9IZaix7pnYjRvvSu37Ojtn7mjZKzD/OS0Goamuu61T9ekZ7EBeMMV TiXA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=4Q/+ty8YH/7NC+1r/Q91xVAqEVNqsmZiYUT5XFfJbQs=; b=fLcoOv/8iqtEIRWeM32cJK0Vd7w4HfdLeCprurB1wadMe+MflTnboYCbvm2+EV08DL 0HR/sv/H9PM6MWj2iIIo3cDTurXue49bLrXU9W9AxXoWrdiW9E4z2T4od8vr970C4GDY oqAJRUPIGIWp1+UDc3iVgy2z3qymHYZQWjDevR80j9Ce161COJ/heh5jdYFZVmj2Ilcj jmQxrBdZNOUSFnSFAdMBxU8qcPCDSIieuZmjUf1wJbJc9HoZOmGV9IR6ebOg4M+Uapx1 +EZIApU+mVZXZl96aJbWocklTPyUUHkvM01hSayXYYj5RbW2RqOK6YW17/ogdkrH0z1s lZdA== X-Gm-Message-State: AOAM533LTJF94i3L6a6RHf8c8mc/woTbw21PC88KZHoYDq+JkBMo17O+ DAL5kzBUgIxjgLsLOpneyuIWNHldnKaiJ0W1tY5E7A== X-Google-Smtp-Source: ABdhPJwg8H6W0jtI8Nv0SsAaB2g5hijEHEmrvpNirWvkgIcXzahSN2l3t0nwJAI10Ib0A0IcGvR8QXY0cogJW35JcY8= X-Received: by 2002:a17:906:35d5:: with SMTP id p21mr207888ejb.194.1600942132576; Thu, 24 Sep 2020 03:08:52 -0700 (PDT) MIME-Version: 1.0 References: <20200911084119.1080694-1-suzuki.poulose@arm.com> <20200911084119.1080694-20-suzuki.poulose@arm.com> In-Reply-To: From: Mike Leach Date: Thu, 24 Sep 2020 11:08:41 +0100 Message-ID: Subject: Re: [PATCH 19/19] dts: bindings: coresight: ETMv4.4 system register access only units To: Suzuki K Poulose X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200924_060854_338262_7C810DCF X-CRM114-Status: GOOD ( 23.08 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Mathieu Poirier , anshuman.khandual@arm.com, Coresight ML , Leo Yan , Rob Herring , linux-arm-kernel Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi suzuki, On Thu, 24 Sep 2020 at 10:43, Suzuki K Poulose wrote: > > On 09/18/2020 04:35 PM, Mike Leach wrote: > > On Fri, 11 Sep 2020 at 09:41, Suzuki K Poulose wrote: > >> > >> Document the bindings for ETMv4.4 and later with only system register > >> access. > >> > >> Cc: devicetree@vger.kernel.org > >> Cc: Mathieu Poirier > >> Cc: Mike Leach > >> Reviewed-by: Rob Herring > >> Signed-off-by: Suzuki K Poulose > >> --- > >> Documentation/devicetree/bindings/arm/coresight.txt | 6 +++++- > >> 1 file changed, 5 insertions(+), 1 deletion(-) > >> > >> diff --git a/Documentation/devicetree/bindings/arm/coresight.txt b/Documentation/devicetree/bindings/arm/coresight.txt > >> index d711676b4a51..cfe47bdda728 100644 > >> --- a/Documentation/devicetree/bindings/arm/coresight.txt > >> +++ b/Documentation/devicetree/bindings/arm/coresight.txt > >> @@ -34,9 +34,13 @@ its hardware characteristcs. > >> Program Flow Trace Macrocell: > >> "arm,coresight-etm3x", "arm,primecell"; > >> > >> - - Embedded Trace Macrocell (version 4.x): > >> + - Embedded Trace Macrocell (version 4.x), with memory mapped access. > >> "arm,coresight-etm4x", "arm,primecell"; > >> > >> + - Embedded Trace Macrocell (version 4.4 and later) with system > >> + register access only. > >> + "arm,coresight-etm-v4.4"; > > > > Any version of ETM can implement register access - including those pre > > ETM 4.4. Perhaps the new name should simply reflect sys reg access > > rather than a version. > > > > You're right. I got it confused with the v8.4 SelfHosted Extensions, which > mandates the sysreg access and makes the mem I/O obsolete. How about : > > "arm,coresight-etm4x-sysreg" ? > > Seems reasonable. Perhaps ensure that the accompanying comment mentions that this is aarch64 access (to cover the unlikely event that some outlier implementation does come along with v8 aarch32 + ETMv4 + sysreg access!) > > Given that the two compatibility strings should be mutually exclusive > > for a given device, should the bindings doc (or at least the etm4x > > component part) be re-written into the .yaml format so that this can > > be enforced? > > I will take a look, haven't played with the yaml. > I used it to describe the CTI bindings as these were brand new. Reasonably straight forwards - there are plenty of examples and the checking tools are pretty good. Regards Mike > Thanks for the review ! > > Suzuki -- Mike Leach Principal Engineer, ARM Ltd. Manchester Design Centre. UK _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel