From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 660CEC433F5 for ; Tue, 12 Apr 2022 09:10:56 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:Subject:Message-ID:Date:From: In-Reply-To:References:MIME-Version:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=KCGvebJF+TSgh/Rs5MLfQvSj1p/NtbI86IGKT0NCqcU=; b=YJCIcBFnAsDA6Z V/4rNSk6MRP3TDiJciWiy4x7YLGqXx8WNTBGXblncJiS9yEYFoNwGYMTYjtzM4r2Hq1q5l7s04uKD 2ummdYRTVvpbspiMJEgvolfY5Hse/+WCXxVdO75Ip5XHbYvnEKRjw57eYrXTKSZoIkF6a8062YJHM RtqyZsQpSOBJ+53kka2EMmxigydXaf1wdN+eakIZhz3HvfKeeDlmsCsIFvNgYtOv0oPOgbkBEZKXF FSnu94a7IqJLYbNEM8hQ5R8WAzbUUxV454ulgcFQARU1D/NXr+VmjFFDuUPDNekfmxlZiAzyGDXgx b+29HkvjUbcH+KyoOz4w==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1neCWx-00CnyM-N6; Tue, 12 Apr 2022 09:09:47 +0000 Received: from mail-wr1-x430.google.com ([2a00:1450:4864:20::430]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1neCWu-00CnwE-4j for linux-arm-kernel@lists.infradead.org; Tue, 12 Apr 2022 09:09:45 +0000 Received: by mail-wr1-x430.google.com with SMTP id c7so26819629wrd.0 for ; Tue, 12 Apr 2022 02:09:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=fzQL91UfqQPbfJ6ZhV1VQ1qjBggTHD9xe3spBn4t+EU=; b=kEvfCIxPRa8U6nebGEh5TI0c+cY4hEmAYNogP7iXYP1uyN3oKb1IiM3WreLELmLKx+ Va/YTQz6ZcYYZssf5kJB/zq4HdY46jjM4dRRqBbaytP65JK7G6NE+CBo5zgkTegI/jR+ NGACrSU2RN7+cYN4IaARg62XIYxgWnEEKT7t7OlAxiIwgCXkJ0jMu61unN58szDi+FIc iR0P5a92pJpqebrJKYHmDhD9EIrHiw/9vKvWgWTYVaintqERiVuloM3wOeNIp9rZNLqb AH4RHgVF6uzJfF2bOMKhZMaFcHDjYwupCKcNRTeuFqiB5/ztMhuj6Cck1FSzi/1w5dGv Z7VQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=fzQL91UfqQPbfJ6ZhV1VQ1qjBggTHD9xe3spBn4t+EU=; b=Fm3Gw8/e9apPN+qV3IfOhMWQ9fBXib8led55HsXh3wCyccg3wqJ5mWD6XwMKquen5C m9Ms/2QGewmXBprTKd9t0rmNi5gZY7iJTvxQLFtk+WUALHmZFjR59dKUnlC4mVKdy7k/ wTAnZpftNUvcWoLYFi9OrZCeQpcara1Un3fGXJ/Hiuh826X4v/1ecx1ZcKQamvSpjnpd DuwqLMpPcGxGTOLvcW5Grok3haV1zz7hvvR7D2DfGtqiD/tfGOFXIJr4ztfN+vDC5hqj 5afnFiJxN46iCyHtCf2TXPLTWxQi8zU+akUpG4bs32qYut5W+gjvMDp+o7H6zf3/SnPV FqFg== X-Gm-Message-State: AOAM533SPEJGqbtrQN61KMBYDXWC38elREhj3ohQxbMsW/Pi0YDMQaiq iD2i1fyO0Sry+eRNdIskGEAfZL6uYvHRohPsOGECkg== X-Google-Smtp-Source: ABdhPJzLpMvnABfw0xK1gK7iwUBeEBPWFl6bs7XbBI4oAttMFjuF+gCYRia1s3oBQlKzuEeVTR3V9rQtEOX05Dy67JA= X-Received: by 2002:adf:cd87:0:b0:207:b0ad:6d8 with SMTP id q7-20020adfcd87000000b00207b0ad06d8mr1035423wrj.111.1649754581637; Tue, 12 Apr 2022 02:09:41 -0700 (PDT) MIME-Version: 1.0 References: <20220304171913.2292458-1-james.clark@arm.com> <20220304171913.2292458-8-james.clark@arm.com> In-Reply-To: <20220304171913.2292458-8-james.clark@arm.com> From: Mike Leach Date: Tue, 12 Apr 2022 10:09:29 +0100 Message-ID: Subject: Re: [PATCH v3 07/15] coresight: etm4x: Cleanup TRCEVENTCTL1R register accesses To: James Clark Cc: suzuki.poulose@arm.com, coresight@lists.linaro.org, Anshuman.Khandual@arm.com, mathieu.poirier@linaro.org, leo.yan@linaro.com, Leo Yan , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220412_020944_232664_BA7A01E8 X-CRM114-Status: GOOD ( 20.93 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Fri, 4 Mar 2022 at 17:19, James Clark wrote: > > This is a no-op change for style and consistency and has no effect on > the binary output by the compiler. In sysreg.h fields are defined as > the register name followed by the field name and then _MASK. This > allows for grepping for fields by name rather than using magic numbers. > > Signed-off-by: James Clark > --- > .../coresight/coresight-etm4x-sysfs.c | 25 +++++++++++-------- > drivers/hwtracing/coresight/coresight-etm4x.h | 8 ++++++ > 2 files changed, 23 insertions(+), 10 deletions(-) > > diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c > index 53f84da3fe44..2d29e9daf515 100644 > --- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c > +++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c > @@ -384,16 +384,16 @@ static ssize_t mode_store(struct device *dev, > /* bit[11], AMBA Trace Bus (ATB) trigger enable bit */ > if ((config->mode & ETM_MODE_ATB_TRIGGER) && > (drvdata->atbtrig == true)) > - config->eventctrl1 |= BIT(11); > + config->eventctrl1 |= TRCEVENTCTL1R_ATB; > else > - config->eventctrl1 &= ~BIT(11); > + config->eventctrl1 &= ~TRCEVENTCTL1R_ATB; > > /* bit[12], Low-power state behavior override bit */ > if ((config->mode & ETM_MODE_LPOVERRIDE) && > (drvdata->lpoverride == true)) > - config->eventctrl1 |= BIT(12); > + config->eventctrl1 |= TRCEVENTCTL1R_LPOVERRIDE; > else > - config->eventctrl1 &= ~BIT(12); > + config->eventctrl1 &= ~TRCEVENTCTL1R_LPOVERRIDE; > > /* bit[8], Instruction stall bit */ > if ((config->mode & ETM_MODE_ISTALL_EN) && (drvdata->stallctl == true)) > @@ -534,7 +534,7 @@ static ssize_t event_instren_show(struct device *dev, > struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); > struct etmv4_config *config = &drvdata->config; > > - val = BMVAL(config->eventctrl1, 0, 3); > + val = FIELD_GET(TRCEVENTCTL1R_INSTEN_MASK, config->eventctrl1); > return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); > } > > @@ -551,23 +551,28 @@ static ssize_t event_instren_store(struct device *dev, > > spin_lock(&drvdata->spinlock); > /* start by clearing all instruction event enable bits */ > - config->eventctrl1 &= ~(BIT(0) | BIT(1) | BIT(2) | BIT(3)); > + config->eventctrl1 &= ~TRCEVENTCTL1R_INSTEN_MASK; > switch (drvdata->nr_event) { > case 0x0: > /* generate Event element for event 1 */ > - config->eventctrl1 |= val & BIT(1); > + config->eventctrl1 |= val & TRCEVENTCTL1R_INSTEN_1; > break; > case 0x1: > /* generate Event element for event 1 and 2 */ > - config->eventctrl1 |= val & (BIT(0) | BIT(1)); > + config->eventctrl1 |= val & (TRCEVENTCTL1R_INSTEN_0 | TRCEVENTCTL1R_INSTEN_1); > break; > case 0x2: > /* generate Event element for event 1, 2 and 3 */ > - config->eventctrl1 |= val & (BIT(0) | BIT(1) | BIT(2)); > + config->eventctrl1 |= val & (TRCEVENTCTL1R_INSTEN_0 | > + TRCEVENTCTL1R_INSTEN_1 | > + TRCEVENTCTL1R_INSTEN_2); > break; > case 0x3: > /* generate Event element for all 4 events */ > - config->eventctrl1 |= val & 0xF; > + config->eventctrl1 |= val & (TRCEVENTCTL1R_INSTEN_0 | > + TRCEVENTCTL1R_INSTEN_1 | > + TRCEVENTCTL1R_INSTEN_2 | > + TRCEVENTCTL1R_INSTEN_3); > break; > default: > break; > diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h > index 4c8d7be3c159..cbba46f14ada 100644 > --- a/drivers/hwtracing/coresight/coresight-etm4x.h > +++ b/drivers/hwtracing/coresight/coresight-etm4x.h > @@ -188,6 +188,14 @@ > #define TRCCONFIGR_DA BIT(16) > #define TRCCONFIGR_DV BIT(17) > > +#define TRCEVENTCTL1R_INSTEN_MASK GENMASK(3, 0) > +#define TRCEVENTCTL1R_INSTEN_0 BIT(0) > +#define TRCEVENTCTL1R_INSTEN_1 BIT(1) > +#define TRCEVENTCTL1R_INSTEN_2 BIT(2) > +#define TRCEVENTCTL1R_INSTEN_3 BIT(3) > +#define TRCEVENTCTL1R_ATB BIT(11) > +#define TRCEVENTCTL1R_LPOVERRIDE BIT(12) > + > /* > * System instructions to access ETM registers. > * See ETMv4.4 spec ARM IHI0064F section 4.3.6 System instructions > -- > 2.28.0 > Reviewed-by: Mike Leach -- Mike Leach Principal Engineer, ARM Ltd. Manchester Design Centre. UK _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A6F76C433FE for ; Tue, 12 Apr 2022 10:18:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S245313AbiDLKSF (ORCPT ); Tue, 12 Apr 2022 06:18:05 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46216 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1354136AbiDLKDQ (ORCPT ); Tue, 12 Apr 2022 06:03:16 -0400 Received: from mail-wr1-x431.google.com (mail-wr1-x431.google.com [IPv6:2a00:1450:4864:20::431]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5C0666E55F for ; Tue, 12 Apr 2022 02:09:43 -0700 (PDT) Received: by mail-wr1-x431.google.com with SMTP id m14so2335460wrb.6 for ; Tue, 12 Apr 2022 02:09:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=fzQL91UfqQPbfJ6ZhV1VQ1qjBggTHD9xe3spBn4t+EU=; b=kEvfCIxPRa8U6nebGEh5TI0c+cY4hEmAYNogP7iXYP1uyN3oKb1IiM3WreLELmLKx+ Va/YTQz6ZcYYZssf5kJB/zq4HdY46jjM4dRRqBbaytP65JK7G6NE+CBo5zgkTegI/jR+ NGACrSU2RN7+cYN4IaARg62XIYxgWnEEKT7t7OlAxiIwgCXkJ0jMu61unN58szDi+FIc iR0P5a92pJpqebrJKYHmDhD9EIrHiw/9vKvWgWTYVaintqERiVuloM3wOeNIp9rZNLqb AH4RHgVF6uzJfF2bOMKhZMaFcHDjYwupCKcNRTeuFqiB5/ztMhuj6Cck1FSzi/1w5dGv Z7VQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=fzQL91UfqQPbfJ6ZhV1VQ1qjBggTHD9xe3spBn4t+EU=; b=krZ/hxxL61TfmiXzLVMFnsIUtuPQID0W+6Yc/y929rcUW+BhR9clmXfcNbP8Fcw41K +T/h9ssdDiiq3VE8yH8KadT9QqUxuHukKQA5tHOm0f2lnWIOuddTi4NPRGeTD1J4Qv/k YVk/XjZwquRonAc9OJ7i3kBqkSb5VgCNn7lYZjjYVLBvkzkAIFMtwlBQnxTGnCSts1OR BBaKS+GFlgTIU5Jy2bqpXJfXAeA1dX+3JaEQlUILHKrfN+eST9FS+YFTnx9Mf5GVDBse AI9jwMDMB7w76ggaEWLRbYYjffPw3/UCenCHvqQyzaNpjQN7CMkTYG6QjNbkydaTD8HB FLqA== X-Gm-Message-State: AOAM532iZVQSBdx5VJEg8D6eMC5cvaloE/+c5fnvhtyfEjcP2AggkST0 PSOV/ZN9ZSf7u2Sb1adivUqI744a7PGlTm6kkUm2sw== X-Google-Smtp-Source: ABdhPJzLpMvnABfw0xK1gK7iwUBeEBPWFl6bs7XbBI4oAttMFjuF+gCYRia1s3oBQlKzuEeVTR3V9rQtEOX05Dy67JA= X-Received: by 2002:adf:cd87:0:b0:207:b0ad:6d8 with SMTP id q7-20020adfcd87000000b00207b0ad06d8mr1035423wrj.111.1649754581637; Tue, 12 Apr 2022 02:09:41 -0700 (PDT) MIME-Version: 1.0 References: <20220304171913.2292458-1-james.clark@arm.com> <20220304171913.2292458-8-james.clark@arm.com> In-Reply-To: <20220304171913.2292458-8-james.clark@arm.com> From: Mike Leach Date: Tue, 12 Apr 2022 10:09:29 +0100 Message-ID: Subject: Re: [PATCH v3 07/15] coresight: etm4x: Cleanup TRCEVENTCTL1R register accesses To: James Clark Cc: suzuki.poulose@arm.com, coresight@lists.linaro.org, Anshuman.Khandual@arm.com, mathieu.poirier@linaro.org, leo.yan@linaro.com, Leo Yan , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, 4 Mar 2022 at 17:19, James Clark wrote: > > This is a no-op change for style and consistency and has no effect on > the binary output by the compiler. In sysreg.h fields are defined as > the register name followed by the field name and then _MASK. This > allows for grepping for fields by name rather than using magic numbers. > > Signed-off-by: James Clark > --- > .../coresight/coresight-etm4x-sysfs.c | 25 +++++++++++-------- > drivers/hwtracing/coresight/coresight-etm4x.h | 8 ++++++ > 2 files changed, 23 insertions(+), 10 deletions(-) > > diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c > index 53f84da3fe44..2d29e9daf515 100644 > --- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c > +++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c > @@ -384,16 +384,16 @@ static ssize_t mode_store(struct device *dev, > /* bit[11], AMBA Trace Bus (ATB) trigger enable bit */ > if ((config->mode & ETM_MODE_ATB_TRIGGER) && > (drvdata->atbtrig == true)) > - config->eventctrl1 |= BIT(11); > + config->eventctrl1 |= TRCEVENTCTL1R_ATB; > else > - config->eventctrl1 &= ~BIT(11); > + config->eventctrl1 &= ~TRCEVENTCTL1R_ATB; > > /* bit[12], Low-power state behavior override bit */ > if ((config->mode & ETM_MODE_LPOVERRIDE) && > (drvdata->lpoverride == true)) > - config->eventctrl1 |= BIT(12); > + config->eventctrl1 |= TRCEVENTCTL1R_LPOVERRIDE; > else > - config->eventctrl1 &= ~BIT(12); > + config->eventctrl1 &= ~TRCEVENTCTL1R_LPOVERRIDE; > > /* bit[8], Instruction stall bit */ > if ((config->mode & ETM_MODE_ISTALL_EN) && (drvdata->stallctl == true)) > @@ -534,7 +534,7 @@ static ssize_t event_instren_show(struct device *dev, > struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); > struct etmv4_config *config = &drvdata->config; > > - val = BMVAL(config->eventctrl1, 0, 3); > + val = FIELD_GET(TRCEVENTCTL1R_INSTEN_MASK, config->eventctrl1); > return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); > } > > @@ -551,23 +551,28 @@ static ssize_t event_instren_store(struct device *dev, > > spin_lock(&drvdata->spinlock); > /* start by clearing all instruction event enable bits */ > - config->eventctrl1 &= ~(BIT(0) | BIT(1) | BIT(2) | BIT(3)); > + config->eventctrl1 &= ~TRCEVENTCTL1R_INSTEN_MASK; > switch (drvdata->nr_event) { > case 0x0: > /* generate Event element for event 1 */ > - config->eventctrl1 |= val & BIT(1); > + config->eventctrl1 |= val & TRCEVENTCTL1R_INSTEN_1; > break; > case 0x1: > /* generate Event element for event 1 and 2 */ > - config->eventctrl1 |= val & (BIT(0) | BIT(1)); > + config->eventctrl1 |= val & (TRCEVENTCTL1R_INSTEN_0 | TRCEVENTCTL1R_INSTEN_1); > break; > case 0x2: > /* generate Event element for event 1, 2 and 3 */ > - config->eventctrl1 |= val & (BIT(0) | BIT(1) | BIT(2)); > + config->eventctrl1 |= val & (TRCEVENTCTL1R_INSTEN_0 | > + TRCEVENTCTL1R_INSTEN_1 | > + TRCEVENTCTL1R_INSTEN_2); > break; > case 0x3: > /* generate Event element for all 4 events */ > - config->eventctrl1 |= val & 0xF; > + config->eventctrl1 |= val & (TRCEVENTCTL1R_INSTEN_0 | > + TRCEVENTCTL1R_INSTEN_1 | > + TRCEVENTCTL1R_INSTEN_2 | > + TRCEVENTCTL1R_INSTEN_3); > break; > default: > break; > diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h > index 4c8d7be3c159..cbba46f14ada 100644 > --- a/drivers/hwtracing/coresight/coresight-etm4x.h > +++ b/drivers/hwtracing/coresight/coresight-etm4x.h > @@ -188,6 +188,14 @@ > #define TRCCONFIGR_DA BIT(16) > #define TRCCONFIGR_DV BIT(17) > > +#define TRCEVENTCTL1R_INSTEN_MASK GENMASK(3, 0) > +#define TRCEVENTCTL1R_INSTEN_0 BIT(0) > +#define TRCEVENTCTL1R_INSTEN_1 BIT(1) > +#define TRCEVENTCTL1R_INSTEN_2 BIT(2) > +#define TRCEVENTCTL1R_INSTEN_3 BIT(3) > +#define TRCEVENTCTL1R_ATB BIT(11) > +#define TRCEVENTCTL1R_LPOVERRIDE BIT(12) > + > /* > * System instructions to access ETM registers. > * See ETMv4.4 spec ARM IHI0064F section 4.3.6 System instructions > -- > 2.28.0 > Reviewed-by: Mike Leach -- Mike Leach Principal Engineer, ARM Ltd. Manchester Design Centre. UK