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a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=1yvOjDDhZx+9u1idO4dVb1NidYgCdd5CDBAaaYqS6wk=; b=l5YX3cNPvXbvz9etjpcB8/9avmozbwiImVfnXITgYNsqbyKpZG7tAEEmjKbBt4Mioe ufgAbuwxq/e2OTw92qIS0se/Vc3hWSnrojVJEtcPjFKa3lU6dSNaJFdyEKGcC4PS/VZi t+hu9sGGywOMoNS6dxaC/DIPmZ5IVyt3cZquN7DDHycSnHz8tDU2UJESeA1SZaaOwJ2/ ql2X2AB+ghV3Lvq1nEqb1ppX2v+duBx/XFOoj2v1ZP/eLw+ZJUyhXpDSxGmmqeHsct6y gkwBHSw2YGrrlXu5knsh8+M86I6WXP8Y8z3pTawfusAA0Eak25BPIBHQ25CueTB+yB7g YrhQ== X-Gm-Message-State: AOAM5324Rtz+ciY5o2ClG3TxaidgLTb/J3ChJaP0Dk8YzIKnRcfAii66 pHwh5U8eS4riJiAxaWVfwK7bdrkiXeSTndso3NIcs1hcHyI= X-Google-Smtp-Source: ABdhPJwB21Dpego/EpGoPo+Vmy7t5ogG5AjtyX1Q0140UDDo74+xQ6+eObRXwBmIAzxxredV9xWBSav1ttSYtGXHttA= X-Received: by 2002:aa7:d891:: with SMTP id u17mr34355153edq.188.1600443329505; Fri, 18 Sep 2020 08:35:29 -0700 (PDT) MIME-Version: 1.0 References: <20200911084119.1080694-1-suzuki.poulose@arm.com> <20200911084119.1080694-14-suzuki.poulose@arm.com> In-Reply-To: <20200911084119.1080694-14-suzuki.poulose@arm.com> From: Mike Leach Date: Fri, 18 Sep 2020 16:35:18 +0100 Message-ID: Subject: Re: [PATCH 13/19] coresight: etm4x: Clean up exception level masks To: Suzuki K Poulose X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200918_113532_675633_196C1FAE X-CRM114-Status: GOOD ( 23.37 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Coresight ML , Anshuman.Khandual@arm.com, Mathieu Poirier , linux-arm-kernel , Leo Yan Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Suzuki, On Fri, 11 Sep 2020 at 09:41, Suzuki K Poulose wrote: > > etm4_get_access_type() calculates the exception level bits > for use in address comparator registers. This is also used > by the TRCVICTLR register by shifting to the required position. > > This patch cleans up the logic to make etm4_get_access_type() > calcualte a generic mask which can be used by all users by Spelling^^ > shifting to their field. > > No functional changes, only code cleanups. > > Signed-off-by: Suzuki K Poulose > --- > .../coresight/coresight-etm4x-sysfs.c | 12 +++--- > drivers/hwtracing/coresight/coresight-etm4x.c | 27 ++++++------ > drivers/hwtracing/coresight/coresight-etm4x.h | 43 ++++++++++++------- > 3 files changed, 47 insertions(+), 35 deletions(-) > > diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c > index 321ad0dc09b0..b18805694350 100644 > --- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c > +++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c > @@ -743,7 +743,7 @@ static ssize_t s_exlevel_vinst_show(struct device *dev, > struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); > struct etmv4_config *config = &drvdata->config; > > - val = (config->vinst_ctrl & ETM_EXLEVEL_S_VICTLR_MASK) >> 16; > + val = (config->vinst_ctrl & TRCVICTLR_EXLEVEL_S_MASK) >> TRCVICTLR_EXLEVEL_S_SHIFT; > return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); > } > > @@ -760,10 +760,10 @@ static ssize_t s_exlevel_vinst_store(struct device *dev, > > spin_lock(&drvdata->spinlock); > /* clear all EXLEVEL_S bits */ > - config->vinst_ctrl &= ~(ETM_EXLEVEL_S_VICTLR_MASK); > + config->vinst_ctrl &= ~(TRCVICTLR_EXLEVEL_S_MASK); > /* enable instruction tracing for corresponding exception level */ > val &= drvdata->s_ex_level; > - config->vinst_ctrl |= (val << 16); > + config->vinst_ctrl |= (val << TRCVICTLR_EXLEVEL_S_SHIFT); > spin_unlock(&drvdata->spinlock); > return size; > } > @@ -778,7 +778,7 @@ static ssize_t ns_exlevel_vinst_show(struct device *dev, > struct etmv4_config *config = &drvdata->config; > > /* EXLEVEL_NS, bits[23:20] */ > - val = (config->vinst_ctrl & ETM_EXLEVEL_NS_VICTLR_MASK) >> 20; > + val = (config->vinst_ctrl & TRCVICTLR_EXLEVEL_NS_MASK) >> TRCVICTLR_EXLEVEL_NS_SHIFT; > return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); > } > > @@ -795,10 +795,10 @@ static ssize_t ns_exlevel_vinst_store(struct device *dev, > > spin_lock(&drvdata->spinlock); > /* clear EXLEVEL_NS bits */ > - config->vinst_ctrl &= ~(ETM_EXLEVEL_NS_VICTLR_MASK); > + config->vinst_ctrl &= ~(TRCVICTLR_EXLEVEL_NS_MASK); > /* enable instruction tracing for corresponding exception level */ > val &= drvdata->ns_ex_level; > - config->vinst_ctrl |= (val << 20); > + config->vinst_ctrl |= (val << TRCVICTLR_EXLEVEL_NS_SHIFT); > spin_unlock(&drvdata->spinlock); > return size; > } > diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c b/drivers/hwtracing/coresight/coresight-etm4x.c > index 439e9da41006..53687ec06db9 100644 > --- a/drivers/hwtracing/coresight/coresight-etm4x.c > +++ b/drivers/hwtracing/coresight/coresight-etm4x.c > @@ -867,20 +867,16 @@ static void etm4_init_arch_data(void *info) > etm4_cs_lock(drvdata, &csa); > } > > +static inline u32 etm4_get_victlr_access_type(struct etmv4_config *config) > +{ > + return etm4_get_access_type(config) << TRCVICTLR_EXLEVEL_SHIFT; > +} > + > /* Set ELx trace filter access in the TRCVICTLR register */ > static void etm4_set_victlr_access(struct etmv4_config *config) > { > - u64 access_type; > - > - config->vinst_ctrl &= ~(ETM_EXLEVEL_S_VICTLR_MASK | ETM_EXLEVEL_NS_VICTLR_MASK); > - > - /* > - * TRCVICTLR::EXLEVEL_NS:EXLEVELS: Set kernel / user filtering > - * bits in vinst_ctrl, same bit pattern as TRCACATRn values returned by > - * etm4_get_access_type() but with a relative shift in this register. > - */ > - access_type = etm4_get_access_type(config) << ETM_EXLEVEL_LSHIFT_TRCVICTLR; > - config->vinst_ctrl |= (u32)access_type; > + config->vinst_ctrl &= ~(TRCVICTLR_EXLEVEL_S_MASK | TRCVICTLR_EXLEVEL_NS_MASK); > + config->vinst_ctrl |= etm4_get_victlr_access_type(config); > } > > static void etm4_set_default_config(struct etmv4_config *config) > @@ -942,10 +938,15 @@ static u64 etm4_get_access_type(struct etmv4_config *config) > return access_type; > } > > +static u64 etm4_get_comparator_access_type(struct etmv4_config *config) > +{ > + return etm4_get_access_type(config) << TRCACATR_EXLEVEL_SHIFT; > +} > + > static void etm4_set_comparator_filter(struct etmv4_config *config, > u64 start, u64 stop, int comparator) > { > - u64 access_type = etm4_get_access_type(config); > + u64 access_type = etm4_get_comparator_access_type(config); > > /* First half of default address comparator */ > config->addr_val[comparator] = start; > @@ -980,7 +981,7 @@ static void etm4_set_start_stop_filter(struct etmv4_config *config, > enum etm_addr_type type) > { > int shift; > - u64 access_type = etm4_get_access_type(config); > + u64 access_type = etm4_get_comparator_access_type(config); > > /* Configure the comparator */ > config->addr_val[comparator] = address; > diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h > index 407ad6647f36..277c22540db6 100644 > --- a/drivers/hwtracing/coresight/coresight-etm4x.h > +++ b/drivers/hwtracing/coresight/coresight-etm4x.h > @@ -524,24 +524,35 @@ > > #define TRCACATR_EXLEVEL_SHIFT 8 #defined twice^^ - this one needs deleting. > > -/* secure state access levels - TRCACATRn */ > -#define ETM_EXLEVEL_S_APP BIT(8) > -#define ETM_EXLEVEL_S_OS BIT(9) > -#define ETM_EXLEVEL_S_HYP BIT(10) > -#define ETM_EXLEVEL_S_MON BIT(11) > -/* non-secure state access levels - TRCACATRn */ > -#define ETM_EXLEVEL_NS_APP BIT(12) > -#define ETM_EXLEVEL_NS_OS BIT(13) > -#define ETM_EXLEVEL_NS_HYP BIT(14) > -#define ETM_EXLEVEL_NS_NA BIT(15) > - > -/* access level control in TRCVICTLR - same bits as TRCACATRn but shifted */ > -#define ETM_EXLEVEL_LSHIFT_TRCVICTLR 8 > +/* > + * Exception level mask for Secure and Non-Secure ELs. > + * ETM defines the bits for EL control (e.g, TRVICTLR, TRCACTRn). > + * The Secure and Non-Secure ELs are always to gether. > + * Non-secure EL3 is never implemented. > + */ > +#define ETM_EXLEVEL_S_APP BIT(0) > +#define ETM_EXLEVEL_S_OS BIT(1) > +#define ETM_EXLEVEL_S_HYP BIT(2) > +#define ETM_EXLEVEL_S_MON BIT(3) > +#define ETM_EXLEVEL_NS_APP BIT(4) > +#define ETM_EXLEVEL_NS_OS BIT(5) > +#define ETM_EXLEVEL_NS_HYP BIT(6) > + > +#define ETM_EXLEVEL_MASK (GENMASK(6, 0)) > +#define ETM_EXLEVEL_S_MASK (GENMASK(3, 0)) > +#define ETM_EXLEVEL_NS_MASK (GENMASK(6, 4)) > + > +/* access level controls in TRCACATRn */ > +#define TRCACATR_EXLEVEL_SHIFT 8 > + > +/* access level control in TRCVICTLR */ > +#define TRCVICTLR_EXLEVEL_SHIFT 16 > +#define TRCVICTLR_EXLEVEL_S_SHIFT 16 > +#define TRCVICTLR_EXLEVEL_NS_SHIFT 20 > > /* secure / non secure masks - TRCVICTLR, IDR3 */ > -#define ETM_EXLEVEL_S_VICTLR_MASK GENMASK(19, 16) > -/* NS MON (EL3) mode never implemented */ > -#define ETM_EXLEVEL_NS_VICTLR_MASK GENMASK(22, 20) > +#define TRCVICTLR_EXLEVEL_S_MASK (ETM_EXLEVEL_S_MASK << TRCVICTLR_EXLEVEL_S_SHIFT) > +#define TRCVICTLR_EXLEVEL_NS_MASK (ETM_EXLEVEL_NS_MASK << TRCVICTLR_EXLEVEL_NS_SHIFT) > > /* > * TRCOSLSR.OSM - Bit[3,0] > -- > 2.24.1 > Regards Mike -- Mike Leach Principal Engineer, ARM Ltd. Manchester Design Centre. UK _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel