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a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=Ri4fbhz/q33sjkMPqc04lwWPRKsqTsKKasW91k9aNKY=; b=LLTUNzmyotjmDrudJcc/6HX9JXTBagk31RRlI3LH3YdnD/vetvbg4sJ8eqJ1MGvtuZ AJom/hKMXGlqBekalUW/w1QvO/AA93PFr21LXaKqHjPJ0IWQalJhByir9jHlRU24vuMf kEbse6X/KDCxxArww69yZ39KHfKtLuhPRpWq9hivuL6qVzPrB4ZMCg4sKz2Eo7csA+h/ zG6P1X8fFtSc+z8m3/u02i5GFChH5EtcjnZGbhUksQrt2fmR9c4IRYTZpc3bXPW1JTPi yYenBSvy5t/1+3GQDJFJYDjz4ZOfrfturmkmJITY/OEPQptXHGH1Wu+rsEpKT4dddOAv Nw0A== X-Gm-Message-State: AOAM530IG94sCnO5VUPkOFaxREZUkYA+ZPwfx0N7G5SAncQbY+yJl9J6 /TMYphJ7wtsxN3g8+lNahDqHN4bd1oAx9x92fhRbRJVqPpc= X-Google-Smtp-Source: ABdhPJzmS/U1UwnfDtXcB8HW+3EMDvyUJJSZl91a1Tft02hIUiHo9fb2FQzEzmTMX8iiqonVeNRIDmIv7XnOaWcL5Vk= X-Received: by 2002:a50:cc9a:: with SMTP id q26mr40575252edi.64.1600443353740; Fri, 18 Sep 2020 08:35:53 -0700 (PDT) MIME-Version: 1.0 References: <20200911084119.1080694-1-suzuki.poulose@arm.com> <20200911084119.1080694-17-suzuki.poulose@arm.com> In-Reply-To: <20200911084119.1080694-17-suzuki.poulose@arm.com> From: Mike Leach Date: Fri, 18 Sep 2020 16:35:42 +0100 Message-ID: Subject: Re: [PATCH 16/19] coresight: etm4x: Detect system instructions support To: Suzuki K Poulose X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200918_113556_772138_FB45FF46 X-CRM114-Status: GOOD ( 22.20 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Coresight ML , Anshuman.Khandual@arm.com, Mathieu Poirier , linux-arm-kernel , Leo Yan Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Suzuki, On Fri, 11 Sep 2020 at 09:41, Suzuki K Poulose wrote: > > ETM v4.4 onwards adds support for system instruction access > to the ETM. Detect the support on an ETM and switch to using the > mode when available. > > Signed-off-by: Suzuki K Poulose > --- > drivers/hwtracing/coresight/coresight-etm4x.c | 31 +++++++++++++++++++ > 1 file changed, 31 insertions(+) > > diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c b/drivers/hwtracing/coresight/coresight-etm4x.c > index 0fce9fb12cff..dc5ac171db35 100644 > --- a/drivers/hwtracing/coresight/coresight-etm4x.c > +++ b/drivers/hwtracing/coresight/coresight-etm4x.c > @@ -693,11 +693,39 @@ static void etm_detect_lock_status(struct etmv4_drvdata *drvdata, > drvdata->os_lock_model = TRCOSLSR_OSM(os_lsr); > } > > +static inline bool cpu_supports_sysreg_trace(void) > +{ > + u64 dfr0 = read_sysreg_s(SYS_ID_AA64DFR0_EL1); > + > + return ((dfr0 >> ID_AA64DFR0_TRACEVER_SHIFT) & 0xfUL) > 0; > +} > + This will be an issue if you have an aarch32 device (eg Cortex-A32 or similar, with ETM support but no aarch64) > static inline bool trace_unit_supported(u32 devarch) > { > return (devarch & ETM_DEVARCH_ID_MASK) == ETM_DEVARCH_ETMv4x_ARCH; > } > > +static bool etm_init_sysreg_access(struct etmv4_drvdata *drvdata, > + struct csdev_access *csa) > +{ > + u32 devarch; > + > + if (!cpu_supports_sysreg_trace()) > + return false; > + > + devarch = read_etm4x_sysreg_const_offset(TRCDEVARCH); > + if (!trace_unit_supported(devarch)) > + return false; > + *csa = (struct csdev_access) { > + .io_mem = false, > + .read = etm4x_sysreg_read, > + .write = etm4x_sysreg_write, > + }; > + > + drvdata->arch = devarch; > + return true; > +} > + > static bool etm_init_iomem_access(struct etmv4_drvdata *drvdata, > struct csdev_access *csa) > { > @@ -716,6 +744,9 @@ static bool etm_init_iomem_access(struct etmv4_drvdata *drvdata, > static bool etm_init_csdev_access(struct etmv4_drvdata *drvdata, > struct csdev_access *csa) > { > + if (etm_init_sysreg_access(drvdata, csa)) > + Don't think we should enforce system instruction access if the device tree has defined memory access. The driver cannot possibly know if this is a mistake or deliberate (e.g. test / implementation bug fix).> + return true; > if (drvdata->base) > return etm_init_iomem_access(drvdata, csa); > > -- > 2.24.1 > The device tree bindings define the access support intended - and there is access specific probing. i.e. the next patch splits amba (mem access) / platform (sys access) driver probes, followed by the common probe section. The register / memory access support used should be made there, and the detection of a compatible device for the register access i.e. check TRCDEVARCH should be in the platform probe path too - possibly simplifying things and ensuring the common code changes are reduced. Regards Mike -- Mike Leach Principal Engineer, ARM Ltd. Manchester Design Centre. UK _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel