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a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=fRJMc9uYmRAo2MIcDUP/qwCpNYHg3b2mNU+bPSGNRlg=; b=pJIPPzOVJojLkvhqar2mODoyEhUt0mFcPm+8D7S0idf4V/wDNigoHpm4VRM5NAmuIQ yZhhDE0AHXd3BuM14hxETk/ZcyDFC3ovTfodTUbXVqxHqHurMY3i1hPwn5VXp43ndSTj ZiBAh4jhnqLL2oMoP/1rEAfZF6ybLzW66JpCieDJjZdBndaa8CNU5+sr2CnOGQnmyWKq b6n91uaw5Qgudkr9N/jdqw90iNLPnx/tcPocfLQSk2iV9nyy18O9AJIZ3YMgIzdSKzYH wt9nb2Wllp1Vz+zNAlxkoP//PeL28LHCzZznJreQj4Qp1jdXlRJUVSnJanw7WF2mvFlm bvag== X-Gm-Message-State: APjAAAWzTY4bdd+mMRcTW5nOGTtWAltkXSPDTYH3KDP69RVlq2gANzo+ mKs5ycAbJ2sVtJ2jA98vgANPal/jLz+iSVv0ZYHB/g== X-Google-Smtp-Source: APXvYqxAUaRNn9KQ0WLSkZB8h+jzjImrm4GKTXicTV4YjcRNgcclLzp/RKJ9IpDXJj8mshiNoTY1Zpjn9NN/5Y2ZnTI= X-Received: by 2002:ac8:6b8f:: with SMTP id z15mr8879486qts.62.1565780776084; Wed, 14 Aug 2019 04:06:16 -0700 (PDT) MIME-Version: 1.0 References: <20190730125157.884-1-andrew.murray@arm.com> <20190730125157.884-7-andrew.murray@arm.com> <9df0eea2-a9bd-3a93-ca51-9c3d2391a1cf@arm.com> <20190802143751.GP56241@e119886-lin.cambridge.arm.com> <20190814100152.GB43882@e119886-lin.cambridge.arm.com> In-Reply-To: <20190814100152.GB43882@e119886-lin.cambridge.arm.com> From: Mike Leach Date: Wed, 14 Aug 2019 12:06:05 +0100 Message-ID: Subject: Re: [PATCH v4 6/6] dt-bindings: arm: coresight: Add support for coresight-needs-save-restore To: Andrew Murray X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190814_040619_664542_6B4370E4 X-CRM114-Status: GOOD ( 35.34 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Al Grant , Mathieu Poirier , Suzuki K Poulose , Alexander Shishkin , Coresight ML , Leo Yan , Sudeep Holla , linux-arm-kernel Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi, On Wed, 14 Aug 2019 at 11:01, Andrew Murray wrote: > > On Sun, Aug 04, 2019 at 07:13:45AM -0600, Mathieu Poirier wrote: > > On Fri, 2 Aug 2019 at 08:37, Andrew Murray wrote: > > > > > > On Fri, Aug 02, 2019 at 11:40:54AM +0100, Suzuki K Poulose wrote: > > > > Hi Andrew, > > > > > > > > On 30/07/2019 13:51, Andrew Murray wrote: > > > > > Some coresight components, because of choices made during hardware > > > > > integration, require their state to be saved and restored across CPU low > > > > > power states. > > > > > > > > > > The software has no reliable method of detecting when save/restore is > > > > > required thus let's add a binding to inform the kernel. > > > > > > > > > > Signed-off-by: Andrew Murray > > > > > --- > > > > > Documentation/devicetree/bindings/arm/coresight.txt | 3 +++ > > > > > 1 file changed, 3 insertions(+) > > > > > > > > > > diff --git a/Documentation/devicetree/bindings/arm/coresight.txt b/Documentation/devicetree/bindings/arm/coresight.txt > > > > > index fcc3bacfd8bc..7cbdb7893af8 100644 > > > > > --- a/Documentation/devicetree/bindings/arm/coresight.txt > > > > > +++ b/Documentation/devicetree/bindings/arm/coresight.txt > > > > > @@ -92,6 +92,9 @@ its hardware characteristcs. > > > > > * arm,cp14: must be present if the system accesses ETM/PTM management > > > > > registers via co-processor 14. > > > > > + * arm,coresight-needs-save-restore: boolean. Indicates that software > > > > > + should save/restore state across power down. > > > > > + > > > > > > > > Do you think we could be a bit more descriptive here about when people could add > > > > it to the DT ? Here we don't mention when someone should use this property and > > > > it may be added to platforms where it may be absolutely unnecessary. How about : > > > > > > > > "Indicates that the hardware implementation may not honor the Powerup request > > > > from the software and thus might loose the register context on CPU power > > > > down (e.g, during CPUIdle). Software must save/restore the context during a > > > > CPU power transition cycle." > > > > > > How about the following: > > > > > > "Indicates that the hardware will loose register context on CPU power down (e.g. > > > CPUIdle), despite the TRCPDCR.PU bit being set." > > > > > > I'm keen to avoid making suggestions about what the kernel will do when it sees > > > this flag and thus prefer to focus on describing what the hardware does. So I > > > dropped your last sentence. However the name of the flag still implies policy > > > which I don't like. > > > > > > I also changed the 'may not honor' wording, I'm not sure if this is really the > > > case or if the spec is open to interpretation. > > > > > > It would great for this wording to also apply to other CS components though I > > > haven't investigated if these have a PU bit or something different. > > > > Exactly - the definition needs to be broad enough to apply to other CS > > components. Mike what do you think would be appropriate for CTIs? > CTIs have no power control at all - i.e. no PU bit to request we stay up - and reside in the debug power domain. So they are coupled to the CS/CPU/ETM/ power domains and reliant on outside forces to request power. The expectation is that for a PE bound CTI, if debug is powered then it will be fully powered - so an ETM with PU respected, or the external debug logic with DBGNOPWRDWN respected should be sufficient for CTI to stay alive. > How about we keep this short and simple: > > * arm,coresight-loses-context-with-cpu : boolean. Indicates that the hardware > will lose register context on CPU power down (e.g. CPUIdle). > So the above name is generic enough to encompass the CTI as well. > I could have added something like "... despite TRCPDCR.PU being set", or to > apply more generically: "... despite available register controls being set to > prevent such context loss". However whilst these are more informative - they > elude to some of reasons as to why context is lost and as we cannot be > exhaustive I'd rather not give a limited example. > > However if a longer explaination is required: > > * arm,coresight-loses-context-with-cpu : boolean. Indicates that the hardware > will lose register context on CPU power down (e.g. CPUIdle). An example of > where this may be needed are systems which contain a coresight component and > CPU in the same power domain. When the CPU powers down the coresight > component also powers down and loses its context. > > Any objections/preference? :) > Don't really care about length of explanation - but shouldn't mention ETM specific features. Mike > Thanks, > > Andrew Murray > > > > > > > > > Thanks, > > > > > > Andrew Murray > > > > > > > > > > > Cheers > > > > Suzuki -- Mike Leach Principal Engineer, ARM Ltd. Manchester Design Centre. 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