From: Julien Grall <julien.grall.oss@gmail.com>
To: Jan Beulich <jbeulich@suse.com>
Cc: xen-devel <xen-devel@lists.xenproject.org>,
Stefano Stabellini <sstabellini@kernel.org>
Subject: Re: [PATCH] Arm32: MSR to SPSR needs qualification
Date: Fri, 11 Jun 2021 09:00:01 +0100 [thread overview]
Message-ID: <CAJ=z9a07v-cnMhK=cVjjdN3-f4t8qGc3oQz17zRdLxOauBp=qA@mail.gmail.com> (raw)
In-Reply-To: <e4946a69-bc1a-d54c-dadf-e71feecd99ab@suse.com>
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On Fri, 11 Jun 2021, 08:55 Jan Beulich, <jbeulich@suse.com> wrote:
> The Arm ARM's description of MSR doesn't even allow for plain "SPSR"
> here, and while gas accepts this, it takes it to mean SPSR_cf. Yet
> surely all of SPSR wants updating on this path, not just the lowest and
> highest 8 bits.
>
Can you provide a reference to the Arm Arm? This would help to navigate
through the 8000 pages.
Cheers,
> Fixes: dfcffb128be4 ("xen/arm32: SPSR_hyp/SPSR")
> Signed-off-by: Jan Beulich <jbeulich@suse.com>
>
> --- a/xen/arch/arm/arm32/entry.S
> +++ b/xen/arch/arm/arm32/entry.S
> @@ -395,7 +395,7 @@ return_to_hypervisor:
> ldr r11, [sp, #UREGS_pc]
> msr ELR_hyp, r11
> ldr r11, [sp, #UREGS_cpsr]
> - msr SPSR, r11
> + msr SPSR_cxsf, r11
> #ifdef CONFIG_ARM32_HARDEN_BRANCH_PREDICTOR
> /*
> * Hardening branch predictor may require to setup a different
>
>
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next prev parent reply other threads:[~2021-06-11 8:00 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-06-11 7:55 [PATCH] Arm32: MSR to SPSR needs qualification Jan Beulich
2021-06-11 8:00 ` Julien Grall [this message]
2021-06-11 9:16 ` Jan Beulich
2021-06-11 10:41 ` Julien Grall
2021-06-11 13:02 ` Jan Beulich
2021-06-11 13:22 ` Julien Grall
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