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Wed, 25 Aug 2021 09:35:03 -0700 (PDT) X-Google-Smtp-Source: ABdhPJy1qnchkaTZcBfmWyq/1yQYdyXp/+Z3M+FOK2Yf4cbXw9y0IEOC91NUl67v9mEPJ/sBm9dc4ezIMm6/HeKu2RY= X-Received: by 2002:a9f:35ca:: with SMTP id u10mr3080517uad.82.1629909303378; Wed, 25 Aug 2021 09:35:03 -0700 (PDT) MIME-Version: 1.0 References: <20210825043522.346512-1-koba.ko@canonical.com> <20210825043522.346512-2-koba.ko@canonical.com> <87y28pev59.fsf@intel.com> <87sfyxes9b.fsf@intel.com> In-Reply-To: From: Koba Ko Date: Thu, 26 Aug 2021 00:34:52 +0800 Message-ID: To: Alex Deucher Cc: "Lazar, Lijo" , Jani Nikula , Intel Graphics Development , amd-gfx list , "Feng, Kenneth" , Alex Deucher Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Subject: Re: [Intel-gfx] [PATCH 2/2] drm/amdgpu: Disable PCIE_DPM on Intel RKL Platform X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" On Wed, Aug 25, 2021 at 10:33 PM Alex Deucher wrote= : > > On Wed, Aug 25, 2021 at 10:22 AM Lazar, Lijo wrote: > > > > > > > > On 8/25/2021 4:46 PM, Koba Ko wrote: > > > On Wed, Aug 25, 2021 at 6:24 PM Jani Nikula wrote: > > >> > > >> On Wed, 25 Aug 2021, Koba Ko wrote: > > >>> On Wed, Aug 25, 2021 at 5:22 PM Jani Nikula wrote: > > >>>> > > >>>> On Wed, 25 Aug 2021, Koba Ko wrote: > > >>>>> AMD polaris GPUs have an issue about audio noise on RKL platform, > > >>>>> they provide a commit to fix but for SMU7-based GPU still > > >>>>> need another module parameter, > > >>>>> > > >>>>> For avoiding the module parameter, switch PCI_DPM by determining > > >>>>> intel platform in amd drm driver. > > >>>> > > >>>> I'll just note that you could have a Tiger Lake PCH combined with = a > > >>>> number of platforms other than Rocket Lake, including not just the > > >>>> obvious Tiger Lake but also Sky Lake, Kaby Lake, Coffee Lake, and = Comet > > >>>> Lake. > > >>>> > > >>>> Again, I don't know what the root cause or fix should be, the work= around > > >>>> presented here impacts a much larger number of platforms than wher= e > > >>>> you're claiming the issue is. > > >>> > > >>> Hi Jani, thanks for your feedback. > > >>> Is there any way to identify the RKL PCH? > > >>> I trace the intel_pch.c and can't find the only pch id for RKL. > > >>> > > >>> INTEL_PCH_TGP_DEVICE_ID_TYPE is used by both TGL and RKL. > > >>> > > >>> so it seems that using IS_ROCKETLAKE() is the only way. > > >> > > >> I don't think there is a Rocket Lake PCH. But is the problem related= to > > >> the PCH or not? > > > > > > I thought its' not because the issue wouldn't be observed on the TGL = platform. > > > I only tried RKL platform and it use > > > INTEL_PCH_TGP_DEVICE_ID_TYPE/INTEL_PCH_TGP2_DEVICE_ID_TYPE, > > > As per AMD guys, they said the issue is only triggered in RKL platfor= m. > > > > > >> > > >> The GPU PCI IDs are in i915_pciids.h. See INTEL_RKL_IDS() for > > >> RKL. There's a lot of indirection, but that's what IS_ROCKETLAKE() b= oils > > >> down to. But again, I'm not sure if that's what you want or not. > > > Thanks for suggestions, > > > > > > Just want a way to check if it's a RKL platform, > > > After tracing the kernel, can check by CPU VENDOR(lacks type), check > > > igpu(but there're cpus without igpu) > > > and check pch type(it seems one pch has multiple combinations with CP= U). > > > for check igpu, as per my current understanding, only found RKL CPU = with igpu. > > > Is there a RKL CPU without integrated gpu? > > > > > > > Just for RKL - you could do fetch the x86 info and check > > > > #ifdef CONFIG_X86_64 > > struct cpuinfo_x86 *c =3D &cpu_data(0); > > // Family/Model check, find the model > > (c->x86 =3D=3D 6 && c->x86_model =3D=3D INTEL_FAM6_ROCKETLAKE) > > #endif > > > > I think we don't use anything like this so far. So Alex should give a > > nod as well. > > I think that makes sense. For some background the issue that was > observed with RKL was that the PCIE gen switching has a very high > latency which can lead to audio problems during playback if PCIE DPM > is enabled. > > Alex Thanks, use Lazar's suggestion and don't need any information from i915. I will send the next patch. Thanks Koba > > > > > Thanks, > > Lijo > > > > >> > > >> BR, > > >> Jani. > > >> > > >> > > >>> > > >>> Thanks > > >>>> > > >>>> BR, > > >>>> Jani. > > >>>> > > >>>> > > >>>>> > > >>>>> Fixes: 1a31474cdb48 ("drm/amd/pm: workaround for audio noise issu= e") > > >>>>> Ref: https://nam11.safelinks.protection.outlook.com/?url=3Dhttps%= 3A%2F%2Flists.freedesktop.org%2Farchives%2Famd-gfx%2F2021-August%2F067413.h= tml&data=3D04%7C01%7Clijo.lazar%40amd.com%7C888ab428f2bb4f32e4d408d967c= 4ae08%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637654916721463596%7CUnk= nown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJX= VCI6Mn0%3D%7C1000&sdata=3DBgf14CmIx%2FTOD54LN6dccZL0U5gT9lv9yTw7MfKc2sQ= %3D&reserved=3D0 > > >>>>> Signed-off-by: Koba Ko > > >>>>> --- > > >>>>> .../drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c | 21 ++++++++++++= ++++++- > > >>>>> 1 file changed, 20 insertions(+), 1 deletion(-) > > >>>>> > > >>>>> diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c = b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c > > >>>>> index 0541bfc81c1b..346110dd0f51 100644 > > >>>>> --- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c > > >>>>> +++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c > > >>>>> @@ -1733,6 +1733,25 @@ static int smu7_disable_dpm_tasks(struct p= p_hwmgr *hwmgr) > > >>>>> return result; > > >>>>> } > > >>>>> > > >>>>> +#include > > >>>>> + > > >>>>> +static bool intel_tgp_chk(void) > > >>>>> +{ > > >>>>> + struct pci_dev *pch =3D NULL; > > >>>>> + unsigned short id; > > >>>>> + > > >>>>> + while ((pch =3D pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, pc= h))) { > > >>>>> + if (pch->vendor !=3D PCI_VENDOR_ID_INTEL) > > >>>>> + continue; > > >>>>> + > > >>>>> + id =3D pch->device & INTEL_PCH_DEVICE_ID_MASK; > > >>>>> + if (id =3D=3D INTEL_PCH_TGP_DEVICE_ID_TYPE || INTEL= _PCH_TGP2_DEVICE_ID_TYPE) > > >>>> > > >>>> PS. This is always true. ;) > > >>> > > >>> got, thanks > > >>> > > >>>> > > >>>>> + return true; > > >>>>> + } > > >>>>> + > > >>>>> + return false; > > >>>>> +} > > >>>>> + > > >>>>> static void smu7_init_dpm_defaults(struct pp_hwmgr *hwmgr) > > >>>>> { > > >>>>> struct smu7_hwmgr *data =3D (struct smu7_hwmgr *)(hwmgr->b= ackend); > > >>>>> @@ -1758,7 +1777,7 @@ static void smu7_init_dpm_defaults(struct p= p_hwmgr *hwmgr) > > >>>>> > > >>>>> data->mclk_dpm_key_disabled =3D hwmgr->feature_mask & PP_M= CLK_DPM_MASK ? false : true; > > >>>>> data->sclk_dpm_key_disabled =3D hwmgr->feature_mask & PP_S= CLK_DPM_MASK ? false : true; > > >>>>> - data->pcie_dpm_key_disabled =3D hwmgr->feature_mask & PP_PC= IE_DPM_MASK ? false : true; > > >>>>> + data->pcie_dpm_key_disabled =3D intel_tgp_chk() || !(hwmgr-= >feature_mask & PP_PCIE_DPM_MASK); > > >>>>> /* need to set voltage control types before EVV patching *= / > > >>>>> data->voltage_control =3D SMU7_VOLTAGE_CONTROL_NONE; > > >>>>> data->vddci_control =3D SMU7_VOLTAGE_CONTROL_NONE; > > >>>> > > >>>> -- > > >>>> Jani Nikula, Intel Open Source Graphics Center > > >> > > >> -- > > >> Jani Nikula, Intel Open Source Graphics Center From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DA376C4338F for ; Wed, 25 Aug 2021 16:37:01 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 8859F60F5C for ; Wed, 25 Aug 2021 16:37:01 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 8859F60F5C Authentication-Results: mail.kernel.org; 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Wed, 25 Aug 2021 09:35:03 -0700 (PDT) X-Google-Smtp-Source: ABdhPJy1qnchkaTZcBfmWyq/1yQYdyXp/+Z3M+FOK2Yf4cbXw9y0IEOC91NUl67v9mEPJ/sBm9dc4ezIMm6/HeKu2RY= X-Received: by 2002:a9f:35ca:: with SMTP id u10mr3080517uad.82.1629909303378; Wed, 25 Aug 2021 09:35:03 -0700 (PDT) MIME-Version: 1.0 References: <20210825043522.346512-1-koba.ko@canonical.com> <20210825043522.346512-2-koba.ko@canonical.com> <87y28pev59.fsf@intel.com> <87sfyxes9b.fsf@intel.com> In-Reply-To: From: Koba Ko Date: Thu, 26 Aug 2021 00:34:52 +0800 Message-ID: Subject: Re: [PATCH 2/2] drm/amdgpu: Disable PCIE_DPM on Intel RKL Platform To: Alex Deucher Cc: "Lazar, Lijo" , Jani Nikula , Intel Graphics Development , amd-gfx list , "Feng, Kenneth" , Alex Deucher Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Mailman-Approved-At: Wed, 25 Aug 2021 16:36:59 +0000 X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" On Wed, Aug 25, 2021 at 10:33 PM Alex Deucher wrote= : > > On Wed, Aug 25, 2021 at 10:22 AM Lazar, Lijo wrote: > > > > > > > > On 8/25/2021 4:46 PM, Koba Ko wrote: > > > On Wed, Aug 25, 2021 at 6:24 PM Jani Nikula wrote: > > >> > > >> On Wed, 25 Aug 2021, Koba Ko wrote: > > >>> On Wed, Aug 25, 2021 at 5:22 PM Jani Nikula wrote: > > >>>> > > >>>> On Wed, 25 Aug 2021, Koba Ko wrote: > > >>>>> AMD polaris GPUs have an issue about audio noise on RKL platform, > > >>>>> they provide a commit to fix but for SMU7-based GPU still > > >>>>> need another module parameter, > > >>>>> > > >>>>> For avoiding the module parameter, switch PCI_DPM by determining > > >>>>> intel platform in amd drm driver. > > >>>> > > >>>> I'll just note that you could have a Tiger Lake PCH combined with = a > > >>>> number of platforms other than Rocket Lake, including not just the > > >>>> obvious Tiger Lake but also Sky Lake, Kaby Lake, Coffee Lake, and = Comet > > >>>> Lake. > > >>>> > > >>>> Again, I don't know what the root cause or fix should be, the work= around > > >>>> presented here impacts a much larger number of platforms than wher= e > > >>>> you're claiming the issue is. > > >>> > > >>> Hi Jani, thanks for your feedback. > > >>> Is there any way to identify the RKL PCH? > > >>> I trace the intel_pch.c and can't find the only pch id for RKL. > > >>> > > >>> INTEL_PCH_TGP_DEVICE_ID_TYPE is used by both TGL and RKL. > > >>> > > >>> so it seems that using IS_ROCKETLAKE() is the only way. > > >> > > >> I don't think there is a Rocket Lake PCH. But is the problem related= to > > >> the PCH or not? > > > > > > I thought its' not because the issue wouldn't be observed on the TGL = platform. > > > I only tried RKL platform and it use > > > INTEL_PCH_TGP_DEVICE_ID_TYPE/INTEL_PCH_TGP2_DEVICE_ID_TYPE, > > > As per AMD guys, they said the issue is only triggered in RKL platfor= m. > > > > > >> > > >> The GPU PCI IDs are in i915_pciids.h. See INTEL_RKL_IDS() for > > >> RKL. There's a lot of indirection, but that's what IS_ROCKETLAKE() b= oils > > >> down to. But again, I'm not sure if that's what you want or not. > > > Thanks for suggestions, > > > > > > Just want a way to check if it's a RKL platform, > > > After tracing the kernel, can check by CPU VENDOR(lacks type), check > > > igpu(but there're cpus without igpu) > > > and check pch type(it seems one pch has multiple combinations with CP= U). > > > for check igpu, as per my current understanding, only found RKL CPU = with igpu. > > > Is there a RKL CPU without integrated gpu? > > > > > > > Just for RKL - you could do fetch the x86 info and check > > > > #ifdef CONFIG_X86_64 > > struct cpuinfo_x86 *c =3D &cpu_data(0); > > // Family/Model check, find the model > > (c->x86 =3D=3D 6 && c->x86_model =3D=3D INTEL_FAM6_ROCKETLAKE) > > #endif > > > > I think we don't use anything like this so far. So Alex should give a > > nod as well. > > I think that makes sense. For some background the issue that was > observed with RKL was that the PCIE gen switching has a very high > latency which can lead to audio problems during playback if PCIE DPM > is enabled. > > Alex Thanks, use Lazar's suggestion and don't need any information from i915. I will send the next patch. Thanks Koba > > > > > Thanks, > > Lijo > > > > >> > > >> BR, > > >> Jani. > > >> > > >> > > >>> > > >>> Thanks > > >>>> > > >>>> BR, > > >>>> Jani. > > >>>> > > >>>> > > >>>>> > > >>>>> Fixes: 1a31474cdb48 ("drm/amd/pm: workaround for audio noise issu= e") > > >>>>> Ref: https://nam11.safelinks.protection.outlook.com/?url=3Dhttps%= 3A%2F%2Flists.freedesktop.org%2Farchives%2Famd-gfx%2F2021-August%2F067413.h= tml&data=3D04%7C01%7Clijo.lazar%40amd.com%7C888ab428f2bb4f32e4d408d967c= 4ae08%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637654916721463596%7CUnk= nown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJX= VCI6Mn0%3D%7C1000&sdata=3DBgf14CmIx%2FTOD54LN6dccZL0U5gT9lv9yTw7MfKc2sQ= %3D&reserved=3D0 > > >>>>> Signed-off-by: Koba Ko > > >>>>> --- > > >>>>> .../drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c | 21 ++++++++++++= ++++++- > > >>>>> 1 file changed, 20 insertions(+), 1 deletion(-) > > >>>>> > > >>>>> diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c = b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c > > >>>>> index 0541bfc81c1b..346110dd0f51 100644 > > >>>>> --- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c > > >>>>> +++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c > > >>>>> @@ -1733,6 +1733,25 @@ static int smu7_disable_dpm_tasks(struct p= p_hwmgr *hwmgr) > > >>>>> return result; > > >>>>> } > > >>>>> > > >>>>> +#include > > >>>>> + > > >>>>> +static bool intel_tgp_chk(void) > > >>>>> +{ > > >>>>> + struct pci_dev *pch =3D NULL; > > >>>>> + unsigned short id; > > >>>>> + > > >>>>> + while ((pch =3D pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, pc= h))) { > > >>>>> + if (pch->vendor !=3D PCI_VENDOR_ID_INTEL) > > >>>>> + continue; > > >>>>> + > > >>>>> + id =3D pch->device & INTEL_PCH_DEVICE_ID_MASK; > > >>>>> + if (id =3D=3D INTEL_PCH_TGP_DEVICE_ID_TYPE || INTEL= _PCH_TGP2_DEVICE_ID_TYPE) > > >>>> > > >>>> PS. This is always true. ;) > > >>> > > >>> got, thanks > > >>> > > >>>> > > >>>>> + return true; > > >>>>> + } > > >>>>> + > > >>>>> + return false; > > >>>>> +} > > >>>>> + > > >>>>> static void smu7_init_dpm_defaults(struct pp_hwmgr *hwmgr) > > >>>>> { > > >>>>> struct smu7_hwmgr *data =3D (struct smu7_hwmgr *)(hwmgr->b= ackend); > > >>>>> @@ -1758,7 +1777,7 @@ static void smu7_init_dpm_defaults(struct p= p_hwmgr *hwmgr) > > >>>>> > > >>>>> data->mclk_dpm_key_disabled =3D hwmgr->feature_mask & PP_M= CLK_DPM_MASK ? false : true; > > >>>>> data->sclk_dpm_key_disabled =3D hwmgr->feature_mask & PP_S= CLK_DPM_MASK ? false : true; > > >>>>> - data->pcie_dpm_key_disabled =3D hwmgr->feature_mask & PP_PC= IE_DPM_MASK ? false : true; > > >>>>> + data->pcie_dpm_key_disabled =3D intel_tgp_chk() || !(hwmgr-= >feature_mask & PP_PCIE_DPM_MASK); > > >>>>> /* need to set voltage control types before EVV patching *= / > > >>>>> data->voltage_control =3D SMU7_VOLTAGE_CONTROL_NONE; > > >>>>> data->vddci_control =3D SMU7_VOLTAGE_CONTROL_NONE; > > >>>> > > >>>> -- > > >>>> Jani Nikula, Intel Open Source Graphics Center > > >> > > >> -- > > >> Jani Nikula, Intel Open Source Graphics Center