From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.0 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 20746C43461 for ; Sun, 11 Apr 2021 16:51:21 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id E6A3D60FE5 for ; Sun, 11 Apr 2021 16:51:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236519AbhDKQvf (ORCPT ); Sun, 11 Apr 2021 12:51:35 -0400 Received: from mail.kernel.org ([198.145.29.99]:55336 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233514AbhDKQvd (ORCPT ); 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Sun, 11 Apr 2021 09:51:15 -0700 (PDT) MIME-Version: 1.0 References: <1617201040-83905-1-git-send-email-guoren@kernel.org> <1617201040-83905-4-git-send-email-guoren@kernel.org> In-Reply-To: From: Guo Ren Date: Mon, 12 Apr 2021 00:51:03 +0800 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH v6 3/9] riscv: locks: Introduce ticket-based spinlock implementation To: Guo Ren Cc: linux-riscv , Linux Kernel Mailing List , linux-csky@vger.kernel.org, linux-arch , linuxppc-dev@lists.ozlabs.org, linux-xtensa@linux-xtensa.org, openrisc@lists.librecores.org, sparclinux , Guo Ren , Peter Zijlstra , Anup Patel , Arnd Bergmann Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, Apr 12, 2021 at 12:02 AM Guo Ren wrote: > > On Wed, Mar 31, 2021 at 10:32 PM wrote: > > > > From: Guo Ren > > > > This patch introduces a ticket lock implementation for riscv, along the > > same lines as the implementation for arch/arm & arch/csky. > > > > We still use qspinlock as default. > > > > Signed-off-by: Guo Ren > > Cc: Peter Zijlstra > > Cc: Anup Patel > > Cc: Arnd Bergmann > > --- > > arch/riscv/Kconfig | 7 ++- > > arch/riscv/include/asm/spinlock.h | 84 +++++++++++++++++++++++++ > > arch/riscv/include/asm/spinlock_types.h | 17 +++++ > > 3 files changed, 107 insertions(+), 1 deletion(-) > > > > diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig > > index 67cc65ba1ea1..34d0276f01d5 100644 > > --- a/arch/riscv/Kconfig > > +++ b/arch/riscv/Kconfig > > @@ -34,7 +34,7 @@ config RISCV > > select ARCH_WANT_FRAME_POINTERS > > select ARCH_WANT_HUGE_PMD_SHARE if 64BIT > > select ARCH_USE_QUEUED_RWLOCKS > > - select ARCH_USE_QUEUED_SPINLOCKS > > + select ARCH_USE_QUEUED_SPINLOCKS if !RISCV_TICKET_LOCK > > select ARCH_USE_QUEUED_SPINLOCKS_XCHG32 > > select CLONE_BACKWARDS > > select CLINT_TIMER if !MMU > > @@ -344,6 +344,11 @@ config NEED_PER_CPU_EMBED_FIRST_CHUNK > > def_bool y > > depends on NUMA > > > > +config RISCV_TICKET_LOCK > > + bool "Ticket-based spin-locking" > > + help > > + Say Y here to use ticket-based spin-locking. > > + > > config RISCV_ISA_C > > bool "Emit compressed instructions when building Linux" > > default y > > diff --git a/arch/riscv/include/asm/spinlock.h b/arch/riscv/include/asm/spinlock.h > > index a557de67a425..90b7eaa950cf 100644 > > --- a/arch/riscv/include/asm/spinlock.h > > +++ b/arch/riscv/include/asm/spinlock.h > > @@ -7,7 +7,91 @@ > > #ifndef _ASM_RISCV_SPINLOCK_H > > #define _ASM_RISCV_SPINLOCK_H > > > > +#ifdef CONFIG_RISCV_TICKET_LOCK > > +#ifdef CONFIG_32BIT > > +#define __ASM_SLLIW "slli\t" > > +#define __ASM_SRLIW "srli\t" > > +#else > > +#define __ASM_SLLIW "slliw\t" > > +#define __ASM_SRLIW "srliw\t" > > +#endif > > + > > +/* > > + * Ticket-based spin-locking. > > + */ > > +static inline void arch_spin_lock(arch_spinlock_t *lock) > > +{ > > + arch_spinlock_t lockval; > > + u32 tmp; > > + > > + asm volatile ( > > + "1: lr.w %0, %2 \n" > > + " mv %1, %0 \n" > > + " addw %0, %0, %3 \n" > > + " sc.w %0, %0, %2 \n" > > + " bnez %0, 1b \n" > > + : "=&r" (tmp), "=&r" (lockval), "+A" (lock->lock) > > + : "r" (1 << TICKET_NEXT) > > + : "memory"); > > + > > + smp_cond_load_acquire(&lock->tickets.owner, > > + VAL == lockval.tickets.next); > It's wrong, blew is fixup: > > diff --git a/arch/csky/include/asm/spinlock.h b/arch/csky/include/asm/spinlock.h > index fe98ad8ece51..2be627ceb9df 100644 > --- a/arch/csky/include/asm/spinlock.h > +++ b/arch/csky/include/asm/spinlock.h > @@ -27,7 +27,8 @@ static inline void arch_spin_lock(arch_spinlock_t *lock) > : "r"(p), "r"(ticket_next) > : "cc"); > > - smp_cond_load_acquire(&lock->tickets.owner, > + if (lockval.owner != lockval.tickets.next) > + smp_cond_load_acquire(&lock->tickets.owner, > VAL == lockval.tickets.next); eh... plus __smp_acquire_fence: if (lockval.owner != lockval.tickets.next) smp_cond_load_acquire(&lock->tickets.owner, VAL == lockval.tickets.next); else __smp_acquire_fence(); > > +} > > + > > +static inline int arch_spin_trylock(arch_spinlock_t *lock) > > +{ > > + u32 tmp, contended, res; > > + > > + do { > > + asm volatile ( > > + " lr.w %0, %3 \n" > > + __ASM_SRLIW "%1, %0, %5 \n" > > + __ASM_SLLIW "%2, %0, %5 \n" > > + " or %1, %2, %1 \n" > > + " li %2, 0 \n" > > + " sub %1, %1, %0 \n" > > + " bnez %1, 1f \n" > > + " addw %0, %0, %4 \n" > > + " sc.w %2, %0, %3 \n" > > + "1: \n" > > + : "=&r" (tmp), "=&r" (contended), "=&r" (res), > > + "+A" (lock->lock) > > + : "r" (1 << TICKET_NEXT), "I" (TICKET_NEXT) > > + : "memory"); > > + } while (res); > > + > > + if (!contended) > > + __atomic_acquire_fence(); > > + > > + return !contended; > > +} > > + > > +static inline void arch_spin_unlock(arch_spinlock_t *lock) > > +{ > > + smp_store_release(&lock->tickets.owner, lock->tickets.owner + 1); > > +} > > + > > +static inline int arch_spin_value_unlocked(arch_spinlock_t lock) > > +{ > > + return lock.tickets.owner == lock.tickets.next; > > +} > > + > > +static inline int arch_spin_is_locked(arch_spinlock_t *lock) > > +{ > > + return !arch_spin_value_unlocked(READ_ONCE(*lock)); > > +} > > + > > +static inline int arch_spin_is_contended(arch_spinlock_t *lock) > > +{ > > + struct __raw_tickets tickets = READ_ONCE(lock->tickets); > > + > > + return (tickets.next - tickets.owner) > 1; > > +} > > +#define arch_spin_is_contended arch_spin_is_contended > > +#else /* CONFIG_RISCV_TICKET_LOCK */ > > #include > > +#endif /* CONFIG_RISCV_TICKET_LOCK */ > > + > > #include > > > > #endif /* _ASM_RISCV_SPINLOCK_H */ > > diff --git a/arch/riscv/include/asm/spinlock_types.h b/arch/riscv/include/asm/spinlock_types.h > > index d033a973f287..afbb19841d0f 100644 > > --- a/arch/riscv/include/asm/spinlock_types.h > > +++ b/arch/riscv/include/asm/spinlock_types.h > > @@ -10,7 +10,24 @@ > > # error "please don't include this file directly" > > #endif > > > > +#ifdef CONFIG_RISCV_TICKET_LOCK > > +#define TICKET_NEXT 16 > > + > > +typedef struct { > > + union { > > + u32 lock; > > + struct __raw_tickets { > > + /* little endian */ > > + u16 owner; > > + u16 next; > > + } tickets; > > + }; > > +} arch_spinlock_t; > > + > > +#define __ARCH_SPIN_LOCK_UNLOCKED { { 0 } } > > +#else > > #include > > +#endif > > #include > > > > #endif /* _ASM_RISCV_SPINLOCK_TYPES_H */ > > -- > > 2.17.1 > > > > > -- > Best Regards > Guo Ren > > ML: https://lore.kernel.org/linux-csky/ -- Best Regards Guo Ren ML: https://lore.kernel.org/linux-csky/ From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-14.0 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id BAB1EC433ED for ; Sun, 11 Apr 2021 16:51:32 +0000 (UTC) Received: from desiato.infradead.org (desiato.infradead.org [90.155.92.199]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 41BDC610A2 for ; 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Sun, 11 Apr 2021 09:51:15 -0700 (PDT) MIME-Version: 1.0 References: <1617201040-83905-1-git-send-email-guoren@kernel.org> <1617201040-83905-4-git-send-email-guoren@kernel.org> In-Reply-To: From: Guo Ren Date: Mon, 12 Apr 2021 00:51:03 +0800 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH v6 3/9] riscv: locks: Introduce ticket-based spinlock implementation To: Guo Ren Cc: linux-riscv , Linux Kernel Mailing List , linux-csky@vger.kernel.org, linux-arch , linuxppc-dev@lists.ozlabs.org, linux-xtensa@linux-xtensa.org, openrisc@lists.librecores.org, sparclinux , Guo Ren , Peter Zijlstra , Anup Patel , Arnd Bergmann X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210411_095118_287871_9F2DE26A X-CRM114-Status: GOOD ( 30.48 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Mon, Apr 12, 2021 at 12:02 AM Guo Ren wrote: > > On Wed, Mar 31, 2021 at 10:32 PM wrote: > > > > From: Guo Ren > > > > This patch introduces a ticket lock implementation for riscv, along the > > same lines as the implementation for arch/arm & arch/csky. > > > > We still use qspinlock as default. > > > > Signed-off-by: Guo Ren > > Cc: Peter Zijlstra > > Cc: Anup Patel > > Cc: Arnd Bergmann > > --- > > arch/riscv/Kconfig | 7 ++- > > arch/riscv/include/asm/spinlock.h | 84 +++++++++++++++++++++++++ > > arch/riscv/include/asm/spinlock_types.h | 17 +++++ > > 3 files changed, 107 insertions(+), 1 deletion(-) > > > > diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig > > index 67cc65ba1ea1..34d0276f01d5 100644 > > --- a/arch/riscv/Kconfig > > +++ b/arch/riscv/Kconfig > > @@ -34,7 +34,7 @@ config RISCV > > select ARCH_WANT_FRAME_POINTERS > > select ARCH_WANT_HUGE_PMD_SHARE if 64BIT > > select ARCH_USE_QUEUED_RWLOCKS > > - select ARCH_USE_QUEUED_SPINLOCKS > > + select ARCH_USE_QUEUED_SPINLOCKS if !RISCV_TICKET_LOCK > > select ARCH_USE_QUEUED_SPINLOCKS_XCHG32 > > select CLONE_BACKWARDS > > select CLINT_TIMER if !MMU > > @@ -344,6 +344,11 @@ config NEED_PER_CPU_EMBED_FIRST_CHUNK > > def_bool y > > depends on NUMA > > > > +config RISCV_TICKET_LOCK > > + bool "Ticket-based spin-locking" > > + help > > + Say Y here to use ticket-based spin-locking. > > + > > config RISCV_ISA_C > > bool "Emit compressed instructions when building Linux" > > default y > > diff --git a/arch/riscv/include/asm/spinlock.h b/arch/riscv/include/asm/spinlock.h > > index a557de67a425..90b7eaa950cf 100644 > > --- a/arch/riscv/include/asm/spinlock.h > > +++ b/arch/riscv/include/asm/spinlock.h > > @@ -7,7 +7,91 @@ > > #ifndef _ASM_RISCV_SPINLOCK_H > > #define _ASM_RISCV_SPINLOCK_H > > > > +#ifdef CONFIG_RISCV_TICKET_LOCK > > +#ifdef CONFIG_32BIT > > +#define __ASM_SLLIW "slli\t" > > +#define __ASM_SRLIW "srli\t" > > +#else > > +#define __ASM_SLLIW "slliw\t" > > +#define __ASM_SRLIW "srliw\t" > > +#endif > > + > > +/* > > + * Ticket-based spin-locking. > > + */ > > +static inline void arch_spin_lock(arch_spinlock_t *lock) > > +{ > > + arch_spinlock_t lockval; > > + u32 tmp; > > + > > + asm volatile ( > > + "1: lr.w %0, %2 \n" > > + " mv %1, %0 \n" > > + " addw %0, %0, %3 \n" > > + " sc.w %0, %0, %2 \n" > > + " bnez %0, 1b \n" > > + : "=&r" (tmp), "=&r" (lockval), "+A" (lock->lock) > > + : "r" (1 << TICKET_NEXT) > > + : "memory"); > > + > > + smp_cond_load_acquire(&lock->tickets.owner, > > + VAL == lockval.tickets.next); > It's wrong, blew is fixup: > > diff --git a/arch/csky/include/asm/spinlock.h b/arch/csky/include/asm/spinlock.h > index fe98ad8ece51..2be627ceb9df 100644 > --- a/arch/csky/include/asm/spinlock.h > +++ b/arch/csky/include/asm/spinlock.h > @@ -27,7 +27,8 @@ static inline void arch_spin_lock(arch_spinlock_t *lock) > : "r"(p), "r"(ticket_next) > : "cc"); > > - smp_cond_load_acquire(&lock->tickets.owner, > + if (lockval.owner != lockval.tickets.next) > + smp_cond_load_acquire(&lock->tickets.owner, > VAL == lockval.tickets.next); eh... plus __smp_acquire_fence: if (lockval.owner != lockval.tickets.next) smp_cond_load_acquire(&lock->tickets.owner, VAL == lockval.tickets.next); else __smp_acquire_fence(); > > +} > > + > > +static inline int arch_spin_trylock(arch_spinlock_t *lock) > > +{ > > + u32 tmp, contended, res; > > + > > + do { > > + asm volatile ( > > + " lr.w %0, %3 \n" > > + __ASM_SRLIW "%1, %0, %5 \n" > > + __ASM_SLLIW "%2, %0, %5 \n" > > + " or %1, %2, %1 \n" > > + " li %2, 0 \n" > > + " sub %1, %1, %0 \n" > > + " bnez %1, 1f \n" > > + " addw %0, %0, %4 \n" > > + " sc.w %2, %0, %3 \n" > > + "1: \n" > > + : "=&r" (tmp), "=&r" (contended), "=&r" (res), > > + "+A" (lock->lock) > > + : "r" (1 << TICKET_NEXT), "I" (TICKET_NEXT) > > + : "memory"); > > + } while (res); > > + > > + if (!contended) > > + __atomic_acquire_fence(); > > + > > + return !contended; > > +} > > + > > +static inline void arch_spin_unlock(arch_spinlock_t *lock) > > +{ > > + smp_store_release(&lock->tickets.owner, lock->tickets.owner + 1); > > +} > > + > > +static inline int arch_spin_value_unlocked(arch_spinlock_t lock) > > +{ > > + return lock.tickets.owner == lock.tickets.next; > > +} > > + > > +static inline int arch_spin_is_locked(arch_spinlock_t *lock) > > +{ > > + return !arch_spin_value_unlocked(READ_ONCE(*lock)); > > +} > > + > > +static inline int arch_spin_is_contended(arch_spinlock_t *lock) > > +{ > > + struct __raw_tickets tickets = READ_ONCE(lock->tickets); > > + > > + return (tickets.next - tickets.owner) > 1; > > +} > > +#define arch_spin_is_contended arch_spin_is_contended > > +#else /* CONFIG_RISCV_TICKET_LOCK */ > > #include > > +#endif /* CONFIG_RISCV_TICKET_LOCK */ > > + > > #include > > > > #endif /* _ASM_RISCV_SPINLOCK_H */ > > diff --git a/arch/riscv/include/asm/spinlock_types.h b/arch/riscv/include/asm/spinlock_types.h > > index d033a973f287..afbb19841d0f 100644 > > --- a/arch/riscv/include/asm/spinlock_types.h > > +++ b/arch/riscv/include/asm/spinlock_types.h > > @@ -10,7 +10,24 @@ > > # error "please don't include this file directly" > > #endif > > > > +#ifdef CONFIG_RISCV_TICKET_LOCK > > +#define TICKET_NEXT 16 > > + > > +typedef struct { > > + union { > > + u32 lock; > > + struct __raw_tickets { > > + /* little endian */ > > + u16 owner; > > + u16 next; > > + } tickets; > > + }; > > +} arch_spinlock_t; > > + > > +#define __ARCH_SPIN_LOCK_UNLOCKED { { 0 } } > > +#else > > #include > > +#endif > > #include > > > > #endif /* _ASM_RISCV_SPINLOCK_TYPES_H */ > > -- > > 2.17.1 > > > > > -- > Best Regards > Guo Ren > > ML: https://lore.kernel.org/linux-csky/ -- Best Regards Guo Ren ML: https://lore.kernel.org/linux-csky/ _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.8 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6E673C433ED for ; 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Sun, 11 Apr 2021 09:51:16 -0700 (PDT) X-Gm-Message-State: AOAM533qat+8EQZrSNNqe1Y4iZyv2JoG0bDvo/LQDrkujX5jXhaGnNxK LnJk+8EaLgdtmwW8Kfq1wjV1x0+lL646+ES1yFc= X-Google-Smtp-Source: ABdhPJwytlwOM+Rr5ik6o9Gt0Np/mypGW3IwYId67m7mmduUv1Bjo9G3FOhKEOOdYbF0Wmx6IQxmHYMGzhwXowpdgyc= X-Received: by 2002:ac2:4191:: with SMTP id z17mr5521549lfh.557.1618159875345; Sun, 11 Apr 2021 09:51:15 -0700 (PDT) MIME-Version: 1.0 References: <1617201040-83905-1-git-send-email-guoren@kernel.org> <1617201040-83905-4-git-send-email-guoren@kernel.org> In-Reply-To: From: Guo Ren Date: Mon, 12 Apr 2021 00:51:03 +0800 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH v6 3/9] riscv: locks: Introduce ticket-based spinlock implementation To: Guo Ren Content-Type: text/plain; charset="UTF-8" X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-arch , linux-xtensa@linux-xtensa.org, Guo Ren , Arnd Bergmann , Peter Zijlstra , Anup Patel , Linux Kernel Mailing List , linux-csky@vger.kernel.org, openrisc@lists.librecores.org, sparclinux , linux-riscv , linuxppc-dev@lists.ozlabs.org Errors-To: linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Sender: "Linuxppc-dev" On Mon, Apr 12, 2021 at 12:02 AM Guo Ren wrote: > > On Wed, Mar 31, 2021 at 10:32 PM wrote: > > > > From: Guo Ren > > > > This patch introduces a ticket lock implementation for riscv, along the > > same lines as the implementation for arch/arm & arch/csky. > > > > We still use qspinlock as default. > > > > Signed-off-by: Guo Ren > > Cc: Peter Zijlstra > > Cc: Anup Patel > > Cc: Arnd Bergmann > > --- > > arch/riscv/Kconfig | 7 ++- > > arch/riscv/include/asm/spinlock.h | 84 +++++++++++++++++++++++++ > > arch/riscv/include/asm/spinlock_types.h | 17 +++++ > > 3 files changed, 107 insertions(+), 1 deletion(-) > > > > diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig > > index 67cc65ba1ea1..34d0276f01d5 100644 > > --- a/arch/riscv/Kconfig > > +++ b/arch/riscv/Kconfig > > @@ -34,7 +34,7 @@ config RISCV > > select ARCH_WANT_FRAME_POINTERS > > select ARCH_WANT_HUGE_PMD_SHARE if 64BIT > > select ARCH_USE_QUEUED_RWLOCKS > > - select ARCH_USE_QUEUED_SPINLOCKS > > + select ARCH_USE_QUEUED_SPINLOCKS if !RISCV_TICKET_LOCK > > select ARCH_USE_QUEUED_SPINLOCKS_XCHG32 > > select CLONE_BACKWARDS > > select CLINT_TIMER if !MMU > > @@ -344,6 +344,11 @@ config NEED_PER_CPU_EMBED_FIRST_CHUNK > > def_bool y > > depends on NUMA > > > > +config RISCV_TICKET_LOCK > > + bool "Ticket-based spin-locking" > > + help > > + Say Y here to use ticket-based spin-locking. > > + > > config RISCV_ISA_C > > bool "Emit compressed instructions when building Linux" > > default y > > diff --git a/arch/riscv/include/asm/spinlock.h b/arch/riscv/include/asm/spinlock.h > > index a557de67a425..90b7eaa950cf 100644 > > --- a/arch/riscv/include/asm/spinlock.h > > +++ b/arch/riscv/include/asm/spinlock.h > > @@ -7,7 +7,91 @@ > > #ifndef _ASM_RISCV_SPINLOCK_H > > #define _ASM_RISCV_SPINLOCK_H > > > > +#ifdef CONFIG_RISCV_TICKET_LOCK > > +#ifdef CONFIG_32BIT > > +#define __ASM_SLLIW "slli\t" > > +#define __ASM_SRLIW "srli\t" > > +#else > > +#define __ASM_SLLIW "slliw\t" > > +#define __ASM_SRLIW "srliw\t" > > +#endif > > + > > +/* > > + * Ticket-based spin-locking. > > + */ > > +static inline void arch_spin_lock(arch_spinlock_t *lock) > > +{ > > + arch_spinlock_t lockval; > > + u32 tmp; > > + > > + asm volatile ( > > + "1: lr.w %0, %2 \n" > > + " mv %1, %0 \n" > > + " addw %0, %0, %3 \n" > > + " sc.w %0, %0, %2 \n" > > + " bnez %0, 1b \n" > > + : "=&r" (tmp), "=&r" (lockval), "+A" (lock->lock) > > + : "r" (1 << TICKET_NEXT) > > + : "memory"); > > + > > + smp_cond_load_acquire(&lock->tickets.owner, > > + VAL == lockval.tickets.next); > It's wrong, blew is fixup: > > diff --git a/arch/csky/include/asm/spinlock.h b/arch/csky/include/asm/spinlock.h > index fe98ad8ece51..2be627ceb9df 100644 > --- a/arch/csky/include/asm/spinlock.h > +++ b/arch/csky/include/asm/spinlock.h > @@ -27,7 +27,8 @@ static inline void arch_spin_lock(arch_spinlock_t *lock) > : "r"(p), "r"(ticket_next) > : "cc"); > > - smp_cond_load_acquire(&lock->tickets.owner, > + if (lockval.owner != lockval.tickets.next) > + smp_cond_load_acquire(&lock->tickets.owner, > VAL == lockval.tickets.next); eh... plus __smp_acquire_fence: if (lockval.owner != lockval.tickets.next) smp_cond_load_acquire(&lock->tickets.owner, VAL == lockval.tickets.next); else __smp_acquire_fence(); > > +} > > + > > +static inline int arch_spin_trylock(arch_spinlock_t *lock) > > +{ > > + u32 tmp, contended, res; > > + > > + do { > > + asm volatile ( > > + " lr.w %0, %3 \n" > > + __ASM_SRLIW "%1, %0, %5 \n" > > + __ASM_SLLIW "%2, %0, %5 \n" > > + " or %1, %2, %1 \n" > > + " li %2, 0 \n" > > + " sub %1, %1, %0 \n" > > + " bnez %1, 1f \n" > > + " addw %0, %0, %4 \n" > > + " sc.w %2, %0, %3 \n" > > + "1: \n" > > + : "=&r" (tmp), "=&r" (contended), "=&r" (res), > > + "+A" (lock->lock) > > + : "r" (1 << TICKET_NEXT), "I" (TICKET_NEXT) > > + : "memory"); > > + } while (res); > > + > > + if (!contended) > > + __atomic_acquire_fence(); > > + > > + return !contended; > > +} > > + > > +static inline void arch_spin_unlock(arch_spinlock_t *lock) > > +{ > > + smp_store_release(&lock->tickets.owner, lock->tickets.owner + 1); > > +} > > + > > +static inline int arch_spin_value_unlocked(arch_spinlock_t lock) > > +{ > > + return lock.tickets.owner == lock.tickets.next; > > +} > > + > > +static inline int arch_spin_is_locked(arch_spinlock_t *lock) > > +{ > > + return !arch_spin_value_unlocked(READ_ONCE(*lock)); > > +} > > + > > +static inline int arch_spin_is_contended(arch_spinlock_t *lock) > > +{ > > + struct __raw_tickets tickets = READ_ONCE(lock->tickets); > > + > > + return (tickets.next - tickets.owner) > 1; > > +} > > +#define arch_spin_is_contended arch_spin_is_contended > > +#else /* CONFIG_RISCV_TICKET_LOCK */ > > #include > > +#endif /* CONFIG_RISCV_TICKET_LOCK */ > > + > > #include > > > > #endif /* _ASM_RISCV_SPINLOCK_H */ > > diff --git a/arch/riscv/include/asm/spinlock_types.h b/arch/riscv/include/asm/spinlock_types.h > > index d033a973f287..afbb19841d0f 100644 > > --- a/arch/riscv/include/asm/spinlock_types.h > > +++ b/arch/riscv/include/asm/spinlock_types.h > > @@ -10,7 +10,24 @@ > > # error "please don't include this file directly" > > #endif > > > > +#ifdef CONFIG_RISCV_TICKET_LOCK > > +#define TICKET_NEXT 16 > > + > > +typedef struct { > > + union { > > + u32 lock; > > + struct __raw_tickets { > > + /* little endian */ > > + u16 owner; > > + u16 next; > > + } tickets; > > + }; > > +} arch_spinlock_t; > > + > > +#define __ARCH_SPIN_LOCK_UNLOCKED { { 0 } } > > +#else > > #include > > +#endif > > #include > > > > #endif /* _ASM_RISCV_SPINLOCK_TYPES_H */ > > -- > > 2.17.1 > > > > > -- > Best Regards > Guo Ren > > ML: https://lore.kernel.org/linux-csky/ -- Best Regards Guo Ren ML: https://lore.kernel.org/linux-csky/ From mboxrd@z Thu Jan 1 00:00:00 1970 From: Guo Ren Date: Mon, 12 Apr 2021 00:51:03 +0800 Subject: [OpenRISC] [PATCH v6 3/9] riscv: locks: Introduce ticket-based spinlock implementation In-Reply-To: References: <1617201040-83905-1-git-send-email-guoren@kernel.org> <1617201040-83905-4-git-send-email-guoren@kernel.org> Message-ID: List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: openrisc@lists.librecores.org On Mon, Apr 12, 2021 at 12:02 AM Guo Ren wrote: > > On Wed, Mar 31, 2021 at 10:32 PM wrote: > > > > From: Guo Ren > > > > This patch introduces a ticket lock implementation for riscv, along the > > same lines as the implementation for arch/arm & arch/csky. > > > > We still use qspinlock as default. > > > > Signed-off-by: Guo Ren > > Cc: Peter Zijlstra > > Cc: Anup Patel > > Cc: Arnd Bergmann > > --- > > arch/riscv/Kconfig | 7 ++- > > arch/riscv/include/asm/spinlock.h | 84 +++++++++++++++++++++++++ > > arch/riscv/include/asm/spinlock_types.h | 17 +++++ > > 3 files changed, 107 insertions(+), 1 deletion(-) > > > > diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig > > index 67cc65ba1ea1..34d0276f01d5 100644 > > --- a/arch/riscv/Kconfig > > +++ b/arch/riscv/Kconfig > > @@ -34,7 +34,7 @@ config RISCV > > select ARCH_WANT_FRAME_POINTERS > > select ARCH_WANT_HUGE_PMD_SHARE if 64BIT > > select ARCH_USE_QUEUED_RWLOCKS > > - select ARCH_USE_QUEUED_SPINLOCKS > > + select ARCH_USE_QUEUED_SPINLOCKS if !RISCV_TICKET_LOCK > > select ARCH_USE_QUEUED_SPINLOCKS_XCHG32 > > select CLONE_BACKWARDS > > select CLINT_TIMER if !MMU > > @@ -344,6 +344,11 @@ config NEED_PER_CPU_EMBED_FIRST_CHUNK > > def_bool y > > depends on NUMA > > > > +config RISCV_TICKET_LOCK > > + bool "Ticket-based spin-locking" > > + help > > + Say Y here to use ticket-based spin-locking. > > + > > config RISCV_ISA_C > > bool "Emit compressed instructions when building Linux" > > default y > > diff --git a/arch/riscv/include/asm/spinlock.h b/arch/riscv/include/asm/spinlock.h > > index a557de67a425..90b7eaa950cf 100644 > > --- a/arch/riscv/include/asm/spinlock.h > > +++ b/arch/riscv/include/asm/spinlock.h > > @@ -7,7 +7,91 @@ > > #ifndef _ASM_RISCV_SPINLOCK_H > > #define _ASM_RISCV_SPINLOCK_H > > > > +#ifdef CONFIG_RISCV_TICKET_LOCK > > +#ifdef CONFIG_32BIT > > +#define __ASM_SLLIW "slli\t" > > +#define __ASM_SRLIW "srli\t" > > +#else > > +#define __ASM_SLLIW "slliw\t" > > +#define __ASM_SRLIW "srliw\t" > > +#endif > > + > > +/* > > + * Ticket-based spin-locking. > > + */ > > +static inline void arch_spin_lock(arch_spinlock_t *lock) > > +{ > > + arch_spinlock_t lockval; > > + u32 tmp; > > + > > + asm volatile ( > > + "1: lr.w %0, %2 \n" > > + " mv %1, %0 \n" > > + " addw %0, %0, %3 \n" > > + " sc.w %0, %0, %2 \n" > > + " bnez %0, 1b \n" > > + : "=&r" (tmp), "=&r" (lockval), "+A" (lock->lock) > > + : "r" (1 << TICKET_NEXT) > > + : "memory"); > > + > > + smp_cond_load_acquire(&lock->tickets.owner, > > + VAL == lockval.tickets.next); > It's wrong, blew is fixup: > > diff --git a/arch/csky/include/asm/spinlock.h b/arch/csky/include/asm/spinlock.h > index fe98ad8ece51..2be627ceb9df 100644 > --- a/arch/csky/include/asm/spinlock.h > +++ b/arch/csky/include/asm/spinlock.h > @@ -27,7 +27,8 @@ static inline void arch_spin_lock(arch_spinlock_t *lock) > : "r"(p), "r"(ticket_next) > : "cc"); > > - smp_cond_load_acquire(&lock->tickets.owner, > + if (lockval.owner != lockval.tickets.next) > + smp_cond_load_acquire(&lock->tickets.owner, > VAL == lockval.tickets.next); eh... plus __smp_acquire_fence: if (lockval.owner != lockval.tickets.next) smp_cond_load_acquire(&lock->tickets.owner, VAL == lockval.tickets.next); else __smp_acquire_fence(); > > +} > > + > > +static inline int arch_spin_trylock(arch_spinlock_t *lock) > > +{ > > + u32 tmp, contended, res; > > + > > + do { > > + asm volatile ( > > + " lr.w %0, %3 \n" > > + __ASM_SRLIW "%1, %0, %5 \n" > > + __ASM_SLLIW "%2, %0, %5 \n" > > + " or %1, %2, %1 \n" > > + " li %2, 0 \n" > > + " sub %1, %1, %0 \n" > > + " bnez %1, 1f \n" > > + " addw %0, %0, %4 \n" > > + " sc.w %2, %0, %3 \n" > > + "1: \n" > > + : "=&r" (tmp), "=&r" (contended), "=&r" (res), > > + "+A" (lock->lock) > > + : "r" (1 << TICKET_NEXT), "I" (TICKET_NEXT) > > + : "memory"); > > + } while (res); > > + > > + if (!contended) > > + __atomic_acquire_fence(); > > + > > + return !contended; > > +} > > + > > +static inline void arch_spin_unlock(arch_spinlock_t *lock) > > +{ > > + smp_store_release(&lock->tickets.owner, lock->tickets.owner + 1); > > +} > > + > > +static inline int arch_spin_value_unlocked(arch_spinlock_t lock) > > +{ > > + return lock.tickets.owner == lock.tickets.next; > > +} > > + > > +static inline int arch_spin_is_locked(arch_spinlock_t *lock) > > +{ > > + return !arch_spin_value_unlocked(READ_ONCE(*lock)); > > +} > > + > > +static inline int arch_spin_is_contended(arch_spinlock_t *lock) > > +{ > > + struct __raw_tickets tickets = READ_ONCE(lock->tickets); > > + > > + return (tickets.next - tickets.owner) > 1; > > +} > > +#define arch_spin_is_contended arch_spin_is_contended > > +#else /* CONFIG_RISCV_TICKET_LOCK */ > > #include > > +#endif /* CONFIG_RISCV_TICKET_LOCK */ > > + > > #include > > > > #endif /* _ASM_RISCV_SPINLOCK_H */ > > diff --git a/arch/riscv/include/asm/spinlock_types.h b/arch/riscv/include/asm/spinlock_types.h > > index d033a973f287..afbb19841d0f 100644 > > --- a/arch/riscv/include/asm/spinlock_types.h > > +++ b/arch/riscv/include/asm/spinlock_types.h > > @@ -10,7 +10,24 @@ > > # error "please don't include this file directly" > > #endif > > > > +#ifdef CONFIG_RISCV_TICKET_LOCK > > +#define TICKET_NEXT 16 > > + > > +typedef struct { > > + union { > > + u32 lock; > > + struct __raw_tickets { > > + /* little endian */ > > + u16 owner; > > + u16 next; > > + } tickets; > > + }; > > +} arch_spinlock_t; > > + > > +#define __ARCH_SPIN_LOCK_UNLOCKED { { 0 } } > > +#else > > #include > > +#endif > > #include > > > > #endif /* _ASM_RISCV_SPINLOCK_TYPES_H */ > > -- > > 2.17.1 > > > > > -- > Best Regards > Guo Ren > > ML: https://lore.kernel.org/linux-csky/ -- Best Regards Guo Ren ML: https://lore.kernel.org/linux-csky/